Active Receive Mixer LF to 3 GHz AD8342 Broadband RF, LO, and IF ports Conversion gain: 3.7 dB Noise figure: 12.2 dB Input IP3: 22.7 dBm Input P1dB: 8.3 dBm LO drive: 0 dBm Differential high impedance RF input port Single-ended, 50 LO input port Open-collector IF output port Single-supply operation: 5 V @ 98 mA Power-down mode Exposed paddle LFCSP: 3 mm x 3 mm FUNCTIONAL BLOCK DIAGRAM VPDC PWDN 12 11 COMM 13 EXRB COMM 10 9 8 COMM 7 IFOP RFIN 15 6 IFOM VPMX 16 5 COMM BIAS RFCM 14 AD8342 1 2 3 4 VPLO LOCM LOIN COMM 05352-001 FEATURES Figure 1. APPLICATIONS Cellular base station receivers ISM receivers Radio links RF instrumentation GENERAL DESCRIPTION The AD8342 is a high performance, broadband active mixer. It is well suited for demanding receive-channel applications that require wide bandwidth on all ports and very low intermodulation distortion and noise figure. The AD8342 provides a typical conversion gain of 3.7 dB with an RF frequency of 238 MHz. The integrated LO driver presents a 50 input impedance with a low LO drive level, helping to minimize the external component count. The differential high impedance broadband RF port allows for easy interfacing to both active devices and passive filters. The RF input accepts input signals as large as 1.6 V p-p or 8 dBm (relative to 50 ) at P1dB. The open-collector differential outputs provide excellent balance and can be used with a differential filter or IF amplifier, such as the AD8370, AD8375, AD8351, AD8352, or ADL5561. These outputs can also be converted to a single-ended signal using a matching network or a balun transformer. The outputs are capable of swinging 2 V p-p when biased to the VPOS supply rail. The AD8342 is fabricated on an Analog Devices, Inc., proprietary, high performance SiGe IC process. The AD8342 is available in a 16-lead LFCSP. It operates over a -40C to +85C temperature range. An evaluation board is also available. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2007-2009 Analog Devices, Inc. All rights reserved. AD8342 TABLE OF CONTENTS Features .............................................................................................. 1 Typical Performance Characteristics ..............................................8 Applications ....................................................................................... 1 Circuit Description......................................................................... 14 Functional Block Diagram .............................................................. 1 AC Interfaces ................................................................................... 15 General Description ......................................................................... 1 IF Port .......................................................................................... 16 Revision History ............................................................................... 2 LO Considerations ..................................................................... 17 Specifications..................................................................................... 3 High Frequency Applications ................................................... 18 AC Performance ........................................................................... 4 Low Frequency Applications .................................................... 19 Spur Table .......................................................................................... 5 Evaluation Board ............................................................................ 21 Absolute Maximum Ratings............................................................ 6 Outline Dimensions ....................................................................... 24 ESD Caution .................................................................................. 6 Ordering Guide .......................................................................... 24 Pin Configuration and Function Descriptions ............................. 7 REVISION HISTORY 7/09--Rev. A to Rev. B Changed RF and LO Frequency Range from 2.4 GHz to 3 GHz Throughout ........................................................................... 1 Changes to General Description Section ...................................... 1 Added Endnote 2 .............................................................................. 4 Added Low Frequency Applications Section .............................. 19 Added Figure 56 and Figure 57..................................................... 20 Changes to the Evaluation Board Section ................................... 21 Added Figure 59 to Figure 62........................................................ 22 Updated Outline Dimensions ....................................................... 24 Changes to Ordering Guide .......................................................... 24 1/07--Rev. 0 to Rev. A Changes to Features.......................................................................... 1 Changes to General Description .................................................... 1 Changes to Table 2 ............................................................................ 4 Replaced the High Frequency Applications Section .................. 18 4/05--Revision 0: Initial Version Rev. B | Page 2 of 24 AD8342 SPECIFICATIONS VS = 5 V, TA = 25C, fRF = 238 MHz, fLO = 286 MHz, LO power = 0 dBm, ZO = 50 , RBIAS = 1.82 k, RF termination = 100 , IF terminated into 100 through a 2:1 ratio balun, unless otherwise noted. Table 1. Parameter RF INPUT INTERFACE Return Loss Input Impedance DC Bias Level OUTPUT INTERFACE Output Impedance DC Bias Voltage Power Range LO INTERFACE Return Loss DC Bias Voltage POWER-DOWN INTERFACE PWDN Threshold PWDN Response Time PWDN Input Bias Current POWER SUPPLY Positive Supply Voltage Quiescent Current VPDC VPMX, IFOP, IFOM VPLO Total Quiescent Current Power-Down Current Conditions Min High-Z input terminated with 100 off-chip resistor Frequency = 238 MHz (measured at RFIN with RFCM ac-grounded) Internally generated; port must be ac-coupled Differential impedance, frequency = 48 MHz Supplied externally Via a 2:1 impedance ratio transformer 4.75 Typ Max Unit 10 1||0.4 dB k||pF 2.4 V 10||0.5 VS 5.25 13 k||pF V dBm Internally generated; port must be ac-coupled 10 VS - 1.6 dB V Device enabled, IF output to 90% of its final level Device disabled, supply current <5 mA Device enabled Device disabled 3.5 0.4 4 -80 +100 V s s A A 4.75 Supply current for bias cells Supply current for mixer, RBIAS = 1.82 k Supply current for LO limiting amplifier VS = 5 V Device disabled Rev. B | Page 3 of 24 85 5 5 58 35 98 500 5.25 113 V mA mA mA mA A AD8342 AC PERFORMANCE VS = 5 V, TA = 25C, LO power = 0 dBm, ZO = 50 , RBIAS = 1.82 k, RF termination 100 , IF terminated into 100 via a 2:1 ratio balun, unless otherwise noted. Table 2. Parameter RF Frequency Range 1 LO Frequency Range1 IF Frequency Range1, 2 Conversion Gain SSB Noise Figure Input Third-Order Intercept Input Second-Order Intercept Input 1 dB Compression Point LO to IF Output Leakage LO to RF Input Leakage 2x LO to IF Output Leakage RF to IF Output Leakage IF/2 Spurious 1 2 Conditions Min fRF = 460 MHz, fLO = 550 MHz, fIF = 90 MHz fRF = 238 MHz, fLO = 286 MHz, fIF = 48 MHz fRF = 460 MHz, fLO = 550 MHz, fIF = 90 MHz fRF = 238 MHz, fLO = 286 MHz, fIF = 48 MHz fRF1 = 460 MHz, fRF2 = 461 MHz, fLO = 550 MHz, fIF1 = 90 MHz, fIF2 = 89 MHz, each RF tone -10 dBm fRF1 = 238 MHz, fRF2 = 239 MHz, fLO = 286 MHz, fIF1 = 48 MHz, fIF2 = 47 MHz, each RF tone -10 dBm fRF1 = 460 MHz, fRF2 = 410 MHz, fLO = 550 MHz, fIF1 = 90 MHz, fIF2 = 140 MHz fRF1 = 238 MHz, fRF2 = 188 MHz, fLO = 286 MHz, fIF1 = 48 MHz, fIF2 = 98 MHz fRF = 460 MHz, fLO = 550 MHz, fIF = 90 MHz fRF = 238 MHz, fLO = 286 MHz, fIF = 48 MHz LO power = 0 dBm, fLO = 286 MHz LO power = 0 dBm, fLO = 286 MHz LO power = 0 dBm, fRF = 238 MHz, fLO = 286 MHz IF terminated into 100 and measured with a differential probe RF power = -10 dBm, fRF = 238 MHz, fLO = 286 MHz RF power = -10 dBm, fRF = 238 MHz, fLO = 286 MHz See the High Frequency Applications section for details. See the Low Frequency Applications section for details. Rev. B | Page 4 of 24 Typ 3.0 3.0 2.4 3.2 3.7 12.5 12.2 22.2 Max Unit GHz GHz GHz dB dB dB dB dBm 22.7 dBm 50 dBm 44 dBm 8.5 8.3 -27 -55 -47 dBm dBm dBc dBc dBm -32 -62 dBc dBc AD8342 SPUR TABLE VS = 5 V, TA = 25C, RF and LO power = 0 dBm, fRF = 238 MHz, fLO = 286MHz, ZO = 50 , RBIAS = 1.82 k, RF termination 100 , IF terminated into 100 via a 2:1 ratio balun. Note: Measured using standard test board. Typical noise floor of measurement system = -100 dBm. Table 3. m n nfRF - mfLO 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 <-100 -32 -52 -81 -78 -98 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 -25 3.5 -47 -57 -70 -79 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 -54 -42 -51 -79 -80 -95 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 -28 -6 -49 -61 -79 -87 -99 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 -45 -48 -54 -82 -80 -96 <-100 -96 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 -35 -16 -56 -61 -85 -94 -96 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 -39 -50 -56 -74 -87 -95 <-100 -98 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 -36 -28 -62 -69 -92 -88 <-100 <-100 <-100 <-100 <-100 -96 <-100 <-100 <-100 <-100 -42 -57 -62 -94 -93 -98 <-100 <-100 -97 <-100 <-100 <-100 -99 <-100 <-100 <-100 -57 -37 -66 -85 -96 -94 <-100 <-100 <-100 <-100 <-100 -97 <-100 -97 <-100 <-100 -44 -68 -71 -89 -95 <-100 <-100 <-100 <-100 <-100 -99 <-100 -98 <-100 -98 <-100 -42 -45 -80 -86 <-100 <-100 <-100 <-100 <-100 -99 <-100 -96 <-100 -97 -98 <-100 -41 -54 -80 -86 -97 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 -99 <-100 <-100 -46 -37 -67 -90 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 -59 -61 -79 -81 -95 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 <-100 Rev. B | Page 5 of 24 AD8342 ABSOLUTE MAXIMUM RATINGS Table 4. Parameter Supply Voltage, VS RF Input Level LO Input Level PWDN Pin IFOP, IFOM Bias Voltage Minimum Resistor from EXRB to COMM Internal Power Dissipation JA Maximum Junction Temperature Operating Temperature Range Storage Temperature Range Rating 5.5 V 12 dBm 12 dBm VS + 0.5 V 5.5 V 1.8 k 650 mW 77C/W 135C -40C to +85C -65C to +150C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION Rev. B | Page 6 of 24 AD8342 14 RFCM 9 COMM 05352-002 10 EXRB COMM 8 IFOP 7 11 PWDN TOP VIEW (Not to Scale) COMM 5 COMM 4 12 VPDC AD8342 IFOM 6 LOIN 3 13 COMM PIN 1 INDICATOR VPLO 1 LOCM 2 15 RFIN 16 VPMX PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 2. 16-Lead LFCSP Table 5. Pin Function Descriptions Pin No. 1 2 3 Mnemonic VPLO LOCM LOIN 4, 5, 8, 9, 13 6, 7 10 COMM IFOM, IFOP EXRB 11 12 14 15 16 PWDN VPDC RFCM RFIN VPMX Description Positive Supply Voltage for the LO Buffer: 4.75 V to 5.25 V. AC Ground for Limiting LO Amplifier. Internally biased to VS - 1.6 V. AC-couple to ground. LO Input. Nominal input level: 0 dBm. Input level range: -10 dBm to +4 dBm (relative to 50 ). Internally biased to VS - 1.6 V. Must be ac-coupled. Device Common (DC Ground). Differential IF Outputs (Open Collectors). Each requires dc bias of 5.00 V (nominal). Mixer Bias Voltage. Connect resistor from EXRB to ground. Typical value of 1.82 k sets mixer current to nominal value. Minimum resistor value from EXRB to ground = 1.8 k. Internally biased to 1.17 V. Connect to Ground for Normal Operation. Connect pin to VS for disable mode. Positive Supply Voltage for the DC Bias Cell: 4.75 V to 5.25 V. AC Ground for RF Input. Internally biased to 2.4 V. AC-couple to ground. RF Input. Internally biased to 2.4 V. Must be ac-coupled. Positive Supply Voltage for the Mixer: 4.75 V to 5.25 V. Rev. B | Page 7 of 24 AD8342 TYPICAL PERFORMANCE CHARACTERISTICS 6 6 5 5 IF = 48MHz 4 3 RF = 238MHz 4 GAIN (dB) GAIN (dB) VS = 5 V, TA = 25C, RF power = -10 dBm, LO power = 0 dBm, ZO = 50 , RBIAS = 1.82 k, RF termination 100 , IF terminated into 100 via a 2:1 ratio balun, unless otherwise noted. RF = 460MHz 3 IF = 140MHz IF = 10MHz IF = 90MHz 2 100 150 200 250 300 350 400 450 500 05352-005 1 50 05352-004 2 1 10 550 50 100 RF FREQUENCY (MHz) 150 200 250 300 350 IF FREQUENCY (MHz) Figure 3. Conversion Gain vs. RF Frequency Figure 6. Conversion Gain vs. IF Frequency 5 5.0 4.5 IF = 48MHz IF = 10MHz 4 4.0 IF = 140MHz GAIN (dB) GAIN (dB) 3.5 3 IF = 90MHz 2 3.0 2.5 2.0 1.5 1 0 -15 -10 -5 0 05352-026 05352-025 1.0 0.5 0 4.75 5 4.85 4.95 LO LEVEL (dBm) 50 4.5 45 4.0 40 3.5 35 3.0 2.5 2.0 25 20 15 1.0 10 0.5 20 40 60 NORMAL MEAN = 3.7 STD. DEV. = 0.06 30 1.5 0 5.25 05352-054 PERCENTAGE 5.0 -20 5.15 Figure 7. Gain vs. VPOS, fRF = 238 MHz, fLO = 286 MHz 05352-039 GAIN (dB) Figure 4. Gain vs. LO Level, RF Frequency = 238 MHz 0 -40 5.05 VPOS (V) 5 0 3.40 80 TEMPERATURE (C) 3.45 3.50 3.55 3.60 3.65 3.70 3.75 3.80 3.85 3.90 CONVERSION GAIN (238MHz) Figure 5. Gain vs. Temperature, fRF = 238 MHz, fLO = 286 MHz Figure 8. Conversion Gain Distribution, fRF = 238 MHz, fLO = 286 MHz Rev. B | Page 8 of 24 AD8342 27 27 26 26 25 25 IF = 48MHz 24 IF = 90MHz IF = 10MHz INPUT IP3 (dBm) 23 22 21 IF = 140MHz 20 23 RF = 238MHz 21 20 19 05352-007 19 18 17 50 RF = 460MHz 22 100 150 200 250 300 350 400 450 500 05352-008 INPUT IP3 (dBm) 24 18 17 10 550 50 100 RF FREQUENCY (MHz) Figure 9. Input IP3 vs. RF Frequency 27 26 26 25 350 INPUT IP3 (dBm) 21 140MHz IF = 90MHz 22 21 20 20 19 19 -13 -11 -9 -7 -5 -3 -1 1 3 05352-028 22 23 05352-027 INPUT IP3 (dBm) 300 24 IF = 10MHz 23 18 18 17 4.75 5 4.80 4.85 4.90 LO LEVEL (dBm) 4.95 5.00 5.05 5.10 5.15 5.20 5.25 VPOS (V) Figure 10. Input IP3 vs. LO Level, fRF1 = 238 MHz, fRF2 = 239 MHz Figure 13. Input IP3 vs. VPOS, fRF = 238 MHz, fRF2 = 239 MHz LO Frequency = 286 MHz 20 27 NORMAL MEAN = 22.7 18 STD. DEV. = 0.41 25 16 24 14 23 22 21 12 10 8 20 6 19 4 18 -20 0 20 40 60 05352-055 PERCENTAGE 26 05352-032 INPUT IP3 (dBm) 250 25 IF = 48MHz 24 17 -40 200 Figure 12. Input IP3 vs. IF Frequency 27 17 -15 150 IF FREQUENCY (MHz) 2 0 20.6 80 21.0 21.4 21.8 22.2 22.6 23.0 23.4 23.8 24.2 INPUT IP3 (238MHz) TEMPERATURE (C) Figure 11. Input IP3 vs. Temperature, fRF1 = 238 MHz, fRF2 = 239 MHz, fLO = 286 MHz Figure 14. Input IP3 Distribution, fRF = 238 MHz, fLO = 286 MHz Rev. B | Page 9 of 24 13 10 12 9 11 8 10MHz 90MHz 9 8 7 48MHz 140MHz 6 7 RF = 238MHz 6 5 4 3 2 05352-013 5 4 3 50 RF = 460MHz 100 150 200 250 300 350 400 450 500 05352-014 10 INPUT P1dB (dBm) INPUT P1dB (dBm) AD8342 1 0 550 10 50 100 Figure 15. Input P1dB vs. RF Frequency 10 9.5 9 8.5 8.0 IF = 140MHz 7.5 IF = 48MHz 7.0 6.5 300 350 7 6 5 4 3 6.0 -13 -11 -9 -7 -5 -3 -1 1 3 05352-031 05352-038 2 5.5 5.0 -15 250 8 INPUT P1dB (dBm) INPUT P1dB (dBm) IF = 10MHz IF = 90MHz 200 Figure 18. Input P1dB vs. IF Frequency 10.0 9.0 150 IF FREQUENCY (MHz) RF FREQUENCY (MHz) 1 0 4.75 5 4.85 LO LEVEL (dBm) 4.95 5.05 5.15 5.25 VPOS (V) Figure 16. Input P1dB vs. LO Level, fRF = 238 MHz Figure 19. Input P1dB vs. VPOS, fRF = 238 MHz, fLO = 286 MHz 10 28 26 9 NORMAL MEAN = 8.3 STD. DEV. = 0.07 20 PERCENTAGE 22 7 5 4 18 16 14 12 10 3 8 2 6 1 0 -40 4 -20 0 20 40 60 05352-056 6 05352-033 INPUT P1dB (dBm) 24 8 2 0 8.00 8.05 8.10 8.15 8.20 8.25 8.30 8.35 8.40 8.45 8.50 8.55 8.60 80 TEMPERATURE (C) IP1dB (238MHz) Figure 17. Input P1dB vs. Temperature, fRF = 238 MHz, fLO = 286 MHz Figure 20. Input IP3 Distribution, fRF = 238 MHz, fLO = 286 MHz Rev. B | Page 10 of 24 AD8342 60 RF = 238MHz IF = 140MHz 50 40 IF = 48MHz 30 20 40 30 20 150 200 250 300 350 400 450 500 0 10 550 05352-011 10 05352-010 10 0 100 RF = 460MHz 50 INPUT IP2 (dBm) INPUT IP2 (dBm) 60 IF = 90MHz IF = 10MHz 50 100 RF FREQUENCY (MHz) Figure 21. Input IP2 vs. RF Frequency (Second RF = RF - 50 MHz) 300 350 58 IF = 10MHz 56 56 IF = 48MHz 54 54 INPUT IP2 (dBm) 52 50 48 IF = 90MHz 46 05352-029 -11 -9 -7 -5 48 44 42 -13 50 46 IF = 140MHz 44 52 -3 -1 1 3 05352-030 INPUT IP2 (dBm) 250 60 58 42 40 4.75 5 4.85 4.95 LO LEVEL (dBm) 5.05 5.15 5.25 VPOS (V) Figure 22. Input IP2 vs. LO Level, fRF = 238 MHz, fRF2 = 188 MHz Figure 25. Input IP2 vs. VPOS, fRF1 = 238 MHz, fRF2 = 188 MHz, fLO = 286 MHz 14.0 16 RF = 460MHz 14 13.5 NOISE FIGURE (dB) 12 NOISE FIGURE (dB) 200 Figure 24. Input IP2 vs. IF Frequency (Second RF = RF - 50 MHz) 60 40 -15 150 IF FREQUENCY (MHz) 13.0 12.5 12.0 RF = 238MHz 10 8 6 4 11.5 100 150 200 250 300 350 400 450 500 0 10 550 RF FREQUENCY (MHz) 05352-017 05352-016 11.0 50 2 60 110 160 210 260 IF FREQUENCY (MHz) Figure 23. Noise Figure vs. RF Frequency, IF Frequency = 48 MHz Figure 26. Noise Figure vs. IF Frequency Rev. B | Page 11 of 24 310 AD8342 30 16 NORMAL MEAN = 12.25 STD. DEV. = 0.14 25 15 NF = 140MHz NF = 90MHz 13 20 PERCENTAGE NF (dB) 14 15 10 12 NF = 10MHz NF = 48MHz -13 -11 -9 -7 -5 -3 -1 1 3 0 11.8 5 05352-023 10 -15 5 05352-018 11 11.9 12.0 12.1 12.2 12.3 12.4 12.5 12.6 12.7 12.8 NOISE FIGURE (dB) LO POWER (dBm) Figure 27. Noise Figure vs. LO Power, fRF = 238 MHz Figure 30. Noise Figure Distribution, fRF = 238 MHz, fLO = 286 MHz 5.0 105 30 NOISE FIGURE AND INPUT IP3 (dBm) 4.5 3.0 2.5 2.0 1.5 05352-024 1.0 0.5 0 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 INPUT IP3 20 95 15 90 NOISE FIGURE 10 85 CURRENT 80 5 0 1.8 3.4 2.0 2.2 RBIAS (k) 2.4 2.6 2.8 75 3.0 RBIAS (k) Figure 28. Gain vs. RBIAS, RF Frequency = 238 MHz, LO Frequency = 286 MHz Figure 31. Noise Figure, Input IP3, and Supply Current vs. RBIAS, fRF1 = 238 MHz, fRF2 = 239 MHz, fLO = 286 MHz 61 10 59 9 8 INPUT P1dB (dBm) 57 INPUT IP2 (dBm) SUPPLY CURRENT (mA) GAIN (dB) 3.5 100 25 05352-015 4.0 55 53 51 49 7 6 5 4 3 05352-037 45 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 05352-036 2 47 1 0 1.8 3.4 RBIAS (k) 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 RBIAS (k) Figure 29. Input IP2 vs. RBIAS, fRF = 238 MHz (Second RF = RF - 50 MHz), fLO = 286 MHz Rev. B | Page 12 of 24 Figure 32. Input P1dB vs. RBIAS, fRF = 238 MHz, fLO = 286 MHz AD8342 0 120 -10 100 SUPPLY CURRENT (mA) LEAKAGE (dBc) -20 -30 -40 -50 -60 80 60 40 -70 05352-021 -90 50 250 450 650 05352-034 20 -80 0 -40 850 -20 0 20 LO FREQUENCY (MHz) 60 80 Figure 36. Supply Current vs. Temperature 0 0 -5 -2 -10 -4 RETURN LOSS (dB) -15 -20 IF = 10MHz -30 -6 -8 -10 -12 -14 -35 IF = 48MHz -45 50 100 150 200 250 300 350 400 -16 05352-035 -40 450 500 -18 60 550 05352-059 FEEDTHROUGH (dBc) Figure 33. LO to RF Leakage vs. LO Frequency, LO Power = 0 dBm -25 40 TEMPERATURE (C) 160 260 360 RF FREQUENCY (MHz) 460 560 660 760 860 LO FREQUENCY (MHz) Figure 34. RF to IF Feedthrough, RF Power = -10 dBm Figure 37. LO Return Loss vs. LO Frequency 0 100pF VPOS -5 1.82k 0.1F 100pF -15 -20 12 11 10 9 VPDC PWDN EXRB COMM 13 COMM 14 RFCM COMM 8 IFOP 7 1nF -25 RF IN -30 -35 0.1F 100pF 05352-020 -40 150 250 350 450 550 650 750 15 RFIN 16 VPMX TC2-1T IFOM 6 COMM 5 1nF VPOS -45 50 AD8342 100 VPLO LOCM LOIN COMM 1 2 3 4 VPOS 100pF 0.1F 850 LO FREQUENCY (MHz) 100pF 1nF 0.1F 1nF LO IN Figure 35. LO to IF Feedthrough vs. LO Frequency, LO Power = 0 dBm IF OUT (50) 05352-058 FEEDTHROUGH (dBc) -10 Figure 38. Characterization Circuit Used to Measure Typical Performance Characteristics Data Rev. B | Page 13 of 24 AD8342 CIRCUIT DESCRIPTION The device also features a power-down function. Application of a logic low at the PWDN pin allows normal operation. A high logic level at the PWDN pin shuts down the AD8342. Power consumption when the part is disabled is less than 10 mW. The bias for the mixer is set with an external resistor (RBIAS) from the EXRB pin to ground. The value of this resistor directly affects the dynamic range of the mixer. The external resistor should not be lower than 1.82 k. Permanent damage to the VPDC EXTERNAL BIAS RESISTOR PWDN BIAS RFIN IFOP V TO I RFCM IFOM LO INPUT VPLO Figure 39. Simplified Schematic Showing the Key Elements of the AD8342 As shown in Figure 40, the IF output pins, IFOP and IFOM, are directly connected to the open collectors of the NPN transistors in the mixer core so the differential and single-ended impedances looking into this port are relatively high, on the order of several k. A connection between the supply voltage and these output pins is required for proper mixer core operation. IFOP IFOM LOIN RFIN RFCM COMM 05352-041 The RF voltage to RF current conversion is done via a resistively degenerated differential pair. To drive this port single-ended, the RFCM pin should be ac-grounded while the RFIN pin is accoupled to the signal source. The RF inputs can also be driven differentially. The voltage-to-current converter then drives the emitters of a four-transistor switching core. This switching core is driven by an amplified version of the local oscillator signal connected to the LO input. There are three limiting gain stages between the external LO signal and the switching core. The first stage converts the single-ended LO drive to a well-balanced differential drive. The differential drive then passes through two more gain stages, which ensures that a limited signal drives the switching core. This affords the user a lower LO drive requirement, while maintaining excellent distortion and compression performance. The output signal of these three LO gain stages drives the four transistors within the mixer core to commutate at the rate of the local oscillator frequency. The output of the mixer core is taken directly from its open collectors. The open-collector outputs present a high impedance at the IF frequency. The conversion gain of the mixer depends directly on the impedance presented to these open collectors. In characterization, a 100 load was presented to the part via a 2:1 impedance transformer. part can result if values below 1.8 k are used. This resistor sets the dc current through the mixer core. The performance effects of changing this resistor can be seen in the Typical Performance Characteristics section. 05352-040 The AD8342 is an active mixer, optimized for operation within the input frequency range of near dc to 2.4 GHz. It has a differential, high impedance RF input that can be terminated or matched externally. The RF input can be driven either singleended or differentially. The LO input is a single-ended 50 input. The IF outputs are differential open-collectors. The mixer current can be adjusted by the value of an external resistor to optimize performance for gain, compression, and intermodulation, or for low power operation. Figure 39 shows the basic blocks of the mixer, including the LO buffer, RF voltage-tocurrent converter, bias cell, and mixing core. Figure 40. AD8342 Simplified Schematic The AD8342 has three pins for the supply voltage: VPDC, VPMX, and VPLO. These pins are separated to minimize or eliminate possible parasitic coupling paths within the AD8342 that could cause spurious signals or reduced interport isolation. Consequently, each of these pins should be well bypassed and decoupled as close to the AD8342 as possible. Rev. B | Page 14 of 24 AD8342 AC INTERFACES Table 6. Dynamic Performance for Various Input Networks Input Network Gain (dB) IIP3 (dBm) P1dB (dBm) NF (dB) 50 Shunt 0.66 25.4 10.8 14 50 100nH 3.6pF 1.00 1.75 0.50 0.75 0.50 FREQUENCY (Hz) 0 1G 05352-042 100M 200M 300M 400M 500M 600M 700M 800M 900M ZO = 50 fMAIN = 250MHz 50 100 25 Q=3 200 POINT POINT POINT POINT 0 ZL 10 0.25 0.25 0 1k 1(1000 + j0) 2(500 + j0) 3(55.6 - j157.2) 4(55.6 - j0.1) 500 2 4 1 500 200 Figure 41. RF Input Impedance 100 The matching or termination used at the RF input of the AD8342 has a direct effect on its dynamic range. The characterization circuit, as well as the evaluation board, uses a 100 resistor to terminate the RF port. This termination resistor in shunt with the input stage results in a return loss of better than -10 dBm (relative to 50 ). Table 6 shows gain, IP3, P1dB, and noise figure for four different input networks. This data was measured at an RF frequency of 250 MHz and at an LO frequency of 300 MHz. Rev. B | Page 15 of 24 50 3 25 10 Figure 43. LC Matching Example 05352-044 1.00 (1000 + j0) Impedance transformations of greater than 10:1 result in a higher Q circuit and thus a narrow RF input bandwidth. A 1 k resistor is placed across the RF input of the device in parallel with the device internal input impedance, creating a 500 load. This impedance is matched to as close as possible to 50 for the source, with standard components using a shunt C, series L matching circuit (see Figure 43). CAPACITANCE (pF) RESISTANCE (k) 0.75 1.25 Matched (Figure 42) 9.3 18.5 2.3 10.5 Figure 42. Matching Circuit The RF input of the AD8342 is high impedance, 1 k across the frequency range shown in Figure 41. The input capacitance decreases with frequency due to package parasitics. 1.50 500 Shunt 5.3 20. 6 6.3 10.2 The RF port can also be matched using an LC circuit, as shown in Figure 42. The AD8342 is designed to operate over a broad frequency range. It is essential to ac couple RF and LO ports to prevent dc offsets from skewing the mixer core in an asymmetrical manner, potentially degrading noise figure and linearity. 2.00 100 Shunt 3.5 22.9 8.4 12.5 05352-043 The AD8342 is designed to downconvert radio frequencies (RF) to lower intermediate frequencies (IF) using a high- or low-side local oscillator (LO). The LO is injected into the mixer core at a frequency higher or lower than the desired input RF. The frequency difference between the LO and the RF, fLO - fRF (high side) or fRF - fLO (low side), is the intermediate frequency, fIF. In addition to the desired RF signal, an RF image is downconverted to the desired IF frequency. The image frequency is at fLO + fIF when driven with a high-side LO. When using a broadband load, the conversion gain of the AD8342 is nearly constant over the specified RF input band (see Figure 3). AD8342 IF PORT The IF port comprises open-collector differential outputs. The NPN open collectors can be modeled as current sources that are shunted with resistances of ~10 k in parallel with capacitances of ~1 pF. The specified performance numbers for the AD8342 were measured with 100 differential terminations. However, different load impedances can be used where circumstances dictate. In general, lower load impedances result in lower conversion gain and lower output P1dB. Higher load impedances result in higher conversion gain for small signals, but lower IP3 values for both input and output. If the IF signal is to be delivered to a remote load, more than a few millimeters away at high output frequencies, avoid unintended parasitic effects due to the intervening PCB traces. One approach is to use an impedance transforming network or transformer located close to the AD8342. If very wideband output is desired, a nearby buffer amplifier may be a better choice, especially if IF response to dc is required. An example of such a circuit is presented in Figure 45, in which the AD8351 differential amplifier is used to drive a pair of 75 transmission lines. The gain of the buffer can be independently set by appropriate choice of the value for the gain resistor, RG. 50 0.5 45 0.4 0.3 35 30 0.2 25 0.1 20 15 0 CAPACITANCE (pF) RESISTANCE (k) 40 The high input impedance of the AD8351 allows for a shunt differential termination to provide the desired 100 load to the AD8342 IF output port. It is necessary to bias the open-collector outputs using one of the schemes presented in Figure 47 and Figure 48. Figure 47 illustrates the application of a center-tapped impedance transformer. The turns ratio of the transformer should be selected to provide the desired impedance transformation. In the case of a 50 load impedance, a 2-to-1 impedance ratio transformer should be used to transform the 50 load into a 100 differential load at the IF output pins. Figure 48 illustrates a differential IF interface where pull-up choke inductors are used to bias the open-collector outputs. The shunting impedance of the choke inductors used to couple dc current into the mixer core should be large enough at the IF operating frequency so it does not load down the output current before reaching the intended load. Additionally, the dc current handling capability of the selected choke inductors needs to be at least 45 mA. The self-resonant frequency of the selected choke should be higher than the intended IF frequency. A variety of suitable choke inductors is commercially available from manufacturers such as Murata and Coilcraft(R). Figure 46 shows the loading effects when using nonideal inductors. An impedance transforming network may be required to transform the final load impedance to 100 at the IF outputs. There are several good reference books that explain general impedance matching procedures, including: * Chris Bowick, RF Circuit Design, Newnes, Reprint Edition, 1997. * David M. Pozar, Microwave Engineering, Wiley, 3rd Edition, 2004. * Guillermo Gonzalez, Microwave Transistor Amplifiers: Analysis and Design, Prentice Hall, Second Edition, 1996. 10 -0.1 0 0 100M 200M 300M 400M 500M 600M 700M 800M 900M -0.2 1G FREQUENCY (Hz) 90 05352-045 5 60 120 Figure 44. IF Port Impedance 150 +VS 30 50MHz AD8342 REAL CHOKES +VS COMM 8 RFC 180 IFOP 7 100 IFOM 6 RG + AD8351 - Tx LINE ZO = 75 50MHz ZL 500MHz Tx LINE ZO = 75 210 RFC COMM 5 0 IDEAL CHOKES 330 ZL = 100 Figure 45. AD8351 Used as Transmission Line Driver and Impedance Buffer 240 300 270 05352-049 +VS 05352-046 500MHz Figure 46. IF Port Loading Effects Due to Finite Q Pull-Up Inductors (Murata BLM18HD601SN1D Chokes) Rev. B | Page 16 of 24 AD8342 30 +VS AD8342 MODELED 25 2:1 IFOP 7 IF OUT ZO = 50 VOLTAGE GAIN (dB) COMM 8 COMM 5 ZL = 100 05352-047 IFOM 6 Figure 47. Biasing the IF Port Open-Collector Outputs Using a Center-Tapped Impedance Transformer 20 MEASURED 15 10 +VS 0 10 AD8342 RFC Figure 49. Voltage Conversion Gain vs. IF Loading IF OUT+ IFOP 7 ZL = 100 IFOM 6 IMPEDANCE TRANSFORMING NETWORK ZL LO CONSIDERATIONS IF OUT- The LOIN port provides a 50 load impedance with commonmode decoupling on LOCM. Again, common-grade ceramic capacitors provide sufficient signal coupling and bypassing of the LO interface. +VS 05352-048 RFC COMM 5 Figure 48. Biasing the IF Port Open-Collector Outputs Using Pull-Up Choke Inductors The AD8342 is optimized for driving a 100 load. Although the device is capable of driving a wide variety of loads, to maintain optimum distortion and noise performance, it is advised that the presented load at the IF outputs is close to 100 . The linear differential voltage conversion gain of the mixer can be modeled as AV = G m x R LOAD where: Gm = 1 x 1000 100 IF LOAD () gm 1 + g m Re RLOAD is the single-ended load impedance. gm is the transistor transconductance and is equal to 1810/RBIAS. Re = 15 . The external RBIAS resistor is used to control the power dissipation and dynamic range of the AD8342. Because the AD8342 has internal resistive degeneration, the conversion gain is primarily determined by the load impedance and the on-chip degeneration resistors. Figure 49 shows how gain varies with IF load. The external RBIAS resistor has only a small effect. The most direct way to affect conversion gain is by varying the load impedance. Small loads result in lower gains while larger loads increase the conversion gain. If the IF load impedance is too large, it causes a decrease in linearity (P1dB, IP3). In order to maintain positive conversion gain and preserve SFDR performance, the differential load presented at the IF port should remain in the range of about 100 to 250 . The LO signal needs to have adequate phase noise characteristics and low second-harmonic content to prevent degradation of the noise figure performance of the AD8342. An LO plagued with poor phase noise can result in reciprocal mixing, a mechanism that causes spectral spreading of the downconverted signal, limiting the sensitivity of the mixer at frequencies adjacent to any large input signals. The internal LO buffer provides enough gain to hard-limit the input LO and provide fast switching of the mixer core. Odd harmonic content present on the LO drive signal should not impact mixer performance; however, evenorder harmonics cause the mixer core to commutate in an unbalanced manner, potentially degrading noise performance. Simple lumped element low-pass filtering can be applied to help reject the harmonic content of a given local oscillator, as shown in Figure 50. The filter depicted is a common 3-pole Chebyshev, designed to maintain a 1-to-1 source-to-load impedance ratio with no more than 0.5 dB of ripple in the pass band. Other filter structures can be effective as long as the second harmonic of the LO is filtered to negligible levels, for example, ~30 dB below the fundamental. AD8342 LOCM LOIN COMM 2 RS LO SOURCE 3 4 L2 C1 C3 RL FOR RS = RL 1.864 C1 = 2fcRL L2 = 1.28RL 2fc C3 = fC - FILTER CUTOFF FREQUENCY 1.834 2fcRL 05352-050 COMM 8 05352-057 5 Figure 50. Using a Low-Pass Filter to Reduce LO Second Harmonic Rev. B | Page 17 of 24 AD8342 HIGH FREQUENCY APPLICATIONS The AD8342 is a broadband mixer capable of both up and down conversion. Unlike other mixers that rely on on-chip reactive circuitry to optimize performance over a specific band, the AD8342 is a versatile general-purpose device that can be used from arbitrarily low frequencies to several GHz. In general, the following considerations help to ensure optimum performance: * Minimize ac loading impedance of IF port bias network. * Maximize power transfer to the desired ac load. * For maximum conversion gain and the lowest noise performance, reactively match the input as described in the IF Port section. * For maximum input compression point and input intercept points, resistively terminate the input as described in the IF Port section. As an example, Figure 51 shows the AD8342 as an upconverting mixer for a W-CDMA single-carrier transmitter design. For this application, it was desirable to achieve -65 dBc adjacent channel power ratio (ACPR) at a -13 dBm output power level. The ACPR is a measure of both distortion and noise carried into an adjacent frequency channel due to the finite intercept points and noise figure of an active device. 100pF 1.82k 100pF VPOS 12 11 10 9 VPDC PWDN EXRB COMM 13 COMM COMM 8 IFOP 7 IFOM 6 1nF 14 RFCM 170MHz INPUT 100nH 1nF 499 AD8342 15 RFIN 4.7pF VPOS 0.1F 16 VPMX 100pF COMM 5 LOCM LOIN COMM 1 2 3 4 1nF 100pF -60 ETC1-1-13 1nF VPLO The performance of the circuit is shown in Figure 52. The average ACPR of the adjacent and alternate channels is presented vs. output power. The circuit provides a 65 dBc ACPR at -13 dBm output power. The optimum ACPR power level can be shifted to the right or left by adjusting the output loading and the loss of the input match. 34nH 2140MHz OUT ADJACENT CHANNELS -62 1nF 34nH 100pF VPOS 1nF 05352-052 0.1pF External pull-up choke inductors are used to feed dc bias into the open-collector outputs. It is desirable to select pull-up choke inductors that present high loading reactance at the output frequency. Coilcraft 0302CS series inductors were selected due to their very high self-resonant frequency and Q. A 1:1 balun was ac-coupled to the output to convert the differential output to a single-ended signal and present the output with a 50- ac loading impedance. 100pF 1970MHz OSC ACPR (dBc) VPOS input impedance using an external shunt termination resistor to allow for a lower Q reactive matching network. The input is terminated across the RFIN and RFCM pins using a 499 termination. The termination should be as close to the device as possible to minimize standing wave concerns. The RFCM is bypassed to ground using a 1 nF capacitor. A dc blocking capacitor of 1 nF is used to isolate the dc input voltage present on the RFIN pin from the source. A step-up impedance transformation is realized using a series L shunt C reactive network. The actual values used need to accommodate for the series L and stray C parasitics of the connecting transmission line segments. When using the customer evaluation board with the components specified in Figure 51, the return loss over a 5 MHz band centered at 170 MHz was better than 10 dB. -64 -66 Figure 51. W-CDMA Tx Up-Conversion Application Circuit Rev. B | Page 18 of 24 -70 -25 05352-053 Because a W-CDMA channel encompasses a bandwidth of almost 5 MHz, it is necessary to keep the Q of the matching circuit low enough so that phase and magnitude variations are below an acceptable level over the 5 MHz band. It is possible to use purely reactive matching to transform a 50 source to match the raw ~1 k input impedance of the AD8342. However, the L and C component variations could present production concerns due to the sensitivity of the match. For this application, it is advantageous to shunt down the ~1 k ALTERNATE CHANNELS -68 -20 -15 -10 -5 0 OUTPUT POWER (dBm) Figure 52. Single Carrier W-CDMA ACPR Performance of Tx Up-Conversion Circuit (Test Model 1_64) AD8342 The available frequency range of the AD8342 is extremely broad. With adequate care, any of the mixer ports can be optimized for extremely low frequencies, or up to several GHz. The standard evaluation board is populated for broadband performance from a few MHz to ~1GHz. The input match of the RF port degrades at higher frequencies when using the standard eval board. The broadband frequency range can be extended by minimizing parasitics between the input terminating resistor, R5, and the input pins. 100pF VPOS The broadband frequency capabilities of the AD8342 makes it an attractive solution for a variety of applications, including cellular, CATV, point-to-point radio links, and test equipment. As an example, the circuit depicted in Figure 53 can easily be applied as a feedback mixer in a predistortion receiver design. The performance depicted in Figure 55 was measured using a 160 MHz IF. Here, four W-CDMA carriers with high PAR are down-converted for IF sampling so that transmit path nonlinearities can be measured and minimized using digital predistortion techniques. 1.82k 0.1F 1000pF -30 11 10 9 VPDC PWDN EXRB COMM COMM COMM 8 14 RFCM IFOP 7 IFOM 6 COMM 5 AD8342 100 TC2-1T 15 RFIN VPOS 16 0.1F 1000pF -50 IF OUT (190MHz) VPMX VPLO LOCM LOIN COMM 1 2 3 4 -60 -70 -80 VPOS 100pF 1nF 0.1F -90 1nF 05352-060 1000pF 0.1F LO IN NOTES 1. INPUT TERMINATION PLACED AS CLOSE AS POSSIBLE TO RFIN AND RFCM INPUTS. -100 -110 Figure 53. Modified Evaluation Board Schematic for Broadband Down-Conversion Performance up to 3 GHz -120 CENTER 160MHz The measurements in Figure 54 were made using the modified evaluation board as configured in Figure 53. Tx CHANNELS CH1 (REF) -20.65dBm CH2 -20.29dBm CH3 -20.25dBm CH4 -20.29dBm OIP3 TOTAL 20 15 10 5 0 500 SPAN 40.6MHz ADJACENT CHANNE L LOWER -61.36dB UPPER -60.84dB ALTERNATE CHANNEL LOWER -61.94dB UPPER -61.72dB -14.35dBm Figure 55. ACPR Performance for Multiple W-CDMA Carriers Being DownConverted from 2140 MHz to 160 MHz for Distortion Analysis LOW FREQUENCY APPLICATIONS NF IP1dB GAIN 05352-061 NF, GAIN, OIP3, IP1dB (dB, dBm) 30 25 4.06MHz STANDARD: W-CDMA 3GPP FWD 05352-062 1nF RBW 30kHz VBW 300kHz SWT 4s -40 1nF RF IN ATT 5dB POS -22.564dBm 12 13 REF -22.6dBm 1000 1500 2000 2500 3000 RF FREQUENCY (MHz) Figure 54. Input OIP3, IP1dB, Gain and NF vs. RF Frequency for a 190 MHz IF Using a Low-Side LO. The AD8342 can be used in extremely low frequency applications. Figure 56 depicts the configuration with necessary modifications at IF ports. Two 10 resistors are used to bias the open collector outputs, and the output coupling capacitors need to be large enough to allow intended low frequency operation. Figure 57 illustrates the gain performance at fixed IF of 10 kHz and 1 MHz for broadband down-conversion using low-side LO. Rev. B | Page 19 of 24 AD8342 100pF 20 +5V 13 8 RFCM 14 100 RF IN 1nF RFIN 7 AD8342 15 6 VPMX 5 100pF 100pF 1nF 10 IFOP 10F BALANCED OUTPUT IFOM 10 IF = 1MHz IF = 10kHz 5 10F 10 4 COMM 3 LOIN 2 LOCM VPLO 1 0.1F COMM COMM 16 0.1F +5V 9 15 0 0.7 +5V 1nF LO IN 0.9 1.1 1.3 1.5 1.7 1.9 2.1 RF FREQUENCY (GHz) 2.3 2.5 2.7 05352-102 1nF 10 CONVERSION GAIN (dB) COMM 11 05352-101 12 EXRB PWDN VPDC 100pF 0.1F COMM 1.82k 1N4148 Figure 57. Gain Performance for 1 MHz and 10 kHz IF of Broadband DownConversion Figure 56. Modified Evaluation Board Schematic for Down-Converting Broadband RF to Low IF Frequencies. Rev. B | Page 20 of 24 AD8342 EVALUATION BOARD An evaluation board is available for the AD8342. The evaluation board is configured for single-ended signaling at the IF output port via a balun transformer. The schematic for the evaluation board is presented in Figure 58. The representations of the board layout are included in Figure 59 through Figure 62. R8 PWDN C11 100pF 10k W1 GND VPOS VPOS R7 C12 0.1F 0 R6 R9 0 1.82k C13 100pF 12 9 10 11 Z2 OPEN VPDC PWDN EXRB COMM 13 L1 0 RF_IN 50 TRACE C14 OPEN R5 100 C2 0.1F 0 14 RFCM IFOP 7 C3 1000pF DUT 15 16 C4 1000pF RFIN IFOM 6 C5 0.1F C6 1000pF Z3 OPEN COMM 5 VPMX C7 1000pF 2 3 4 3 2 1 R11 6 100 TRACES, NO GROUND PLANE R4 OPEN Z4 OPEN IF_OUT- R15 0 R16 C8 1000pF IF_OUT+ 4 TC2-1T 0 0 R3 OPEN T1 Z1 OPEN R12 OPEN VPLO LOCM LOIN COMM 1 R2 0 COMM 8 COMM C1 1000pF R1 VPOS R10 0 VPOS C10 100pF C9 0.1F 05352-003 PWDN INLO Figure 58. Evaluation Board Table 7. Evaluation Board Configuration Options Component R1, R2, R7, C2, C4, C5, C6, C9, C10, C12, C13 Description Supply decoupling. Shorts or power supply decoupling resistors and filter capacitors. R3, R4 R6, C11 Options for single-ended IF output circuit. RBIAS resistor that sets the bias current for the mixer core. The capacitor provides ac bypass for R6. Pull down for the PWDN pin. Link to PWDN pin. RF input. C3 provides dc block for RF input. R5 provides a resistive input termination. C16 and L1 are provided for reactive matching of the input. R8 R9 C3, R5, C14, L1 C1 C8 C7 W1 T1, R10, R11, R12, R15, R16, Z3, Z4, Z1, Z2, RF common ac coupling. Provides dc block for RF input common connection. LO input ac coupling. Provides dc block for the LO input. LO common ac coupling. Provides dc block for LO input common connection. Power down. The part is on when the PWDN is connected to ground via a 10 k resistor. The part is disabled when PWDN is connected to the positive supply (VS) via W1. IF output interface. T1 converts a differential high impedance IF output to single-ended. When loaded with 50 , this balun presents a 100 load to the mixers collectors. The center tap of the primary is used to supply the bias voltage (VS) to the IF output pins. Rev. B | Page 21 of 24 Default Conditions R1, R2, R7 = 0 C4, C6 = 1000 pF C10, C13 = 100 pF C2, C5, C9, C12 = 0.1 F R3, R4 = Open R6 = 1.82 k C11 = 100 pF R8 = 10 k R9 = 0 C3 = 1000 pF R5 = 100 C14 = Open L1 = 0 C1 = 1000 pF C8 = 1000 pF C7 = 1000 pF T1 = TC2-1T, 2:1 (Mini-Circuits(R)) R12 = Open R10, R11, R15, R16 = 0 Z3, Z4 = Open Z1, Z2 = Open 05352-104 AD8342 05352-105 Figure 59. Evaluation Board Artwork Top Figure 60. Evaluation Board Artwork Internal 1 Rev. B | Page 22 of 24 05352-106 AD8342 05352-107 Figure 61. Evaluation Board Artwork Internal 2 Figure 62. Evaluation Board Artwork Bottom Rev. B | Page 23 of 24 AD8342 OUTLINE DIMENSIONS 0.60 MAX 3.00 BSC SQ BOTTOM VIEW 0.45 TOP VIEW 13 12 2.75 BSC SQ 0.80 MAX 0.65 TYP 12 MAX SEATING PLANE 0.05 MAX 0.02 NOM 0.30 0.23 0.18 *1.65 1 EXPOSED PAD 0.50 BSC 0.90 0.85 0.80 16 PIN 1 INDICATOR 9 4 8 5 1.50 SQ 1.35 0.25 MIN 1.50 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 0.20 REF 071708-A PIN 1 INDICATOR 0.50 0.40 0.30 *COMPLIANT TO JEDEC STANDARDS MO-220-VEED-2 EXCEPT FOR EXPOSED PAD DIMENSION. Figure 63. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 3 mm x 3 mm Body, Very Thin Quad (CP-16-3) Dimensions in millimeters ORDERING GUIDE Model AD8342ACPZ-REEL7 1 Temperature Range -40C to +85C AD8342ACPZ-R21 -40C to +85C AD8342ACPZ-WP1 -40C to +85C AD8342-EVALZ1 1 Package Description 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ], Reel 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ], Reel 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ], Waffle Pack Evaluation Board Z = RoHS Compliant Part. (c)2007-2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05352-0-7/09(B) Rev. B | Page 24 of 24 Package Option CP-16-3 Branding Q01 Ordering Quantity 1,500 CP-16-3 Q01 250 CP-16-3 Q01 50 1