Active Receive Mixer
LF to 3 GHz
AD8342
Rev. B
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rights of third parties that may result from its use. Specifications subject to change without notice. No
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Fax: 781.461.3113 ©2007–2009 Analog Devices, Inc. All rights reserved.
FEATURES
Broadband RF, LO, and IF ports
Conversion gain: 3.7 dB
Noise figure: 12.2 dB
Input IP3: 22.7 dBm
Input P1dB: 8.3 dBm
LO drive: 0 dBm
Differential high impedance RF input port
Single-ended, 50 Ω LO input port
Open-collector IF output port
Single-supply operation: 5 V @ 98 mA
Power-down mode
Exposed paddle LFCSP: 3 mm × 3 mm
APPLICATIONS
Cellular base station receivers
ISM receivers
Radio links
RF instrumentation
FUNCTIONAL BLOCK DIAGRAM
8
7
6
13
15
16
COMM
IFOP
IFOM
5COMM
14
2
134
COMM
RFCM
RFIN
VPMX
V
PDC PWDN EXRB COMM
11
12 10 9
VPLO LOCM LOIN COMM
BIAS
AD8342
05352-001
Figure 1.
GENERAL DESCRIPTION
The AD8342 is a high performance, broadband active mixer.
It is well suited for demanding receive-channel applications
that require wide bandwidth on all ports and very low
intermodulation distortion and noise figure.
The AD8342 provides a typical conversion gain of 3.7 dB with
an RF frequency of 238 MHz. The integrated LO driver presents
a 50 Ω input impedance with a low LO drive level, helping to
minimize the external component count.
The differential high impedance broadband RF port allows for
easy interfacing to both active devices and passive filters. The
RF input accepts input signals as large as 1.6 V p-p or 8 dBm
(relative to 50 Ω) at P1dB.
The open-collector differential outputs provide excellent balance
and can be used with a differential filter or IF amplifier, such as
the AD8370, AD8375, AD8351, AD8352, or ADL5561. These
outputs can also be converted to a single-ended signal using a
matching network or a balun transformer. The outputs are
capable of swinging 2 V p-p when biased to the VPOS supply
rail.
The AD8342 is fabricated on an Analog Devices, Inc.,
proprietary, high performance SiGe IC process. The AD8342 is
available in a 16-lead LFCSP. It operates over a −40°C to +85°C
temperature range. An evaluation board is also available.
AD8342
Rev. B | Page 2 of 24
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
AC Performance ........................................................................... 4
Spur Table .......................................................................................... 5
Absolute Maximum Ratings ............................................................ 6
ESD Caution .................................................................................. 6
Pin Configuration and Function Descriptions ............................. 7
Typical Performance Characteristics ..............................................8
Circuit Description......................................................................... 14
AC Interfaces ................................................................................... 15
IF Port .......................................................................................... 16
LO Considerations ..................................................................... 17
High Frequency Applications ................................................... 18
Low Frequency Applications .................................................... 19
Evaluation Board ............................................................................ 21
Outline Dimensions ....................................................................... 24
Ordering Guide .......................................................................... 24
REVISION HISTORY
7/09—Rev. A to Rev. B
Changed RF and LO Frequency Range from 2.4 GHz to
3 GHz Throughout ........................................................................... 1
Changes to General Description Section ...................................... 1
Added Endnote 2 .............................................................................. 4
Added Low Frequency Applications Section .............................. 19
Added Figure 56 and Figure 57..................................................... 20
Changes to the Evaluation Board Section ................................... 21
Added Figure 59 to Figure 62 ........................................................ 22
Updated Outline Dimensions ....................................................... 24
Changes to Ordering Guide .......................................................... 24
1/07—Rev. 0 to Rev. A
Changes to Features .......................................................................... 1
Changes to General Description .................................................... 1
Changes to Table 2 ............................................................................ 4
Replaced the High Frequency Applications Section .................. 18
4/05—Revision 0: Initial Version
AD8342
Rev. B | Page 3 of 24
SPECIFICATIONS
VS = 5 V, TA = 25°C, fRF = 238 MHz, fLO = 286 MHz, LO power = 0 dBm, ZO = 50 Ω, RBIAS = 1.82 kΩ, RF termination = 100 Ω, IF
terminated into 100 Ω through a 2:1 ratio balun, unless otherwise noted.
Table 1.
Parameter Conditions Min Typ Max Unit
RF INPUT INTERFACE
Return Loss High-Z input terminated with 100 Ω off-chip resistor 10 dB
Input Impedance Frequency = 238 MHz (measured at RFIN with RFCM
ac-grounded)
1||0.4 kΩ||pF
DC Bias Level Internally generated; port must be ac-coupled 2.4 V
OUTPUT INTERFACE
Output Impedance Differential impedance, frequency = 48 MHz 10||0.5 kΩ||pF
DC Bias Voltage Supplied externally 4.75 VS 5.25 V
Power Range Via a 2:1 impedance ratio transformer 13 dBm
LO INTERFACE
Return Loss 10 dB
DC Bias Voltage Internally generated; port must be ac-coupled VS − 1.6 V
POWER-DOWN INTERFACE
PWDN Threshold 3.5 V
PWDN Response Time Device enabled, IF output to 90% of its final level 0.4 μs
Device disabled, supply current <5 mA 4 μs
PWDN Input Bias Current Device enabled −80 μA
Device disabled +100 μA
POWER SUPPLY
Positive Supply Voltage 4.75 5 5.25 V
Quiescent Current
VPDC Supply current for bias cells 5 mA
VPMX, IFOP, IFOM Supply current for mixer, RBIAS = 1.82 kΩ 58 mA
VPLO Supply current for LO limiting amplifier 35 mA
Total Quiescent Current VS = 5 V 85 98 113 mA
Power-Down Current Device disabled 500 μA
AD8342
Rev. B | Page 4 of 24
AC PERFORMANCE
VS = 5 V, TA = 25°C, LO power = 0 dBm, ZO = 50 Ω, RBIAS = 1.82 kΩ, RF termination 100 Ω, IF terminated into 100 Ω via a 2:1 ratio balun,
unless otherwise noted.
Table 2.
Parameter Conditions Min Typ Max Unit
RF Frequency Range1 3.0 GHz
LO Frequency Range1 3.0 GHz
IF Frequency Range1, 2 2.4 GHz
Conversion Gain fRF = 460 MHz, fLO = 550 MHz, fIF = 90 MHz 3.2 dB
f
RF = 238 MHz, fLO = 286 MHz, fIF = 48 MHz 3.7 dB
SSB Noise Figure fRF = 460 MHz, fLO = 550 MHz, fIF = 90 MHz 12.5 dB
f
RF = 238 MHz, fLO = 286 MHz, fIF = 48 MHz 12.2 dB
Input Third-Order Intercept fRF1 = 460 MHz, fRF2 = 461 MHz, fLO = 550 MHz,
fIF1 = 90 MHz, fIF2 = 89 MHz, each RF tone −10 dBm
22.2 dBm
fRF1 = 238 MHz, fRF2 = 239 MHz, fLO = 286 MHz,
fIF1 = 48 MHz, fIF2 = 47 MHz, each RF tone −10 dBm
22.7 dBm
Input Second-Order Intercept fRF1 = 460 MHz, fRF2 = 410 MHz, fLO = 550 MHz, fIF1 = 90 MHz,
fIF2 = 140 MHz
50 dBm
fRF1 = 238 MHz, fRF2 = 188 MHz, fLO = 286 MHz, fIF1 = 48 MHz,
fIF2 = 98 MHz
44 dBm
Input 1 dB Compression Point fRF = 460 MHz, fLO = 550 MHz, fIF = 90 MHz 8.5 dBm
f
RF = 238 MHz, fLO = 286 MHz, fIF = 48 MHz 8.3 dBm
LO to IF Output Leakage LO power = 0 dBm, fLO = 286 MHz −27 dBc
LO to RF Input Leakage LO power = 0 dBm, fLO = 286 MHz −55 dBc
2× LO to IF Output Leakage LO power = 0 dBm, fRF = 238 MHz, fLO = 286 MHz
IF terminated into 100 Ω and measured with a differential probe
−47 dBm
RF to IF Output Leakage RF power = −10 dBm, fRF = 238 MHz, fLO = 286 MHz −32 dBc
IF/2 Spurious RF power = −10 dBm, fRF = 238 MHz, fLO = 286 MHz −62 dBc
1 See the section for details. High Frequency Applications
2 See the Low Frequency Applications section for details.
AD8342
Rev. B | Page 5 of 24
SPUR TABLE
VS = 5 V, TA = 25°C, RF and LO power = 0 dBm, fRF = 238 MHz, fLO = 286MHz, ZO = 50 Ω, RBIAS = 1.82 kΩ, RF termination 100 Ω,
IF terminated into 100 Ω via a 2:1 ratio balun.
Note: Measured using standard test board. Typical noise floor of measurement system = −100 dBm.
Table 3.
m
n
nfRF − mfLO 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
0 <−100 −25 −54 −28 −45 −35 −39 −36 −42 −57 −44 −42 −41 −46 −59
1 −32 3.5 −42 −6 −48 −16 −50 −28 −57 −37 −68 −45 −54 −37 −61
2 −52 −47 −51 −49 −54 −56 −56 −62 −62 −66 −71 −80 −80 −67 −79
3 −81 −57 −79 −61 −82 −61 −74 −69 −94 −85 −89 −86 −86 −90 −81
4 −78 −70 −80 −79 −80 −85 −87 −92 −93 −96 −95 <−100 −97 <−100 −95
5 −98 −79 −95 −87 −96 −94 −95 −88 −98 −94 <−100 <−100 <−100 <−100 <−100
6 <−100 <−100 <−100 −99 <−100 −96 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
7 <−100 <−100 <−100 <−100 −96 <−100 −98 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
8 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 −97 <−100 <−100 <−100 <−100 <−100 <−100
9 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 −99 <−100 <−100 <−100
10 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 −99 <−100 <−100 <−100 <−100
11 <−100 <−100 <−100 <−100 <−100 <−100 <−100 −96 <−100 −97 <−100 −96 <−100 <−100 <−100
12 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 −99 <−100 −98 <−100 <−100 <−100 <−100
13 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 −97 <−100 −97 −99 <−100 <−100
14 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 −98 −98 <−100 <−100 <−100
15 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100 <−100
AD8342
Rev. B | Page 6 of 24
ABSOLUTE MAXIMUM RATINGS
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 4.
Parameter Rating
Supply Voltage, VS 5.5 V
RF Input Level 12 dBm
LO Input Level 12 dBm
PWDN Pin VS + 0.5 V
IFOP, IFOM Bias Voltage 5.5 V
Minimum Resistor from EXRB to COMM 1.8 kΩ
Internal Power Dissipation 650 mW
θJA 77°C/W
Maximum Junction Temperature 135°C
Operating Temperature Range −40°C to +85°C
Storage Temperature Range −65°C to +150°C
ESD CAUTION
AD8342
Rev. B | Page 7 of 24
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
0
5352-002
PIN 1
INDICATOR
1VPLO
2LOCM
3LOIN
4COMM
11 PWDN
12 VPDC
10 EXRB
9COMM
5
COMM
6
IFOM
7
IFOP
8
COMM
15 RFIN
16 VPMX
14 RFCM
13 COMM
TOP VIEW
(Not to Scale)
AD8342
Figure 2. 16-Lead LFCSP
Table 5. Pin Function Descriptions
Pin No. Mnemonic Description
1 VPLO Positive Supply Voltage for the LO Buffer: 4.75 V to 5.25 V.
2 LOCM AC Ground for Limiting LO Amplifier. Internally biased to VS − 1.6 V. AC-couple to ground.
3 LOIN
LO Input. Nominal input level: 0 dBm. Input level range: −10 dBm to +4 dBm (relative to 50 Ω). Internally
biased to VS − 1.6 V. Must be ac-coupled.
4, 5, 8, 9, 13 COMM Device Common (DC Ground).
6, 7 IFOM, IFOP Differential IF Outputs (Open Collectors). Each requires dc bias of 5.00 V (nominal).
10 EXRB
Mixer Bias Voltage. Connect resistor from EXRB to ground. Typical value of 1.82 kΩ sets mixer current to
nominal value. Minimum resistor value from EXRB to ground = 1.8 kΩ. Internally biased to 1.17 V.
11 PWDN Connect to Ground for Normal Operation. Connect pin to VS for disable mode.
12 VPDC Positive Supply Voltage for the DC Bias Cell: 4.75 V to 5.25 V.
14 RFCM AC Ground for RF Input. Internally biased to 2.4 V. AC-couple to ground.
15 RFIN RF Input. Internally biased to 2.4 V. Must be ac-coupled.
16 VPMX Positive Supply Voltage for the Mixer: 4.75 V to 5.25 V.
AD8342
Rev. B | Page 8 of 24
TYPICAL PERFORMANCE CHARACTERISTICS
VS = 5 V, TA = 25°C, RF power = −10 dBm, LO power = 0 dBm, ZO = 50 Ω, RBIAS = 1.82 kΩ, RF termination 100 Ω, IF terminated into
100 Ω via a 2:1 ratio balun, unless otherwise noted.
05352-004
RF FREQUENCY (MHz)
GAIN (dB)
IF = 10MHz
50 550100 150 200 250 300 350 400 450 500
IF = 90MHz
6
5
4
3
2
1
IF = 48MHz
IF = 140MHz
Figure 3. Conversion Gain vs. RF Frequency
5
0
05352-025
LO LEVEL (dBm)
GAIN (dB)
–15 –10 –5 0 5
IF = 48MHz
IF = 90MHz
IF = 140MHz
4
3
2
1
IF = 10MHz
Figure 4. Gain vs. LO Level, RF Frequency = 238 MHz
5.0
0
05352-039
TEMPERATURE (°C)
GAIN (dB)
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
–200 20406080
–40
Figure 5. Gain vs. Temperature, fRF = 238 MHz, fLO = 286 MHz
5
1
05352-005
IF FREQUENCY (MHz)
GAIN (dB)
6
4
3
2
5010 100 150 200 250 300 350
RF = 238MHz
RF = 460MHz
Figure 6. Conversion Gain vs. IF Frequency
5.0
0
05352-026
VPOS (V)
GAIN (dB)
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
4.75 5.254.85 4.95 5.05 5.15
Figure 7. Gain vs. VPOS, fRF = 238 MHz, fLO = 286 MHz
50
0
3.40 3.90
05352-054
CONVERSION GAIN (238MHz)
PERCENTAGE
45
40
35
30
25
20
15
10
5
3.45 3.50 3.55 3.60 3.65 3.70 3.75 3.80 3.85
NORMAL MEAN = 3.7
STD. DEV. = 0.06
Figure 8. Conversion Gain Distribution, fRF = 238 MHz, fLO = 286 MHz
AD8342
Rev. B | Page 9 of 24
27
17
50 550
05352-007
RF FREQUENCY (MHz)
INPUT IP3 (dBm)
100 150 200 250 300 350 400 450 500
26
25
24
23
22
21
20
19
18
IF = 10MHz
IF = 140MHz
IF = 90MHz
IF = 48MHz
Figure 9. Input IP3 vs. RF Frequency
27
17
–15 5
05352-027
LO LEVEL (dBm)
INPUT IP3 (dBm)
26
25
24
23
22
21
20
19
18
–13–11–9–7–5–3–1 1 3
IF = 10MHz
IF = 48MHz
IF = 90MHz 140MHz
Figure 10. Input IP3 vs. LO Level, fRF1 = 238 MHz, fRF2 = 239 MHz
27
17
05352-032
TEMPERATURE (°C)
INPUT IP3 (dBm)
–200 20406080
–40
26
25
24
23
22
21
20
19
18
Figure 11. Input IP3 vs. Temperature, fRF1 = 238 MHz, fRF2 = 239 MHz,
fLO = 286 MHz
27
17
10
05352-008
IF FREQUENCY (MHz)
INPUT IP3 (dBm)
350
26
25
24
23
22
21
20
19
18
50 100 150 200 250 300
RF = 460MHz
RF = 238MHz
Figure 12. Input IP3 vs. IF Frequency
05352-028
VPOS (V)
INPUT IP3 (dBm)
27
17
4.75 5.25
26
25
24
23
22
21
20
19
18
4.80 4.85 4.90 4.95 5.00 5.05 5.10 5.15 5.20
Figure 13. Input IP3 vs. VPOS, fRF = 238 MHz, fRF2 = 239 MHz
LO Frequency = 286 MHz
20
0
20.6
05352-055
INPUT IP3 (238MHz)
PERCENTAGE
18
16
14
12
10
8
6
4
2
21.0 21.4 21.8 22.2 22.6 23.0 23.4 23.8 24.2
NORMAL MEAN = 22.7
STD. DEV. = 0.41
Figure 14. Input IP3 Distribution, fRF = 238 MHz, fLO = 286 MHz
AD8342
Rev. B | Page 10 of 24
13
3
50 550
05352-013
RF FREQUENCY (MHz)
INPUT P1dB (dBm)
12
11
10
9
8
7
6
5
4
100 150 200 250 300 350 400 450 500
10MHz
140MHz
48MHz
90MHz
Figure 15. Input P1dB vs. RF Frequency
10.0
5.0
–15 5
05352-038
LO LEVEL (dBm)
INPUT P1dB (dBm)
9.5
9.0
8.5
8.0
7.5
7.0
6.5
6.0
5.5
–13–11–9–7–5–3–1 1 3
IF = 10MHz
IF = 48MHz
IF = 90MHz
IF = 140MHz
Figure 16. Input P1dB vs. LO Level, fRF = 238 MHz
10
0
05352-033
TEMPERATURE (°C)
INPUT P1dB (dBm)
9
8
7
6
5
4
3
2
1
–200 20406080
–40
Figure 17. Input P1dB vs. Temperature, fRF = 238 MHz, fLO = 286 MHz
10
0
10
05352-014
IF FREQUENCY (MHz)
INPUT P1dB (dBm)
9
8
7
6
5
4
3
2
1
50 100 150 200 250 300 350
RF = 460MHz
RF = 238MHz
Figure 18. Input P1dB vs. IF Frequency
05352-031
INPUT P1dB (dBm)
10
0
9
8
7
6
5
4
3
2
1
VPOS (V)
4.75 5.254.85 4.95 5.05 5.15
Figure 19. Input P1dB vs. VPOS, fRF = 238 MHz,
fLO = 286 MHz
28
0
8.00
05352-056
IP1dB (238MHz)
PERCENTAGE
8.60
26
24
22
20
18
16
14
12
10
8
6
4
2
8.05 8.10 8.15 8.20 8.25 8.30 8.35 8.40 8.45 8.50 8.55
NORMAL MEAN = 8.3
STD. DEV. = 0.07
Figure 20. Input IP3 Distribution, fRF = 238 MHz, fLO = 286 MHz
AD8342
Rev. B | Page 11 of 24
60
0
100 550
05352-010
RF FREQUENCY (MHz)
INPUT IP2 (dBm)
50
40
30
20
10
IF = 10MHz
IF = 140MHz
IF = 90MHz
IF = 48MHz
150 200 250 300 350 400 450 500
Figure 21. Input IP2 vs. RF Frequency (Second RF = RF − 50 MHz)
60
40
05352-029
INPUT IP2 (dBm)
58
56
54
52
50
48
46
44
42
–15 5
LO LEVEL (dBm)
–13 –11 –9 –7 –5 –3 –1 1 3
IF = 10MHz IF = 48MHz
IF = 90MHz
IF = 140MHz
Figure 22. Input IP2 vs. LO Level, fRF = 238 MHz, fRF2 = 188 MHz
14.0
11.0
50 550
05352-016
RF FREQUENCY (MHz)
NOISE FIGURE (dB)
13.5
13.0
12.5
12.0
11.5
100 150 200 250 300 350 400 450 500
Figure 23. Noise Figure vs. RF Frequency, IF Frequency = 48 MHz
60
0
10
05352-011
IF FREQUENCY (MHz)
INPUT IP2 (dBm)
50
40
30
20
10
50 100 150 200 250 300 350
RF = 238MHz RF = 460MHz
Figure 24. Input IP2 vs. IF Frequency (Second RF = RF − 50 MHz)
05352-030
INPUT IP2 (dBm)
60
40
58
56
54
52
50
48
46
44
42
VPOS (V)
4.75 5.254.85 4.95 5.05 5.15
Figure 25. Input IP2 vs. VPOS, fRF1 = 238 MHz,
fRF2 = 188 MHz, fLO = 286 MHz
16
0
10
05352-017
IF FREQUENCY (MHz)
NOISE FIGURE (dB)
14
12
10
8
6
4
2
60 110 160 210 260 310
RF = 460MHz
RF = 238MHz
Figure 26. Noise Figure vs. IF Frequency
AD8342
Rev. B | Page 12 of 24
16
10
–15 5
05352-018
LO POWER (dBm)
NF (dB)
15
14
13
12
11
–13–11–9–7–5–3–1 1 3
NF = 10MHz
NF = 48MHz
NF = 90MHz
NF = 140MHz
Figure 27. Noise Figure vs. LO Power, fRF = 238 MHz
5.0
0
1.8
05352-024
R
BIAS
(kΩ)
GAIN (dB)
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4
Figure 28. Gain vs. RBIAS, RF Frequency = 238 MHz, LO Frequency = 286 MHz
61
45
1.8
05352-037
R
BIAS
(kΩ)
INPUT IP2 (dBm)
2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4
59
57
55
53
51
49
47
Figure 29. Input IP2 vs. RBIAS, fRF = 238 MHz (Second RF = RF – 50 MHz),
fLO = 286 MHz
30
0
11.8 12.8
05352-023
NOISE FIGURE (dB)
PERCENTAGE
25
20
15
10
5
11.9 12.0 12.1 12.2 12.3 12.4 12.5 12.6 12.7
NORMAL MEAN = 12.25
STD. DEV. = 0.14
Figure 30. Noise Figure Distribution, fRF = 238 MHz, fLO = 286 MHz
30
0
1.8 3.0
05352-015
R
BIAS
(kΩ)
NOISE FIGURE AND INPUT IP3 (dBm)
25
20
15
10
5
2.0 2.2 2.4 2.6 2.8
105
75
100
95
90
85
80
SUPPLY CURRENT (mA)
INPUT IP3
NOISE FIGURE
CURRENT
Figure 31. Noise Figure, Input IP3, and Supply Current vs. RBIAS,
fRF1 = 238 MHz, fRF2 = 239 MHz, fLO = 286 MHz
10
0
1.8
05352-036
R
BIAS
(kΩ)
INPUT P1dB (dBm)
9
8
7
6
5
4
3
2
1
2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4
Figure 32. Input P1dB vs. RBIAS, fRF = 238 MHz, fLO = 286 MHz
AD8342
Rev. B | Page 13 of 24
0
–90
50
05352-021
LO FREQUENCY (MHz)
LEAKAGE (dBc)
–10
–20
–30
–40
–50
–60
–70
–80
250 450 650 850
Figure 33. LO to RF Leakage vs. LO Frequency, LO Power = 0 dBm
0
–45
50 550
05352-035
RF FREQUENCY (MHz)
FEEDTHROUGH (dBc)
–5
–10
–15
–20
–25
–30
–35
–40
100 150 200 250 300 350 400 450 500
IF = 10MHz
IF = 48MHz
Figure 34. RF to IF Feedthrough, RF Power = −10 dBm
0
–45
50 850
05352-020
LO FREQUENCY (MHz)
FEEDTHROUGH (dBc)
–5
–10
–15
–20
–25
–30
–35
–40
150 250 350 450 550 650 750
Figure 35. LO to IF Feedthrough vs. LO Frequency, LO Power = 0 dBm
120
0
05352-034
TEMPERATURE (°C)
SUPPLY CURRENT (mA)
–200 20406080
–40
100
80
60
40
20
Figure 36. Supply Current vs. Temperature
0
–18
60 860
05352-059
LO FREQUENCY (MHz)
RETURN LOSS (dB)
–2
–4
–6
–8
–10
–12
–14
–16
160 260 360 460 560 660 760
Figure 37. LO Return Loss vs. LO Frequency
8
7
6
13
15
16
COMM
IFOP
IFOM
5
COMM
14
21 34
COMM
RFCM
RFIN
VPMX
VPDC PWDN EXRB COMM
1112 10 9
VPLO LOCM LOIN COMM
AD8342
RF IN
1nF
100pF0.1µF
100pF0.1µF
V
POS
1nF 1nF
LO IN
TC2-1T
IF OUT
(50Ω)
100pF 0.1µF
VPOS
1nF
100Ω
1.82kΩ
100pF
VPOS
100pF0.1µF
05352-058
Figure 38. Characterization Circuit Used to Measure Typical Performance
Characteristics Data
AD8342
Rev. B | Page 14 of 24
CIRCUIT DESCRIPTION
The AD8342 is an active mixer, optimized for operation within
the input frequency range of near dc to 2.4 GHz. It has a
differential, high impedance RF input that can be terminated or
matched externally. The RF input can be driven either single-
ended or differentially. The LO input is a single-ended 50 Ω
input. The IF outputs are differential open-collectors. The mixer
current can be adjusted by the value of an external resistor to
optimize performance for gain, compression, and intermodula-
tion, or for low power operation. Figure 39 shows the basic
blocks of the mixer, including the LO buffer, RF voltage-to-
current converter, bias cell, and mixing core.
The RF voltage to RF current conversion is done via a resistively
degenerated differential pair. To drive this port single-ended,
the RFCM pin should be ac-grounded while the RFIN pin is ac-
coupled to the signal source. The RF inputs can also be driven
differentially. The voltage-to-current converter then drives the
emitters of a four-transistor switching core. This switching core
is driven by an amplified version of the local oscillator signal
connected to the LO input. There are three limiting gain stages
between the external LO signal and the switching core. The first
stage converts the single-ended LO drive to a well-balanced
differential drive. The differential drive then passes through two
more gain stages, which ensures that a limited signal drives the
switching core. This affords the user a lower LO drive
requirement, while maintaining excellent distortion and
compression performance. The output signal of these three LO
gain stages drives the four transistors within the mixer core to
commutate at the rate of the local oscillator frequency. The
output of the mixer core is taken directly from its open
collectors. The open-collector outputs present a high
impedance at the IF frequency. The conversion gain of the
mixer depends directly on the impedance presented to these
open collectors. In characterization, a 100 Ω load was presented
to the part via a 2:1 impedance transformer.
The device also features a power-down function. Application of
a logic low at the PWDN pin allows normal operation. A high
logic level at the PWDN pin shuts down the AD8342. Power
consumption when the part is disabled is less than 10 mW.
The bias for the mixer is set with an external resistor (RBIAS)
from the EXRB pin to ground. The value of this resistor directly
affects the dynamic range of the mixer. The external resistor
should not be lower than 1.82 kΩ. Permanent damage to the
part can result if values below 1.8 kΩ are used. This resistor sets
the dc current through the mixer core. The performance effects
of changing this resistor can be seen in the Typical Performance
Characteristics section.
0
5352-040
LO
INPUT
VPLO
IFOP
IFOM
RFIN
RFCM
BIAS
EXTERN
A
L
BIAS
RESISTORVPDC PWDN
V
TO
I
Figure 39. Simplified Schematic Showing the Key Elements of the AD8342
As shown in Figure 40, the IF output pins, IFOP and IFOM, are
directly connected to the open collectors of the NPN transistors
in the mixer core so the differential and single-ended
impedances looking into this port are relatively high, on the
order of several k. A connection between the supply voltage
and these output pins is required for proper mixer core
operation.
05352-041
IFOP IFOM
LOIN
RFCMRFIN
COMM
Figure 40. AD8342 Simplified Schematic
The AD8342 has three pins for the supply voltage: VPDC,
VPMX, and VPLO. These pins are separated to minimize or
eliminate possible parasitic coupling paths within the AD8342
that could cause spurious signals or reduced interport isolation.
Consequently, each of these pins should be well bypassed and
decoupled as close to the AD8342 as possible.
AD8342
Rev. B | Page 15 of 24
AC INTERFACES
The AD8342 is designed to downconvert radio frequencies (RF)
to lower intermediate frequencies (IF) using a high- or low-side
local oscillator (LO). The LO is injected into the mixer core at
a frequency higher or lower than the desired input RF. The
frequency difference between the LO and the RF, fLO − fRF (high
side) or fRF − fLO (low side), is the intermediate frequency, fIF. In
addition to the desired RF signal, an RF image is downconverted
to the desired IF frequency. The image frequency is at fLO + fIF
when driven with a high-side LO. When using a broadband
load, the conversion gain of the AD8342 is nearly constant over
the specified RF input band (see Figure 3).
The AD8342 is designed to operate over a broad frequency
range. It is essential to ac couple RF and LO ports to prevent
dc offsets from skewing the mixer core in an asymmetrical
manner, potentially degrading noise figure and linearity.
The RF input of the AD8342 is high impedance, 1 kΩ across the
frequency range shown in Figure 41. The input capacitance
decreases with frequency due to package parasitics.
2.00 1.00
00
01G
05352-042
FREQUENCY (Hz)
RESISTANCE (kΩ)
CAPACITANCE (pF)
1.75
1.50 0.75
1.25
1.00 0.50
0.75
0.50 0.25
0.25
100M 200M 300M 400M 500M 600M 700M 800M 900M
Figure 41. RF Input Impedance
The matching or termination used at the RF input of the
AD8342 has a direct effect on its dynamic range. The
characterization circuit, as well as the evaluation board, uses a
100 Ω resistor to terminate the RF port. This termination
resistor in shunt with the input stage results in a return loss of
better than −10 dBm (relative to 50 Ω). Table 6 shows gain, IP3,
P1dB, and noise figure for four different input networks. This
data was measured at an RF frequency of 250 MHz and at an
LO frequency of 300 MHz.
Table 6. Dynamic Performance for Various Input Networks
Input
Network
50 Ω
Shunt
100 Ω
Shunt
500 Ω
Shunt
Matched
(Figure 42)
Gain (dB) 0.66 3.5 5.3 9.3
IIP3 (dBm) 25.4 22.9 20. 6 18.5
P1dB (dBm) 10.8 8.4 6.3 2.3
NF (dB) 14 12.5 10.2 10.5
The RF port can also be matched using an LC circuit, as shown
in Figure 42.
0
5352-043
Z
L
1kΩ
Z
O
= 50Ω
f
MAIN
= 250MHz
50Ω
3.6pF
100nH (1000 + j0) Ω
Figure 42. Matching Circuit
Impedance transformations of greater than 10:1 result in a
higher Q circuit and thus a narrow RF input bandwidth. A 1 kΩ
resistor is placed across the RF input of the device in parallel
with the device internal input impedance, creating a 500 Ω load.
This impedance is matched to as close as possible to 50 Ω for
the source, with standard components using a shunt C, series L
matching circuit (see Figure 43).
05352-044
25
10
10
25
50
100
200
500
500
200
100
50
Q = 3
12
3
4
POINT 1(1000 + j0) Ω
POINT 2(500 + j0) Ω
POINT 3(55.6 – j157.2) Ω
POINT 4(55.6 – j0.1) Ω
Figure 43. LC Matching Example
AD8342
Rev. B | Page 16 of 24
IF PORT
The IF port comprises open-collector differential outputs. The
NPN open collectors can be modeled as current sources that are
shunted with resistances of ~10 kΩ in parallel with capacitances
of ~1 pF.
The specified performance numbers for the AD8342 were
measured with 100 Ω differential terminations. However,
different load impedances can be used where circumstances
dictate. In general, lower load impedances result in lower
conversion gain and lower output P1dB. Higher load imped-
ances result in higher conversion gain for small signals, but
lower IP3 values for both input and output.
If the IF signal is to be delivered to a remote load, more than a
few millimeters away at high output frequencies, avoid
unintended parasitic effects due to the intervening PCB traces.
One approach is to use an impedance transforming network or
transformer located close to the AD8342. If very wideband
output is desired, a nearby buffer amplifier may be a better
choice, especially if IF response to dc is required. An example of
such a circuit is presented in Figure 45, in which the AD8351
differential amplifier is used to drive a pair of 75 Ω transmission
lines. The gain of the buffer can be independently set by
appropriate choice of the value for the gain resistor, RG.
50 0.5
0
01G
05352-045
FREQUENCY (Hz)
RESISTANCE (kΩ)
CAPACITANCE (pF)
45
0.4
40
0.3
35
0.2
30
0.1
25
0
20
–0.1
15
–0.2
10
5
100M 200M 300M 400M 500M 600M 700M 800M 900M
Figure 44. IF Port Impedance
05352-046
COMM
8
IFOP
7
IFOM
6
COMM
5
AD8342
AD8351
+
–
RFC
+V
S
RFC
Z
L
= 100Ω
+V
S
+V
S
100ΩR
G
Z
L
Tx LINE Z
O
= 75Ω
Tx LINE Z
O
= 75Ω
Figure 45. AD8351 Used as Transmission Line Driver and Impedance Buffer
The high input impedance of the AD8351 allows for a shunt
differential termination to provide the desired 100 Ω load to the
AD8342 IF output port.
It is necessary to bias the open-collector outputs using one of
the schemes presented in Figure 47 and Figure 48. Figure 47
illustrates the application of a center-tapped impedance
transformer. The turns ratio of the transformer should be
selected to provide the desired impedance transformation. In
the case of a 50 Ω load impedance, a 2-to-1 impedance ratio
transformer should be used to transform the 50 Ω load into a
100 Ω differential load at the IF output pins. Figure 48
illustrates a differential IF interface where pull-up choke
inductors are used to bias the open-collector outputs. The
shunting impedance of the choke inductors used to couple dc
current into the mixer core should be large enough at the IF
operating frequency so it does not load down the output current
before reaching the intended load. Additionally, the dc current
handling capability of the selected choke inductors needs to be
at least 45 mA. The self-resonant frequency of the selected
choke should be higher than the intended IF frequency. A
variety of suitable choke inductors is commercially available
from manufacturers such as Murata and Coilcraft®. Figure 46
shows the loading effects when using nonideal inductors. An
impedance transforming network may be required to transform
the final load impedance to 100 Ω at the IF outputs. There are
several good reference books that explain general impedance
matching procedures, including:
• Chris Bowick, RF Circuit Design, Newnes, Reprint Edition,
1997.
• David M. Pozar, Microwave Engineering, Wiley,
3rd Edition, 2004.
• Guillermo Gonzalez, Microwave Transistor Amplifiers:
Analysis and Design, Prentice Hall, Second Edition, 1996.
05352-049
0180
30
330
50MHz
50MHz
500MHz
500MHz
60
90
270
300
120
240
150
210
REAL
CHOKES
IDEAL
CHOKES
Figure 46. IF Port Loading Effects Due to Finite Q Pull-Up Inductors
(Murata BLM18HD601SN1D Chokes)
AD8342
Rev. B | Page 17 of 24
05352-047
COMM
8
IFOP
7
IFOM
6
COMM
5
AD8342
Z
L
= 100Ω
IF OUT
Z
O
= 50Ω
+V
S
2:1
Figure 47. Biasing the IF Port Open-Collector Outputs
Using a Center-Tapped Impedance Transformer
05352-048
COMM
8
IFOP
7
IFOM
6
COMM
5
AD8342
RFC
+V
S
RFC
Z
L
= 100Ω
IF OUT+
IF OUT–
+V
S
Z
L
IMPEDANCE
TRANSFORMING
NETWORK
Figure 48. Biasing the IF Port Open-Collector Outputs
Using Pull-Up Choke Inductors
The AD8342 is optimized for driving a 100 Ω load. Although
the device is capable of driving a wide variety of loads, to
maintain optimum distortion and noise performance, it is
advised that the presented load at the IF outputs is close to
100 Ω. The linear differential voltage conversion gain of the
mixer can be modeled as
LOAD
m
VRGA ×=
where:
em
m
mRg
g
G+
×
π
=
1
1
RLOAD is the single-ended load impedance.
gm is the transistor transconductance and is equal to 1810/RBIAS.
Re = 15 Ω.
The external RBIAS resistor is used to control the power
dissipation and dynamic range of the AD8342. Because the
AD8342 has internal resistive degeneration, the conversion gain
is primarily determined by the load impedance and the on-chip
degeneration resistors. Figure 49 shows how gain varies with IF
load. The external RBIAS resistor has only a small effect. The
most direct way to affect conversion gain is by varying the load
impedance. Small loads result in lower gains while larger loads
increase the conversion gain. If the IF load impedance is too
large, it causes a decrease in linearity (P1dB, IP3). In order to
maintain positive conversion gain and preserve SFDR
performance, the differential load presented at the IF port
should remain in the range of about 100 Ω to 250 Ω.
30
0
10 1000
05352-057
IF LOAD (Ω)
VOLTAGE GAIN (dB)
100
25
20
15
10
5
MEASURED
MODELED
Figure 49. Voltage Conversion Gain vs. IF Loading
LO CONSIDERATIONS
The LOIN port provides a 50 Ω load impedance with common-
mode decoupling on LOCM. Again, common-grade ceramic
capacitors provide sufficient signal coupling and bypassing of
the LO interface.
The LO signal needs to have adequate phase noise characteristics
and low second-harmonic content to prevent degradation of the
noise figure performance of the AD8342. An LO plagued with
poor phase noise can result in reciprocal mixing, a mechanism
that causes spectral spreading of the downconverted signal,
limiting the sensitivity of the mixer at frequencies adjacent to
any large input signals. The internal LO buffer provides enough
gain to hard-limit the input LO and provide fast switching of
the mixer core. Odd harmonic content present on the LO drive
signal should not impact mixer performance; however, even-
order harmonics cause the mixer core to commutate in an
unbalanced manner, potentially degrading noise performance.
Simple lumped element low-pass filtering can be applied to help
reject the harmonic content of a given local oscillator, as shown
in Figure 50. The filter depicted is a common 3-pole Chebyshev,
designed to maintain a 1-to-1 source-to-load impedance ratio
with no more than 0.5 dB of ripple in the pass band. Other filter
structures can be effective as long as the second harmonic of the
LO is filtered to negligible levels, for example, ~30 dB below the
fundamental.
05352-050
AD8342
LOIN
3
COMM
4
LOCM
2
R
L
FOR R
S
= R
L
f
C
- FILTER CUTOFF FREQUENCY
R
S
C1 C3
LO
SOURCE
L2
C1 = 1.864
2π
f
cR
L
C3 = 1.834
2π
f
cR
L
L2 = 1.28R
L
2π
f
c
Figure 50. Using a Low-Pass Filter to Reduce LO Second Harmonic
AD8342
Rev. B | Page 18 of 24
HIGH FREQUENCY APPLICATIONS
The AD8342 is a broadband mixer capable of both up and
down conversion. Unlike other mixers that rely on on-chip
reactive circuitry to optimize performance over a specific band,
the AD8342 is a versatile general-purpose device that can be
used from arbitrarily low frequencies to several GHz. In
general, the following considerations help to ensure optimum
performance:
• Minimize ac loading impedance of IF port bias network.
• Maximize power transfer to the desired ac load.
• For maximum conversion gain and the lowest noise
performance, reactively match the input as described in the
IF Port section.
• For maximum input compression point and input intercept
points, resistively terminate the input as described in the
IF Port section.
As an example, Figure 51 shows the AD8342 as an up-
converting mixer for a W-CDMA single-carrier transmitter
design. For this application, it was desirable to achieve −65 dBc
adjacent channel power ratio (ACPR) at a −13 dBm output
power level. The ACPR is a measure of both distortion and
noise carried into an adjacent frequency channel due to the
finite intercept points and noise figure of an active device.
8
7
6
13
15
16
COMM
IFOP
IFOM
5
COMM
14
2
134
COMM
RFCM
RFIN
VPMX
VPDC PWDN EXRB COMM
11
12 10 9
VPLO LOCM LOIN COMM
AD8342
05352-052
VPOS
VPOS
34nH
34nH
100pF
100pF
1nF
1nF
ETC1-1-13
100pF
100pF0.1µF
VPOS
1nF
1nF
1970MHz
OSC
1.82kΩ
100pF
4.7pF
170MHz
INPUT
100nH
1nF
499Ω
VPOS
100pF0.1pF
2140MHz OUT
1nF
Figure 51. W-CDMA Tx Up-Conversion Application Circuit
Because a W-CDMA channel encompasses a bandwidth of
almost 5 MHz, it is necessary to keep the Q of the matching
circuit low enough so that phase and magnitude variations are
below an acceptable level over the 5 MHz band. It is possible
to use purely reactive matching to transform a 50 Ω source
to match the raw ~1 kΩ input impedance of the AD8342.
However, the L and C component variations could present
production concerns due to the sensitivity of the match. For
this application, it is advantageous to shunt down the ~1 kΩ
input impedance using an external shunt termination resistor
to allow for a lower Q reactive matching network. The input is
terminated across the RFIN and RFCM pins using a 499 Ω
termination. The termination should be as close to the device as
possible to minimize standing wave concerns. The RFCM is
bypassed to ground using a 1 nF capacitor. A dc blocking
capacitor of 1 nF is used to isolate the dc input voltage present
on the RFIN pin from the source. A step-up impedance
transformation is realized using a series L shunt C reactive
network. The actual values used need to accommodate for the
series L and stray C parasitics of the connecting transmission
line segments. When using the customer evaluation board with
the components specified in Figure 51, the return loss over a
5 MHz band centered at 170 MHz was better than 10 dB.
External pull-up choke inductors are used to feed dc bias into
the open-collector outputs. It is desirable to select pull-up choke
inductors that present high loading reactance at the output
frequency. Coilcraft 0302CS series inductors were selected due
to their very high self-resonant frequency and Q. A 1:1 balun
was ac-coupled to the output to convert the differential output
to a single-ended signal and present the output with a 50-Ω ac
loading impedance.
The performance of the circuit is shown in Figure 52. The
average ACPR of the adjacent and alternate channels is
presented vs. output power. The circuit provides a 65 dBc ACPR
at −13 dBm output power. The optimum ACPR power level can
be shifted to the right or left by adjusting the output loading
and the loss of the input match.
–
60
–70
–25 0
05352-053
OUTPUT POWER (dBm)
ACPR (dBc)
–62
–64
–66
–68
–20 –15 –10 –5
ADJACENT
CHANNELS
ALTERNATE
CHANNELS
Figure 52. Single Carrier W-CDMA ACPR Performance of Tx
Up-Conversion Circuit (Test Model 1_64)
AD8342
Rev. B | Page 19 of 24
The available frequency range of the AD8342 is extremely
broad. With adequate care, any of the mixer ports can be
optimized for extremely low frequencies, or up to several GHz.
The standard evaluation board is populated for broadband
performance from a few MHz to ~1GHz. The input match of
the RF port degrades at higher frequencies when using the
standard eval board. The broadband frequency range can be
extended by minimizing parasitics between the input
terminating resistor, R5, and the input pins.
8
7
6
13
15
16
COMM
IFOP
IFOM
5
COMM
14
21 34
COMM
RFCM
RFIN
VPMX
VPDC PWDN EXRB COMM
1112 10 9
VPLO LOCM LOIN COMM
AD8342
VPOS
1000pF
1000pF0.1µF
VPOS
1nF
1nF
LO IN
1.82kΩ
100pF
RF IN
1nF
100Ω
VPOS
1000pF0.1µF
1nF
0.1µF
100pF
IF OUT
(190MHz)
TC2-1T
0.1µF
NOTES
1. INPUT TERMINATION PLACED AS CLOSE AS POSSIBLE TO RFIN AND RFCM INPUTS.
05352-060
Figure 53. Modified Evaluation Board Schematic for Broadband
Down-Conversion Performance up to 3 GHz
The measurements in Figure 54 were made using the modified
evaluation board as configured in Figure 53.
30
0
500 3000
NF, GAIN, OIP3, IP1dB (dB, dBm)
RF FREQUENCY (MHz)
05352-061
25
20
15
10
5
1000 1500 2000 2500
NF
GAIN
OIP3
IP1dB
Figure 54. Input OIP3, IP1dB, Gain and NF vs. RF Frequency for a 190 MHz IF
Using a Low-Side LO.
The broadband frequency capabilities of the AD8342 makes it
an attractive solution for a variety of applications, including
cellular, CATV, point-to-point radio links, and test equipment.
As an example, the circuit depicted in Figure 53 can easily be
applied as a feedback mixer in a predistortion receiver design.
The performance depicted in Figure 55 was measured using a
160 MHz IF. Here, four W-CDMA carriers with high PAR are
down-converted for IF sampling so that transmit path
nonlinearities can be measured and minimized using digital
predistortion techniques.
–30
CENTER 160MHz SPAN 40.6MHz
–50
–40
–70
–60
–90
–80
–110
–100
–120
4.06MHz
POS –22.564dBm
REF –22.6dBm ATT 5dB
RBW 30kHz
VBW 300kHz
SWT 4s
STANDARD: W-CDMA 3GPP FWD
Tx CHANNELS
CH1 (REF) –20.65dBm
CH2 –20.29dBm
CH3 –20.25dBm
CH4 –20.29dBm
TOTAL –14.35dBm
ADJACENT CHANNE L
LOWER –61.36dB
UPPER –60.84dB
ALTERNATE CHANNEL
LOWER –61.94dB
UPPER –61.72dB
05352-062
Figure 55. ACPR Performance for Multiple W-CDMA Carriers Being Down-
Converted from 2140 MHz to 160 MHz for Distortion Analysis
LOW FREQUENCY APPLICATIONS
The AD8342 can be used in extremely low frequency appli-
cations. Figure 56 depicts the configuration with necessary
modifications at IF ports. Two 10 resistors are used to bias
the open collector outputs, and the output coupling capacitors
need to be large enough to allow intended low frequency
operation. Figure 57 illustrates the gain performance at fixed
IF of 10 kHz and 1 MHz for broadband down-conversion using
low-side LO.
AD8342
Rev. B | Page 20 of 24
13
12 11 10 9
1 2 3 4
14
15
16
8
7
6
5
COMM
1nF
1nF 1nF
LO IN
0.1µF
1N4148
+5
V
+5V
+5V
100pF
100pF
1.82kΩ
0.1µF 100pF
0.1µF 100pF
1nF
RF IN
100Ω
10Ω
10Ω
10µF
10µF
VPDC
PWDN
EXRB
COMM
VPLO
LOCM
LOIN
COMM
RFCM
AD8342
RFIN
VPMX
COMM
IFOP
IFOM BALANCED
OUTPUT
COMM
05352-101
0
5
10
15
20
0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 2.5 2.7
CONVERSION GAIN (dB)
RF FREQUENCY (GHz)
IF = 1MHz
IF = 10 kH z
05352-102
Figure 57. Gain Performance for 1 MHz and 10 kHz IF of Broadband Down-
Conversion
Figure 56. Modified Evaluation Board Schematic for Down-Converting
Broadband RF to Low IF Frequencies.
AD8342
Rev. B | Page 21 of 24
EVALUATION BOARD
An evaluation board is available for the AD8342. The evaluation board is configured for single-ended signaling at the IF output port via a
balun transformer. The schematic for the evaluation board is presented in Figure 58. The representations of the board layout are included
in Figure 59 through Figure 62.
R2
0Ω
R1
0Ω
C6
1000pF
C4
1000pF
C1
1000pF
C3
1000pF
C5
0.1µF
C2
0.1µF
VPOS
RF_IN
C7
1000pF
INLO
C8
1000pF
C9
0.1µF
C10
100pF
VPOS
R11
0Ω
R16
0Ω
R10
0Ω
R12
OPEN
Z4
OPEN
R4
OPEN
34
16
2
TC2-1T
Z2
OPEN R3
OPEN
100Ω TRACES,
NO GROUND PLANE
IF_OUT+
IF_OUT–
R15
0Ω
T1
Z1
OPEN
Z3
OPEN
R5
100Ω
C14
OPEN
L1
0Ω
COMM
IFOP
IFOM
COMM
COMM
RFCM
RFIN
VPMX
VPDC PWDN EXRB COMM
VPLO LOCM LOIN COMM
DUT
12 11 10 9
13
14
15
16
1234
8
7
6
5
R6
1.82kΩ
C11
100pF
R7
0ΩC13
100pF
C12
0.1µF
VPOSGND
PWDN
VPOS
W1
R8
10kΩ
R9
0Ω
PWDN
05352-003
50Ω
TRACE
Figure 58. Evaluation Board
Table 7. Evaluation Board Configuration Options
Component Description Default Conditions
R1, R2, R7,
C2, C4, C5, C6, C9,
C10, C12, C13
Supply decoupling. Shorts or power supply decoupling resistors and filter
capacitors.
R1, R2, R7 = 0 Ω
C4, C6 = 1000 pF
C10, C13 = 100 pF
C2, C5, C9, C12 = 0.1 μF
R3, R4 Options for single-ended IF output circuit. R3, R4 = Open
R6, C11 RBIAS resistor that sets the bias current for the mixer core. The capacitor
provides ac bypass for R6.
R6 = 1.82 kΩ
C11 = 100 pF
R8 Pull down for the PWDN pin. R8 = 10 kΩ
R9 Link to PWDN pin. R9 = 0 Ω
C3, R5, C14, L1 RF input. C3 provides dc block for RF input. R5 provides a resistive input
termination. C16 and L1 are provided for reactive matching of the input.
C3 = 1000 pF
R5 = 100 Ω
C14 = Open
L1 = 0 Ω
C1 RF common ac coupling. Provides dc block for RF input common
connection.
C1 = 1000 pF
C8 LO input ac coupling. Provides dc block for the LO input. C8 = 1000 pF
C7 LO common ac coupling. Provides dc block for LO input common
connection.
C7 = 1000 pF
W1 Power down. The part is on when the PWDN is connected to ground via a
10 kΩ resistor. The part is disabled when PWDN is connected to the positive
supply (VS) via W1.
T1, R10, R11, R12,
R15, R16, Z3, Z4,
Z1, Z2,
IF output interface. T1 converts a differential high impedance IF output to
single-ended. When loaded with 50 Ω, this balun presents a 100 Ω load to
the mixers collectors. The center tap of the primary is used to supply the
bias voltage (VS) to the IF output pins.
T1 = TC2-1T, 2:1 (Mini-Circuits®)
R12 = Open
R10, R11, R15, R16 = 0 Ω
Z3, Z4 = Open
Z1, Z2 = Open
AD8342
Rev. B | Page 22 of 24
05352-104
Figure 59. Evaluation Board Artwork Top
05352-105
Figure 60. Evaluation Board Artwork Internal 1
AD8342
Rev. B | Page 23 of 24
05352-106
Figure 61. Evaluation Board Artwork Internal 2
05352-107
Figure 62. Evaluation Board Artwork Bottom
AD8342
Rev. B | Page 24 of 24
OUTLINE DIMENSIONS
*COMPLIANT
TO
JEDEC STANDARDS MO-220-VEED-2
EXCEPT FOR EXPOSED PAD DIMENSION.
1
0.50
BSC
0.60 MAX
PIN 1
INDICATOR
1.50 REF
0.50
0.40
0.30
0.25 MIN
0.45
2.75
BSC SQ
TOP
VIEW
12° MAX 0.80 MAX
0.65 TYP
SEATING
PLANE
PIN 1
INDICATOR
0.90
0.85
0.80
0.30
0.23
0.18
0.05 MAX
0.02 NOM
0.20 REF
3.00
BSC SQ
*1.65
1.50 SQ
1.35
16
5
13
8
9
12
4
EXPOSED
PAD
BOTTOM VIEW
071708-A
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
Figure 63. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
3 mm x 3 mm Body, Very Thin Quad
(CP-16-3)
Dimensions in millimeters
ORDERING GUIDE
Model Temperature Range Package Description Package Option Branding
Ordering
Quantity
AD8342ACPZ-REEL71 −40°C to +85°C 16-Lead Lead Frame Chip Scale Package
[LFCSP_VQ], Reel
CP-16-3 Q01 1,500
AD8342ACPZ-R21 −40°C to +85°C 16-Lead Lead Frame Chip Scale Package
[LFCSP_VQ], Reel
CP-16-3 Q01 250
AD8342ACPZ-WP1 −40°C to +85°C 16-Lead Lead Frame Chip Scale Package
[LFCSP_VQ], Waffle Pack
CP-16-3 Q01 50
AD8342-EVALZ1 Evaluation Board 1
1 Z = RoHS Compliant Part.
©2007–2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05352-0-7/09(B)
