MF595-04
Technical Manual
CMOS 4-BIT SINGLE CHIP MICROCOMPUTER
S1C62N82 Technical Hardware/S1C62N82 Technical Software
S1C62N82
NOTICE
No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko
Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any
liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or
circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such
as medical products. Moreover, no license to any intellectual property rights is granted by implication or otherwise, and there
is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright
infringement of a third party. This material or portions thereof may contain technology or the subject relating to strategic
products under the control of the Foreign Exchange and Foreign Trade Law of Japan and may require an export license from
the Ministry of International Trade and Industry or other approval from another government agency.
Royalty on Copyrighted Musical Pieces
When a musical selection under copyright is created in the melody ROM section of EPSON’s S1C62N82 and then marketed
in your country or any other country, permission to use the copyright is required in accordance with the Copyright Law.
For such purpose, in connection with the contract we have concluded with the Japan Music Copyright Association regarding
copyrights, customers using the S1C62N82 are required to apply with us before starting any software developments,
regardless of whether the melody ROM section will be used or not. We shall process the necessary copyrights based on said
application.
Due to the above-stated reasons, we shall bear no responsibility whatsoever in the following cases:
• When the musical selection applied with us differs from the actual musical selection used;
• When no application has been made with us in spite of the fact that musical selection has been incorporated in the ROM
section (this also applies to pirated musical pieces).
Moreover, please take note that there are exceptional cases in which processing anew of copyrights may be required in
accordance with the laws of the country of destination of the marketed product(s).
© SEIK O EPSON CORPORATION 2001 All rights reserved.
PREFACE
This manual is individualy described about the hardware and the software
of the S1C62N82.
I. S1C62N82 Technical Hardware
This part explains the function of the S1C62N82, the circuit configu-
rations, and details the controlling method.
II. S1C62N82 Technical Software
This part explains the programming method of the S1C62N82.
Software
Hardware
The information of the product number change
Configuration of product number
Devices
Comparison table between new and previous number
S1C60 Family processors
Starting April 1, 2001, the product number will be changed as listed below. To order from April 1,
2001 please use the new product number. For further information, please contact Epson sales
representative.
S1 C60N01 F0A01 Packing specification
Specification
Package (D: die form; F: QFP)
Model number
Model name (C: microcomputer, digital products)
Product classification (S1: semiconductor)
Development tools
S5U1 C60R08 D1 1Packing specification
Version (1: Version 1 ∗2)
Tool type (D1: Development Tool ∗1)
Corresponding model number (60R08: for S1C60R08)
Tool classification (C: microcomputer use)
Product classification
(S5U1: development tool for semiconductor products)
∗1: For details about tool types, see the tables below. (In some manuals, tool types are represented by one digit.)
∗2: Actual versions are not written in the manuals.
Previous No.
E0C6001
E0C6002
E0C6003
E0C6004
E0C6005
E0C6006
E0C6007
E0C6008
E0C6009
E0C6011
E0C6013
E0C6014
E0C60R08
New No.
S1C60N01
S1C60N02
S1C60N03
S1C60N04
S1C60N05
S1C60N06
S1C60N07
S1C60N08
S1C60N09
S1C60N11
S1C60N13
S1C60140
S1C60R08
S1C62 Family processors
Previous No.
E0C621A
E0C6215
E0C621C
E0C6S27
E0C6S37
E0C623A
E0C623E
E0C6S32
E0C6233
E0C6235
E0C623B
E0C6244
E0C624A
E0C6S46
New No.
S1C621A0
S1C62150
S1C621C0
S1C6S2N7
S1C6S3N7
S1C6N3A0
S1C6N3E0
S1C6S3N2
S1C62N33
S1C62N35
S1C6N3B0
S1C62440
S1C624A0
S1C6S460
Previous No.
E0C6247
E0C6248
E0C6S48
E0C624C
E0C6251
E0C6256
E0C6292
E0C6262
E0C6266
E0C6274
E0C6281
E0C6282
E0C62M2
E0C62T3
New No.
S1C62470
S1C62480
S1C6S480
S1C624C0
S1C62N51
S1C62560
S1C62920
S1C62N62
S1C62660
S1C62740
S1C62N81
S1C62N82
S1C62M20
S1C62T30
Comparison table between new and previous number of development tools
Development tools for the S1C60/62 Family
Previous No.
ASM62
DEV6001
DEV6002
DEV6003
DEV6004
DEV6005
DEV6006
DEV6007
DEV6008
DEV6009
DEV6011
DEV60R08
DEV621A
DEV621C
DEV623B
DEV6244
DEV624A
DEV624C
DEV6248
DEV6247
New No.
S5U1C62000A
S5U1C60N01D
S5U1C60N02D
S5U1C60N03D
S5U1C60N04D
S5U1C60N05D
S5U1C60N06D
S5U1C60N07D
S5U1C60N08D
S5U1C60N09D
S5U1C60N11D
S5U1C60R08D
S5U1C621A0D
S5U1C621C0D
S5U1C623B0D
S5U1C62440D
S5U1C624A0D
S5U1C624C0D
S5U1C62480D
S5U1C62470D
Previous No.
DEV6262
DEV6266
DEV6274
DEV6292
DEV62M2
DEV6233
DEV6235
DEV6251
DEV6256
DEV6281
DEV6282
DEV6S27
DEV6S32
DEV6S37
EVA6008
EVA6011
EVA621AR
EVA621C
EVA6237
EVA623A
New No.
S5U1C62620D
S5U1C62660D
S5U1C62740D
S5U1C62920D
S5U1C62M20D
S5U1C62N33D
S5U1C62N35D
S5U1C62N51D
S5U1C62560D
S5U1C62N81D
S5U1C62N82D
S5U1C6S2N7D
S5U1C6S3N2D
S5U1C6S3N7D
S5U1C60N08E
S5U1C60N11E
S5U1C621A0E2
S5U1C621C0E
S5U1C62N37E
S5U1C623A0E
Previous No.
EVA623B
EVA623E
EVA6247
EVA6248
EVA6251R
EVA6256
EVA6262
EVA6266
EVA6274
EVA6281
EVA6282
EVA62M1
EVA62T3
EVA6S27
EVA6S32R
ICE62R
KIT6003
KIT6004
KIT6007
New No.
S5U1C623B0E
S5U1C623E0E
S5U1C62470E
S5U1C62480E
S5U1C62N51E1
S5U1C62N56E
S5U1C62620E
S5U1C62660E
S5U1C62740E
S5U1C62N81E
S5U1C62N82E
S5U1C62M10E
S5U1C62T30E
S5U1C6S2N7E
S5U1C6S3N2E2
S5U1C62000H
S5U1C60N03K
S5U1C60N04K
S5U1C60N07K
00
00
Hardware
S1C62N82
I.
Technical Hardware
Hardware
S1C62N82 TECHNICAL HARDWARE EPSON I-i
CONTENTS
CONTENTS
CHAPTER 1 INTRODUCTION............................................................... I-1
1.1 Configuration ................................................................... I-1
1.2 Features .......................................................................... I-2
1.3 Block Diagram ................................................................. I-4
1.4 Pin Layout Diagram......................................................... I-5
1.5 Pin Description ................................................................ I-7
CHAPTER 2 POWER SUPPLY AND INITIAL RESET ................................ I-8
2.1 Power Supply .................................................................. I-8
2.2 Initial Reset...................................................................... I-9
Oscillation detection circuit..................................... I-10
Reset pin (RESET) ................................................... I-10
Simultaneous high input to input ports (K00–K03) .. I-10
Internal register following initialization.................... I-11
2.3 Test Pin (TEST).............................................................. I-11
CHAPTER 3 CPU, ROM, RAM ............................................................ I-12
3.1 CPU............................................................................... I-12
3.2 ROM .............................................................................. I-13
3.3 RAM .............................................................................. I-13
I-ii EPSON S1C62N82 TECHNICAL HARDWARE
CONTENTS
CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION ...................... I-14
4.1 Memory Map .................................................................. I-14
4.2 Oscillation Circuit............................................................ I-22
OSC1 oscillation circuit........................................... I-22
OSC3 oscillation circuit........................................... I-23
Configuration of oscillation circuit........................... I-24
Control of oscillation circuit .................................... I-25
4.3 Input Ports (K00–K03, K10) ........................................... I-27
Configuration of input ports .................................... I-27
Input comparison registers and interrupt function .. I-28
Mask option ............................................................ I-31
Control of input ports.............................................. I-32
4.4 Output Ports (R00–R03, R10–R12) ............................... I-36
Configuration of output ports .................................. I-36
Mask option ............................................................ I-37
Control of output ports............................................ I-39
4.5 I/O Ports (P00–P03) ....................................................... I-41
Configuration of I/O port ........................................ I-41
I/O control register and I/O mode........................... I-41
Mask option ............................................................ I-42
Control of I/O port .................................................. I-42
4.6 LCD Driver...................................................................... I-45
Configuration of LCD driver..................................... I-45
Switching between dynamic and static drive............ I-48
Mask option (segment allocation)............................. I-49
Control of LCD driver .............................................. I-51
4.7 Clock Timer .................................................................... I-53
Configuration of clock timer .................................... I-53
Interrupt function ................................................... I-54
Control of clock timer.............................................. I-55
Hardware
S1C62N82 TECHNICAL HARDWARE EPSON I-iii
CONTENTS
4.8 Stopwatch Timer ............................................................ I-58
Configuration of stopwatch timer ............................ I-58
Count-up pattern .................................................... I-59
Interrupt function ................................................... I-60
Control of stopwatch timer ...................................... I-61
4.9 Supply Voltage Detection (SVD) Circuit
and Heavy Load Protection Function ............................. I-64
Configuration of SVD circuit
and heavy load protection function.......................... I-64
Operation of SVD detection timing .......................... I-66
Operation of heavy load protection function ............ I-67
Control of SVD circuit
and heavy load protection function.......................... I-68
4.10 Analog Voltage Comparator ........................................... I-70
Configuration of analog voltage comparator............. I-70
Operation of analog voltage comparator................... I-71
Control of analog voltage comparator ...................... I-72
4.11 Melody Generator........................................................... I-73
Outline of melody generator .................................... I-73
Melody data ............................................................ I-92
Playing of silent note ............................................... I-95
Envelope function ................................................... I-96
Playing tempo ......................................................... I-98
Playing mode.......................................................... I-100
Control of the melody generator ............................. I-104
4.12 Interrupt and HALT........................................................ I-108
Interrupt factors..................................................... I-110
Specific masks and factor flags for interrupt........... I-111
Interrupt vectors and priorities............................... I-112
Control of interrupt ................................................ I-113
I-iv EPSON S1C62N82 TECHNICAL HARDWARE
CONTENTS
CHAPTER 5 BASIC EXTERNAL WIRING DIAGRAM........................... I-117
CHAPTER 6 ELECTRICAL CHARACTERISTICS ................................... I-121
6.1 Absolute Maximum Rating ............................................ I-121
6.2 Recommended Operating Conditions ........................... I-122
6.3 DC Characteristics ........................................................ I-123
6.4 Analog Circuit Characteristics
and Power Current Consumption .................................. I-125
6.5 Oscillation Characteristics ............................................. I-131
CHAPTER 7 PACKAGE ..................................................................... I-133
7.1 Plastic Package............................................................. I-133
7.2 Ceramic Package for Test Sample................................ I-135
CHAPTER 8 PAD LAYOUT ................................................................. I-136
8.1 Diagram of Pad Layout.................................................. I-136
8.2 Pad Coordinates............................................................ I-137
S1C62N82 TECHNICAL HARDWARE EPSON I-1
CHAPTER 1: INTRODUCTION
INTRODUCTION
Each member of the S1C62N82 Series of single chip micro-
computers feature a 4-bit S1C6200A core CPU, 2,048 words
of ROM (12 bits per word), 224 words of RAM (4 bits per
word), an LCD driver, 5 bits for input ports (K00–K03 and
K10), 7 bits for output ports (R00–R03 and R10–R12), one 4-
bit I/O port (P00–P03), two timer (clock timer and stopwatch
timer), and a melody generator.
Because of their low voltage operation and low power con-
sumption, the S1C62N82 Series are ideal for a wide range of
applications, and are especially suitable for battery-driven
systems with a melody.
Configuration
The S1C62N82 Series are configured as follows, depending
on the supply voltage and oscillation circuits.
CHAPTER 1
1.1
Table 1.1.1
Configuration of the
S1C62N82 Series
Model Supply Voltage Oscillation Circuits
S1C62L82
S1C62N82
S1C62A82
1.5 V
3.0 V
3.0 V
Single Clock (Crystal or CR)
Single Clock (Crystal or CR)
Twin Clock (Crystal or CR, Ceramic or CR)
I-2 EPSON S1C62N82 TECHNICAL HARDWARE
CHAPTER 1: INTRODUCTION
Features
Crystal or CR oscillation circuit (32.768 kHz)
CR oscillation circuit or Ceramic oscillation circuit (1 MHz)
100 instructions
At 32 kHz : 153 µs, 214 µs, 366 µs
At 1 MHz : 5 µs, 7 µs, 12 µs
2,048 words × 12 bits
224 words × 4 bits (including segment memory)
5 bits(Supplementary pull-down resistors may be used by
mask option)
4 bits(general purpose)
1 bit (melody output)
1 bit (melody reverse output and also serves as external CR
connecting terminal for envelope)
1 bit (general purpose output)
1 bit (clock output)
Either OSC3 output or 256 Hz–32 kHz may be specified
with mask option
4 bits
42 segments × 4 common duty/38 segments × 8 common duty
(Switching between 1/4 duty and 1/8 duty,
and assignment of segment are possible
with mask option)
1 sound source output, 31 musical intervals (from among 3
octaves), 8 notes, and tempos (from among 16 types);
the number of musical pieces is optional within the ROM
capacity (128 words).
Envelope addition and piezo buzzer direct driving are
possible through mask option selection.
Built-in operating amplifier for the MOS input analog com-
parator
1.2 V / 2.4 V
Built-in oscillation circuit
Instruction set
Instruction execution time
ROM capacity
RAM capacity (data RAM)
Input port
Output port
Input/output port
LCD driver
Melody generation circuit
Comparator
Supply voltage detection
circuit (SVD)
1.2
S1C62N82 TECHNICAL HARDWARE EPSON I-3
CHAPTER 1: INTRODUCTION
Input port interrupt 2 systems
Timer interrupt 2 systems
Melody interrupt 1 system
S1C62N82........At 32 kHz 1.5 µA (Typ.) (when halted)
S1C62N82........At 32 kHz 4.0 µA (Typ.) (when executing)
S1C62L82 ........ At 32 kHz 1.5 µA (Typ.) (when halted)
S1C62L82 ........ At 32 kHz 4.0 µA (Typ.) (when executing)
S1C62A82 ........ At 1 MHz 150 µA (Typ.) (when executing)
80-pin QFP (plastic) or chip
Interrupts:External interrupt
Internal interrupt
Current consumption
Supply form
I-4 EPSON S1C62N82 TECHNICAL HARDWARE
CHAPTER 1: INTRODUCTION
1.3
Fig. 1.3.1
Block diagram
Melody
Comparator
& SVD
Power
Controller
LCD
Driver
RAM
224x4 Interrupt
Generator
I Port
Test Port
I/O Port
O Port
Timer
Stop
Watch
Core CPU S1C6200A
ROM
2,048x12 OSC System
Reset
Control
RESET
OSC3
V
V
V
CA
CD
V
Vss
K10
TEST
P00~P03
R00~R03
R10, R11
DD
S1
L1
L4
OSC2
CMPP
CMPM
MO
R12
OSC4
OSC1
SEG0
COM7/SEG38
COM6/SEG39
COM5/SEG40
COM4/SEG41
COM0
K00~K03
Block Diagram
S1C62N82 TECHNICAL HARDWARE EPSON I-5
CHAPTER 1: INTRODUCTION
1.4
Pin No Pin Name Pin No Pin Name Pin No Pin Name Pin No Pin Name Pin No Pin Name
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
V
TEST
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
R03
R02
R01
R00
MO
R12
R11
R10
K10
K03
K02
K01
K00
RESET
CMPP
CMPM
COM3
COM2
COM1
COM0
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
P03
P02
P01
P00
CD
CC
CB
CA
V
V
V
V
V
OSC4
OSC3
V
OSC2
OSC1
SEG38
COM7
SEG39
COM6
SEG40
COM5
SEG41
COM4
L4
L3
L2
L1
SS
S1
DD
Fig. 1.4.1
Pin assignment
(QFP5)
4164
241
65
80
40
25
Index
Pin Layout Diagram
QFP5
I-6 EPSON S1C62N82 TECHNICAL HARDWARE
CHAPTER 1: INTRODUCTION
Pin No Pin Name Pin No
SEG16
SEG17
SEG18
SEG19
R03
R02
R01
R00
MO
R12
R11
R10
K10
K03
K02
K01
Pin No Pin Name Pin No Pin Name Pin No Pin Name
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
K00
RESET
CMPP
CMPM
COM3
COM2
COM1
COM0
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
P03
P02
P01
P00
CD
CC
CB
CA
V
V
V
V
V
OSC4
OSC3
V
OSC2
OSC1
V
TEST
SEG38
COM7
SEG39
COM6
SEG40
COM5
SEG41
COM4
L4
L3
L2
L1
SS
S1
DD
Pin Name
Fig. 1.4.2
Pin assignment
(QFP14)
4160
201
61
80
40
21
Index
QFP14
S1C62N82 TECHNICAL HARDWARE EPSON I-7
CHAPTER 1: INTRODUCTION
1.5
Table 1.5.1 Pin description
Terminal Name
V
V
V
V –V
CA–CD
OSC1
OSC2
OSC3
OSC4
K00–K03
K10
P00–P03
R00–R03
R10
R11
R12
MO
CMPP
CMPM
SEG0–SEG37
COM0–COM3
SEG38–SEG41
COM4–COM7
RESET
TEST
DD
SS
S1
L1
Input/Output
(I)
(I)
–
–
–
I
O
I
O
I/O
O
I
I
O
O
O
I
I
Function
Power source (+) terminal
Power source (-) terminal
Internal logic and oscillation system regulated voltage power source terminal
LCD system power source terminal
LCD system booster capacitor connector terminal
I/O terminal
Ouput terminal
R10: FOUT output available through mask option selection
R12: Melody inverted output and envelope function
available through mask option selection
MO: Melody signal output terminal
Analog comparator non-inverted input terminal
Analog comparator inverted input terminal
LCD segment output terminal
SEG20 and 21 may be used only when the corresponding chips have been
supplied (convertible to DC output terminal by mask option)
L4
I
O
Input terminal
Pin No.
1
75
78
71–74
67–70
80
79
77
76
32–35
31
63–66
23–26
30
29
28
27
37
38
3–22
43–58
39–42
59–62
36
2
LCD common output terminal
LCD segment output terminal (when selected 1/4 duty)
(convertible to DC output terminal by mask option)
LCD common output terminal (when selected 1/8 duty)
Initial setting input terminal
Test input terminal
Crystal or CR oscillation input terminal
Crystal or CR oscillation output terminal
Ceramic or CR oscillation input terminal (S1C62A82)
Ceramic or CR oscillation output terminal (S1C62A82)
79
73
76
69–72
65–68
78
77
75
74
30–33
29
61–64
21–24
28
27
26
25
35
36
1–20
41–56
37–40
57–60
34
80
QFP5 QFP14
Pin Description
I-8 EPSON S1C62N82 TECHNICAL HARDWARE
CHAPTER 2: POWER SUPPLY AND INITIAL RESET
CHAPTER 2 POWER SUPPLY AND INITIAL RESET
2.1
Note
Fig. 2.1.1
Configuration of power
supply S1C62N82/62A82
(items enclosed in
parentheses are for
S1C62L82)
External
power
supply
Internal
circuit
LCD driver
circuit
LCD system
voltage
booster/reducer
circuit
LCD system regulated
voltage circuit
Internal system
regulated voltage
circuit
V
DD
V
V
L4
V
L1
CA
CB
CC
Vss
V
L1
V
L3
V
V
L2
COM0–7
SEG0–37
S1 S1
Oscillation
circuit OSC1, 2
OSC3, 4
V
L4
V
L3
CD
(V )
L1
V
L2
(V )
L1
(V )
L2
(V )
L2
V
L2
(V )
L1
( )
Power Supply
By externally providing a single power supply (*1) between
VDD and VSS, the S1C62N82 Series produces the internally
required voltage through the constant voltage circuit and
voltage booster/reducer circuit.
In S1C62N82/62A82, the constant voltage circuit produces
VS1 voltage for oscillation and internal circuits, and VL2
voltage for LCD driving. The voltage booster/reducer circuit
produces VL1, VL3 and VL4 based on VL2.
In S1C62L82, the constant voltage circuit VS1 voltage for
oscillation and internal circuits, and VL1 voltage for LCD
driving. The voltage booster/reducer circuit produces VL2,
VL3 and VL4 based on VL1.
Figure 2.1.1 shows the power supply configuration.
*1 Supply voltage: S1C62N82/62A82...3.0 V
S1C62L82...1.5 V
- External loads cannot be driven by the output voltage of the
regulated voltage circuit and voltage booster circuit.
- See Chapter 6, "ELECTRICAL CHARACTERISTICS", for
voltage values.
S1C62N82 TECHNICAL HARDWARE EPSON I-9
CHAPTER 2: POWER SUPPLY AND INITIAL RESET
Initial Reset
To initialize the S1C62N82 Series circuits, an initial reset
must be executed. There are three ways of doing this.
(1)Initial reset by the oscillation detection circuit
(2)External initial reset via the RESET pin
(3)External initial reset by simultaneous high input to pins
K00–K03 (depending on mask option)
Figure 2.2.1 shows the configuration of the initial reset
circuit.
Fig. 2.2.1
Configuration of
initial reset circuit
Vss
RESET
K03
K02
K01
K00
OSC2
OSC1
OSC1
Oscillation
circuit
Vss
Oscillation
detection
circuit Noise
rejection
circuit
Initial
reset
Noise
rejection
circuit
2.2
I-10 EPSON S1C62N82 TECHNICAL HARDWARE
CHAPTER 2: POWER SUPPLY AND INITIAL RESET
The oscillation detection circuit outputs the initial reset
signal at power-on until the crystal oscillation circuit starts
oscillating, or when the crystal oscillation circuit stops
oscillating for some reason.
The circuit may malfunction if the power is turned on erro-
neously. In such cases, use one of the following two initial
resetting methods.
An initial reset can be invoked externally by making the
reset pin high. This high level must be maintained for at
least 5 ms (when oscillating frequency, fosc1 = 32 kHz),
because the initial reset circuit contains a noise rejection
circuit. When the reset pin goes low the CPU begins to
operate.
Another way of invoking an initial reset externally is to input
a high signal simultaneously to the input ports (K00–K03)
selected with the mask option. The specified input port pins
must be kept high for 2–4 sec (when oscillating frequency
fosc1 = 32 kHz), because of the noise rejection circuit. Table
2.2.1 shows the combinations of input ports (K00–K03) that
can be selected with the mask option.
ANot used
BK00*K01
CK00*K01*K02
DK00*K01*K02*K03
When, for instance, mask option D (K00*K01*K02*K03) is
selected, an initial reset is executed when the signals input
to the four ports K00–K03 are all high at the same time.
If you use this function, make sure that the specified ports
do not go high at the same time during normal operation.
Since this function uses a timer-controlled noise rejection
circuit, if the oscillator (OSC1) is not running, or if the timer
remains reset by software, initial resetting by means of this
function is impossible. (See 4.7, Clock Timer.)
Oscillation detection
circuit
Reset pin (RESET)
Simultaneous high
input to input ports
(K00–K03)
Table 2.2.1
Input port combinations
S1C62N82 TECHNICAL HARDWARE EPSON I-11
CHAPTER 2: POWER SUPPLY AND INITIAL RESET
Internal register fol-
lowing initialization
Table 2.2.2
Initial values
2.3
An initial reset initializes the CPU as shown in the table
below.
Name
Program counter step
Program counter page
New page pointer
Stack pointer
Index register X
Index register Y
Register pointer
General register A
General register B
Interrupt flag
Decimal flag
Zero flag
Carry flag
Signal
PCS
PCP
NPP
SP
X
Y
RP
A
B
I
D
Z
C
Number of Bits
8
4
4
8
8
8
4
4
4
1
1
1
1
Setting Value
00H
1H
1H
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0
0
Undefined
Undefined
Peripheral Circuits
CPU Core
Test Pin (TEST)
This pin is used when IC is inspected for shipment.
During normal operation connect it to VSS.
Name
RAM
Display memory
Other peripheral circuit
Number of Bits
144 × 4
80 × 4
–
Setting Value
Undefined
Undefined
*1
*1: See Section 4.1, "Memory Map"
I-12 EPSON S1C62N82 TECHNICAL HARDWARE
CHAPTER 3: CPU, ROM, RAM
CPU, ROM, RAM
CPU
The S1C62N82 Series employs the S1C6200A core CPU, so
that register configuration, instructions, and so forth are
virtually identical to those in other processors in the family
using the S1C6200A. Refer to the "S1C6200/6200A Core
CPU Manual" for details of the S1C6200A.
Note the following points with regard to the S1C62N82
Series:
(1)The SLEEP operation is not provided, so the SLP instruc-
tion cannot be used.
(2)Because the ROM capacity is 2,048 words, 12 bits per
word, bank bits are unnecessary, and PCB and NBP are
not used.
(3)The RAM page is set to 0 only, so the page part (XP, YP)
of the index register that specifies addresses is invalid.
PUSH XP PUSH YP
POP XP POP YP
LD XP,r LD YP,r
LD r,XP LD r,YP
CHAPTER 3
3.1
S1C62N82 TECHNICAL HARDWARE EPSON I-13
CHAPTER 3: CPU, ROM, RAM
ROM
The built-in ROM, a mask ROM for the program, has a
capacity of 2,048 × 12-bit steps. The program area is 8
pages (0–7), each consisting of 256 steps (00H–FFH). After
an initial reset, the program start address is page 1, step
00H. The interrupt vector is allocated to page l, steps 02H–
0BH.
3.2
RAM
The RAM, a data memory for storing a variety of data, has a
capacity of 144 words, 4-bit words. When programming,
keep the following points in mind:
(1)Part of the data memory is used as stack area when
saving subroutine return addresses and registers, so be
careful not to overlap the data area and stack area.
(2)Subroutine calls and interrupts take up three words on
the stack.
(3)Data memory 000H–00FH is the memory area pointed by
the register pointer (RP).
3.3
00H step
02H step
0BH step
0CH step
FFH step
12 bits
Program start address
Interrupt vector area
Bank 0
Program area
0 page
1 page
2 page
3 page
01H step
4 page
5 page
6 page
7 page
Fig. 3.2.1
ROM configuration
I-14 EPSON S1C62N82 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map)
CHAPTER 4 PERIPHERAL CIRCUITS AND
OPERATION
Peripheral circuits (timer, I/O, and so on) of the S1C62N82
Series are memory mapped. Thus, all the peripheral circuits
can be controlled by using memory operations to access the
I/O memory. The following sections describe how the pe-
ripheral circuits operate.
Memory Map
The data memory of the S1C62N82 Series has an address
space of 250 words, of which 80 words are allocated to
display memory and 26 words, to I/O memory. Figure 4.1.1
show the overall memory mas for the S1C62N82 Series, and
Tables 4.1.1 (a)–(g), the memory maps for the peripheral
circuits (I/O space).
4.1
Address
Page High
Low 0123456789ABCDEF
M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF
3
0
1
2
4
5
6
7
8
9
A
B
C
D
E
F
0
RAM area (000H–08FH)
144 words x 4 bits (R/W)
I/O memory area Table 4.1.1 (a)–(g)
Display memory area (090H–0DFH)
80 words x 4 bits (R/W)
Unused area
*
*If the duty of the LCD driver is set to 1/8 by the mask
option in the display memory area (80 words × 4 bits), 304
bits (38 segments × 8 common bits) are used. If the duty
is set to 1/4, 168 bits (42 segments × 4 common bits) are
used. The bits unassigned as display memory can serve
as a general-purpose RAM.
Fig. 4.1.1
Memory map
Memory is not mounted in unused area within the memory map
and in memory area not indicated in this chapter. For this reason,
normal operation cannot be assured for programs that have been
prepared with access to these areas.
Note
S1C62N82 TECHNICAL HARDWARE EPSON I-15
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map)
Table 4.1.1 (a) I/O memory map (0E0H–0E3H)
Address Comment
Register
D3 D2 D1 D0 Name SR *1 10
0E0H
0E1H
0E2H
0E3H
K03 K02 K01 K00
0 0 0 K10
SWL3 SWL2 SWL1 SWL0
SWH3 SWH2 SWH1 SWH0
R
R
R
R
K03
K02
K01
K00
–
–
–
–
0
0
0
K10 –
Input port (K10)
SWL3
SWL2
SWL1
SWL0
0
0
0
0
SWH3
SWH2
SWH1
SWH0
0
0
0
0
MSB
Stopwatch timer
1/100 sec (BCD)
LSB
Input port (K00–K03)
High
High
High
High
Low
Low
Low
Low
High Low
MSB
Stopwatch timer
1/10 sec (BCD)
LSB
*5
*5
*5
*2
*2
*2
*2
*2
* 1 Initial value following initial reset
* 2 Not set in the circuit
* 3 Undefined
* 4 Reset (0) immediately after being read
* 5 Constantly 0 when being read
* 6 Refer to main manual
I-16 EPSON S1C62N82 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map)
Address Comment
Register
D3 D2 D1 D0 Name SR *1 10
0E4H
0E5H
0E6H
0E7H
TM3 TM2 TM1 TM0
KCP03 KCP02 KCP01 KCP00
0 0 0 KCP10
0 0 0 EIMEL
R
R
R/W
R
TM3
TM2
TM1
TM0
–
–
–
–
KCP03
KCP02
KCP01
KCP00
0
0
0
0
Input comparison register (K03)
Input comparison register (K02)
Input comparison register (K01)
Input comparison register (K00)
0
0
0
KCP10 0
0
0
0
EIMEL 0 Enable Mask
Input comparison register (K10)
Timer data (clock timer 2 Hz)
Timer data (clock timer 4 Hz)
Timer data (clock timer 8 Hz)
Timer data (clock timer 16 Hz)
High
High
High
High
Low
Low
Low
Low
Falling
Falling
Falling
Falling
Rising
Rising
Rising
Rising
Interrupt mask register (melody)
Falling Rising
*5
*5
*5
R/W
*5
*5
*5
R/W
Table 4.1.1 (b) I/O memory map (0E4H–0E7H)
* 1 Initial value following initial reset
* 2 Not set in the circuit
* 3 Undefined
* 4 Reset (0) immediately after being read
* 5 Constantly 0 when being read
* 6 Refer to main manual
S1C62N82 TECHNICAL HARDWARE EPSON I-17
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map)
Address Comment
Register
D3 D2 D1 D0 Name SR *1 10
0E8H
0E9H
0EAH
0EBH
EIK03 EIK02 EIK01 EIK00
0 0 0 EIK10
0 0 EISW1 EISW0
0 EIT2 EIT8 EIT32
R
R
R
R/W
EIK03
EIK02
EIK01
EIK00
0
0
0
0
0
0
0
EIK10 0
Interrupt mask register (K10)
0
0
EISW1
EISW0
0
0
0
EIT2
EIT8
EIT32
0
0
0
Enable
Enable
Enable
Mask
Mask
Mask
Interrupt mask register (stopwatch 1 Hz)
Interrupt mask register (stopwatch 10 Hz)
Interrupt mask register (K03)
Interrupt mask register (K02)
Interrupt mask register (K01)
Interrupt mask register (K00)
Enable
Enable
Enable
Enable
Mask
Mask
Mask
Mask
Enable Mask
Interrupt mask register (clock timer 2 Hz)
Interrupt mask register (clock timer 8 Hz)
Interrupt mask register (clock timer 32 Hz)
Enable
Enable
Mask
Mask
*5
*5
R/W
*5
R/W
R/W
*5
*5
*5
Table 4.1.1 (c) I/O memory map (0E8H–0EBH)
* 1 Initial value following initial reset
* 2 Not set in the circuit
* 3 Undefined
* 4 Reset (0) immediately after being read
* 5 Constantly 0 when being read
* 6 Refer to main manual
I-18 EPSON S1C62N82 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map)
Address Comment
Register
D3 D2 D1 D0 Name SR
*1
10
0ECH
0EDH
0EEH
0EFH
0 0 0 IMEL
00IK1IK0
0 0 ISW1 ISW0
0 IT2 IT8 IT32
R
R
R
0
0
0
IMEL 0
0
0
IK1
IK0
0
0
Interrupt factor flag (K10)
Interrupt factor flag (K00–K03)
0
0
ISW1
ISW0
0
0
0
IT2
IT8
IT32
0
0
0
Yes
Yes
Yes
No
No
No
Interrupt factor flag (stopwatch 1 Hz)
Interrupt factor flag (stopwatch 10 Hz)
Interrupt factor flag (melody)
Yes No
Yes
Yes
No
No
Interrupt factor flag (clock timer 2 Hz)
Interrupt factor flag (clock timer 8 Hz)
Interrupt factor flag (clock timer 32 Hz)
Yes
Yes
No
No
*5
*5
*4
*4
R
*5
*4
*4
*4
*5
*5
*4
*4
*5
*5
*5
*4
* 1 Initial value following initial reset
* 2 Not set in the circuit
* 3 Undefined
* 4 Reset (0) immediately after being read
* 5 Constantly 0 when being read
* 6 Refer to main manual
Table 4.1.1 (d) I/O memory map (0ECH–0EFH)
S1C62N82 TECHNICAL HARDWARE EPSON I-19
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map)
Address Comment
Register
D3 D2 D1 D0 Name SR *1 10
0F0H
0F1H
0F2H
0F3H
MAD3 MAD2 MAD1 MAD0
0 MAD6 MAD5 MAD4
CLKC1 CLKC0 TEMPC MELC
R03 R02 R01 R00
R/W
R
R/W
MAD3
MAD2
MAD1
MAD0
0
0
0
0
0
MAD6
MAD5
MAD4
0
0
0
Melody ROM address (AD6, MSB)
Melody ROM address (AD5)
Melody ROM address (AD4)
CLKC1
CLKC0
TEMPC
MELC
0
0
0
0
R03
R02
R01
R00
0
0
0
0
High
High
High
High
Low
Low
Low
Low
CLKC1(0)&CLKC0(0) : melody speed 1
CLKC1(0)&CLKC0(1) : melody speed 8
CLKC1(1)&CLKC0(0) : melody speed 16
CLKC1(1)&CLKC0(1) : melody speed 32
Tempo change control
Melody control ON/OFF
Melody ROM address (AD3)
Melody ROM address (AD2)
Melody ROM address (AD1)
Melody ROM address (AD0, LSB)
High
High
High
High
Low
Low
Low
Low
High
High
High
Low
Low
Low
Output port data (R00–R03)
High
High
High
ON
Low
Low
Low
OFF
R/W
*5
R/W
×
×
×
×
* 1 Initial value following initial reset
* 2 Not set in the circuit
* 3 Undefined
* 4 Reset (0) immediately after being read
* 5 Constantly 0 when being read
* 6 Refer to main manual
Table 4.1.1 (e) I/O memory map (0F0H–0F3H)
I-20 EPSON S1C62N82 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map)
Address Comment
Register
D3 D2 D1 D0 Name SR *1 10
0F4H
0F6H
0F9H
0FAH
R12
MO
ENV
R11 R10
FOUT
P03 P02 P01 P00
0 TMRST SWRUN SWRST
HLMOD 0 SVDDT SVDON
W
R/W
MELD
R12
MO
ENV
R11
R10
FOUT
P03
P02
P01
P00
–
–
–
–
I/O port (P00–P03)
0
TMRST
SWRUN
SWRST
Reset
0
Reset
HLMOD
0
SVDDT
SVDON
0
0
0 ON OFF
Clock timer reset
Stopwatch timer RUN/STOP
Stopwatch timer reset
Melody output mask
Output port data (R12)
Inverting melody output
Melody envelope control
Output port data (R11)
Output port data (R10)
Frequency output
Disable
High
–
–
High
High
ON
Enable
Low
–
–
Low
Low
OFF
High
High
High
High
Low
Low
Low
Low
Heavy load protection mode register
Supply voltage detector data
Supply voltage detector ON/OFF
Reset
Run
Reset
–
Stop
–
R
*2
*2
*2
*2
R/W
R/W WR
R/W R/W
Heavy
load
Supply
voltage
low
Normal
load
Supply
voltage
normal
*5
*5
*5
*5
0
0
–
Hz
0
0
MELD
*6
Table 4.1.1 (f) I/O memory map (0F4H, 0F6H, 0F9H–0FAH)
* 1 Initial value following initial reset
* 2 Not set in the circuit
* 3 Undefined
* 4 Reset (0) immediately after being read
* 5 Constantly 0 when being read
* 6 Refer to main manual
S1C62N82 TECHNICAL HARDWARE EPSON I-21
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map)
Address Comment
Register
D3 D2 D1 D0 Name SR *1 10
0FBH
0FCH
CSDC 0 CMPDT CMPON
CLKCHG OSCC 0 IOC
R/W
R
0
1
0
CLKCHG
OSCC
0
IOC
0
0
0
CPU clock switch
OSC3 oscillator ON/OFF
I/O port P00–P03 Input/Output
LCD drive switch
Analog voltage comparator ON/OFF
Static
+ > -
ON
Dynamic
- > +
OFF
OSC3
ON
Output
OSC1
OFF
Input
*5
*5
R/W
R/W R/W
CSDC
0
CMPDT
CMPON
Comparator's voltage condition:
1 = CMPP(+)input > CMPM(-)input,
0 = CMPM(-)input > CMPP(+)input
R
Table 4.1.1 (g) I/O memory map (0FBH–0FCH)
* 1 Initial value following initial reset
* 2 Not set in the circuit
* 3 Undefined
* 4 Reset (0) immediately after being read
* 5 Constantly 0 when being read
* 6 Refer to main manual
I-22 EPSON S1C62N82 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit)
4.2
V
DD
C
GX
X'tal
OSC2
OSC1
R
R
DX
C
DX
V
DD
To CPU and peripheral
circuits
S1C62N82 Series
FX
As Figure 4.2.1 indicates, the crystal oscillation circuit can
be configured simply by connecting the crystal oscillator
(X'tal) between terminals OSC1 and OSC2 to the trimmer
capacitor (CGX) between terminals OSC1 and VDD.
CR oscillation circuit
For the S1C62N82 Series, CR oscillation circuit (typ. 32.768
kHz) may also be selected by a mask option. Figure 4.2.2 is
the block diagram of the OSC1 CR oscillation circuit.
OSC2
OSC1
C
To CPU and
peripheral circuits
The S1C62N82 Series
R
CR
CR
As Figure 4.2.2 indicates, the CR oscillation circuit can be
configured simply by connecting the resistor (RCR) between
pins OSC1 and OSC2 since capacity (CCR) is built-in.
See Chapter 6, "ELECTRICAL CHARACTERISTICS" for RCR
value.
Fig. 4.2.1
OSC1 crystal oscillation circuit
Fig. 4.2.2
OSC1 CR oscillation circuit
Oscillation Circuit
Crystal oscillation circuit
The S1C62N82 Series has a built-in OSC1 crystal oscillation
circuit (Typ. 32.768 kHz). As an external element, the OSC1
crystal oscillation circuit generates the operating clock for
the CPU and peripheral circuitry by connecting the crystal
oscillator (Typ. 32.768 kHz) and trimmer capacitor (5–25
pF).
Figure 4.2.1 is the block diagram of the OSC1 crystal oscilla-
tion circuit.
OSC1 oscillation
circuit
S1C62N82 TECHNICAL HARDWARE EPSON I-23
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit)
OSC3 oscillation
circuit
Fig. 4.2.3
OSC3 oscillation circuit
In the S1C62N82 Series, the S1C62A82 has twin clock
specification. The mask option enables selection of either
the CR or ceramic oscillation circuit (OSC3 oscillation cir-
cuit) as the CPU's subclock. Because the oscillation circuit
itself is built-in, it provides the resistance as an external
element when CR oscillation is selected, but when ceramic
oscillation is selected both the ceramic oscillator and two
capacitors (gate and drain capacitance) are required.
Figure 4.2.3 is the block diagram of the OSC3 oscillation
circuit.
As indicated in Figure 4.2.3, the CR oscillation circuit can
be configured simply by connecting the resistor (RCR) be-
tween terminals OSC3 and OSC4 when CR oscillation is
selected. When 35 k is used for R CR, the oscillation fre-
quency is about 1 MHz. When ceramic oscillation is se-
lected, the ceramic oscillation circuit can be configured by
connecting the ceramic oscillator (Typ. 1 MHz) between
terminals OSC3 and OSC4 to the two capacitors (CGC and
CDC) located between terminals OSC3 and OSC4 and VDD.
For both CGC and CDC, connect capacitors that are about
100 pF. To lower current consumption of the OSC3 oscilla-
tion circuit, oscillation can be stopped through the software.
For the S1C62N82 and 62L82 (single clock specification), do
not connect anything to terminals OSC3 and OSC4.
To CPU
Oscillation circuit
control signal
S1C62A82
C
CR
OSC3
OSC4
R
CR
V
DD
C
GC
C
DC
Ceramic
OSC4
OSC3
R
R
DC
To CPU
Oscillation circuit
control signal
S1C62A82
FC
I-24 EPSON S1C62N82 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit)
Configuration of
oscillation circuit
The S1C62N82 and 62L82 have one oscillation circuit
(OSC1), and the S1C62A82 has two oscillation circuits
(OSC1 and OSC3). OSC1 is a crystal oscillation circuit or
CR oscillation circuit (S1C62N82/62L82) that supplies the
operating clock the CPU and peripheral circuits. OSC3 is
either a CR or ceramic oscillation circuit. When processing
with the S1C62A82 requires high-speed operation, the CPU
operating clock can be switched from OSC1 to OSC3.
Figure 4.2.4 is the block diagram of this oscillation system.
Fig. 4.2.4
Oscillation system
For S1C62A82, selection of either OSC1 or OSC3 for the
CPU's operating clock can be made through the software.
Oscillation circuit control signal
CPU clock selection signal
To CPU
To peripheral circuit
Clock
switch
OSC1
oscillation
circuit
OSC3
oscillation
circuit
S1C62N82 TECHNICAL HARDWARE EPSON I-25
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit)
Table 4.2.1 lists the control bits and their addresses for the
oscillation circuit.
Table 4.2.1 Control bits of oscillation circuit and prescaler
Control of oscillation
circuit
Address Comment
Register
D3 D2 D1 D0 Name SR 1 0
0FCH
CLKCHG OSCC 0 IOC CLKCHG
OSCC
0
IOC
0
0
0
CPU clock switch
OSC3 oscillator ON/OFF
I/O port P00–P03 Input/Output
OSC3
ON
Output
OSC1
OFF
Input
R/WR/W R
OSC3 oscillation control (0FCH D2)
Controls oscillation ON/OFF for the OSC3 oscillation circuit.
(S1C62A82 only.)
When 1 is written: The OSC3 oscillation ON
When 0 is written: The OSC3 oscillation OFF
Read-out: Valid
When it is necessary to operate the CPU of the S1C62A82 at
high speed, set OSCC to 1. At other times, set it to 0 to
lessen the current consumption.
For the S1C62N82 and 62L82, keep OSCC set to 0.
At initial reset, OSCC is set to 0.
The CPU's clock switch (0FCH D3)
The CPU's operation clock is selected with this register.
(S1C62A82 only.)
When 1 is written: OSC3 clock is selected
When 0 is written: OSC1 clock is selected
Read-out: Valid
When the S1C62A82's CPU clock is to be OSC3, set
CLKCHG to 1; for OSC1, set CLKCHG to 0. This register
cannot be controlled for the S1C62N82 and 62L82, so that
OSC1 is selected no matter what the set value.
At initial reset, CLKCHG is set to 0.
OSCC
CLKCHG
I-26 EPSON S1C62N82 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit)
Note
-
It takes at least 5 ms from the time the OSC3 oscillation circuit
goes ON until the oscillation stabilizes. Consequently, when
switching the CPU operation clock from OSC1 to OSC3, do this
after a minimum of 5 ms have elapsed since the OSC3 oscilla-
tion went ON.
Further, the oscillation stabilization time varies depending on
the external oscillator characteristics and conditions of use, so
allow ample margin when setting the wait time.
-
When switching the clock form OSC3 to OSC1, use a separate
instruction for switching the OSC3 oscillation OFF. An error in
the CPU operation can result if this processing is performed at
the same time by the one instruction.
S1C62N82 TECHNICAL HARDWARE EPSON I-27
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports)
Input Ports (K00–K03, K10)
The S1C62N82 Series have a general-purpose input (4 bits +
1 bit). Each of the input port pins (K00–K03, K10) has an
internal pull-down resistance. The pull-down resistance can
be selected for each bit with the mask option.
Figure 4.3.1 shows the configuration of input port.
4.3
Configuration of
input ports
Fig. 4.3.1
Configuration of input port
Kxx
Mask option
Address
V
DD
Interrupt
request
Data bus
V
SS
Selecting "pull-down resistance enabled" with the mask
option allows input from a push button, key matrix, and so
forth. When "pull-down resistance disabled" is selected, the
port can be used for slide switch input and interfacing with
other LSIs.
I-28 EPSON S1C62N82 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports)
All five input port bits (K00–K03, K10) provide the interrupt
function. The conditions for issuing an interrupt can be set
by the software for the five bits. Also, whether to mask the
interrupt function can be selected individually for all five
bits by the software. Figure 4.3.2 shows the configuration of
K00–K03 and K10.
The input interrupt timing for K00–K03 and K10 depends on
the value set in the input comparison registers (KCP00–
KCP03 and KCP10). An interrupt can be set to occur on the
rising or falling edge of the input.
The interrupt mask registers (EIK00–EIK03, EIK10) enable
the interrupt mask to be selected individually for K00–K03
and K10. An interrupt occurs when the input value which
are not masked change so they no longer match those of the
input comparison register. An interrupt for K10 can be
generated by setting the same conditions individually.
When an interrupt is generated, the interrupt factor flag (IK0
and IK1) is set to 1.
Figure 4.3.3 shows an example of an interrupt for K00–K03.
Writing to the interrupt mask registers (EIK00–EIK03, EIK10)
should be done only in the DI status (interrupt flag = 0).
Otherwise, it causes malfunction.
Note
Data bus
Address
Address
Interrupt mask
register (EIK)
Input comparison
register (KCP)
Kxx
Address
Mask option
(K00–K03, K10)
Noise
rejector
One for each pin series
Interrupt factor
flag (IK)
Interrupt
request
Address
Fig. 4.3.2
Input interrupt
circuit configuration
(K00–K03, K10)
Input comparison
registers and inter-
rupt function
S1C62N82 TECHNICAL HARDWARE EPSON I-29
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports)
Interrupt mask registers Input comparison registers
EIK03 EIK02 EIK01 EIK00 KCP03 KCP02 KCP01 KCP00
1110 1010
With the above setting, an interrupt for K00–K03 occurs under
the following conditions.
Input ports
(1) K03 K02 K01 K00
1010 (Initial value)
↓
(2) K03 K02 K01 K00
1011
↓
(3) K03 K02 K01 K00
0011
↓
(4) K03 K02 K01 K00
0111
↓
(5) K03 K02 K01 K00
1011
Fig. 4.3.3
Example of interrupt of
K00–K03
→Interrupt generated
K00 is masked, so the three
bits of K01–K03 cease to
match those of the input
comparison register KCP01–
KCP03, and an interrupt
occurs.
K00 is masked by the interrupt mask register (EIK00), so an
interrupt does not occur at (2). At (3), K03 changes to 0; the
data of the pin that is interrupt-enabled no longer matches
the data of the input comparison register, so an interrupt
occurs. As already explained, the condition for the interrupt
to occur is the change in the port data and contents of the
input comparison register so they no longer match. Hence,
in (4) or (5), when the nonmatching pattern changes to
another nonmatching pattern or matching pattern, an
interrupt does not occur. Also, pins that have been masked
for interrupt do not affect the conditions for interrupt gen-
eration.
I-30 EPSON S1C62N82 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports)
Input interrupt programing related precautions
When the content of the mask register is rewritten, while the port K
input is in the active status. The input interrupt factor flags are set at
➀ and ➁, ➀ being the interrupt due to the falling edge and ➁ the
interrupt due to the rising edge.
Fig. 4.3.4
Input interrupt timing
When using an input interrupt, if you rewrite the content
of the mask register, when the value of the input terminal
which becomes the interrupt input is in the active status,
the factor flag for input interrupt may be set. Therefore,
when using the input interrupt, the active status of the
input terminal implies
input terminal = Low status, when the falling edge
interrupt is effected and
input terminal = High status, when the rising edge
interrupt is effected.
When an interrupt is triggered at the falling edge of an
input terminal, a factor flag is set with the timing of ➀
shown in Figure 4.3.4. However, when clearing the
content of the mask register with the input terminal kept
in the LOW status and then setting it, the factor flag of
the input interrupt is again set at the timing that has
been set.
Consequently, when the input terminal is in the active
status (Low status), do not rewrite the mask register
(clearing, then setting the mask register), so that a factor
flag will only set at the falling edge in this case. When
clearing, then setting the mask register, set the mask
register, when the input terminal is not in the active
status (High status).
When an interrupt is triggered at the rising edge of the
input terminal, a factor flag will be set at the timing of ➁
shown in Figure 4.3.4. In this case, when the mask
registers cleared, then set, you should set the mask
register, when the input terminal is in the Low status.
Port K input
Factor flag set Not set
➁
Factor flag set
Input comparison
register
Mask register
Active status Active status
Rising edge interrupt
➀
Falling edge interrupt
S1C62N82 TECHNICAL HARDWARE EPSON I-31
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports)
The contents that can be selected with the input port mask
option are as follows:
(1)An internal pull-down resistance can be selected for each
of the five bits of the input ports (K00–K03, K10). Having
selected "Not Use" (pull-down resistance disabled), take
care that the input does not float. Select "Use" (pull-
down resistance enabled) for input ports that are not
being used.
(2)The input interrupt circuit contains a noise rejector to
prevent interrupts from occurring through noise.
Whether or not to use this noise rejector may be selected
for K00–K03 or K10. When "Use" is selected, a maximum
delay of 0.5 ms (fosc1 = 32 kHz) occurs from the time an
interrupt condition is established until the interrupt
factor flag (IK) is set to 1.
Mask option
In addition, when the mask register = 1 and the content
of the input comparison register is rewritten in the input
terminal active status, an input interrupt factor flag may
be set. Thus, you should rewrite the content of the input
comparison register in the mask register = 0 status.
I-32 EPSON S1C62N82 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports)
Tables 4.3.1 (a) and 4.3.1 (b) list the input port control bits
and their addresses.
Table 4.3.1 (a) Input port control bits (1)
Control of input ports
Address Comment
Register
D3 D2 D1 D0 Name SR 1 0
0E0H
0E1H
K03 K02 K01 K00
0 0 0 K10
R
R
K03
K02
K01
K00
–
–
–
–
0
0
0
K10 –
Input port (K10)
Input port (K00–K03)
High
High
High
High
Low
Low
Low
Low
High Low
0E5H
0E6H
KCP03 KCP02 KCP01 KCP00
0 0 0 KCP10
R
R/W
KCP03
KCP02
KCP01
KCP00
0
0
0
0
Input comparison register (K03)
Input comparison register (K02)
Input comparison register (K01)
Input comparison register (K00)
0
0
0
KCP10 0
Input comparison register (K10)
Falling
Falling
Falling
Falling
Rising
Rising
Rising
Rising
Falling Rising
R/W
S1C62N82 TECHNICAL HARDWARE EPSON I-33
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports)
K00–K03, K10
Table 4.3.1 (b) Input port control bits (2)
Input port data (0E0H, 0E1H D0)
The input data of the input port pins can be read with these
registers.
When 1 is read: High level
When 0 is read: Low level
Writing: Invalid
The value read is 1 when the pin voltage of the five bits of
the input ports (K00–K03, K10) goes high (VDD), and 0 when
the voltage goes low (VSS). These bits are reading, so writing
cannot be done.
Address Comment
Register
D3 D2 D1 D0 Name SR 1 0
0E8H
0E9H
EIK03 EIK02 EIK01 EIK00
0 0 0 EIK10
R
R/W
EIK03
EIK02
EIK01
EIK00
0
0
0
0
0
0
0
EIK10 0
Interrupt mask register (K10)
Interrupt mask register (K03)
Interrupt mask register (K02)
Interrupt mask register (K01)
Interrupt mask register (K00)
Enable
Enable
Enable
Enable
Mask
Mask
Mask
Mask
Enable Mask
R/W
0EDH
00IK1IK0
R
0
0
IK1
IK0
0
0
Interrupt factor flag (K10)
Interrupt factor flag (K00–K03)
Yes
Yes
No
No
I-34 EPSON S1C62N82 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports)
Input comparison registers (0E5H, 0E6H D0)
The interrupt conditions for pins K00–K03 and K10 can be
set with these registers.
When 1 is read: Falling edge
When 0 is read: Rising edge
Reading: Valid
Of the five bits of the input ports, the interrupt conditions
can be set for the rising or falling edge of the input for each
of the five bits (K00–K03 and K10) through the input com-
parison registers (KCP00–KCP03 and KCP10).
After an initial reset, these registers are set to 0.
Interrupt mask registers (0E8H, 0E9H D0)
Masking the interrupt of the input port pins can be done
with these registers.
When 1 is written: Enable
When 0 is written: Mask
Reading: Valid
With these registers, masking of the input port bits can be
done for each of the five bits. After an initial reset, these
registers are all set to 0.
Writing to these registers should be done only in the DI
status (interrupt flag = 0). Otherwise, it causes malfunction.
Interrupt factor flags (0EDH D0 and D1)
These flags indicate the occurrence of an input interrupt.
When 1 is read: Interrupt has occurred
When 0 is read: Interrupt has not occurred
Writing: Invalid
The interrupt factor flags IK0 and IK1 are associated with
K00–K03 and K10, respectively. From the status of these
flags, the software can decide whether an input interrupt
has occurred.
These flags are reset when the software has read them.
KCP00–KCP03, KCP10
EIK00–EIK03, EIK10
K0, IK1
S1C62N82 TECHNICAL HARDWARE EPSON I-35
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports)
Note
Reading of interrupt factor flags is available at EI, but be
careful in the following cases.
If the interrupt mask register value corresponding to the
interrupt factor flags to be read is set to 1, an interrupt
request will be generated by the interrupt factor flags set
timing, or an interrupt request will not be generated.
Be very careful when interrupt factor flags are in the same
address.
After an initial reset, these flags are set to 0.
- When input ports are changed from high to low by pull-down
resistance, the fall of the waveform is delayed on account of the
time constant of the pull-down resistance and input gate capaci-
tance. Hence, when fetching input ports, set an appropriate
wait time.
Particular care needs to be taken of the key scan during key
matrix configuration. Aim for a wait time of about 1 ms.
- When "Use" (noise rejector enable) is selected with the mask
option, a maximum delay of 1 ms occurs from time the interrupt
conditions are established until the interrupt factor flag (IK) is
set to 1 (until the interrupt is actually generated).
Hence, pay attention to the timing when reading out (resetting)
the interrupt factor flag.
For example, when performing a key scan with the key matrix,
the key scan changes the input status to set the interrupt factor
flag, so it has to be read out to reset it. However, if the interrupt
factor flag is read out immediately after key scanning, the delay
will cause the flag to be set after read-out, so that it will not be
reset.
I-36 EPSON S1C62N82 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports)
Output Ports (R00–R03, R10–R12)
The S1C62N82 Series have 7 bits for general output ports
(R00–R03 and R10–R12).
Output specifications of the output ports can be selected
individually with the mask option. Two kinds of output
specifications are available: complementary output, and Pch
open drain output. Also, the mask option enables the
output ports R10 and R12 to be used as special output
ports. Figure 4.4.1 shows the configuration of the output
ports.
Configuration of
output ports
4.4
Fig. 4.4.1
Configuration of output
ports
Register
Data bus
Address
VDD
VSS
Rxx
Complementary
Pch open drain
Mask option
S1C62N82 TECHNICAL HARDWARE EPSON I-37
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports)
The mask option enables the following output port selection.
(1)Output specifications of output ports
The output specifications for the output ports (R00–R03,
R10–R12) may be either complementary output or Pch
open drain output for each of the seven bits. However,
even when Pch open drain output is selected, a voltage
exceeding the source voltage must not be applied to the
output port.
(2)Special output
In addition to the regular DC output, special output can
be selected for output ports R10 and R12, as shown in
Table 4.4.1. Figure 4.4.2 shows the structure of output
ports R10–R12.
Pin Name When Special Output is Selected
R12 MO or ENV
R10 FOUT
Mask option
Table 4.4.1
Special output
Fig. 4.4.2
Structure of output port
R10–R12
Address
(0F4H)
FOUT
Data bus
R10
R11
R12
Mask option
Register
(R12)
Register
(R11)
Register
(R10)
MO or
ENV
I-38 EPSON S1C62N82 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports)
When output port R10 is set for FOUT output, it outputs the
clock of fosc3 and fosc1 or the divided fosc1. The clock
frequency is selectable by mask option from the frequencies
listed in Table 4.4.2.
FOUT (R10)
fosc1 / 1
fosc1 / 2
fosc1 / 4
fosc1 / 8
fosc1 / 16
fosc1 / 32
fosc1 / 64
fosc1 / 128
32,768
16,384
8,192
4,096
2,048
1,024
512
256
Setting Value Clock Frequency (Hz)
fosc3 1,000,000 (Typ.)
A hazard may occur when the FOUT signal is turned on or off.
R12 can select the following two functions using the mask
option as special output.
(1)Inverse output (MO) of melody output (MO)
Using the MO and MO terminals together, piezoelectric
buzzer may be driven directly. This means the minimum
number of external parts is necessary to play melodies.
(2)Envelope function
An envelope can be added when playing a melody by
connecting the play sound pressure damping capacitor to
terminal R12.
For details, see Chapter 5, "BASIC EXTERNAL WIRING
DIAGRAM", and Section 4.11, "Melody Generator".
Note
MO, ENV (R12)
Table 4.4.2
FOUT clock frequency
S1C62N82 TECHNICAL HARDWARE EPSON I-39
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports)
Table 4.4.3 lists the output port control bits and their ad-
dresses.
Table 4.4.3 Control bits of output ports
Control of output
ports
Output port data (0F3H, 0F4H D0–D2)
Sets the output data for the output ports.
When 1 is written: High output
When 0 is written: Low output
Reading: Valid
The output port pins output the data written to the corre-
sponding registers (R00–R03, R10–R12) without changing it.
When 1 is written to the register, the output port pin goes
high (VDD), and when 0 is written, the output port pin goes
low (VSS). After an initial reset, all registers are set to 0.
R00–R03, R10–R12
(DC output)
Address Comment
Register
D3 D2 D1 D0 Name SR 1 0
0F3H
R03 R02 R01 R00 R03
R02
R01
R00
0
0
0
0
High
High
High
High
Low
Low
Low
Low
Output port data (R00–R03)
R/W
0F4H
R12
MO
ENV R11 R10
FOUT
R/W
MELD
R12
MO
ENV
R11
R10
FOUT
Melody output mask
Output port data (R12)
Inverting melody output
Melody envelope control
Output port data (R11)
Output port data (R10)
Frequency output
Disable
High
–
–
High
High
ON
Enable
Low
–
–
Low
Low
OFF
0
0
–
Hz
0
0
MELD
I-40 EPSON S1C62N82 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports)
Special output port data (0F4H D2)
This bit will not affect the melody (MO) or envelope (ENV)
signal at Rl2. R12 register is a general purpose register
which can be read and written.
When 1 is written: No effect at R12
When 0 is written: No effect at R12
Reading: Valid
Special output port data (0F4H D0)
Controls the FOUT (clock) output.
When 1 is written: Clock output
When 0 is written: Low level (DC) output
Reading: Valid
FOUT output can be controlled by writing data to R10. After
an initial reset, this register is set to 0.
Figure 4.4.3 shows the output waveform for FOUT output.
R12 (when MO or ENV is
selected)
R10 (when FOUT is
selected)
R10 Register
FOUT output
waveform
01
Fig. 4.4.3
FOUT output waveform
Note A hazard may occur when the FOUT signal is turned on or off.
S1C62N82 TECHNICAL HARDWARE EPSON I-41
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports)
I/O Ports (P00–P03)
The S1C62N82 Series have a 4-bit general-purpose I/O port.
Figure 4.5.1 shows the configuration of the I/O port. The
four bits of the I/O port P00–P03 can be set to either input
mode or output mode. The mode can be set by writing data
to the I/O control register (IOC).
4.5
Configuration of I/O
port
Fig. 4.5.1
Configuration of I/O port
Input or output mode can be set for the four bits of I/O port
P00–P03 by writing data into I/O control register IOC.
To set the input mode, 0 is written to the I/O control regis-
ter. When an I/O port is set to input mode, its impedance
becomes high and it works as an input port. However, the
input line is pulled down when input data is read.
The output mode is set when 1 is written to the I/O control
register (IOC). When an I/O port set to output mode works
as an output port, it outputs a high signal (VDD) when the
port output data is 1, and a low signal (VSS) when the port
output data is 0.
After an initial reset, the I/O control register is set to 0, and
the I/O port enters the input mode.
I/O control register
and I/O mode
Address
Register
Input
control
I/O control
register
(IOC)
Data bus
Pxx
V
SS
Address
I-42 EPSON S1C62N82 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports)
The output specification during output mode (IOC = 1) of the
I/O port can be set with the mask option for either comple-
mentary output or Pch open drain output. This setting can
be performed for each bit of the I/O port. However, when
Pch open drain output has been selected, voltage in excess
of the supply voltage must not be applied to the port.
Table 4.5.1 lists the I/O port control bits and their ad-
dresses.
Mask option
Control of I/O port
Table 4.5.1 I/O port control bits
I/O port data (0F6H)
I/O port data can be read and output data can be written
through the port.
• When writing data
When 1 is written: High level
When 0 is written: Low level
When an I/O port is set to the output mode, the written
data is output from the I/O port pin unchanged. When 1
is written as the port data, the port pin goes high (VDD),
and when 0 is written, the level goes low (VSS). Port data
can also be written in the input mode.
P00–P03
Address Comment
Register
D3 D2 D1 D0 Name SR 1 0
0F6H
P03 P02 P01 P00 P03
P02
P01
P00
–
–
–
–
I/O port (P00–P03)
High
High
High
High
Low
Low
Low
Low
R/W
0FCH
CLKCHG OSCC 0 IOC CLKCHG
OSCC
0
IOC
0
0
0
CPU clock switch
OSC3 oscillator ON/OFF
I/O port P00–P03 Input/Output
OSC3
ON
Output
OSC1
OFF
Input
R/W
R/W R
S1C62N82 TECHNICAL HARDWARE EPSON I-43
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports)
• When reading data
When 1 is read: High level
When 0 is read: Low level
The pin voltage level of the I/O port is read. When the I/
O port is in the input mode the voltage level being input
to the port pin can be read; in the output mode the
output voltage level can be read. When the pin voltage is
high (VDD) the port data read is 1, and when the pin
voltage is low (VSS) the data is 0. Also, the built-in pull-
down resistance functions during reading, so the I/O port
pin is pulled down.
- When the I/O port is set to the output mode and a low-imped-
ance load is connected to the port pin, the data written to the
register may differ from the data read.
- When the I/O port is set to the input mode and a low-level
voltage (Vss) is input by the built-in pull-down resistance, an
erroneous input results if the time constant of the capacitive
load of the input line and the built- in pull-down resistance load
is greater than the read-out time. When the input data is being
read, the time that the input line is pulled down is equivalent to
0.5 cycles of the CPU system clock. Hence, the electric poten-
tial of the pins must settle within 0.5 cycles. If this condition
cannot be met, some measure must be devised, such as
arranging a pull-down resistance externally, or performing
multiple read-outs.
Note
I-44 EPSON S1C62N82 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports)
IOC I/O control register (0FCH D0)
The input or output I/O port mode can be set with this
register.
When 1 is written: Output mode
When 0 is written: Input mode
Reading: Valid
The input or output mode of the I/O port is set in units of
four bits. For instance, IOC sets the mode for P00–P03.
Writing 1 to the I/O control register makes the I/O port
enter the output mode, and writing 0, the input mode.
After an initial reset, the IOC register is set to 0, so the I/O
port is in the input mode.
S1C62N82 TECHNICAL HARDWARE EPSON I-45
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)
LCD Driver
In the S1C62N82 Series, when selecting 1/8 duty, there are
8 common terminals (COM0–COM7) and 38 segment termi-
nals (SEG0–SEG37) available which allow up to 304 (i.e., 38
× 8) LCD segments to be driven. During selection of 1/4
duty, there are 4 common terminals (COM0–COM3) and 42
segment terminals (SEG0–SEG41) available which allow up
to 168 (i.e., 42 × 4) LCD segments to be driven.
1/8 duty and 1/4 duty may be selected by mask option.
Because the power for LCD driving is produced through the
internal circuit of the CPU, there is no particular need to
externally supply it.
Driving method is 1/8 duty dynamic driving through VDD,
VL1, VL2, VL3 and VL4 (or VDD, VL1, VL2 and VL3 if 1/4 duty
were selected). The frame frequency is 32 Hz (fosc1 =
32,768 Hz) for both 1/8 and 1/4 duties. Figure 4.6.1 shows
the drive waveform for 1/4 duty, and Figure 4.6.2 shows the
drive waveform for 1/8 duty.
fosc1 indicates the oscillation frequency of the oscillation circuit.
In case 1/4 duty was selected with the mask option, set CD and
VL4 to N.C. (not connected). (Refer to Chapter 5, "BASIC EXTER-
NAL WIRING DIAGRAM".)
Configuration of LCD
driver
4.6
Note
I-46 EPSON S1C62N82 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)
Fig. 4.6.1
Drive waveform for
1/4 duty
LCD lighting status
COM0
COM1
COM2
COM3
Not lit
Lit
-V
-V
-V
-V
-V
-V
-V
-V
COM0
COM1
COM2
COM3
SEG
0–41
Frame frequency
SEG0–41
DD
L1
L2
L3
DD
L1
L2
L3
S1C62N82 TECHNICAL HARDWARE EPSON I-47
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)
Fig. 4.6.2
Drive waveform for
1/8 duty
COM0
COM1
COM2
0123456701234567
V
DD
V
L1
V
L2
V
L3
V
L4
V
DD
V
L1
V
L2
V
L3
V
L4
V
DD
V
L1
V
L2
V
L3
V
L4
V
DD
V
L1
V
L2
V
L3
V
L4
V
DD
V
L1
V
L2
V
L3
V
L4
V
DD
V
L1
V
L2
V
L3
V
L4
V
DD
V
L1
V
L2
V
L3
V
L4
SEG0–37
LCD lighting status
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
Not lit
Lit
SEG0–37
Frame frequency
I-48 EPSON S1C62N82 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)
The S1C62N82 Series members allow software setting of the
LCD static drive. This function enables easy adjustment
(cadence adjustment) of the oscillation frequency of the OSC
circuit.
The procedure for executing of the LCD static drive is as
follows:
➀Write 1 to the CSDC register at address 0FBH D3.
➁Write the same value to all registers corresponding to
COM0–COM7 of the display memory.
- Even in case 1/4 duty were selected, when SEG terminal is set
to static driving, set the same values on all the display memo-
ries corresponding to COM4–COM7.
- For cadence adjustment, set the display data including display
data corresponding to COM7, so that all the LCD segments go
on.
Figures 4.6.3 and 4.6.4 shows the drive waveform for static
drive.
Switching between
dynamic and static
drive
Fig. 4.6.4
LCD static drive
waveform (1/8 duty)
Fig. 4.6.3
LCD static drive
waveform (1/4 duty)
SEG
0–41
COM
0–3
Frame frequency
LCD lighting status
COM0
COM1
COM2
COM3
SEG0–41
-V
-V
-V
-V
-V
-V
-V
-V
-V
-V
-V
-V
Not lit Lit
DD
L1
L2
L3
DD
L1
L2
L3
DD
L1
L2
L3
Note
SEG
0–37
COM
0–7
Frame frequency
LCD lighting status
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
-V
-V
-V
-V
-V
-V
-V
-V
-V
-V
-V
-V
-V
-V
-V
Not lit
Lit
DD
L1
L2
L3
L4
DD
L1
L2
L3
L4
DD
L1
L2
L3
L4
S1C62N82 TECHNICAL HARDWARE EPSON I-49
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)
(1)Segment allocation
As shown in Figure 4.l.1, the S1C62N82 Series display
data is decided by the display data written to the display
memory (write-only) at address 090H–0DFH.
The address and bits of the display memory can be made
to correspond to the segment pins (SEG0–SEG41) in any
combination through mask option. This simplifies design
by increasing the degree of freedom with which the liquid
crystal panel can be designed.
Figure 4.6.5 shows an example of the relationship be-
tween the LCD segments (on the panel) and the display
memory in the case of 1/4 duty.
Mask option
(segment allocation)
Fig. 4.6.5
Segment allocation
a
f
g
e
dp
c
SEG10 SEG11
Common 0
Common 1
Common 2
0A0H
0A1H
Address
d
p
D3
c
g
D2
b
f
D1
a
e
D0
Data
Display data memory allocation
SEG10
SEG11
A1, D1
(f)
A0, D0
(a)
A1, D0
(e)
A1, D2
(g)
A0, D2
(c)
A0, D1
(b)
Pin address allocation
Common 0 Common 1 Common 2
A0, D3
(d)
A1, D3
(p)
Common 3
Common 3
b
I-50 EPSON S1C62N82 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)
(2)Drive duty
According to the mask option, either 1/4 or 1/8 duty can
be selected as the LCD drive duty.
Table 4.6.1 shows the differences in the number of seg-
ments according to the selected duty.
Pins Used Maximum Number Frame Frequency
in Common of Segments (when fosc1 = 32 kHz)
1/4 COM0–3 168 (42 × 4) 32 Hz
1/8 COM0–7 304 (38 × 8) 32 Hz
(3)Output specification
➀The segment pins (SEG0–SEG41) are selected by mask
option in pairs for either segment signal output or DC
output (VDD and VSS binary output). When DC output
is selected, the data corresponding to COM0 of each
segment pin is output.
➁When DC output is selected, either complementary
output or Pch open drain output can be selected for
each pin by mask option.
The pin pairs are the combination of SEG (2
*
n) and SEG (2
*
n +
1) (where n is an integer from 0 to 20).
Table 4.6.1
Differences according to
selected duty
Note
Duty
S1C62N82 TECHNICAL HARDWARE EPSON I-51
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)
Table 4.6.2 shows the control bits of the LCD driver and
their addresses. Figure 4.6.6 shows the display memory
map.
Table 4.6.2 Control bits of LCD driver
Control of LCD
driver
Fig. 4.6.6
Display
memory map
Address 0123456789ABCDEF
090
0A0
0B0
0C0
0D0
Display memory (R/W)
80 words x 4 bits
In the display memory (80 words × 4 bits), the memory
which is not assigned may be used as general-purpose RAM.
Address Comment
Register
D3 D2 D1 D0 Name SR 1 0
0FBH
CSDC 0 CMPDT CMPON
R
0
1
0
LCD drive switch
Voltage comparator ON/OFF
Static
+ > -
ON
Dynamic
- > +
OFF
R/W R/W
CSDC
0
CMPDT
CMPON
Comparator's voltage condition:
1 = CMPP(+)input > CMPM(-)input,
0 = CMPM(-)input > CMPP(+)input
I-52 EPSON S1C62N82 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver)
CSDC
Display memory
LCD drive switch (0FBH D3)
The LCD drive format can be selected with this switch.
When 1 is written: Static drive
When 0 is written: Dynamic drive
Reading: Valid
After an initial reset, dynamic drive (CSDC = 0) is selected.
(090H–0DFH)
The LCD segments are turned on or off according to this
data.
When 1 is written: On
When 0 is written: Off
Reading: Valid
By writing data into the display memory allocated to the
LCD segment (on the panel), the segment can be turned on
or off. After an initial reset, the contents of the display
memory are undefined.
The contents of the display memory is indefinite during initial reset
and until the display memory is initialized (i.e., through memory
clearing process from the CPU, etc.), the data of the memory and
the contents of LCD display will not match.
Perform display memory initialization through initializing processes.
Note
S1C62N82 TECHNICAL HARDWARE EPSON I-53
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer)
Clock Timer
The S1C62N82 Series have a built-in clock timer driven by
the source oscillator. The clock timer is configured as a
seven-bit binary counter that serves as a frequency divider
taking a 256 Hz source clock from a prescaler. The four
high-order bits (16 Hz–2 Hz) can be read by the software.
Figure 4.7.1 is the block diagram of the clock timer.
Normally, this clock timer is used for all kinds of timing
purpose, such as clocks.
4.7
Configuration of
clock timer
Fig. 4.7.1
Block diagram of
clock timer
128 Hz–32 Hz
Data bus
32 Hz, 8 Hz, 2 Hz
256 Hz
Clock timer reset signal
OSC
(oscillation
circuit)
Interrupt
request
Interrupt
control
16 Hz–2 Hz
I-54 EPSON S1C62N82 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer)
The clock timer can interrupt on the falling edge of the 32
Hz, 8 Hz, and 2 Hz signals. The software can mask any of
these interrupt signals.
Figure 4.7.2 is the timing chart of the clock timer.
Interrupt function
As shown in Figure 4.7.2, an interrupt is generated on the
falling edge of the 32 Hz, 8 Hz, and 2 Hz frequencies. When
this happens, the corresponding interrupt event flag (IT32,
IT8, IT2) is set to 1. Masking the separate interrupts can be
done with the interrupt mask register (EIT32, EIT8, EIT2).
However, regardless of the interrupt mask register setting,
the interrupt event flags will be set to 1 on the falling edge of
their corresponding signal (e.g. the falling edge of the 2 Hz
signal sets the 2 Hz interrupt factor flag to 1).
Reading of interrupt factor flags is available at EI, but be careful in
the following cases.
If the interrupt mask register value corresponding to the interrupt
factor flags to be read is set to 1, an interrupt request will be
generated by the interrupt factor flags set timing, or an interrupt
request will not be generated.
Be very careful when interrupt factor flags are in the same address.
Clock timer timing chart
Frequency
Register
bits
Address
0E4H
D0 16 Hz
D1
D2
D3
8 Hz
4 Hz
2 Hz
Occurrence of
32 Hz interrupt request
Occurrence of
8 Hz interrupt request
Occurrence of
2 Hz interrupt request
Fig. 4.7.2 Timing chart of the clock timer
Note
S1C62N82 TECHNICAL HARDWARE EPSON I-55
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer)
Table 4.7.1 shows the clock timer control bits and their
addresses.
Control of clock
timer
Table 4.7.1 Control bits of clock timer
Address Comment
Register
D3 D2 D1 D0 Name SR 1 0
0E4H
TM3 TM2 TM1 TM0
R
TM3
TM2
TM1
TM0
–
–
–
–
Timer data (clock timer 2 Hz)
Timer data (clock timer 4 Hz)
Timer data (clock timer 8 Hz)
Timer data (clock timer 16 Hz)
High
High
High
High
Low
Low
Low
Low
0EBH
0 EIT2 EIT8 EIT32
R
0
EIT2
EIT8
EIT32
0
0
0
Enable
Enable
Enable
Mask
Mask
Mask
Interrupt mask register (clock timer 2 Hz)
Interrupt mask register (clock timer 8 Hz)
Interrupt mask register (clock timer 32 Hz)
R/W
0EFH
0 IT2 IT8 IT32 0
IT2
IT8
IT32
0
0
0
Yes
Yes
Yes
No
No
No
Interrupt factor flag (clock timer 2 Hz)
Interrupt factor flag (clock timer 8 Hz)
Interrupt factor flag (clock timer 32 Hz)
R
0F9H
0 TMRST SWRUN SWRST
W
0
TMRST
SWRUN
SWRST
Reset
0
Reset
Clock timer reset
Stopwatch timer RUN/STOP
Stopwatch timer reset
Reset
Run
Reset
–
Stop
–
R/W WR
I-56 EPSON S1C62N82 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer)
Timer data (0E4H)
The 16 Hz to 2 Hz timer data of the clock timer can be read
from this register. These four bits are read-only, and write
operations are invalid.
After an initial reset, the timer data is initialized to 0H.
Interrupt mask registers (0EBH D0–D2)
These registers are used to mask the clock timer interrupt.
When 1 is written: Enabled
When 0 is written: Masked
Reading: Valid
The interrupt mask register bits (EIT32, EIT8, EIT2) mask
the corresponding interrupt frequencies (32 Hz, 8 Hz, 2 Hz).
Writing to the interrupt mask registers should be done only
in the DI status. Otherwise, it causes malfunction.
After an initial reset, these registers are all set to 0.
Interrupt factor flags (0EFH D0–D2)
These flags indicate the status of the clock timer interrupt.
When 1 is read: Interrupt has occurred
When 0 is read: Interrupt has not occurred
Writing: Invalid
The interrupt factor flags (IT32, IT8, IT2) correspond to the
clock timer interrupts (32 Hz, 8 Hz, 2 Hz). The software can
determine from these flags whether there is a clock timer
interrupt. However, even if the interrupt is masked, the
flags are set to 1 on the falling edge of the signal. These
flags can be reset when the register is read by the software.
Reading of interrupt factor flags is available at EI, but be
careful in the following cases.
If the interrupt mask register value corresponding to the
interrupt factor flags to be read is set to 1, an interrupt
request will be generated by the interrupt factor flags set
timing, or an interrupt request will not be generated.
Be very careful when interrupt factor flags are in the same
address.
After an initial reset, these flags are set to 0.
TM0–TM3
EIT32, EIT8, EIT2
IT32, IT8, IT2
S1C62N82 TECHNICAL HARDWARE EPSON I-57
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer)
TMRST Clock timer reset (0F9H D2)
This bit resets the clock timer.
When 1 is written: Clock timer reset
When 0 is written: No operation
Reading: Always 0
The clock timer is reset by writing 1 to TMRST. The clock
timer starts immediately after this. No operation results
when 0 is written to TMRST.
This bit is write-only, and so is always 0 when read.
I-58 EPSON S1C62N82 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Stopwatch Timer)
Stopwatch Timer
The S1C62N82 Series incorporate a 1/100 sec and 1/10 sec
stopwatch timer. The stopwatch timer is configured as a
two-stage, four-bit BCD timer serving as the clock source for
an approximately 100 Hz signal (obtained by approximately
dividing the 256 Hz signal output from the prescaler). Data
can be read out four bits at a time by the software.
Figure 4.8.1 is the block diagram of the stopwatch timer.
Configuration of
stopwatch timer
4.8
The stopwatch timer can be used separately from the clock
timer. In particular, digital stopwatch functions can be
easily realized by software.
Fig. 4.8.1
Block diagram of stop-
watch timer
SWL timer
Data bus
10 Hz, 1 Hz
256 Hz
Stopwatch timer reset signal
Stopwatch timer RUN/STOP signal
OSC
(oscillation
circuit)
Interrupt
request
Interrupt
control
10 Hz SWH timer
S1C62N82 TECHNICAL HARDWARE EPSON I-59
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Stopwatch Timer)
The stopwatch timer is configured as two four-bit BCD
timers, SWL and SWH. The SWL timer, at the stage preced-
ing the stopwatch timer, has an approximate 100 Hz signal
as its input clock. It counts up every 1/100 sec and gener-
ates an approximate 10 Hz signal. The SWH timer has an
approximate 10 Hz signal generated by the SWL timer for its
input clock. It counts up every 1/10 sec and generates a 1
Hz signal.
Figure 4.8.2 shows the count-up pattern of the stopwatch
timer.
Count-up pattern
Fig. 4.8.2
Count-up pattern of
stopwatch timer
SWL generates an approximate 10 Hz signal from the 256
Hz based signal. The count-up intervals are 2/256 sec and
3/256 sec, so that two final patterns are generated: a 25/
256 sec interval and a 26/256 sec interval. Consequently,
the count-up intervals are 2/256 sec and 3/256 sec, which
do not amount to an accurate 1/100 sec. SWH counts the
approximate 10 Hz signals generated by the 25/256 sec and
26/256 sec intervals in the ratio of 4:6 to generate a 1 Hz
signal. The count-up intervals are 25/256 sec and 26/256
sec, which do not amount to an accurate 1/10 sec.
26
256 26
256
26
256
26
256
26
256
26
256 25
256 25
256 25
256 25
256
3
256 2
256 3
256 2
256
2
256
2
256 3
256
3
256
3
256 2
256
3
256 2
256
3
256 3
256 3
256 3
256 3
256
2
256 2
256 2
256
26
256
25
256
26
256 25
256
x 6 + x 4 = 1 (S)
0 1 2 3 4 5 6 7 8 9 0
0 1 2 3 4 5 6 7 8 9 0
0 1 2 3 4 5 6 7 8 9 0
1 Hz
signal
generation
Approximate
10 Hz
signal
generation
Approximate
10 Hz
signal
generation
SWH count value
Counting time (S)
(S)
(S)
SWL count value
Counting time (S)
SWL count value
Counting time (S)
SWH count-up pattern
SWL count-up pattern 1
SWL count-up pattern 2
I-60 EPSON S1C62N82 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Stopwatch Timer)
The 10 Hz (approximate 10 Hz) and 1 Hz interrupts can be
generated by the overflow of the SWL and SWH stopwatch
timers, respectively. Also, software can separately mask the
frequencies as described earlier.
Figure 4.8.3 is the timing chart for the stopwatch timer.
Interrupt function
Address
Address
Register bit Stopwatch timer (SWL) timing chart
Stopwatch timer (SWH) timing chart
Occurrence of
10 Hz interrupt request
Occurrence of
1 Hz interrupt request
0E3H
(1/10 sec BCD)
0E2H
(1/100 sec BCD)
D0
D1
D2
D3
D0
D1
D2
D3
Register bit
Fig. 4.8.3
Timing chart for
stopwatch timer
As shown in Figure 4.8.3, the interrupts are generated by
the overflow of the respective timers (9 changing to 0). Also
when this happens, the corresponding interrupt factor flags
(ISW0, ISW1) are set to 1. The respective interrupts can be
masked separately with the interrupt mask registers
(EISW0, EISW1). However, regardless of the setting of the
interrupt mask registers, the interrupt factor flags are set to
1 by the overflow of the corresponding timers.
Reading of interrupt factor flags is available at EI, but be careful in
the following cases. If the interrupt mask register value corre-
sponding to the interrupt factor flags to be read is set to 1, an
interrupt request will be generated by the interrupt factor flags set
timing, or an interrupt request will not be generated.
Be very careful when interrupt factor flags are in the same address.
Note
S1C62N82 TECHNICAL HARDWARE EPSON I-61
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Stopwatch Timer)
Table 4.8.1 shows the stopwatch timer control bits and their
addresses.
Table 4.8.1 Stopwatch timer control bits
Control of stopwatch
timer
Address Comment
Register
D3 D2 D1 D0 Name SR 1 0
0E2H
0E3H
SWL3 SWL2 SWL1 SWL0
SWH3 SWH2 SWH1 SWH0
R
R
SWL3
SWL2
SWL1
SWL0
0
0
0
0
SWH3
SWH2
SWH1
SWH0
0
0
0
0
MSB
Stopwatch timer
1/100 sec (BCD)
LSB
MSB
Stopwatch timer
1/10 sec (BCD)
LSB
0EAH
0 0 EISW1 EISW0
R
0
0
EISW1
EISW0
0
0
Interrupt mask register (stopwatch 1 Hz)
Interrupt mask register (stopwatch 10 Hz)
Enable
Enable
Mask
Mask
R/W
0EEH
0 0 ISW1 ISW0
R
0
0
ISW1
ISW0
0
0
Interrupt factor flag (stopwatch 1 Hz)
Interrupt factor flag (stopwatch 10 Hz)
Yes
Yes
No
No
0F9H
0 TMRST SWRUN SWRST
W
0
TMRST
SWRUN
SWRST
Reset
0
Reset
Clock timer reset
Stopwatch timer RUN/STOP
Stopwatch timer reset
Reset
Run
Reset
–
Stop
–
R/W WR
I-62 EPSON S1C62N82 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Stopwatch Timer)
1/100 sec stopwatch timer (0E2H)
Data (BCD) of the 1/100 sec column of the stopwatch timer
can be read. These four bits are read-only, and cannot be
written to.
After an initial reset, the timer data is set to 0H.
1/10 sec stopwatch timer (0E3H)
Data (BCD) of the 1/10 sec column of the stopwatch timer
can be read. These four bits are read-only, and cannot be
written to.
After an initial reset, the timer data is set to 0H.
Interrupt mask register (0EAH D0 and D1)
These registers mask the stopwatch timer interrupt.
When 1 is written: Enabled
When 0 is written: Masked
Reading: Valid
The interrupt mask register bits (EISW0, EISW1) are used to
mask the 10 Hz and 1 Hz interrupts, respectively. Writing
to the interrupt mask registers should be done only in the
DI status (interrupt flag = 0). Otherwise, it causes malfunc-
tion.
After an initial reset, these registers are both set to 0.
Interrupt factor flags (0EEH D0 and D1)
These flags indicate the status of the stopwatch timer inter-
rupt.
When 1 is read: Interrupt has occurred
When 0 is read: Interrupt has not occurred
Writing: Invalid
The interrupt factor flags (ISW0, ISW1) correspond to the 10
Hz and 1 Hz interrupts, respectively. With these flags, the
software can determine whether a stopwatch timer interrupt
has occurred. However, regardless of the interrupt mask
register setting, these flags are set to 1 by the timer over-
flow. They are reset when the register is read by the soft-
ware.
SWL0–SWL3
EISW0, EISW1
SWH0–SWH3
ISW0, ISW1
S1C62N82 TECHNICAL HARDWARE EPSON I-63
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Stopwatch Timer)
Reading of interrupt factor flags is available at EI, but be
careful in the following cases. If the interrupt mask register
value corresponding to the interrupt factor flags to be read
is set to 1, an interrupt request will be generated by the
interrupt factor flags set timing, or an interrupt request will
not be generated.
Be very careful when interrupt factor flags are in the same
address.
After an initial reset, these flags are set to 0.
Stopwatch timer reset (0F9H D0)
This bit resets the stopwatch timer.
When 1 is written: Stopwatch timer reset
When 0 is written: No operation
Reading: Always 0
The stopwatch timer is reset when 1 is written to SWRST.
When the stopwatch timer is reset while running, operation
restarts immediately. Also, while stopped, the reset data is
maintained.
This bit is write-only, and is always 0 when read.
Stopwatch timer run/stop (0F9H D1)
This bit controls run/stop of the stopwatch timer.
When 1 is written: Run
When 0 is written: Stop
Reading: Valid
The stopwatch timer runs when 1 is written to SWRUN, and
stops when 0 is written.
When stopped, the timer data is maintained until the timer
next Run or is reset. Also, when the timer runs after being
stopped, the data that was maintained can be used to re-
sume the count.
If the timer data is read while running, a correct read may
be impossible because of the carry from the low-order bit
(SWL) to the high-order bit (SWH). This occurs if reading
has extended over the SWL and SWH bits when the carry
occurs. To prevent this, read after stopping, and then
continue running. Also, the stopped duration must be
within 976 µs (256 Hz, 1/4 cycle).
After an initial reset, this register is set to 0.
SWRST
SWRUN
I-64 EPSON S1C62N82 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (SVD Circuit and Heavy Load Protection Function)
Supply Voltage Detection (SVD) Circuit and
Heavy Load Protection Function
The S1C62N82 Series have a built-in supply voltage detec-
tion (SVD) circuit and a heavy load protection function.
Figure 4.9.1 shows the configuration of the circuit.
SVD circuit
The SVD circuit monitors the conditions of the supply
voltage (battery voltage), and software can check whether
the supply voltage has dropped below the detecting voltage
level of the SVD circuit: 2.4 V when supply voltage is 3.0 V
(S1C62N82), or 1.2 V when supply voltage is 1.5 V
(S1C62L82). Registers SVDON (SVD control on/off) and
SVDDT (SVD data) are used for the SVD circuit. The soft-
ware can turn SVD operation on and off. When SVD is on,
the IC draws a large current, so keep SVD off unless it is.
Heavy load protection function circuit
When using the S1C62N82, the melody, lamp, and other
features impose a heavy load on the battery. Therefore, a
heavy load protection function is incorporated in case of a
voltage drop. Software-initiated switching can be effected in
heavy load protection mode. The HLMOD register controls
the heavy load protection function. Conversely, when the
SVD circuit detects a voltage drop below 1.2 V (S1C62L82),
or 2.4 V (S1C62N82/62A82), switching to heavy load protec-
tion mode is carried out automatically.
This function enables 0.9 V operation (S1C62L82).
In the heavy load protection mode, the SVD circuit is acti-
vated intermittently by hardware. The cycle is 2 Hz and the
operating time is 122 µs (when the oscillation frequency,
fosc1, of the oscillation circuit is 32,768 Hz).
4.9
Configuration of SVD
circuit and heavy
load protection
function
S1C62N82 TECHNICAL HARDWARE EPSON I-65
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (SVD Circuit and Heavy Load Protection Function)
If the source voltage is reduced by a heavy load while in the
heavy load protection mode, the rate of decrease can be
detected by hardware. After this, the heavy load is lost and
even when the heavy load protection mode is released by
software, the mode continues until the source voltage ex-
ceeds the voltage detected by the SVD circuit. Therefore,
malfunctioning due to a reduced source voltage can be
prevented completely.
Since supply voltage detection is automatically performed by
the hardware every 2 Hz (0.5 sec) when the heavy load
protection function operates, do not permit the operation of
the SVD circuit by the software in order to minimize power
current consumption.
V
V
HLMOD
SVDDT
SVDON
SVD
circuit
Regulated
voltage
circuit
Data bus
Address 0FAH
SVD
sampling
control
S1
L2
D3
D1
D0
V
SS
V
SS
Fig. 4.9.1
Configuration of SVD and
heavy load protection circuits
I-66 EPSON S1C62N82 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (SVD Circuit and Heavy Load Protection Function)
The following explains the timing when the SVD circuit
writes the result of supply voltage detection to the SVDDT
register.
The result of supply voltage detection is written to the
SVDDT register by the SVD circuit, and this data can be
read by the software to determine the supply voltage.
There are two methods, explained below, for executing the
detection by the SVD circuit.
(1)Sampling with HLMOD set to 1
When HLMOD is set to 1 and SVD sampling is executed,
the detection results can be written to the SVDDT regis-
ter with the following timing:
Immediately after sampling with the 2 Hz cycle output by
the oscillation circuit while HLMOD = 1 (sampling time is
122 µs in the case of fosc1 = 32,768 Hz).
Consequently, after HLMOD has been set to 1, the new
detection result is written in a 2 Hz.
(2)Sampling with SVDON set to 1
When SVDON is set to 1, SVD detection is executed. As
soon as SVDON is reset to 0, the result is loaded to in the
SVDDT register. To obtain a stable SVD detection result,
the SVD circuit must be on for at least 100 µs. So, to
obtain the SVD detection result, follow the programming
sequence below.
➀Set SVDON to 1
➁Maintain for 100 µs minimum
➂Set SVDON to 0
➃Read SVDDT
However, at 32 kHz for the S1C62N82 and S1C62L82,
the instruction cycles are long enough, so there is no
need to worry about maintaining 100 µs for SVDON = 1
in the software.
Operation of SVD
detection timing
S1C62N82 TECHNICAL HARDWARE EPSON I-67
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (SVD Circuit and Heavy Load Protection Function)
Notice that even if the SVD circuit detects a drop in the
supply voltage (1.2 V/2.4 V or less) and invokes the heavy
load protection mode, this will be the same as when the
software invokes the heavy load protection mode, in that the
SVD circuit will be sampled with a timing synchronized to
the 2 Hz output from the prescaler. If the SVD circuit
detects a voltage drop and enters the heavy load protection
mode, it will return to the normal mode once the supply
voltage recovers and the SVD circuit determines that the
supply voltage is 1.2 V/2.4 V or more.
The S1C62N82 has a heavy load protection function for
when the battery load becomes heavy and the supply voltage
drops, such as when a melody is played or an external lamp
lights. This functions works in the heavy load protection
mode. The normal mode changes to the heavy load protec-
tion mode in the following two cases:
➀When the software changes the mode to the heavy load
protection mode
➁When the SVD circuit detects a supply voltage less than
2.4 V (S1C62N82/62A82) or 1.2 V (S1C62L82), in which
case the mode is automatically changed to the heavy load
protection mode
Based on the operation of the SVD circuit and the heavy
load protection function, the S1C62L82 obtains an opera-
tion supply voltage as low as 0.9 V. See the electrical char-
acteristics for the precision of voltage detection by the SVD
circuit.
In the heavy load protection mode, the internally regulated
voltage is generated by the liquid crystal driver supply
output, VL2, in order to operate the internal circuit. Conse-
quently, more current is consumed in the heavy load protec-
tion mode than in the normal mode. Unless necessary, do
not select the heavy load protection mode with the software.
Activation of the SVD circuit by software in the heavy load protec-
tion mode causes a malfunction. Avoid such activation if possible.
Note
Operation of heavy
load protection
function
I-68 EPSON S1C62N82 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (SVD Circuit and Heavy Load Protection Function)
Table 4.9.1 shows the control bits and their addresses for
the SVD circuit and the heavy load protection function.
Table 4.9.1 Control bits for SVD circuit and heavy load protection function
Control of SVD cir-
cuit and heavy load
protection function
Heavy load protection mode on/off (0FAH D3)
When 1 is written: Heavy load protection mode on
When 0 is written: Heavy load protection mode off
Reading: Valid
When HLMOD is set to 1, the IC enters the heavy load
protection mode, and sampling control is executed for the
time the SVD circuit is on. The sampling timing is as fol-
lows:
Sampling in cycles of 2 Hz output by the oscillation circuit
while HLMOD = 1 (sampling time is 122 µs in the case of
fosc1 = 32,768 Hz).
When SVD sampling is done with HLMOD set to 1, the
results are written to the SVDDT register with the as follow-
ing timing:
Immediately on completion of sampling in cycles of 2 Hz
output by the oscillation circuit while HLMOD = 1.
Consequently, after HLMOD is set to 1, the new detected
result is written in 2 Hz.
In the heavy load protection mode, the consumed current
becomes larger. Unless necessary, do not select the heavy
load protection mode with the software.
HLMOD
Address Comment
Register
D3 D2 D1 D0 Name SR 1 0
0FAH
HLMOD 0 SVDDT SVDON HLMOD
0
SVDDT
SVDON
0
0
0 ON OFF
Heavy load protection mode register
Supply voltage detector data
Supply voltage detector ON/OFF
RR/W R/W
Heavy
load
Supply
voltage
low
Normal
load
Supply
voltage
normal
S1C62N82 TECHNICAL HARDWARE EPSON I-69
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (SVD Circuit and Heavy Load Protection Function)
SVDDT
SVDON SVD control on/off (0FAH D0)
When 0 is written: SVD detection off
When 1 is written: SVD detection on
Reading: Valid
When this bit is written, the SVD detection on/off operation
is controlled. Large current is drawn during SVD detection,
so keep SVD detection off except when necessary. When
SVDON is set to 1, SVD detection is executed. As soon as
SVDON is reset to 0, the detected result is loaded into the
SVDDT register.
SVD data (0FAH D1)
When 0 is read: Supply voltage ≥ Criteria voltage
When 1 is read: Supply voltage < Criteria voltage
When SVDDT is 1, the S1C62N82 enters the heavy load
protection mode. In this mode, the detection operation of
the SVD circuit is sampled in 2 Hz cycles and the respective
detection results are written to the SVDDT register.
I-70 EPSON S1C62N82 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Analog Voltage Comparator)
Analog Voltage Comparator
The S1C62N82 Series have a built-in analog voltage com-
parator that compares two analog input voltages to produce
result data 0 or 1 in register CMPDT, according to the com-
pared voltages, CMPP and CMPM. The configuration of the
analog voltage comparator circuit is shown in Figure 4.10.1.
The voltage comparator has two analog voltage inputs,
CMPP (non-inverting input, +) and CMPM (inverting input,
-). When the voltage comparator is turned on by control
register CMPON, the result of comparing CMPP and CMPM
will be stored in register CMPDT. Therefore, the result in
the register will indicate whether CMPP is greater than
CMPM (when CMPDT = 1) or smaller than CMPM (when
CMPDT = 0).
4.10
Configuration of
analog voltage
comparator
CMPON
Output
control
Power
control
Data bus (D1)
Address (0FBH)
Data bus (D0)
Address (0FBH)
CMPP
CMPM
V
DD
V
SS
CMPDT
Fig. 4.10.1
Configuration of analog
voltage comparator circuit
S1C62N82 TECHNICAL HARDWARE EPSON I-71
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Analog Voltage Comparator)
Two registers, CMPON and CMPDT, are used in the analog
voltage comparator. The CMPON register switches the
analog voltage comparator on or off to reduce power con-
sumption. The CMPDT register indicates the result of
comparison of the CMPP and CMPM pins.
Writing 1 to the CMPON register turns on the comparator
circuit. After an initial reset, this bit is set to 0. Data in the
CMPON register is read-accessible or write-accessible. A
wait time of at least 1 ms is required for analog voltage
comparator to become stable after its power is turned on.
The comparator response time depends on the potential
difference between the CMPP and CMPM inputs.
When analog voltage comparator is turned on, the circuit
compares the two analog voltages from the CMPP and
CMPM inputs, then outputs the result as binary 0
(CMPM>CMPP) or 1 (CMPP>CMPM). The result of the com-
parison is read from the CMPDT register. Writing to the
CMPDT register is prohibited.
Data in the CMPDT register becomes 1 when CMPON is 0 (analog
voltage comparator circuit is off), and undefined when the CMPP
and / or CMPM input is disconnected. Avoid reading operation
under those conditions.
Operation of analog
voltage comparator
Note
I-72 EPSON S1C62N82 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Analog Voltage Comparator)
Table 4.10.1 lists the control bits of the analog voltage
comparator and their addresses.
Control of analog
voltage comparator
Comparator on/off control (0FBH D0)
Switches the analog voltage comparator circuit to on or off.
When 1 is written: Comparator turns on
When 0 is written: Comparator turns off
Reading: Valid
After an initial reset, this bit is set to 0.
While analog voltage comparator is ON, the consumed current
becomes large. Unless necessary, do not turn on the analog
comparator.
Comparator data (0FBH D1)
Shows the result of comparing CMPP and CMPM.
When 1 is read: CMPP voltage is greater than
CMPM voltage
When 0 is read: CMPP voltage is smaller than
CMPM voltage
Writing: Invalid
This bit is undefined when the CMPP and/or CMPM input
pin is disconnected, and is 1 when CMPON is 0.
After an initial reset, this bit is set to 1.
CMPON
Table 4.10.1 Control bits of analog voltage comparator
Note
CMPDT
Address Comment
Register
D3 D2 D1 D0 Name SR 1 0
0FBH
CSDC 0 CMPDT CMPON
R
0
1
0
LCD drive switch
Voltage comparator ON/OFF
Static
+ > -
ON
Dynamic
- > +
OFF
R/W R/W
CSDC
0
CMPDT
CMPON
Comparator's voltage condition:
1 = CMPP(+)input > CMPM(-)input,
0 = CMPM(-)input > CMPP(+)input
S1C62N82 TECHNICAL HARDWARE EPSON I-73
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Melody Generator)
4.11 Melody Generator
Outline of melody
generator
The S1C62N82 Series has built-in melody generator. Out-
puts related to the melody function are generated from MO
terminal or R12 terminal. The following 3 types of melody
playing may be selected through the mask option:
(1)Piezo buzzer single terminal driving through the MO
terminal
The R12 output is set to DC output through the mask
option. Melody is output from the MO terminal alone.
This setting increases the number of externally fitted
parts to play the melody but since the R12 output may be
used as a common high-power current output, it is useful
when high-power current driving common output is
required.
(2)Piezo buzzer direct driving through the MO and R12
outputs
The R12 output is set to piezo direct driving through the
mask option. Reversed signal of the MO terminal output
signal is output from the R12 terminal. This allows the
piezo buzzer direct driving to materialize. This setting
makes it possible to keep the number of externally fitted
parts to the minimum.
(3)Envelope driving
The R12 output is set to the envelope function through
the mask option. Sound pressure of the playing is at-
tenuated with time, making it possible to implement a
fully expressive playing.
Moreover, normal HIGH output and normal LOW output
may be selected for each of the above-mentioned melody
output.
Refer to Chapter 5, "BASIC EXTERNAL WIRING DIAGRAM"
for the respective external wirings.
I-74 EPSON S1C62N82 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Melody Generator)
The characteristics of the melody generator are as follows:
(1)Size of the Melody ROM: 128 words
Basically, one note is equivalent to one word. Any num-
ber of melodies may be written as long as it is within 128
words. Data such as note length, intervals and end of
melody may be written.
(2)Size of Scale ROM: 31 scales
C3–C6# (without frequency booster) or C4–C7# (with
frequency booster) may be selected from among 31 scales.
The use of frequency booster may also be selected by the
mask option.
(3)Playing mode:
There are 3 playing modes.
➀One shot mode (Only 1 melody is played)
➁Level hold mode (The same or a different melody is
continuously played)
➂Retrigger mode (Forced change or termination of
melody)
(4)Tempo:
2 types may be selected from among 16 types through the
mask option.
(5)Playing speed:
Aside from the normal speed mode, 8 times, 16 times,
and 32 times speed mode may be controlled through
software. This function allows the generation of sound
effects.
S1C62N82 TECHNICAL HARDWARE EPSON I-75
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Melody Generator)
The block diagram of the melody generator is shown in
Figure 4.11.1. The note and interval data of the melody to
be played is pre-written on the melody ROM. The interval
data of the melody ROM is used to specify the scale ROM
address and according to the scale ROM data read from it,
the interval generating circuit generates the interval. The
output is controlled at the melody output control circuit and
is output at the MO and R12 terminals. The note generator
is generated according to the melody ROM data. The output
is entered in the melody ROM address counter; every time
the playing of a note is completed, one address is
incremented. This results in continuous melody being
automatically played. The playing tempo is created by the
tempo generator based on the signal which divided the
oscillation frequency in the oscillation circuit. Through the
mask option, 2 types of tempo may be selected from among
16 types. Moreover, the division ratio of the divider may be
modified by software and 4 types of playing speed can be
implemented. Envelope function may also be added to the
output melody and R12 output may be implemented by
setting it to correspond with the envelope.
Frequency
booster
Interval
generating
circuit
Melody
output
control circuit
Scale
ROM
Melody
interrupt
generator
Address
register Address
counter Melody
ROM
End-of-melody
signal
generator
Controller Divider Tempo
generator Note
generator
To CPU
R12
MO
32,768 Hz
Address bus
Data bus
Data bus
Address bus
Fig. 4.11.1
Melody generator
block diagram
I-76 EPSON S1C62N82 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Melody Generator)
A detailed description of the circuits which form the melody
generator is provided below.
(a)Frequency booster
The configuration of the frequency booster is shown in
Figure 4.11.2. It is a circuit which raises the input
frequency (32,768 Hz) for the melody generator to 2 times
the frequency. The output of this frequency booster is
provided with a switch through the mask option; by
selecting this switch, scale which can be output may be
changed. In other words, if frequency booster output
were selected for input to interval generating circuit,
interval can be created between C4 to C7# and if 32,768
Hz were selected as is, interval can be created between
C3 to C6#.
Fig. 4.11.2
Frequency booster
Booster
32,768 Hz To interval
generating circuit
(b)Controller
The configuration of the controller is shown in Figure
4.11.3. The controller consists of a 4-bit register located
in the I/O RAM space and an ON/OFF control circuit and
controls the melody's ON/OFF, tempo selection, playing
speed selection. The ON/OFF control circuit controls the
turning ON/OFF of the melody playing by entering the
MELC register output and the signal from the end-of-
melody signal generator. The address of the 4-bit register
is "0F2H" and the meaning of each bit is as follows:
D0 (MELC):
This is the bit that controls the turning ON/OFF of the
melody playing. The controlling function of this bit
makes it possible to control the above-described 3
types of playing. Refer to "Playing mode" regarding the
method of control.
S1C62N82 TECHNICAL HARDWARE EPSON I-77
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Melody Generator)
D1 (TEMPC):
This is the bit that selects the tempo. 2 types of tempo
selected by mask option may be changed. The timing
of tempo change is not done when data is written on
this bit but rather, when the next melody begins.
D2 and D3 (CLKC0 and CLKC1):
This is the bit that changes playing speed. By the
combination of CLKC0 and CLKC1, 4 types of playing
speed may be selected. The playing speed for the
selectable tempo listed in Table 4.11.7 is the normal
speed; playing speeds which are 8, 16 and 32 times
the normal speed may also be selected. This is useful
in generating sound effects. For details, see "Playing
tempo".
MELC
(D0)
ON/OFF
control
circuit
TEMPC
(D1)
CLKC0
(D2)
CLKC1
(D3)
Data bus
Address "0F2H"
Playing speed
control signal
Tempo control
signal
ON/OFF
control signal
End-of-melody signal
Fig. 4.11.3
Controller
Since playing speed is modified simultaneously with data writing
on these bits, caution must be observed when operating these
bits in the middle of a playing.
Note
I-78 EPSON S1C62N82 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Melody Generator)
(c)Address register
The configuration of the melody ROM address registers is
shown in Figure 4.11.4. It consists of the 7-bit register in
the I/O RAM space. The addresses are "0F0H" and
"0F1H". The data of these registers indicate the ad-
dresses of the melody ROM which become the addresses
of the melody ROM when the melody is started. These
melody ROM addresses are written to the melody ROM
address counter when the melody playing begins, i.e.,
before the the melody playing begins, the desired melody
may be played from among the melodies written in the
melody ROM by setting data on these registers.
MAD0
(D0)
MAD1
(D1)
MAD2
(D2)
MAD3
(D3)
Data bus
Address "0F0H" To Address counter
MAD4
(D0)
MAD5
(D1)
MAD6
(D2)
Address "0F1H"
Fig. 4.11.4
Address register
S1C62N82 TECHNICAL HARDWARE EPSON I-79
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Melody Generator)
(d)Address counter
The configuration of the melody ROM address counters is
shown in Figure 4.11.5. It consists of a counter in which
note playing end signal generated from the note generator
is entered and which increases the melody ROM ad-
dresses by 1 address every time a note playing is com-
pleted. Moreover, when a melody playing begins, address
register data (MAD0 to MAD6) are set on these counters.
This causes the address set in the address register to
specify the melody ROM address.
MAD0
Melody ROM Address
MAD1
MAD2
MAD3
MAD4
MAD5
MAD6
Note playing
end signal
Fig. 4.11.5
Address counters
(e)Melody ROM
The melody ROM is a mask ROM with 128 words × 10
bits capacity in which data of the melody to be played
(note, interval, end-of-melody, etc.) is stored beforehand.
Any number of melodies may be stored as long as the
total number of notes is within 128 words (basically, 1
note/word). Details regarding the melody ROM configu-
ration, etc., can be found in next Section, "Melody data".
I-80 EPSON S1C62N82 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Melody Generator)
(f) Divider
The configuration of the divider is shown in Figure
4.11.6. It is a circuit that divides the clock (32,768 Hz)
which is input in the melody generator and inputs the
divided clock into the tempo generator. The dividing ratio
may be controlled by software. The data of the "CLKC0"
and "CLKC1" registers in the above-mentioned controller
is input and the dividing ratio will differ according to the
value of the input data. The dividing ratio and playing
speed for the combinations of CLKC0 and CLKC1 values
are shown in Table 4.11.1. The "normal" speed in the
playing speed column refers to the playing speed by
which the tempo listed in Table 4.11.7 may be imple-
mented. playing speeds 8 times (the normal speed) or
more are useful for generating sound effects.
Table 4.11.1
Dividing ratio
0
0
1
1
0
1
0
1
1/512
1/64
1/32
1/16
Normal
8 times
16 times
32 times
CLKC1 CLKC0
Dividing
Ratio Playing
Speed
Fig. 4.11.6
Divider
32,768 Hz 1/2
divider 1/2
divider 1/2
divider 1/8
divider 1/8
divider
CLKC0
CLKC1
To tempo
generator
S1C62N82 TECHNICAL HARDWARE EPSON I-81
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Melody Generator)
(g)Tempo generator
The configuration of the tempo generator is shown in
Figure 4.11.7. The tempo generator is a circuit which
generates the 2 types of tempo selected by mask option
and consists of the 4-bit counter in which the output
signal from the divider is input and the 4 switches which
set their respective bit. The 4-bit counter output serves
as the note generator input. The 4 switches are auto-
matically set to generate the 2 types of tempo selected by
mask option. Bit settings and the corresponding tempo
generated are shown in Table 4.11.2. On the other hand,
the relationship between the 2 types of tempo selected by
mask option and switch settings are shown in Table
4.11.3. For example, if the respective bit values of the 2
types of tempo selected by mask option are "1" for
TEMPC = 0 and "0" for TEMPC = 1, the switch setting for
this bit combination will be TEMPC (reverse signal of the
TEMPC register output).
Table 4.11.2
Counter setting and tempo
Table 4.11.3
Tempo and switch setting
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
TS2 0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
TS1 0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
TS0 30
32
34.3
36.9
40
43.6
48
53.3
60
68.6
80
96
120
160
240
480
TS3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
1
0
1
TEMPC=0
0
0
1
1
TEMPC=1 Pull down
TEMPC
TEMPC
Pull up
Switch Setting
I-82 EPSON S1C62N82 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Melody Generator)
1/2
divider 1/2
divider 1/2
divider To note generator
Divider
output
signal 1/2
divider
V
DD
V
SS
TEMPC
Mask option
TS3TS2TS1TS0
TEMPC
Fig. 4.11.7
Tempo generator
Fig. 4.11.8
Note generator
(h)Note generator
This is a generator which counts the tempo generator
output and creates various notes. Its configuration is
shown in Figure 4.11.8. It consists of counters in which
3 bits can be set. Each counter is set by the 3 bits (D6–
D8) from the melody ROM causing the counter dividing
ratio to change and hence various notes are generated.
The bit settings and the corresponding notes generated
are shown in Table 4.11.4. The counter output becomes
the note playing end signal and the address of the melody
ROM is incremented 1 step at a time.
Tempo generator
output signal 1/2
divider 1/2
divider 1/2
divider
D8
Note playing
signal
D7
D6
Melody ROM output
(D6–D8)
0
0
0
0
1
1
1
1
D8
0
0
1
1
0
0
1
1
D7
0
1
0
1
0
1
0
1
D6 Note
+
Table 4.11.4
Note data and notes
S1C62N82 TECHNICAL HARDWARE EPSON I-83
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Melody Generator)
Note
(i) Scale ROM
This is a mask ROM in which 31 scale types which have
been optionally selected and created from either C3–C6#
(available output frequency range: 4,096 Hz–125.5 Hz;
without frequency booster) or C4–C7# (available output
frequency range: 8,192 Hz–251.1 Hz; with frequency
booster) are stored beforehand. The 15 available ad-
dresses are "00H"–"1EH". Word length is 8 bits; the data
written on them and the corresponding scale (frequency)
generated are shown in Tables 4.11.5 (a) and (b). The
maximum value which may be written as a data is "FDH".
The address is specified by the melody ROM output and
the output is entered in the interval generating circuit.
Bear in mind that the range of the data which can be written on
the scale ROM is from "00H" to "FDH". If any data beyond this
range is written, the interval generating circuit will not function
normally.
I-84 EPSON S1C62N82 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Melody Generator)
Table 4.11.5 (a)
Scale ROM data and interval
(with frequency booster)
Scale
Data MSB
S7
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
S6
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
S5
0
0
1
1
1
0
0
0
1
1
1
1
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
S4
0
1
0
0
1
0
1
1
0
0
1
1
0
0
1
1
1
0
0
1
1
1
1
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
S3
0
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
1
0
1
0
0
1
1
0
0
1
1
1
0
0
1
1
1
1
0
0
0
0
S2
1
0
0
1
0
1
0
0
1
1
1
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
1
0
1
0
0
1
1
0
0
1
1
S1
0
1
0
1
1
0
0
1
0
0
0
0
0
0
1
0
1
0
1
0
0
0
0
0
0
0
0
1
1
0
0
1
0
1
0
1
0
1
S0
0
0
0
1
1
0
1
1
1
0
0
0
0
1
0
0
0
0
1
1
1
0
0
0
0
0
1
0
1
0
1
1
0
0
0
0
0
0
Frequency
(Hz)
C4
C4#
D4
D4#
E4
F4
F4#
G4
G4#
A4
A4#
B4
C5
C5#
D5
D5#
E5
F5
F5#
G5
G5#
A5
A5#
B5
C6
C6#
D6
D6#
E6
F6
F6#
G6
G6#
A6
A6#
B6
C7
C7#
256
270.810
287.439
304.819
322.837
341.333
362.077
383.251
407.056
431.158
455.111
481.882
512
541.620
574.877
606.815
642.510
682.667
720.176
771.012
809.086
862.316
910.222
963.765
1024
1092.267
1149.754
1213.630
1285.020
1365.333
1456.356
1524.093
1638.400
1724.632
1820.444
1927.529
2048
2194.533
LSB
S1C62N82 TECHNICAL HARDWARE EPSON I-85
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Melody Generator)
Table 4.11.5 (b)
Scale ROM data and interval
(without frequency booster)
Scale
Data MSB
S7
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
S6
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
S5
0
0
1
1
1
0
0
0
1
1
1
1
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
S4
0
1
0
0
1
0
1
1
0
0
1
1
0
0
1
1
1
0
0
1
1
1
1
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
S3
0
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
1
0
1
0
0
1
1
0
0
1
1
1
0
0
1
1
1
1
0
0
0
0
S2
1
0
0
1
0
1
0
0
1
1
1
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
1
0
1
0
0
1
1
0
0
1
1
S1
0
1
0
1
1
0
0
1
0
0
0
0
0
0
1
0
1
0
1
0
0
0
0
0
0
0
0
1
1
0
0
1
0
1
0
1
0
1
S0
0
0
0
1
1
0
1
1
1
0
0
0
0
1
0
0
0
0
1
1
1
0
0
0
0
0
1
0
1
0
1
1
0
0
0
0
0
0
Frequency
(Hz)
C3
C3#
D3
D3#
E3
F3
F3#
G3
G3#
A3
A3#
B3
C4
C4#
D4
D4#
E4
F4
F4#
G4
G4#
A4
A4#
B4
C5
C5#
D5
D5#
E5
F5
F5#
G5
G5#
A5
A5#
B5
C6
C6#
128
135.405
143.719
152.409
161.419
170.667
181.039
191.626
203.528
215.579
227.556
240.941
256
270.810
287.439
303.407
321.255
341.333
360.088
385.506
404.543
431.158
455.111
481.882
512
546.133
574.877
606.815
642.510
682.667
728.178
762.047
819.200
862.316
910.222
963.765
1024
1092.267
LSB
I-86 EPSON S1C62N82 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Melody Generator)
(j) Interval generating circuit
The interval generating circuit generates the interval
(frequency) corresponding to the scale ROM output. Its
configuration is shown in Figure 4.11.9. Using the input
clock (32,768 Hz) to the melody generator or the 8-bit
divider with the booster output (65,536 Hz) as input
clock, dividing ratios (1/8–1/261) set by the scale ROM
output (S0–S7) can be attained. The divider output
passes through the output controller and becomes sound
output. Scales which can be output are C3–C6# (avail-
able output frequency range: 4,096 Hz–125.5 Hz; without
frequency booster) or C4–C7# (available output frequency
range: 8,192 Hz–251.1 Hz; with frequency booster). The
dividing ratio may be derived from S0–S7 values which
are the scale ROM output using the following equation:
N (dividing ratio) = (/S7 × 2
6
+ /S6 × 2
5
+ /S5 × 2
4
+ /S4 × 2
3
+ /S3
× 2
2
+ /S2 × 2
1
+ /S1 × 2
0
+3) × 2 + S0
(Note: /SX = reversed value of SX)
Example:
If
(S7, S6, S5, S4, S3, S2, S1, S0) = (1, 1, 1, 0, 0, 1, 0, 0),
then,
N = (0 × 2
6
+ 0 × 2
5
+ 0 × 2
4
+ 1 × 2
3
+ 1 × 2
2
+ 0 × 2
1
+ 1 × 2
0
+3)
× 2 + 0 = 32
In other words, if the input clock were 32,768 Hz, the
output will be 32,768/32 = 1,024 Hz (C6).
The selection of input clock may be done by changing the
switch (by mask option) explained in the section on
booster.
Divider (dividing ratio: 1/8–1/261)
Booster
output To melody output
control circuit
S0–S7
Scale ROM output (8 bits)
Fig. 4.11.9
Interval generating circuit
S1C62N82 TECHNICAL HARDWARE EPSON I-87
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Melody Generator)
(k)End-of-melody signal generator
This is a circuit that receives the end-of-melody data
written on the melody ROM and generates the end-of-
melody signal which synchronized with the end of a note
playing. The output is entered into the controller and the
melody interrupt generator and becomes the source
signal which informs the end of a melody.
(l) Melody interrupt generator
The configuration of the melody interrupt generator is
shown in Figure 4.11.10. It is a circuit that receives the
end-of-melody signal from the end-of-melody signal
generator and generates the melody interrupt signal
which informs the CPU that a certain melody has been
completed. At the same time, it sets an interrupt factor
flag the timing of which is shown in Figure 4.11.11. The
interrupt factor flag becomes valid approximately 7.8 ms
(in case of normal speed) after the end-of-melody signal is
generated. The interrupt factor flag may be read out by
software and is reset simultaneously with the read out.
The register address is "ECH D0". It can also be masked
for the interrupt signal and masking can be controlled by
software. The mask register address is "E7H D0".
IMEL
EIMEL
Address "0ECH"
Address "0E7H"
Data bus
End-of-melody signal
Interrupt signal
Fig. 4.11.10
Melody interrupt generator
I-88 EPSON S1C62N82 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Melody Generator)
Writing on the mask register should always be performed in the
"DI (interrupt prohibited)" state. Otherwise, misoperation may
result.
(m)Melody output control circuit
Melody output is masked by setting MELD to 1 and is
unmasked by setting it to 0.
Since this function operates independently from the
melody generator, control of melody generator other than
this control circuit is required in order to generate
melody.
Valid
Valid
Approx. 7.8 ms
PlayingPlaying
End-of-melody
signal
Melody interrupt
signal
Interrupt factor
flag
Melody signal
generator
block
MELD
Address "0F4H"
Data bus
Melody signal
Fig. 4.11.12
Melody output control circuit
Fig. 4.11.11
Interrupt generation timing
Note
(n) Melody output terminal (MO and R12)
These are terminals which generate melody during
performance. The performance type (piezo buzzer direct
driving and envelope addition) of the melody is deter-
mined by mask option. The output configuration and
output waveform of these terminals are shown in Figure
4.11.13. The configuration varies with the mask option
selection of R12.
Moreover, whether each option will by set as normal
HIGH level output or normal LOW level output may be
selected through mask option.
S1C62N82 TECHNICAL HARDWARE EPSON I-89
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Melody Generator)
Fig. 4.11.13 Melody terminal output configuration and output waveform
R12
MO
R12
register
output
Melody
signal
V
DD
V
DD
Vss
Vss
R12
MO
V
DD
Attack
signal
Melody
signal
Analog switch
Vss
MO
R12
(with external
capacitor)
R12
MO
R12
MO
(3) R12: With envelope function
(Normal HIGH level output)
(6) R12: With envelope function
(Normal LOW level output)
R12
MO
R12
register
output
Melody
signal
V DD
V DD
Vss
Vss
R12
MO
Melody
control
signal
Melody
signal
V
DD
V
DD
Vss
Vss
R12
MO
Melody
control
signal
Melody
signal
V DD
V DD
Vss
Vss
MO
V
DD
Attack
signal
Melody
signal
Analog switch
Vss
R12
R12
MO
R12
MO
MO
R12
(with external
capacitor)
(1) R12: DC output
(Normal HIGH level output)
(4) R12: DC output
(Normal LOW level output)
(2) R12: Melody reverse output
(Normal HIGH level output)
(5) R12: Melody reverse output
(Normal LOW level output)
I-90 EPSON S1C62N82 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Melody Generator)
(1)R12:DC output
(Melody output: Normal HIGH level)
Melody is output from the MO terminal and from the
R12 terminal, data written on the "R12" register is
output. The MO terminal is a complementary output
terminal and goes high when melody is not played.
Complementary output or Pch open-drain output may
be selected for the R12 terminal by mask option.
(2)R12:Melody reverse output
(Melody output: Normal HIGH level)
Using MO and R12 terminals, the piezo buzzer may be
directly driven. During playing, reverse signal of the
MO terminal is output from the R12 terminal. Both
terminals go high when melody is not being played.
The output configuration of both terminals becomes
complementary.
(3)R12:With envelope function
(Melody output: Normal HIGH level)
Envelope function can be implemented by connecting
an external capacitor to the R12 terminal. Melody is
output from the MO terminal and the signal which will
recharge the external capacitor will be output from the
R12 terminal. The R12 electric potential will turn out
supplying the negative electric potential of the MO
terminal output and when the melody signal goes high,
it will pass the analog switch and will be supplied to the
MO terminal. For details regarding the envelope func-
tion, refer to "Envelope function".
S1C62N82 TECHNICAL HARDWARE EPSON I-91
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Melody Generator)
(4)R12:DC output
(Melody output: Normal LOW level)
Melody is output from the MO terminal and from the
R12 terminal, data written on the "R12" register is
output. The MO terminal is a complementary output
terminal and goes low when melody is not played.
Complementary output or Pch open-drain output may
be selected for the R12 terminal by mask option.
(5)R12:Melody reverse output
(Melody output: Normal LOW level)
Using MO and R12 terminals, the piezo buzzer may be
directly driven. During playing, reverse signal of the
MO terminal is output from the R12 terminal. Both
terminals go low when melody is not being played. The
output configuration of both terminals becomes com-
plementary.
(6)R12:With envelope function
(Melody output: Normal LOW level)
Envelope function can be implemented by connecting
an external capacitor to the R12 terminal. Melody is
output from the MO terminal and the signal which will
recharge the external capacitor will be output from the
R12 terminal. The R12 electric potential will turn out
supplying the positive electric potential of the MO
terminal output and when the melody signal goes low, it
will pass the analog switch and will be supplied to the
MO terminal. For details regarding the envelope func-
tion, refer to "Envelope function".
I-92 EPSON S1C62N82 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Melody Generator)
Melody data • Melody ROM
The melody ROM has an 128-word capacity, the length of
a word being 10 bits. Basically, data of 1 note is stored
in 1 word. These data are continuously read out by the
hardware and melody is played. The 4 types of data
which may be written as 1-note data are as follows:
(1)Interval data
(2)Note data
(3)End data
(4)Attack data
When melody playing starts, the start address is specified
with the address written on the address register. The
melody ROM address is then automatically increased by
the address counter one step at a time and melody is
played. The melody automatically stops at the point
where the end-of-melody data written on the melody ROM
is read out by the hardware. At the same time, interrupt
flag is set and interrupt for the CPU is generated.
Fig. 4.11.14
Data format of
the melody ROM
Since only melody
D8 D7 D6 D5 D4 D3 D2 D1 D0
Note data Scale data
End
data
D9
Attack
data
start address setting and melody start control may be
controlled by software, optional melodies which have
been written on the melody ROM can easily be played by
lessening the load of the software.
The format of the data contained in a melody ROM word
is shown in Figure 4.11.14. These melody data are
explained in details below.
S1C62N82 TECHNICAL HARDWARE EPSON I-93
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Melody Generator)
• Note data (D6–D8)
Note data are data which indicate the notes to be used.
As shown in Figure 4.11.14, note data are written on 3
bits: D6–D8. There are 8 types of notes which can be
used in the S1C62N82 Series and the corresponding 3
note data bits are shown in Table 4.11.6. Although notes
shorter than 32 notes may not be played, notes longer
than 2 notes may be played by operating the above-
mentioned attack note. This procedure is explained in
the section on attack data.
Table 4.11.6
Note data and notes
• Scale data (D1–D5)
Intervals to be used are pre-written on the scale ROM.
There are 31 scale ROM addresses which can be used:
"00H" to "1EH". The addresses are written on the 5 bits
(D1–D5; see Figure 4.11.14) which serve as interval data
area. Intervals written on the interval ROM address
which has been specified with the interval data (refer to
Tables 4.11.5 (a) and (b)) are generated at the interval
generating circuit. Although the scale ROM addresses
are only from "00H" to "1EH", "1FH" also exists in the
hardware and is set for silent notes. Because of this,
writing "1FH" on the melody ROM interval data area will
result in the playing of silent notes. The length of a silent
note depends on the note data written on the same word.
0
0
0
0
1
1
1
1
D8
0
0
1
1
0
0
1
1
D7
0
1
0
1
0
1
0
1
D6 Note
+
I-94 EPSON S1C62N82 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Melody Generator)
• Attack data (D9)
The attack data is a 1-bit data which determines whether
or not to make the break between notes clear. In each
melody first word, set this data to "1". Otherwise, there
will be no melody play even if the user starts play.
If envelope function is not available, writing "1" for this
bit will produce an approximately 12 ms rest every time
the melody ROM address increases by 1 step (i.e., at the
break of the playing of different notes). This is particu-
larly useful when the same notes follow one another. As
a rule, "1" is written on the attack bit of all words. How-
ever, when long notes other than those listed in Table
4.11.6 are desired, they can be implemented by linking
several words of the same interval to a continuous ad-
dress and at the same time setting the attack bit to "0".
On the other hand, when envelope function is available,
setting this bit to "1" will cause the capacitor for the
envelope function which is externally installed to be
recharged when the playing starts and increase the
sound pressure of the playing. Moreover, when this bit is
set to "0", since the capacitor will be continuously dis-
charged without being recharged, the sound pressure of
the playing will continue to diminish. The principle of the
envelope function is explained in details in the next
section.
S1C62N82 TECHNICAL HARDWARE EPSON I-95
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Melody Generator)
• End data (D0)
This is 1-bit data which indicate the end of a set of played
melody. If this bit were written with "1", when the word
is played, end-of-melody signal will be generated at the
end-of-melody signal generator and will then be input to
the melody interrupt generator and the controller. This
signal is received at the melody interrupt generator which
issues interrupt request to the CPU and generates inter-
rupt flag. Moreover, the controller stops the playing
when the melody ON/OFF control register is set to "0"
when the signal is received and either repeats the same
melody or continuously plays new melodies when it is set
to "1". By dividing the 128-word melody ROM with end-
of-melody data, any number of melodies may be written
as long as it is within the capacity. Also, a melody which
will be repeatedly used need be written only once, i.e.,
there is no need to write the melody for as many number
of times you wish to repeat it. Repeated playing can be
easily accomplished by merely specifying the playing start
address repeatedly through the software. Control of
playing is explained in details in "Control of playing".
Playing of silent note Silent note may be played by writing "1FH" on the melody
ROM interval data. The length of the silent note is the same
as the length of the note written on the same word. For
details, refer to "Melody data".
I-96 EPSON S1C62N82 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Melody Generator)
Envelope function The S1C62N82 Series may be added with envelope function
for melody playing by mask option. The IC internal circuit
when the envelope function is valid (when normal HIGH
level output is selected) and the external circuit required is
shown in Figure 4.11.15. The IC internal setting is done by
mask option and the following need to be externally in-
stalled:
- piezo buzzer sounding body;
- booster coil for raising the sound pressure of the playing;
- PNP bipolar transistor to drive the sounding body (piezo
buzzer);
- capacitor for implementing smooth sound pressure
attenuation; and
- resistor for controlling the power current discharge of the
capacitor.
The output waveform when envelope function is shown in
Figure 4.11.16. The attack signal indicated in the diagram
will go high ("H" level) when the playing of the word starts if
the attack data written on the melody ROM were "1". The
pulse width is approximately 12 ms. The ATK (attack) signal
recharges the externally installed capacitor and the R12
terminal output level will be recharged up to the power
voltage as shown in Figure 4.11.16. This will result in the
MO terminal output amplitude becoming the power voltage
since they (R12 and MO terminals) are wired together inside
the IC as shown in Figure 4.11.15. The sound pressure of
the melody played then will be maximum. Henceforth,
because the capacitor connected to the R12 terminal is
discharged as the base current of the externally installed
transistor as time passes, the base current will drop and the
playing sound pressure will attenuate with the passing of
time. The MO terminal output waveform is shown in Figure
4.11.16. The MO terminal output amplitude will decrease
with capacitor discharge. This is the principle of the enve-
lope function.
Furthermore, normal LOW level output may also be se-
lected, in which case NPN transistor is used. The output
waveform in Figure 4.11.16 will also be reversed.
S1C62N82 TECHNICAL HARDWARE EPSON I-97
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Melody Generator)
R12
MO
Vss
V DD
Attack signal
Melody signal
Analog switch
Piezo
buzzer Booster
coil
PNP
Transistor
Capacitor
S1C62N82
Fig. 4.11.15
Configuration of the
envelope function
(when normal HIGH level
output is selected)
Attack signal
R12 pin output
Melody signal
MO pin output
Fig. 4.11.16
Envelope output waveform
(when normal HIGH level
output is selected)
I-98 EPSON S1C62N82 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Melody Generator)
Playing tempo In the S1C62N82 Series, 2 types of melody playing tempo
may be selected from among 16 types by mask option.
Tempos which may be selected are shown in Table 4.11.7
(see also "Tempo generator"). The proper use of the 2 types
of tempo selected is specified through the software. The 2
types of tempo which may selected are: the tempo to be
played when "0" is written on the TEMPC register of the
controller and the tempo to be played when "1" is written on
the said register.
Table 4.11.7
Tempos available
for selection
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
TS2 0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
TS1 0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
TS0 30
32
34.3
36.9
40
43.6
48
53.3
60
68.6
80
96
120
160
240
480
TS3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Note Changing the 2 types of tempo selected by mask option is not done
on the spot when data is written on the TEMPC register but rather,
the tempo is changed when a new melody is played after the data
has been written, i.e., the tempo cannot be changed in the middle
of a melody playing.
S1C62N82 TECHNICAL HARDWARE EPSON I-99
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Melody Generator)
Furthermore, 4 types of playing speed may be selected in
the S1C62N82 Series. The selection can be done through
the software and control is performed by writing data on
CLKC0 and CLKC1 registers of the controller. The data
written on the registers and the corresponding playing speed
are shown in Table 4.11.8. By writing "0" on CLKC0 and
CLKC1, normal speed tempo (i.e., tempo selected by mask
option) may be played. Playing at 8 times, 16 times and 32
times of the normal speed is useful for producing sound
effects for games and animal sounds.
Table 4.11.8
Playing speed
0
0
1
1
0
1
0
1
Normal
8 times
16 times
32 times
CLKC1 CLKC0 Playing Speed
Note Changing the playing speed is instantly accomplished by writing
data on CLKC0 and CLKC1 registers. When speed need not be
changed in the middle of a melody, write the playing speed data
upon completion of a melody playing, i.e., during rest.
I-100 EPSON S1C62N82 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Melody Generator)
Playing mode The S1C62N82 Series have 3 modes for melody playing: one
shot mode, level hold mode and retrigger mode. The control
of these modes is done through operation of the MELC
register of the controller.
(a)One shot mode
In this mode, only one specified melody is played; playing
automatically stops when the melody ends. Control
procedures are as follows:
(1)Set the melody ROM address (start address) of the
desired melody in the address register (MAD0–MAD6).
(2)Immediately after writing "1" (before the melody play-
ing ends), write "0" on the MELC register.
The above operation will allow only one melody to be
played. Melody playing is started from the address
written on the address register, by writing "1" on the
MELC register. When playing of the last word of a
melody (end- of-melody data is "1") ends, end-of-melody
signal is generated and interrupt request to the CPU and
interrupt flag are generated in the melody interrupt
generator. At this point, since "0" has previously been
written on the MELC register with the above operation
(2), signal to halt playing is generated in the controller
and hence, playing will stop.
The relationship between MELC register value and play-
ing output is shown in Figure 4.11.17.
Fig. 4.11.17
One shot mode
100
Approx. 125 ms
Generation of
melody interrupt
PlayingPlaying
"MELC"
register
S1C62N82 TECHNICAL HARDWARE EPSON I-101
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Melody Generator)
Note Bear in mind that playing will start approximately 125 ms (in
case of normal speed) after writing "1" on the MELC register.
(b)Level hold mode
Repetition of the same melody or continuous playing of
different melodies is possible in this mode. The operating
procedure are as follows:
(1)Set the melody ROM address (start address) of the
desired melody in the address register (MAD0–MAD6).
(2)Write "1" on the MELC register.
(3)Immediately after procedure (2) above (before the
melody being played ends), write the start address of
the second melody on the address register (MAD0–
MAD6). When repeating the same melody, there is no
need to write anew on the address register.
(4)Since melody interrupt will be generated when the first
melody ends, write the address for the third melody on
the address register (MAD0–MAD6) with the interrupt
routine. This operation must be completed before the
second melody ends. When the same melody is to be
repeatedly played, there is no need for this operation.
The optional melody in the melody ROM may continu-
ously be played by repeating the above steps.
(5)To stop playing, write "0" on the MELC register while
the last melody is being played. This will cause the
playing to be automatically stopped when playing of
the last melody is completed.
I-102 EPSON S1C62N82 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Melody Generator)
The relationship between MELC register value and play-
ing output is shown in Figure 4.11.18.
(c)Retrigger mode
This playing mode is for modifying or stopping the melody
forcedly in the middle of playing. Its operating procedure
is as follows:
(1)In the middle of a melody playing, write the melody
ROM address of the next melody to be played on the
address register (MAD0–MAD6).
(2)Change the MELC register setting from "0" to "1". At
this point, the played melody will be forcedly changed.
(3)After this operation, the 3 types of playing mode may
be selected freely again.
To stop a melody in the middle of its playing is also
implemented by employing this mode. The operation is
as follows:
(1)In the middle of a melody playing, set the melody ROM
address written with silent notes on the address
register (MAD0–MAD6).
(2)Change the MELC register setting from "0" to "1" and
then to "0" again.
Fig. 4.11.18
Level hold mode
00
Approx. 125 ms
Generation of
melody interrupt
Melody
1
Playing
"MELC"
register 1
Melody
2
....
Melody
n-1 Melody
n
S1C62N82 TECHNICAL HARDWARE EPSON I-103
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Melody Generator)
With the above operation, the melody being played will be
forced to change into silent note playing; as soon as the
playing of the silent notes is completed, the playing will
automatically stop. In the above operation (2), writing
operation for the last "0" must be done before the playing
of silent notes ends.
The relationship between MELC register value and play-
ing output is shown in Figure 4.11.19.
00
Approx.
125 ms
Generation of
melody interrupt
Playing
"MELC"
register 0
Melody 1 Melody 2
11
Approx.
125 ms
Fig. 4.11.19
Retrigger mode
Note Bear in mind that when melody playing is forcedly modified with
the above operations, playing of the modified melody will start
approximately 125 ms (in case of normal speed) after "1" has
been written on the MELC register.
I-104 EPSON S1C62N82 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Melody Generator)
Address Comment
Register
D3 D2 D1 D0 Name SR 1 0
0E7H
0 0 0 EIMEL
R
0
0
0
EIMEL 0 Enable Mask
Interrupt mask register (melody)
R/W
0ECH
0 0 0 IMEL
R
0
0
0
IMEL 0
Interrupt factor flag (melody)
Yes No
0F0H
0F1H
0F2H
MAD3 MAD2 MAD1 MAD0
0 MAD6 MAD5 MAD4
CLKC1 CLKC0 TEMPC MELC
R/W
R
R/W
MAD3
MAD2
MAD1
MAD0
0
0
0
0
0
MAD6
MAD5
MAD4
0
0
0
Melody ROM address (AD6, MSB)
Melody ROM address (AD5)
Melody ROM address (AD4)
CLKC1
CLKC0
TEMPC
MELC
0
0
0
0
CLKC1(0)&CLKC0(0) : melody speed 1
CLKC1(0)&CLKC0(1) : melody speed 8
CLKC1(1)&CLKC0(0) : melody speed 16
CLKC1(1)&CLKC0(1) : melody speed 32
Tempo change control
Melody control ON/OFF
Melody ROM address (AD3)
Melody ROM address (AD2)
Melody ROM address (AD1)
Melody ROM address (AD0, LSB)
High
High
High
High
Low
Low
Low
Low
High
High
High
Low
Low
Low
High
High
High
ON
Low
Low
Low
OFF
R/W
×
×
×
×
0F4H
R12
MO
ENV R11 R10
FOUT
R/W
MELD
R12
MO
ENV
R11
R10
FOUT
Melody output mask
Output port data (R12)
Inverting melody output
Melody envelope control
Output port data (R11)
Output port data (R10)
Frequency output
Disable
High
–
–
High
High
ON
Enable
Low
–
–
Low
Low
OFF
0
0
–
Hz
0
0
MELD
Control of the
melody generator
Operation of registers for melody control is explained in this
section.
Table 4.11.9 Control bits of melody generator
S1C62N82 TECHNICAL HARDWARE EPSON I-105
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Melody Generator)
MELD
MELC
TEMPC
Note
Melody Output Mask (0F4H D3)
The melody signal output from the melody output terminal
(MO) may be masked through this register. After initial
reset, the melody signal becomes ready for output.
When 1 is written: Masked (signal output stops)
When 0 is written: Enabled
Reading: Valid
Melody ON/OFF Control Register (0F2H D0)
By operating this register, control of the melody playing ON/
OFF and the 3 types playing modes—one shot mode, level
hold mode and retrigger mode—can be performed.
When 1 is written: Playing starts
When 0 is written: Playing stops
Reading: Valid
Tempo Control Register (0F2H D1)
By operating this register, 1 type of tempo may be selected
from the 2 types previously selected by mask option.
When 1 is written: Selects the tempo of TEMPC1
selected by mask option
When 0 is written: Selects the tempo of TEMPC0
selected by mask option
Reading: Valid
Changing the tempo through this register is not possible in the
middle of a melody playing even if this register is operated while a
melody is being played. Change of melody will synchronize with
the playing of a new melody.
I-106 EPSON S1C62N82 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Melody Generator)
CLKC0
CLKC1
0
0
1
1
0
1
0
1
Normal
8 times
16 times
32 times
CLKC1 CLKC0 Playing Speed
Note
MAD0–MAD6
Playing Speed Control Register (0F2H D2)
Playing Speed Control Register (0F2H D3)
By operating these registers, playing speed of a melody may
be changed. The combination of CLKC0 and CLKC1 register
values and playing speed are shown in Table 4.11.10.
When 1 is written: 1
When 0 is written: 0
Reading: Valid
Playing speeds are changed the moment these registers are
operated. Take caution when operating these registers in the
middle of a melody playing.
Address Registers (0F0H D0–D3 and 0F1H D0–D2)
These registers are used to set the melody playing start. By
operating the "MELC" register, when playing of a new mel-
ody starts, the addresses set in these registers are read by
the melody ROM address counter and become the melody
start addresses.
When 1 is written: 1
When 0 is written: 0
Reading: Valid
Table 4.11.10
Playing speed
S1C62N82 TECHNICAL HARDWARE EPSON I-107
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Melody Generator)
EIMEL
Note
IMEL
Note
Melody Interrupt Mask Register (0E7H D0)
By operating this register, melody interrupt can be masked.
When 1 is written: Interrupt is valid
When 0 is written: Interrupt is invalid
Reading: Valid
Be sure to operate this register in the "DI (interrupt not allowed)"
state. Otherwise, it may result in misoperation.
Melody Interrupt Factor Flag (0ECH D0)
The moment the melody playing (i.e., playing of the address
the end-of-melody data in the melody ROM of which is "1")
ends, a flag is set on this register. Due to this, the end of a
melody playing can be known by reading out this register.
This register is also reset by the hardware after the readout.
When 1 is read: Interrupt generation; 0 after readout
When 0 is read: Interrupt is not generated
Writing: Invalid
Reading of interrupt factor flags is available at EI, but be careful in
the following cases.
If the interrupt mask register value corresponding to the interrupt
factor flags to be read is set to 1, an interrupt request will be
generated by the interrupt factor flags set timing, or an interrupt
request will not be generated.
I-108 EPSON S1C62N82 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT)
Interrupt and HALT
The S1C62N82 Series provide the following interrupt set-
tings, each of which is maskable.
External interrupt: Input interrupt (two)
Internal interrupt: Timer interrupt (one)
Stopwatch interrupt (one)
Melody interrupt (one)
To enable interrupts, the interrupt flag must be set to 1 (EI)
and the necessary related interrupt mask registers must be
set to 1 (enable). When an interrupt occurs, the interrupt
flag is automatically reset to 0 (DI) and interrupts after that
are inhibited.
When a HALT instruction is input, the CPU operating clock
stops and the CPU enters the halt state. The CPU is reacti-
vated from the halt state when an interrupt request occurs.
Figure 4.12.1 shows the configuration of the interrupt
circuit.
4.12
S1C62N82 TECHNICAL HARDWARE EPSON I-109
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT)
IMEL
EIMEL
KCP10
EIK10
K10
KCP00
EIK00
K00
KCP01
EIK01
K01
KCP02
EIK02
K02
KCP03
EIK03
K03
ISW0
EISW0
ISW1
EISW1
IT2
EIT2
IT8
EIT8
IT32
EIT32
IK1
IK0
Highest
:
:
:
Lowest
Program counter of CPU
(four low-order bits)
Interrupt vector
10A
108
106
104
102
Interrupt factor flag
Interrupt mask register
Input comparison register
Address Priority
Interrupt flag
INT
(Interrupt request)
Fig. 4.12.1 Configuration of interrupt circuit
I-110 EPSON S1C62N82 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT)
Table 4.12.1 shows the factors that generate interrupt
requests.
The interrupt factor flags are set to 1 depending on the
corresponding interrupt factors.
The CPU is interrupted when the following two conditions
occur and an interrupt factor flag is set to 1.
• The corresponding mask register is 1 (enabled)
• The interrupt flag is 1 (EI)
The interrupt factor flag is a read-only register, but can be
reset to 0 when the register data is read.
After an initial reset, the interrupt factor flags are reset to 0.
Reading of interrupt factor flags is available at EI, but be careful in
the following cases.
If the interrupt mask register value corresponding to the interrupt
factor flags to be read is set to 1, an interrupt request will be
generated by the interrupt factor flags set timing, or an interrupt
request will not be generated.
Be very careful when interrupt factor flags are in the same address.
Interrupt factors
Note
Interrupt Factor
Clock timer 2 Hz falling edge
Clock timer 8 Hz falling edge
Clock timer 32 Hz falling edge
Stopwatch timer
1 Hz falling edge
Stopwatch timer
10 Hz falling edge
Input data (K00–K03)
Rising or falling edge
Input data (K10)
Rising or falling edge
Melody generator
End of melody
Interrupt Factor Flag
IT2 (0EFH D2)
IT8 (0EFH D1)
IT32 (0EFH D0)
ISW1 (0EEH D1)
ISW0 (0EEH D0)
IK0 (0EDH D0)
IK1 (0EDH D1)
IMEL (0ECH D0)
Table 4.12.1
Interrupt factors
S1C62N82 TECHNICAL HARDWARE EPSON I-111
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT)
The interrupt factor flags can be masked by the correspond-
ing interrupt mask registers. The interrupt mask registers
are read/write registers. They are enabled (interrupt en-
abled) when 1 is written to them, and masked (interrupt
disabled) when 0 is written to them. After an initial reset,
the interrupt mask register is set to 0.
Table 4.12.2 shows the correspondence between interrupt
mask registers and interrupt factor flags.
Interrupt Mask Register
EIT2 (0EBH D2)
EIT8 (0EBH D1)
EIT32 (0EBH D0)
EISW1 (0EAH D1)
EISW0 (0EAH D0)
EIK03 * (0E8H D3)
EIK02 * (0E8H D2)
EIK01 * (0E8H D1)
EIK00 * (0E8H D0)
EIK10 * (0E9H D0)
EIMEL (0E7H D0)
Interrupt Factor Flag
IT2 (0EFH D2)
IT8 (0EFH D1)
IT32 (0EFH D0)
ISW1 (0EEH D1)
ISW0 (0EEH D0)
IK0 (0EDH D0)
IK1 (0EDH D1)
IMEL (0ECH D0)
* There is an interrupt mask register for each input port pin.
Writing to the interrupt mask registers should be done only in the
DI status (interrupt flag = 0). Otherwise it causes malfunction.
Specific masks and
factor flags for inter-
rupt
Table 4.12.2
Interrupt mask registers and
interrupt factor flags
Note
I-112 EPSON S1C62N82 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT)
Interrupt vectors and
priorities
Note
Table 4.12.3
Interrupt vectors
and priorities
Note
When an interrupt request is input to the CPU, the CPU
begins interrupt processing. After the program being exe-
cuted is suspended, interrupt processing is executed in the
following order:
➀The address data (value of the program counter) of the
program step to be executed next is saved on the stack
(RAM).
➁The interrupt request causes the value of the interrupt
vector (page 1, 02H–0BH) to be loaded into the program
counter.
➂The program at the specified address is executed (execu-
tion of interrupt processing routine).
Table 4.12.3 shows the correspondence of interrupt vectors
and priorities.
The processing in steps 1 and 2, above, takes 12 cycles of the
CPU system clock.
Vector Priority Interrupt Request
10AH 1 Melody interrupt
108H 2 Input (K10) interrupt
106H 3 Input (K00–K03) interrupt
104H 4 Stopwatch timer interrupt
102H 5 Clock timer interrupt
When multiple interrupts occur simultaneously, the interrupt vec-
tors with higher priority will be executed.
S1C62N82 TECHNICAL HARDWARE EPSON I-113
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT)
Tables 4.12.4 (a)–(c) shows the interrupt control bits and
their addresses.
Table 4.12.4 (a) Interrupt control bits (1)
Control of interrupt
Address Comment
Register
D3 D2 D1 D0 Name SR 1 0
0E5H
0E6H
0E7H
KCP03 KCP02 KCP01 KCP00
0 0 0 KCP10
00 0EIMEL
R
R
R/W
KCP03
KCP02
KCP01
KCP00
0
0
0
0
Input comparison register (K03)
Input comparison register (K02)
Input comparison register (K01)
Input comparison register (K00)
0
0
0
KCP10 0
0
0
0
EIMEL 0 Enable Mask
Input comparison register (K10)
Falling
Falling
Falling
Falling
Rising
Rising
Rising
Rising
Interrupt mask register (melody)
Falling Rising
R/W
R/W
0E8H
EIK03 EIK02 EIK01 EIK00
R/W
EIK03
EIK02
EIK01
EIK00
0
0
0
0
Interrupt mask register (K03)
Interrupt mask register (K02)
Interrupt mask register (K01)
Interrupt mask register (K00)
Enable
Enable
Enable
Enable
Mask
Mask
Mask
Mask
I-114 EPSON S1C62N82 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT)
Table 4.12.4 (b) Interrupt control bits (2)
Address Comment
Register
D3 D2 D1 D0 Name SR 1 0
0E9H
0EAH
0EBH
0 0 0 EIK10
0 0 EISW1 EISW0
0 EIT2 EIT8 EIT32
R
R
R
0
0
0
EIK10 0
Interrupt mask register (K10)
0
0
EISW1
EISW0
0
0
0
EIT2
EIT8
EIT32
0
0
0
Enable
Enable
Enable
Mask
Mask
Mask
Interrupt mask register (stopwatch 1 Hz)
Interrupt mask register (stopwatch 10 Hz)
Enable Mask
Interrupt mask register (clock timer 2 Hz)
Interrupt mask register (clock timer 8 Hz)
Interrupt mask register (clock timer 32 Hz)
Enable
Enable
Mask
Mask
R/W
R/W
R/W
0ECH
0 0 0 IMEL
R
0
0
0
IMEL 0
Interrupt factor flag (melody)
Yes No
S1C62N82 TECHNICAL HARDWARE EPSON I-115
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT)
Table 4.12.4 (c) Interrupt control bits (3)
Address Comment
Register
D3 D2 D1 D0 Name SR 1 0
0EDH
0EEH
0EFH
00IK1IK0
0 0 ISW1 ISW0
0 IT2 IT8 IT32
R
R
0
0
IK1
IK0
0
0
Interrupt factor flag (K10)
Interrupt factor flag (K00–K03)
0
0
ISW1
ISW0
0
0
0
IT2
IT8
IT32
0
0
0
Yes
Yes
Yes
No
No
No
Interrupt factor flag (stopwatch 1 Hz)
Interrupt factor flag (stopwatch 10 Hz)
Yes
Yes
No
No
Interrupt factor flag (clock timer 2 Hz)
Interrupt factor flag (clock timer 8 Hz)
Interrupt factor flag (clock timer 32 Hz)
Yes
Yes
No
No
R
I-116 EPSON S1C62N82 TECHNICAL HARDWARE
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT)
Interrupt mask registers (0EBH D0–D2)
Interrupt factor flags (0EFH D0–D2)
See 4.7, "Clock Timer".
Interrupt mask registers (0EAH D0–D1)
Interrupt factor flags (0EEH D0–D1)
See 4.8, "Stopwatch Timer".
Input comparison registers (0E5H)
Interrupt mask registers (0E8H)
Interrupt factor flag (0EDH D0)
See 4.3, "Input Ports".
Input comparison register (0E6H D0)
Interrupt mask register (0E9H D0)
Interrupt factor flag (0EDH D1)
See 4.3, "Input Ports".
Interrupt mask register (0E7H D0)
Interrupt factor flag (0ECH D0)
See 4.11, "Melody Generator".
EIT32, EIT8, EIT2
IT32, IT8, IT2
EISW0, EISW1
ISW0, ISW1
KCP00–KCP03
EIK00–EIK03
IK0
KCP10
EIK10
IK1
EIMEL
IMEL
S1C62N82 TECHNICAL HARDWARE EPSON I-117
CHAPTER 5: BASIC EXTERNAL WIRING DIAGRAM
BASIC EXTERNAL WIRING DIA-
GRAM
(1) Piezo Buzzer Single Terminal Driving
(Piezo buzzer driving through PNP transistor)
CHAPTER 5
CA
CB
CC
CD
V
V
V
V
V
OSC1
OSC2
OSC3
OSC4
V
RESET
TEST
Vss
C1
C2
C3
C4
C5
C6
C7
C
X'tal
L1
L2
L3
L4
DD
S1
1.5V
or
3.0V
Piezo
Buzzer
R12
MO
K00
K03
K10
P00
P03
CMPP
CMPM
R00
R03
R10
R11
I
I/O
O
SEG0
COM7/SEG38
COM6/SEG39
COM5/SEG40
COM4/SEG41
COM3
COM0
LCD
PANEL
S1C62N82
S1C62L82
S1C62A82
O
Coil
GX
Cp
Ceramic
C
GC
C
DC
C8
*1
*2
*2
R
CR1
R
CR3
X'tal
R
Ceramic
R
C , C
C
C1–C8
Cp
Crystal oscillator
CR oscillation resistor
Ceramic oscillator
CR oscillation resistor
Capacitor
Trimmer capacitor
Capacitor
Capacitor
32,768 Hz CI(MAX)=35 k
850 k
1 MHz (Typ.)
35 k
100 pF
5–25 pF
0.1 F
3.3 F
Ω
CR1
CR3
GC
GX
µ
µ
DC
Ω
Ω
*1 OSC3 oscillation circuit can be used only for S1C62A82. For the S1C62N82
and 62L82, do not connect anything to terminals OSC3 and OSC4.
*2 In case 1/4 duty was selected with the mask option, set CD and VL4 to N.C.
(not connected). The C3 and C7 capacitor are not required.
The above table is simply an example, and is not guaranteed to work.
Note
I-118 EPSON S1C62N82 TECHNICAL HARDWARE
CHAPTER 5: BASIC EXTERNAL WIRING DIAGRAM
*1 OSC3 oscillation circuit can be used only for S1C62A82. For the S1C62N82
and 62L82, do not connect anything to terminals OSC3 and OSC4.
*2 In case 1/4 duty was selected with the mask option, set CD and VL4 to N.C.
(not connected). The C3 and C7 capacitor are not required.
The above table is simply an example, and is not guaranteed to work.
X'tal
R
C
Ceramic
R
C , C
C1–C8
Cp
R1, R2
Crystal oscillator
CR oscillation resistor
Trimmer capacitor
Ceramic oscillator
CR oscillation resistor
Capacitor
Capacitor
Capacitor
Protection resistance
32,768 Hz CI(MAX)=35 k
850 k
5–25 pF
1 MHz (Typ.)
35 k
100 pF
0.1 F
3.3 F
100
Ω
CR1
GX
CR3
GC
µ
µ
DC
Ω
Ω
Ω
CA
CB
CC
CD
V
V
V
V
V
OSC1
OSC2
OSC3
OSC4
V
RESET
TEST
Vss
C1
C2
C3
C4
C5
C6
C7
C
X'tal
L1
L2
L3
L4
DD
S1 1.5V
or
3.0V
R12
MO
K00
K03
K10
P00
P03
CMPP
CMPM
R00
R03
R10
R11
I
I/O
O
SEG0
COM7/SEG38
COM6/SEG39
COM5/SEG40
COM4/SEG41
COM3
COM0
LCD
PANEL
S1C62N82
S1C62L82
S1C62A82
GX
Cp
Ceramic
CGC
CDC
C8
*1
Piezo
Buzzer
R1 R2
*2
RCR1
RCR3
*2
Note
(2) Piezo Buzzer Direct Driving
S1C62N82 TECHNICAL HARDWARE EPSON I-119
CHAPTER 5: BASIC EXTERNAL WIRING DIAGRAM
*1 OSC3 oscillation circuit can be used only for S1C62A82. For the S1C62N82
and 62L82, do not connect anything to terminals OSC3 and OSC4.
*2 In case 1/4 duty was selected with the mask option, set CD and VL4 to N.C.
(not connected). The C3 and C7 capacitor are not required.
The above table is simply an example, and is not guaranteed to work.
CA
CB
CC
CD
V
V
V
V
V
OSC1
OSC2
OSC3
OSC4
V
RESET
TEST
Vss
C1
C2
C3
C4
C5
C6
C7
C
X'tal
L1
L2
L3
L4
DD
S1
1.5V
or
3.0V
Piezo
Buzzer
R12
MO
K00
K03
K10
P00
P03
CMPP
CMPM
R00
R03
R10
R11
I
I/O
O
SEG0
COM7/SEG38
COM6/SEG39
COM5/SEG40
COM4/SEG41
COM3
COM0
LCD
PANEL
S1C62N82
S1C62L82
S1C62A82
Coil
GX
Cp
Ceramic
C
GC
C
DC
C8
*1
C9 R3
*2
*2
R
CR1
R
CR3
X'tal
R
C
Ceramic
R
C , C
C1–C8
C9
Cp
R3
Crystal oscillator
CR oscillation resistor
Trimmer capacitor
Ceramic oscillator
CR oscillation resistor
Capacitor
Capacitor
Capacitor
Capacitor
Protection resistance
32,768 Hz CI(MAX)=35 k
850 k
5–25 pF
1 MHz (Typ.)
35 k
100 pF
0.1 F
1 F–10 F
3.3 F
1 k
Ω
CR1
GX
CR3
GC
µ
µ
DC
Ω
Ω
Ω
µ µ
Note
(3) Envelope Driving
(Piezo buzzer driving through PNP transistor)
I-120 EPSON S1C62N82 TECHNICAL HARDWARE
CHAPTER 5: BASIC EXTERNAL WIRING DIAGRAM
*1 OSC3 oscillation circuit can be used only for S1C62A82. For the S1C62N82
and 62L82, do not connect anything to terminals OSC3 and OSC4.
*2 In case 1/4 duty was selected with the mask option, set CD and VL4 to N.C.
(not connected). The C3 and C7 capacitor are not required.
The above table is simply an example, and is not guaranteed to work.
CA
CB
CC
CD
V
V
V
V
V
OSC1
OSC2
OSC3
OSC4
V
RESET
TEST
Vss
C1
C2
C3
C4
C5
C6
C7
C
X'tal
L1
L2
L3
L4
DD
S1
1.5V
or
3.0V
Piezo
Buzzer
R12
MO
K00
K03
K10
P00
P03
CMPP
CMPM
R00
R03
R10
R11
I
I/O
O
SEG0
COM7/SEG38
COM6/SEG39
COM5/SEG40
COM4/SEG41
COM3
COM0
LCD
PANEL
S1C62N82
S1C62L82
S1C62A82
Coil
GX
Cp
Ceramic
C
GC
C
DC
C8
*1
C9 R3
*2
*2
R
CR1
R
CR3
X'tal
R
C
Ceramic
R
C , C
C1–C8
C9
Cp
R3
Crystal oscillator
CR oscillation resistor
Trimmer capacitor
Ceramic oscillator
CR oscillation resistor
Capacitor
Capacitor
Capacitor
Capacitor
Protection resistance
32,768 Hz CI(MAX)=35 k
850 k
5–25 pF
1 MHz (Typ.)
35 k
100 pF
0.1 F
1 F–10 F
3.3 F
1 k
Ω
CR1
GX
CR3
GC
µ
µ
DC
Ω
Ω
Ω
µ µ
(4) Envelope Driving
(Piezo buzzer driving through NPN transistor)
Note
S1C62N82 TECHNICAL HARDWARE EPSON I-121
CHAPTER 6: ELECTRICAL CHARACTERISTICS
CHAPTER 6 ELECTRICAL CHARACTERISTICS
6.1 Absolute Maximum Rating
S1C62N82/62A82
S1C62L82
*1 The permissible total output current is the sum total of the
current (average current) that simultaneously flows from the
output pins (or is drawn in).
*2 In case of 80-pin plastic package.
Power voltage
Input voltage (1)
Input voltage (2)
Permissible total output current *1
Operating temperature
Storage temperature
Soldering temperature / Time
Allowable dissipation *2
Item Symbol
Vss
V
V
Ivss
Topr
Tstg
Tsol
P
Rated Value
-6.0 to 0.5
V -0.3 to 0.5
V -0.3 to 0.5
10
-20 to 70
-65 to 150
260°C, 10sec (lead section)
250
Unit
V
V
V
mA
°C
°C
–
mW
(V =0V)
DD
I
IOSC
D
Σ
SS
S1
Power voltage
Input voltage (1)
Input voltage (2)
Permissible total output current *1
Operating temperature
Storage temperature
Soldering temperature / Time
Allowable dissipation *2
Item Symbol
Vss
V
V
Ivss
Topr
Tstg
Tsol
P
Rated Value
-6.0 to 0.5
V -0.3 to 0.5
V -0.3 to 0.5
10
-20 to 70
-65 to 150
260°C, 10sec (lead section)
250
Unit
V
V
V
mA
°C
°C
–
mW
(V =0V)
DD
I
IOSC
D
Σ
SS
S1
*1 The permissible total output current is the sum total of the
current (average current) that simultaneously flows from the
output pins (or is drawn in).
*2 In case of 80-pin plastic package.
I-122 EPSON S1C62N82 TECHNICAL HARDWARE
CHAPTER 6: ELECTRICAL CHARACTERISTICS
6.2 Recommended Operating Conditions
S1C62N82
S1C62L82
Item
Power voltage
Oscillation frequency
Symbol
Vss
fosc1
Condition
V =0V
V =0V,
With software correspondence
V =0V, When analog
comparator is used
DD
DD
DD
Min
-3.5
-3.5
-3.5
Typ
-1.5
-1.5
-1.5
32,768
Unit
V
V
V
Hz
Max
-1.1
-0.9
-1.3
*2
*1
(Ta=-20 to 70°C)
*1 When switching to the heavy load protection mode.
The SVD circuit and analog voltage comparator are turned OFF.
(For details, refer to Section 4.9).
*2 The voltage which can be displayed on the LCD panel will differ
according to the characteristics of the LCD panel.
S1C62A82
Item
Power voltage
Oscillation frequency
Symbol
Vss
fosc1
fosc3
Condition
V =0V
Duty 50±5%
DD
Min
-5.5 Typ
-3.0
32,768
1,000
Unit
V
Hz
kHz
Max
-2.2
(Ta=-20 to 70°C)
Item
Power voltage
Oscillation frequency
Symbol
Vss
fosc1
Condition
V =0V
DD
Min
-5.5 Typ
-3.0
32,768
Unit
V
Hz
Max
-2.2
(Ta=-20 to 70°C)
S1C62N82 TECHNICAL HARDWARE EPSON I-123
CHAPTER 6: ELECTRICAL CHARACTERISTICS
6.3 DC Characteristics
S1C62N82/62A82
Unless otherwise specified
V
DD
=0 V, V
SS
=-3.0 V, fosc=32,768 Hz, Ta=25°C, V
S1
, V
L1
, V
L2
, V
L3
and V
L4
are internal voltages, and C1=C2=C3=C4=C5=C6=0.1 µF
IH
IH
IH
IL
OH1
OH2
OH3
OL1
OL2
OL3
OH4
OL4
OH5
OL5
OH6
OL6
OH7
OL7
OH8
OL8
OH9
OL9
Item
High level input voltage (1)
High level input voltage (2)
Low level input voltage (1)
Low level input voltage (2)
High level input current (1)
High level input current (2)
High level input current (3)
Low level input current
Symbol
V
V
V
V
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Condition
V =0V
Without pull down resistor
V =0V
With pull down resistor
V =0V
With pull down resistor
V =Vss
V =0.1•Vss
V =0.1•Vss
V =0.1•Vss
V =0.9•Vss
V =0.9•Vss
V =0.9•Vss
V =-0.05V
V =V +0.05V
Min
0.2•Vss
0.10•Vss
Vss
Vss
0
5
30
-0.5
3.0
3.0
4.5
3
3
300
3
3
300
Typ Unit
V
V
V
V
µA
µA
µA
µA
mA
mA
mA
mA
mA
mA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
Max
0
0
0.8•Vss
0.90•Vss
0.5
16
100
0
-1.0
-1.0
-2.0
-3
-3
-300
-3
-3
-300
High level output current (1)
High level output current (2)
High level output current (3)
Low level output current (1)
Low level output current (2)
Low level output current (3)
V =-0.05V
V =V +0.05V
V =0.1•Vss
V =0.9•Vss
V =-0.05V
V =V +0.05V
V =-0.05V
V =V +0.05V
V =0.1•Vss
V =0.9•Vss
K00–K03, K10, P00–P03
CMPP, CMPM
K00–K03, K10
P00–P03
RESET, TEST
K00–K03, K10
P00–P03
CMPP, CMPM
RESET, TEST
R11
R00–R03, R10
P00–P03
MO, R12
R11
R00–R03, R10
P00–P03
MO, R12
COM0–COM3
SEG0–SEG41
SEG0–SEG41
COM0–COM7
SEG0–SEG37
SEG0–SEG37
L3
IH1
IH2
IL1
IL2
IH1
IH2
IH3
IL
OH1
OH2
OH3
OL1
OL2
OL3
OH4
OL4
OH5
OL5
OH6
OL6
OH7
OL7
OH8
OL8
OH9
OL9
L3
L4
L4
Common output current
Segment output current
(during LCD output)
Segment output current
(during DC output)
Common output current
Segment output current
(during LCD output)
Segment output current
(during DC output)
K00–K03, K10, P00–P03
RESET, TEST
K00–K03, K10, P00–P03
RESET, TEST
1/4 duty
1/4 duty
1/4 duty
1/8 duty
1/8 duty
1/8 duty
I-124 EPSON S1C62N82 TECHNICAL HARDWARE
CHAPTER 6: ELECTRICAL CHARACTERISTICS
S1C62L82
Unless otherwise specified
V
DD
=0 V, V
SS
=-1.5 V, fosc=32,768 Hz, Ta=25°C, V
S1
, V
L1
, V
L2
, V
L3
and V
L4
are internal voltages, and C1=C2=C3=C4=C5=C6=0.1 µF
IH
IH
IH
IL
OH1
OH2
OH3
OH4
OL1
OL2
OL3
OL4
OH5
OL5
OH6
OL6
OH7
OL7
OH8
OL8
OH9
OL9
OH10
OL10
Item
High level input current (1)
High level input current (2)
High level input current (3)
Low level input current
High level output current (1)
High level output current (2)
Symbol
V
V
V
V
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Condition
V =0V
Without pull down resistor
V =0V
With pull down resistor
V =0V
With pull down resistor
V =Vss
V =0.1•Vss
V =0.1•Vss
V =0.1•Vss
Min
0.2•Vss
0.10•Vss
Vss
Vss
0
2.0
9.0
-0.5
1,300
700
1.5
750
3
3
130
3
3
130
Typ Unit
V
V
V
V
µA
µA
µA
µA
µA
µA
mA
mA
µA
µA
mA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
Max
High level output current (3)
High level output current (4)
Low level output current (1)
Low level output current (2)
Low level output current (3)
Low level output current (4)
V =-0.05V
V =V +0.05V
V =0.1•Vss
V =0.9•Vss
V =-0.05V
V =V +0.05V
V =-0.05V
V =V +0.05V
V =0.1•Vss
V =0.9•Vss
K00–K03, K10, P00–P03
CMPP, CMPM
K00–K03, K10
P00–P03
RESET, TEST
K00–K03, K10
P00–P03
CMPP, CMPM
RESET, TEST3
R11
R00–R03, R10
P00–P03
MO, R12
MO
(R12=Normal H level)
R11
R00–R03, R10
P00–P03
MO, R12
COM0–COM3
SEG0–SEG41
SEG0–SEG41
COM0–COM7
SEG0–SEG37
SEG0–SEG37
L3
IH1
IH2
IL1
IL2
IH1
IH2
IH3
IL
OH1
OH2
OH3
OH4
OL1
OL2
OL3
OL4
OH5
OL5
OH6
OL6
OH7
OL7
OH8
OL8
OH9
OL9
OH10
OL10
L3
K00–K03, K10, P00–P03
RESET, TEST
K00–K03, K10, P00–P03
RESET, TEST
High level input voltage (1)
High level input voltage (2)
Low level input voltage (1)
Low level input voltage (2)
Common output current
Segment output current
(during LCD output)
Segment output current
(during DC output)
Common output current
Segment output current
(during LCD output)
Segment output current
(during DC output)
V =0.1•Vss
When envelope is used
V =0.9•Vss
V =0.9•Vss
V =0.9•Vss
V =0.9•Vss
When envelope is used
V =-0.05V
V =V +0.05V
1/4 duty
1/4 duty
1/4 duty
1/8 duty
1/8 duty
1/8 duty
MO
(R12=Normal L level)
L4
L4
S1C62N82 TECHNICAL HARDWARE EPSON I-125
CHAPTER 6: ELECTRICAL CHARACTERISTICS
6.4 Analog Circuit Characteristics and Power
Current Consumption
S1C62N82 (Normal Operating Mode)
Unless otherwise specified
VDD=0 V, VSS=-3.0 V, fosc=32,768 Hz, Ta=25°C, CG=25 pF,
VS1, VL1, VL2, VL3 and VL4 are internal voltages, and
C1=C2=C3=C4=C5=C6=0.1 µF
Item
Internal voltage
SVD voltage
SVD circuit response time
Analog comparator
input voltage
Analog comparator
offset voltage
Analog comparator
response time
Power current
consumption
Symbol
V
V
V
V
V
T
V
V
V
T
I
I
Condition
Connect 1M load resistor between V and V
(without panel load)
Connect 1M load resistor between V and V
(without panel load)
Connect 1M load resistor between V and V
(without panel load)
DD
DD
DD
DD
Min
0.5•V
-0.1
-2.25
3•V
-0.1
4•V
-0.1
-2.55
Vss+0.3
Typ
-2.10
-2.40
1.5
4.0
6.0
8.7
Unit
V
V
V
V
V
µs
V
mV
ms
µA
µA
µA
µA
Max
0.5•V
+0.1
-1.95
3•V
0.9
4•V
0.9
-2.25
100
V -0.9
10
1
3.0
7.0
10.5
14.0
L2
L1
L1
DD
L1
L2
L3
L4
During HALT
During execution
During HALT
During execution
Without panel load
OSC1 is crystal oscillation
Without panel load
OSC1 is CR oscillation
*1
L1
L2
L3
L4
SVD
SVD
IP
IM
OF
CMP
OP1
OP2
Ω
Ω
Ω
Ω
V =-1.5V
V =V ±15mV
×
×
IP
IM IP
L2
L1
L1
Connect 1M load resistor between V and V
(without panel load)
Non-inverted input (CMPP)
Inverted input (CMPM)
*1
*1
*1
*1 The SVD circuit and analog voltage comparator are turned OFF.
I-126 EPSON S1C62N82 TECHNICAL HARDWARE
CHAPTER 6: ELECTRICAL CHARACTERISTICS
S1C62N82 (Heavy Load Protection Mode)
Unless otherwise specified
VDD=0 V, VSS=-3.0 V, fosc=32,768 Hz, Ta=25°C, CG=25 pF,
VS1, VL1, VL2, VL3 and VL4 are internal voltages, and
C1=C2=C3=C4=C5=C6=0.1 µF
Item
Internal voltage
SVD voltage
SVD circuit response time
Analog comparator
input voltage
Analog comparator
offset voltage
Analog comparator
response time
Power current
consumption
Symbol
V
V
V
V
V
T
V
V
V
T
I
I
Condition
Connect 1M load resistor between V and V
(without panel load)
Connect 1M load resistor between V and V
(without panel load)
Connect 1M load resistor between V and V
(without panel load)
DD
DD
DD
DD
Min
0.5•V
-0.1
-2.25
3•V
-0.1
4•V
-0.1
-2.55
Vss+0.3
Typ
-2.10
-2.40
11.5
14.0
16.0
18.7
Unit
V
V
V
V
V
µs
V
mV
ms
µA
µA
µA
µA
Max
0.5•V
+0.1
-1.95
3•V
0.9
4•V
0.9
-2.25
100
V -0.9
10
1
33.0
37.0
40.5
44.0
L2
L1
L1
DD
L1
L2
L3
L4
During HALT
During execution
During HALT
During execution
Without panel load
OSC1 is crystal oscillation
Without panel load
OSC1 is CR oscillation
*1
L1
L2
L3
L4
SVD
SVD
IP
IM
OF
CMP
OP1
OP2
Ω
Ω
Ω
Ω
V =-1.5V
V =V ±15mV
×
×
IP
IM IP
L2
L1
L1
Connect 1M load resistor between V and V
(without panel load)
Non-inverted input (CMPP)
Inverted input (CMPM)
*1
*1
*1
*1 The SVD circuit and analog voltage comparator are turned OFF.
S1C62N82 TECHNICAL HARDWARE EPSON I-127
CHAPTER 6: ELECTRICAL CHARACTERISTICS
S1C62L82 (Normal Operating Mode)
Unless otherwise specified
VDD=0 V, VSS=-1.5 V, fosc=32,768 Hz, Ta=25°C, CG=25 pF,
VS1, VL1, VL2, VL3 and VL4 are internal voltages, and
C1=C2=C3=C4=C5=C6=0.1 µF
Item
Internal voltage
SVD voltage
SVD circuit response time
Analog comparator
input voltage
Analog comparator
offset voltage
Analog comparator
response time
Power current
consumption
Symbol
V
V
V
V
V
T
V
V
V
T
I
I
Condition
Connect 1M load resistor between V and V
(without panel load)
Connect 1M load resistor between V and V
(without panel load)
Connect 1M load resistor between V and V
(without panel load)
DD
DD
DD
DD
Min
-1.15
2•V
-0.1
3•V
-0.1
4•V
-0.1
-1.30
Vss+0.3
Typ
-1.05
-1.20
1.5
4.0
6.0
8.7
Unit
V
V
V
V
V
µs
V
mV
ms
µA
µA
µA
µA
Max
-0.95
2•V
0.9
3•V
0.9
4•V
0.9
-1.10
100
V -0.9
20
1
3.0
7.0
10.5
14.0
L1
L1
L1
DD
L1
L2
L3
L4
During HALT
During execution
During HALT
During execution
Without panel load
OSC1 is crystal oscillation
Without panel load
OSC1 is CR oscillation
*1
L1
L2
L3
L4
SVD
SVD
IP
IM
OF
CMP
OP1
OP2
Ω
Ω
Ω
Ω
V =-1.1V
V =V ±30mV
×
×
×
IP
IM IP
L1
L1
L1
Connect 1M load resistor between V and V
(without panel load)
Non-inverted input (CMPP)
Inverted input (CMPM)
*1
*1
*1
*1 The SVD circuit and analog voltage comparator are turned OFF.
I-128 EPSON S1C62N82 TECHNICAL HARDWARE
CHAPTER 6: ELECTRICAL CHARACTERISTICS
S1C62L82 (Heavy Load Protection Mode)
Unless otherwise specified
VDD=0 V, VSS=-1.5 V, fosc=32,768 Hz, Ta=25°C, CG=25 pF,
VS1, VL1, VL2, VL3 and VL4 are internal voltages, and
C1=C2=C3=C4=C5=C6=0.1 µF
Item
Internal voltage
SVD voltage
SVD circuit response time
Analog comparator
input voltage
Analog comparator
offset voltage
Analog comparator
response time
Power current
consumption
Symbol
V
V
V
V
V
T
V
V
V
T
I
I
Condition
Connect 1M load resistor between V and V
(without panel load)
Connect 1M load resistor between V and V
(without panel load)
Connect 1M load resistor between V and V
(without panel load)
DD
DD
DD
DD
Min
-1.15
2•V
-0.1
3•V
-0.1
4•V
-0.1
-1.30
Vss+0.3
Typ
-1.05
-1.20
2.5
7.0
11.5
16.5
Unit
V
V
V
V
V
µs
V
mV
ms
µA
µA
µA
µA
Max
-0.95
2•V
0.85
3•V
0.85
4•V
0.85
-1.10
100
V -0.9
20
1
6.0
12.0
20.5
27.0
L1
L1
L1
DD
L1
L2
L3
L4
During HALT
During execution
During HALT
During execution
Without panel load
OSC1 is crystal oscillation
Without panel load
OSC1 is CR oscillation
*1
L1
L2
L3
L4
SVD
SVD
IP
IM
OF
CMP
OP1
OP2
Ω
Ω
Ω
Ω
V =-1.1V
V =V ±30mV
×
×
×
IP
IM IP
L1
L1
L1
Connect 1M load resistor between V and V
(without panel load)
Non-inverted input (CMPP)
Inverted input (CMPM)
*1
*1
*1
*1 The SVD circuit and analog voltage comparator are turned OFF.
S1C62N82 TECHNICAL HARDWARE EPSON I-129
CHAPTER 6: ELECTRICAL CHARACTERISTICS
S1C62A82 (Normal Operating Mode)
Unless otherwise specified
VDD=0 V, VSS=-3.0 V, fosc=32,768 Hz, Ta=25°C, CG=25 pF,
VS1, VL1, VL2, VL3 and VL4 are internal voltages, and
C1=C2=C3=C4=C5=C6=0.1 µF
Item
Internal voltage
SVD voltage
SVD circuit response time
Analog comparator
input voltage
Analog comparator
offset voltage
Analog comparator
response time
Power current
consumption
Symbol
V
V
V
V
V
T
V
V
V
T
I
I
Condition
Connect 1M load resistor between V and V
(without panel load)
Connect 1M load resistor between V and V
(without panel load)
Connect 1M load resistor between V and V
(without panel load)
DD
DD
DD
DD
Min
0.5•V
-0.1
-2.25
3•V
-0.1
4•V
-0.1
-2.55
Vss+0.3
Typ
-2.10
-2.40
1.70
4.0
150.0
30
30
160
Unit
V
V
V
V
V
µs
V
mV
ms
µA
µA
µA
µA
µA
µA
Max
0.5•V
+0.1
-1.95
3•V
0.9
4•V
0.9
-2.25
100
V -0.9
10
1
3.0
7.0
300.0
60
60
300
L2
L1
L1
DD
L1
L2
L3
L4
During HALT
During 32 kHz execution
During 1 MHz execution
During HALT
During 32 kHz execution
During 1 MHz execution
Without panel load
OSC1 is crystal oscillation
*1
*2
L1
L2
L3
L4
SVD
SVD
IP
IM
OF
CMP
OP1
OP2
Ω
Ω
Ω
Ω
V =-1.5V
V =V ±15mV
×
×
IP
IM IP
L2
L1
L1
Connect 1M load resistor between V and V
(without panel load)
Non-inverted input (CMPP)
Inverted input (CMPM)
*1
Without panel load
OSC1 is CR oscillation
*1
*2
*1
*1 The OSC3 circuit, SVD circuit and analog voltage comparator
are turned OFF.
*2 The SVD circuit and analog voltage comparator are turned OFF.
I-130 EPSON S1C62N82 TECHNICAL HARDWARE
CHAPTER 6: ELECTRICAL CHARACTERISTICS
S1C62A82 (Heavy Load Protection Mode)
Unless otherwise specified
VDD=0 V, VSS=-3.0 V, fosc=32,768 Hz, Ta=25°C, CG=25 pF,
VS1, VL1, VL2, VL3 and VL4 are internal voltages, and
C1=C2=C3=C4=C5=C6=0.1 µF
Item
Internal voltage
SVD voltage
SVD circuit response time
Analog comparator
input voltage
Analog comparator
offset voltage
Analog comparator
response time
Power current
consumption
Symbol
V
V
V
V
V
T
V
V
V
T
I
I
Condition
Connect 1M load resistor between V and V
(without panel load)
Connect 1M load resistor between V and V
(without panel load)
Connect 1M load resistor between V and V
(without panel load)
DD
DD
DD
DD
Min
0.5•V
-0.1
-2.25
3•V
-0.1
4•V
-0.1
-2.55
Vss+0.3
Typ
-2.10
-2.40
11.7
14.0
160.0
40
40
200
Unit
V
V
V
V
V
µs
V
mV
ms
µA
µA
µA
µA
µA
µA
Max
0.5•V
+0.1
-1.95
3•V
0.9
4•V
0.9
-2.25
100
V -0.9
10
1
33.0
37.0
330.0
90
90
420
L2
L1
L1
DD
L1
L2
L3
L4
During HALT
During 32 kHz execution
During 1 MHz execution
During HALT
During 32 kHz execution
During 1 MHz execution
Without panel load
OSC1 is crystal oscillation
*1
*2
L1
L2
L3
L4
SVD
SVD
IP
IM
OF
CMP
OP1
OP2
Ω
Ω
Ω
Ω
V =-1.5V
V =V ±15mV
×
×
IP
IM IP
L2
L1
L1
Connect 1M load resistor between V and V
(without panel load)
Non-inverted input (CMPP)
Inverted input (CMPM)
*1
*1
*2
*1
Without panel load
OSC1 is CR oscillation
*1 The OSC3 circuit, SVD circuit and analog voltage comparator
are turned OFF.
*2 The SVD circuit and analog voltage comparator are turned OFF.
S1C62N82 TECHNICAL HARDWARE EPSON I-131
CHAPTER 6: ELECTRICAL CHARACTERISTICS
6.5 Oscillation Characteristics
Oscillation characteristics will vary according to different
conditions. Use the following characteristics are as refer-
ence values.
S1C62N82/62A82 (OSC1 Crystal Ocsillation)
Unless otherwise specified
VDD=0 V, VSS=-3.0 V, Crystal : Q13MC146, CG=25 pF,
CD=built-in, Ta=25°C
S1C62L82 (OSC1 Crystal Ocsillation)
Unless otherwise specified
VDD=0 V, VSS=-1.5 V, Crystal : Q13MC146, CG=25 pF,
CD=built-in, Ta=25°C
Item
Oscillation start
voltage
Oscillation stop
voltage
Built-in capacity (drain)
Frequency voltage deviation
Frequency IC deviation
Frequency adjustment range
Higher harmonic oscillation
start voltage
Allowable leak resistor
Symbol
Vsta
(Vss)
Vstp
(Vss)
C
f/V
f/I
f/C
Vhho
(Vss)
Rleak
Condition
Tsta 3 sec
Tstp 10 sec
Including the parasitic capacity inside the IC
Vss=-1.1 to -3.5 V (-0.9)
C =5–25 pF
Between OSC1 and V and Vss
DD
Min
-1.1
-1.1
(-0.9)
-10
40
200
Typ
20
Unit
V
V
pF
ppm
ppm
ppm
V
M
Max
5
10
-3.5
Ω
*1
*1
GG
C
D
≤
≤
Item
Oscillation start
voltage
Oscillation stop
voltage
Built-in capacity (drain)
Frequency voltage deviation
Frequency IC deviation
Frequency adjustment range
Higher harmonic oscillation
start voltage
Allowable leak resistor
Symbol
Vsta
(Vss)
Vstp
(Vss)
C
f/V
f/I
f/C
Vhho
(Vss)
Rleak
Condition
Tsta 3 sec
Tstp 10 sec
Including the parasitic capacity inside the IC
Vss=-2.2 to -5.5 V
C =5–25 pF
Between OSC1 and V and Vss
DD
Min
-2.2
-2.2
-10
40
200
Typ
20
Unit
V
V
pF
ppm
ppm
ppm
V
M
Max
5
10
-5.5
Ω
D
C
G
≤
≤
G
*1 Items enclosed in parentheses ( ) are those used when operating
at heavy load protection mode.
I-132 EPSON S1C62N82 TECHNICAL HARDWARE
CHAPTER 6: ELECTRICAL CHARACTERISTICS
S1C62N82/62A82 (OSC1 CR Ocsillation)
Unless otherwise specified
VDD=0 V, VSS=-3.0 V, RCR=850 kΩ, Ta=25°C
Item
Oscillation frequency dispersion
Oscillation start voltage
Oscillation start time
Oscillation stop voltage
Symbol
fosc1
Vsta
Tsta
Vstp
Condition
Vss=-2.2 to -5.5 V
Min
-20
-2.2
-2.2
Typ
32,768 Hz
3
Unit
%
V
ms
V
Max
20
*
* In the S1C62A82, the Typ value of the frequency rises about 10 %.
S1C62L82 (OSC1 CR Ocsillation)
Unless otherwise specified
VDD=0 V, VSS=-1.5 V, RCR=850 kΩ, Ta=25°C
Item
Oscillation frequency dispersion
Oscillation start voltage
Oscillation start time
Oscillation stop voltage
Symbol
fosc1
Vsta
Tsta
Vstp
Condition
Vss=-0.9 to -3.5 V
Min
-20
-0.9
-0.9
Typ
32,768 Hz
3
Unit
%
V
ms
V
Max
20
S1C62A82 (OSC3 CR Ocsillation)
Unless otherwise specified
VDD=0 V, VSS=-3.0 V, RCR=35 kΩ, Ta=25°C
Item
Oscillation frequency dispersion
Oscillation start voltage
Oscillation start time
Oscillation stop voltage
Symbol
fosc3
Vsta
Tsta
Vstp
Condition
Vss=-2.2 to -5.5 V
Min
-30
-2.2
-2.2
Typ
1 MHz Unit
%
V
ms
V
Max
30
3
S1C62A82 (OSC3 Ceramic Ocsillation)
Unless otherwise specified
VDD=0 V, VSS=-3.0 V, ceramic osillator : 1 MHz,
CGC=CDC=100 pF, Ta=25°C
Item
Oscillation start voltage
Oscillation start time
Oscillation stop voltage
Symbol
Vsta
Tsta
Vstp
Condition
Vss=-2.2 to -5.5 V
Min
-2.2
-2.2
Typ Unit
V
ms
V
Max
5
S1C62N82 TECHNICAL HARDWARE EPSON I-133
CHAPTER 7: PACKAGE
CHAPTER 7 PACKAGE
7.1 Plastic Package
QFP5
4164
241
65
80
40
25
14.0
± 0.1
19.6
± 0.4
20.0
± 0.1
25.6
± 0.4
0.8
± 0.1
0.35
± 0.1
Index
0.15
± 0.05
2.7
± 0.1
2.8
1.5
± 0.3
0–12°
I-134 EPSON S1C62N82 TECHNICAL HARDWARE
CHAPTER 7: PACKAGE
QFP14
0.127
± 0.05
1.4
± 0.1
1.0
0.5
± 0.2
0–12°
4160
201
61
80
40
21
Index
12.0
14.0
± 0.4
12.0
± 0.1
14.0
± 0.4
0.5
± 0.1
0.18
± 0.1
± 0.1
S1C62N82 TECHNICAL HARDWARE EPSON I-135
CHAPTER 7: PACKAGE
7.2 Ceramic Package for Test Samples
Pins in parentheses correspond to unconnected pads in the plastic package.
N.C.
N.C.
V
TEST
(K02)
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
(SEG20)
(K03)
N.C.
N.C.
N.C.
R03
R02
R01
R00
MO
R12
R11
R10
K10
K03
K02
K01
K00
RESET
CMPP
CMPM
COM3
COM2
COM1
COM0
N.C.
N.C.
N.C.
(K00)
(SEG21)
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
(K01)
(V )
N.C.
N.C.
N.C.
(V )
P03
P02
P01
P00
CD
CC
CB
CA
V
V
V
V
V
OSC4
OSC3
V
OSC2
OSC1
N.C.
SS
L4
L3
L2
L1
SS
S1
DD
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
SEG38/COM7
SEG39/COM6
SEG40/COM5
SEG41/COM4
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
Pin Name Pin Name Pin Name Pin Name Pin NamePin No Pin No Pin No Pin No Pin No
N.C. : No connection
1
31
20.0
25.75
±0.18
±0.15
30
50
51
80
81100
14.0 ±0.14
19.75 ±0.15
0.35 ±0.05 0.65 ±0.05
0.4 ± 0.08
0.8
0.76± 0.03
0.95± 0.08
Grass
I-136 EPSON S1C62N82 TECHNICAL HARDWARE
CHAPTER 8: PAD LAYOUT
CHAPTER 8 PAD LAYOUT
8.1 Diagram of Pad Layout
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
1716151413121110987654321
21 20 19 18
46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 6244 45
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
X
Y
(0, 0)
2223
63 64 65 66 67
Die No.
Chip size: 4.75 mm × 4.61 mm
Chip thickness: 400 µm
Pad opening: 95 µm
S1C62N82 TECHNICAL HARDWARE EPSON I-137
CHAPTER 8: PAD LAYOUT
8.2 Pad Coordinates
PAD No
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
PAD No
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
PAD NAME
(K02)
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
(SEG20)
(K03)
R03
R02
R01
R00
MO
R12
R11
PAD NAME
R10
K10
K03
K02
K01
K00
RESET
CMPP
CMPM
COM3
COM2
COM1
COM0
(K00)
(SEG21)
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
X
1,957
1,762
1,594
1,426
1,258
1,090
922
754
586
418
250
82
-85
-253
-421
-589
-757
-925
-1,120
-1,313
-1,517
-1,736
-1,902
-2,209
-2,209
-2,209
-2,209
-2,209
-2,209
-2,209
X
-2,209
-2,209
-2,209
-2,209
-2,209
-2,209
-2,209
-2,209
-2,209
-2,209
-2,209
-2,209
-2,209
-1,987
-1,816
-1,648
-1,480
-1,312
-1,144
-976
-757
-589
-421
-174
-6
161
329
497
665
833
Y
2,138
2,138
2,138
2,138
2,138
2,138
2,138
2,138
2,138
2,138
2,138
2,138
2,138
2,138
2,138
2,138
2,138
2,138
2,138
2,138
2,138
2,138
2,138
1,928
1,768
1,607
1,447
1,214
829
668
Y
508
260
91
-77
-246
-414
-667
-1,025
-1,193
-1,353
-1,521
-1,682
-1,849
-2,139
-2,139
-2,139
-2,139
-2,139
-2,139
-2,139
-2,139
-2,139
-2,139
-2,139
-2,139
-2,139
-2,139
-2,139
-2,139
-2,139
PAD No
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
PAD NAME
SEG37
(K01)
(V )
(V )
P03
P02
P01
P00
CD
CC
CB
CA
V
V
V
V
V
OSC4
OSC3
V
OSC2
OSC1
V
TEST
X
1,001
1,214
1,382
1,550
1,718
1,888
2,048
2,209
2,209
2,209
2,209
2,209
2,209
2,209
2,209
2,209
2,209
2,209
2,209
2,209
2,209
2,209
2,209
2,209
2,209
2,209
2,209
2,209
Y
-2,139
-2,139
-2,139
-2,139
-2,139
-2,139
-2,139
-1,757
-1,596
-1,436
-1,275
-1,115
-849
-689
-529
-368
-208
-47
112
273
487
647
807
968
1,128
1,289
1,449
1,850
SS
L4
L3
L2
L1
SS
S1
DD
SEG38
COM7
SEG39
COM6
SEG40
COM5
SEG41
COM4
DD
In pads K00 to K03, VDD and VSS are present at two points, and the same signal line is
connected to each pair of pads. So only one pad can be used. With VDD and VSS,
however, stability can sometimes be improved by connecting both pads to the power
source. The pads in parentheses have no package terminals.
Note
Software
S1C62N82
II.
Technical Software
Software
S1C62N82 TECHNICAL SOFTWARE EPSON II-i
CONTENTS
CONTENTS
CHAPTER 1 CONFIGURATION ........................................................... II-1
1.1 S1C62N82 Block Diagram ............................................. II-1
1.2 ROM Map ....................................................................... II-2
1.3 Interrupt Vectors............................................................. II-3
1.4 Data Memory Map.......................................................... II-4
CHAPTER 2 INITIAL RESET .................................................................. II-12
2.1 Internal Register Status on Initial Reset ........................ II-12
2.2 Initialize Program Example............................................ II-14
CHAPTER 3 PERIPHERAL CIRCUITS.................................................... II-16
3.1 Oscillation Circuit........................................................... II-16
Oscillation circuit memory map............................... II-16
Examples of oscillation circuit control program ....... II-17
3.2 Input Ports ..................................................................... II-19
Input port memory map .......................................... II-19
Control of the input port ......................................... II-20
Examples of input port control program .................. II-21
3.3 Output Ports .................................................................. II-22
Output port memory map........................................ II-22
Control of the output port ....................................... II-22
Examples of output port control program ................ II-23
3.4 Special Use Output Ports .............................................. II-24
Special use output port memory map ...................... II-24
Control of the special use output port ..................... II-25
Example of special use output port control program II-26
II-ii EPSON S1C62N82 TECHNICAL SOFTWARE
CONTENTS
3.5 I/O Ports ........................................................................ II-27
I/O port memory map ............................................. II-27
Control of the I/O port ............................................ II-28
Examples of I/O port control program ..................... II-28
3.6 LCD Driver..................................................................... II-31
LCD driver memory map ......................................... II-31
Control of the LCD driver ........................................ II-32
Examples of LCD driver control program ................. II-34
3.7 Timer ............................................................................. II-39
Timer memory map ................................................. II-39
Control of the timer................................................. II-40
Examples of timer control program.......................... II-41
3.8 Stopwatch Timer ........................................................... II-43
Stopwatch timer memory map................................. II-43
Control of the stopwatch timer ................................ II-44
Examples of stopwatch timer control program ......... II-45
3.9 Supply Voltage Detection (SVD) Circuit
and Heavy Load Protection Function ............................ II-47
SVD circuit and heavy load protection
function memory map ............................................. II-47
Control of the SVD circuit ....................................... II-48
Example of SVD circuit control program
(At fosc1 = 32.768 kHz) ........................................... II-48
Heavy load protection function ................................ II-49
Examples of heavy load protection
function control program......................................... II-51
3.10 Analog Comparator ....................................................... II-54
Analog comparator memory map ............................. II-54
Example of CMP control program
(At fosc1 = 32.768 kHz) ........................................... II-55
Software
S1C62N82 TECHNICAL SOFTWARE EPSON II-iii
CONTENTS
3.11 Melody Generator.......................................................... II-56
Melody generator memory map................................ II-56
Address setting (Addresses 0F0H and 0F1H) ........... II-57
Play mode control.................................................... II-57
Melody interrupt ..................................................... II-64
Melody ROM ........................................................... II-64
Scale ROM .............................................................. II-66
Examples of melody control program....................... II-66
3.12 Interrupt and Halt........................................................... II-70
Interrupt memory map ............................................ II-70
Control of interrupts and halt ................................. II-73
Examples of interrupt and halt control program ...... II-85
CHAPTER 4 SUMMARY OF PROGRAMMING POINTS....................... II-89
APPENDIX A Table of Instructions ...................................................... II-94
B The S1C62N82 I/O Memory Map.................................. II-99
C Table of the ICE Commands ........................................ II-101
D Cross-assembler Pseudo Instruction List..................... II-103
E The Format of Melody Source File ............................... II-104
Source File Name ................................................... II-104
Statement (line)...................................................... II-104
Attack field ........................................................ II-105
Note field ........................................................... II-105
Scale field .......................................................... II-105
End bit field....................................................... II-105
Comment field ................................................... II-105
F Dividing Table............................................................... II-106
G RAM Map ..................................................................... II-108
S1C62N82 TECHNICAL SOFTWARE EPSON II-1
CHAPTER 1: CONFIGURATION
CHAPTER 1
1.1
CONFIGURATION
S1C62N82 Block Diagram
Fig. 1.1.1
S1C62N82 block diagram
Melody
Comparator
& SVD
Power
Controller
LCD
Driver
RAM
224x4 Interrupt
Generator
I Port
Test Port
I/O Port
O Port
Timer
Stop
Watch
Core CPU S1C6200A
ROM
2,048x12 OSC System
Reset
Control
RESET
OSC3
V
V
V
CA
CD
V
Vss
K10
TEST
P00~P03
R00~R03
R10, R11
DD
S1
L1
L4
OSC2
CMPP
CMPM
MO
R12
OSC4
OSC1
SEG0
COM7/SEG38
COM6/SEG39
COM5/SEG40
COM4/SEG41
COM0
K00~K03
II-2 EPSON S1C62N82 TECHNICAL SOFTWARE
CHAPTER 1: CONFIGURATION
ROM Map
The S1C62N82 has a built-in mask ROM with a capacity of
2,048 steps × 12 bits for program storage. The configuration
of the ROM is shown in Figure 1.2.1.
1.2
00H step
02H step
0BH step
0CH step
FFH step
12 bits
Program start address
Interrupt vector area
Bank 0
Program area
0 page
1 page
2 page
3 page
01H step
4 page
5 page
6 page
7 page
Fig. 1.2.1
Configuration of built-in ROM
S1C62N82 TECHNICAL SOFTWARE EPSON II-3
CHAPTER 1: CONFIGURATION
1.3 Interrupt Vectors
When an interrupt request is received by the CPU, the CPU
initiates the following interrupt processing after completing
the instruction being executed.
(1)The address of the next instruction to be executed (the
value of the program counter) is saved on the stack
(RAM).
(2)The interrupt vector address corresponding to the inter-
rupt request is loaded into the program counter.
(3)The branch instruction written in the vector is executed
to branch to the software interrupt processing routine.
Steps 1 and 2 require 12 cycles of the CPU system clock.
The correspondence between interrupt requests and vectors
are shown in Table 1.3.1.
When multiple interrupts occur simultaneously, they are
executed in order of priority.
Note
Table 1.3.1
Interrupt requests and vectors
Vector Priority Interrupt Request
10AH
108H
106H
104H
102H
1
2
3
4
5
Melody interrupt
Input (K10) interrupt
Input (K00–K03) interrupt
Stopwatch timer interrupt
Clock timer interrupt
II-4 EPSON S1C62N82 TECHNICAL SOFTWARE
CHAPTER 1: CONFIGURATION
Data Memory Map
The S1C62N82 built-in RAM has 144 words of data memory,
80 words of display memory for the LCD, and I/O memory
for controlling the peripheral circuit. When writing pro-
grams, note the following:
(1)Since the stack area is in the data memory area, take
care not to overwrite the stack with data. Subroutine
calls or interrupts use 3 words on the stack.
(2)Data memory addresses 000H–00FH are memory register
areas that are addressed with register pointer RP.
1.4
Address
Page High
Low 0123456789ABCDEF
M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF
3
0
1
2
4
5
6
7
8
9
A
B
C
D
E
F
0
RAM area (000H–08FH)
144 words x 4 bits (R/W)
I/O memory area Table 1.4.1 (a)–(g)
Display memory area (090H–0DFH)
80 words x 4 bits (R/W)
Unused area
*
Fig. 1.4.1
Data memory map
*If the duty of the LCD driver is set to 1/8 by the mask
option in the display memory area (80 words × 4 bits), 304
bits (38 segments × 8 common bits) are used. If the duty is
set to 1/4, 168 bits (42 segments × 4 common bits) are
used. The bits unassigned as display memory can serve
as a general-purpose RAM.
Memory is not mounted in unused area within the memory map
and in memory area not indicated in this chapter. For this reason,
normal operation cannot be assured for programs that have been
prepared with access to these areas.
Note
S1C62N82 TECHNICAL SOFTWARE EPSON II-5
CHAPTER 1: CONFIGURATION
Address Comment
Register
D3 D2 D1 D0 Name SR *1 10
0E0H
0E1H
0E2H
0E3H
K03 K02 K01 K00
0 0 0 K10
SWL3 SWL2 SWL1 SWL0
SWH3 SWH2 SWH1 SWH0
R
R
R
R
K03
K02
K01
K00
–
–
–
–
0
0
0
K10 –
Input port (K10)
SWL3
SWL2
SWL1
SWL0
0
0
0
0
SWH3
SWH2
SWH1
SWH0
0
0
0
0
MSB
Stopwatch timer
1/100 sec (BCD)
LSB
Input port (K00–K03)
High
High
High
High
Low
Low
Low
Low
High Low
MSB
Stopwatch timer
1/10 sec (BCD)
LSB
*5
*5
*5
*2
*2
*2
*2
*2
Table 1.4.1 (a) I/O memory map (0E0H–0E3H)
*1 Initial value following initial reset
*2 Not set in the circuit
*3 Undefined
*4 Reset (0) immediately after being read
*5 Always 0 when being read
*6 Refer to main manual
II-6 EPSON S1C62N82 TECHNICAL SOFTWARE
CHAPTER 1: CONFIGURATION
Address Comment
Register
D3 D2 D1 D0 Name SR *1 10
0E4H
0E5H
0E6H
0E7H
TM3 TM2 TM1 TM0
KCP03 KCP02 KCP01 KCP00
0 0 0 KCP10
0 0 0 EIMEL
R
R
R/W
R
TM3
TM2
TM1
TM0
–
–
–
–
KCP03
KCP02
KCP01
KCP00
0
0
0
0
Input comparison register (K03)
Input comparison register (K02)
Input comparison register (K01)
Input comparison register (K00)
0
0
0
KCP10 0
0
0
0
EIMEL 0 Enable Mask
Input comparison register (K10)
Timer data (clock timer 2 Hz)
Timer data (clock timer 4 Hz)
Timer data (clock timer 8 Hz)
Timer data (clock timer 16 Hz)
High
High
High
High
Low
Low
Low
Low
Falling
Falling
Falling
Falling
Rising
Rising
Rising
Rising
Interrupt mask register (melody)
Falling Rising
*5
*5
*5
R/W
*5
*5
*5
R/W
*1 Initial value following initial reset
*2 Not set in the circuit
*3 Undefined
*4 Reset (0) immediately after being read
*5 Always 0 when being read
*6 Refer to main manual
Table 1.4.1 (b) I/O memory map (0E4H–0E7H)
S1C62N82 TECHNICAL SOFTWARE EPSON II-7
CHAPTER 1: CONFIGURATION
Address Comment
Register
D3 D2 D1 D0 Name SR *1 10
0E8H
0E9H
0EAH
0EBH
EIK03 EIK02 EIK01 EIK00
0 0 0 EIK10
0 0 EISW1 EISW0
0 EIT2 EIT8 EIT32
R
R
R
R/W
EIK03
EIK02
EIK01
EIK00
0
0
0
0
0
0
0
EIK10 0
Interrupt mask register (K10)
0
0
EISW1
EISW0
0
0
0
EIT2
EIT8
EIT32
0
0
0
Enable
Enable
Enable
Mask
Mask
Mask
Interrupt mask register (stopwatch 1 Hz)
Interrupt mask register (stopwatch 10 Hz)
Interrupt mask register (K03)
Interrupt mask register (K02)
Interrupt mask register (K01)
Interrupt mask register (K00)
Enable
Enable
Enable
Enable
Mask
Mask
Mask
Mask
Enable Mask
Interrupt mask register (clock timer 2 Hz)
Interrupt mask register (clock timer 8 Hz)
Interrupt mask register (clock timer 32 Hz)
Enable
Enable
Mask
Mask
*5
*5
R/W
*5
R/W
R/W
*5
*5
*5
*1 Initial value following initial reset
*2 Not set in the circuit
*3 Undefined
*4 Reset (0) immediately after being read
*5 Always 0 when being read
*6 Refer to main manual
Table 1.4.1 (c) I/O memory map (0E8H–0EBH)
II-8 EPSON S1C62N82 TECHNICAL SOFTWARE
CHAPTER 1: CONFIGURATION
*1 Initial value following initial reset
*2 Not set in the circuit
*3 Undefined
*4 Reset (0) immediately after being read
*5 Always 0 when being read
*6 Refer to main manual
Address Comment
Register
D3 D2 D1 D0 Name SR *1 10
0ECH
0EDH
0EEH
0EFH
0 0 0 IMEL
00IK1IK0
0 0 ISW1 ISW0
0 IT2 IT8 IT32
R
R
R
0
0
0
IMEL 0
0
0
IK1
IK0
0
0
Interrupt factor flag (K10)
Interrupt factor flag (K00–K03)
0
0
ISW1
ISW0
0
0
0
IT2
IT8
IT32
0
0
0
Yes
Yes
Yes
No
No
No
Interrupt factor flag (stopwatch 1 Hz)
Interrupt factor flag (stopwatch 10 Hz)
Interrupt factor flag (melody)
Yes No
Yes
Yes
No
No
Interrupt factor flag (clock timer 2 Hz)
Interrupt factor flag (clock timer 8 Hz)
Interrupt factor flag (clock timer 32 Hz)
Yes
Yes
No
No
*5
*5
*4
*4
R
*5
*4
*4
*4
*5
*5
*4
*4
*5
*5
*5
*4
Table 1.4.1 (d) I/O memory map (0ECH–0EFH)
S1C62N82 TECHNICAL SOFTWARE EPSON II-9
CHAPTER 1: CONFIGURATION
Address Comment
Register
D3 D2 D1 D0 Name SR *1 10
0F0H
0F1H
0F2H
0F3H
MAD3 MAD2 MAD1 MAD0
0 MAD6 MAD5 MAD4
CLKC1 CLKC0 TEMPC MELC
R03 R02 R01 R00
R/W
R
R/W
MAD3
MAD2
MAD1
MAD0
0
0
0
0
0
MAD6
MAD5
MAD4
0
0
0
Melody ROM address (AD6, MSB)
Melody ROM address (AD5)
Melody ROM address (AD4)
CLKC1
CLKC0
TEMPC
MELC
0
0
0
0
R03
R02
R01
R00
0
0
0
0
High
High
High
High
Low
Low
Low
Low
CLKC1(0)&CLKC0(0) : melody speed 1
CLKC1(0)&CLKC0(1) : melody speed 8
CLKC1(1)&CLKC0(0) : melody speed 16
CLKC1(1)&CLKC0(1) : melody speed 32
Tempo change control
Melody control ON/OFF
Melody ROM address (AD3)
Melody ROM address (AD2)
Melody ROM address (AD1)
Melody ROM address (AD0, LSB)
High
High
High
High
Low
Low
Low
Low
High
High
High
Low
Low
Low
Output port data (R00–R03)
High
High
High
ON
Low
Low
Low
OFF
R/W
*5
R/W
×
×
×
×
*1 Initial value following initial reset
*2 Not set in the circuit
*3 Undefined
*4 Reset (0) immediately after being read
*5 Always 0 when being read
*6 Refer to main manual
Table 1.4.1 (e) I/O memory map (0F0H–0F3H)
II-10 EPSON S1C62N82 TECHNICAL SOFTWARE
CHAPTER 1: CONFIGURATION
Address Comment
Register
D3 D2 D1 D0 Name SR *1 10
0F4H
0F6H
0F9H
0FAH
R12
MO
ENV
R11 R10
FOUT
P03 P02 P01 P00
0 TMRST SWRUN SWRST
HLMOD 0 SVDDT SVDON
W
R/W
MELD
R12
MO
ENV
R11
R10
FOUT
P03
P02
P01
P00
–
–
–
–
I/O port (P00–P03)
0
TMRST
SWRUN
SWRST
Reset
0
Reset
HLMOD
0
SVDDT
SVDON
0
0
0 ON OFF
Clock timer reset
Stopwatch timer RUN/STOP
Stopwatch timer reset
Melody output mask
Output port data (R12)
Inverting melody output
Melody envelope control
Output port data (R11)
Output port data (R10)
Frequency output
Disable
High
–
–
High
High
ON
Enable
Low
–
–
Low
Low
OFF
High
High
High
High
Low
Low
Low
Low
Heavy load protection mode register
Supply voltage detector data
Supply voltage detector ON/OFF
Reset
Run
Reset
–
Stop
–
R
*2
*2
*2
*2
R/W
R/W WR
R/W R/W
Heavy
load
Supply
voltage
low
Normal
load
Supply
voltage
normal
*5
*5
*5
*5
0
0
–
Hz
0
0
MELD
*6
Table 1.4.1 (f) I/O memory map (0F4H, 0F6H, 0F9H–0FAH)
*1 Initial value following initial reset
*2 Not set in the circuit
*3 Undefined
*4 Reset (0) immediately after being read
*5 Always 0 when being read
*6 Refer to main manual
S1C62N82 TECHNICAL SOFTWARE EPSON II-11
CHAPTER 1: CONFIGURATION
Address Comment
Register
D3 D2 D1 D0 Name SR *1 10
0FBH
0FCH
CSDC 0 CMPDT CMPON
CLKCHG OSCC 0 IOC
R/W
R
0
1
0
CLKCHG
OSCC
0
IOC
0
0
0
CPU clock switch
OSC3 oscillator ON/OFF
I/O port P00–P03 Input/Output
LCD drive switch
Analog voltage comparator ON/OFF
Static
+ > -
ON
Dynamic
- > +
OFF
OSC3
ON
Output
OSC1
OFF
Input
*5
*5
R/W
R/W R/W
CSDC
0
CMPDT
CMPON
Comparator's voltage condition:
1 = CMPP(+)input > CMPM(-)input,
0 = CMPM(-)input > CMPP(+)input
R
Table 1.4.1 (g) I/O memory map (0FBH–0FCH)
*1 Initial value following initial reset
*2 Not set in the circuit
*3 Undefined
*4 Reset (0) immediately after being read
*5 Always 0 when being read
*6 Refer to main manual
II-12 EPSON S1C62N82 TECHNICAL SOFTWARE
CHAPTER 2: INITIAL RESET
INITIAL RESET
Internal Register Status on Initial Reset
Following an initial reset, the internal registers and internal
data memory area are initialized to the values shown in
Tables 2.1.1 and 2.1.2.
Internal Register Bit Length Initial Value Following Reset
Program counter step PCS 8 00H
Program counter page PCP 4 1H
New page pointer NPP 4 1H
Stack pointer SP 8 Undefined
Index register X 8 Undefined
Index register Y 8 Undefined
Register pointer RP 4 Undefined
General register A 4 Undefined
General register B 4 Undefined
Interrupt flag I 1 0
Decimal flag D 1 0
Zero flag Z 1 Undefined
Carry flag C 1 Undefined
Internal Data Initial Value
Memory Area Following Reset
RAM data 4 × 144 Undefined 000H–08FH
Display memory 4 × 80 Undefined 090H–0DFH
Internal I/O register See Tables 1.4.1 (a)–(g) 0E0H–0FCH
2.1
Table 2.1.1
Initial values of internal
registers
CHAPTER 2
Table 2.1.2
Initial values of internal data
memory area
Bit Length Address
S1C62N82 TECHNICAL SOFTWARE EPSON II-13
CHAPTER 2: INITIAL RESET
After an initial reset, the program counter page (PCP) is
initialized to 1H, and the program counter step (PCS), to
00H. This is why the program is executed from step 00H of
the first page.
The initial values of some internal registers and internal
data memory area locations are undefined after a reset. Set
them as necessary to the proper initial values in the pro-
gram.
The peripheral I/O functions (memory-mapped I/O) are
assigned to internal data memory area addresses 0E0H to
0FCH. Each address represents a 4-bit internal I/O register,
allowing access to the peripheral functions in 1-word (4-bit)
read/write units.
II-14 EPSON S1C62N82 TECHNICAL SOFTWARE
CHAPTER 2: INITIAL RESET
Initialize Program Example
The following is a program that clears the RAM and LCD,
resets the flags, registers, timer, and stopwatch timer, and
sets the stack pointer immediately after resetting the sys-
tem.
Label Mnemonic/operand Comment
ORG 100H
JP INIT ;Jump to "INIT"
;ORG 110H
INIT RST F,0011B ;Interrupt mask, decimal
;adjustment off
;LD X,0 ;
RAMCLR LDPX MX,0 ;
CP XH,0EH ;
JP NZ,RAMCLR ;
;LD A,0 ;
LD B,9 ;
LD SPL,A ;
LD SPH,B ;
;LD X,0F9H ;
OR MX,0101B ;
;LD X,0EBH ;
OR MX,0111B ;
;LD X,0E8H ;
OR MX,1111B ;
;LD X,0 ;
LD Y,0 ;
LD A,0 ;
LD B,0 ;
RST F,0 ;
EI ;Enable interrupt
2.2
Clear RAM (00H–8FH)
and LCD RAM (90H–DFH)
Enable timer interrupt
Enable input interrupt
(K03–K00)
Reset timer and stopwatch
timer
Set stack pointer to 90H
Reset register flags
S1C62N82 TECHNICAL SOFTWARE EPSON II-15
CHAPTER 2: INITIAL RESET
The above program is a basic initialization program for the
S1C62N82. The setting data are all initialized as shown in
Table 2.1.1 by executing this program. When using this
program, add setting items necessary for each specific
application. (Figure 2.2.1 is the flow chart for this program.)
Fig. 2.2.1
Flow chart of the initialization
program
Initialization
Reset
I (Interrupt flag)
D (Decimal adjustment flag)
Clear RAM
Set SP
Reset timer,
stopwatch timer
Enable timer interrupt
Enable input interrupt
Reset registers (X, Y, A, B)
flags (I, Z, D, C)
EI (enable interrupt)
I:
D:
Clear data RAM (00H to 08FH)
Clear segment RAM (90H to 0DFH)
Set stack pointer to 90H
Enable timer interrupt 2 Hz, 8 Hz, 32 Hz
Enable K03–K00 input port interrupt
To next process
Interrupt flag
Decimal adjustment flag
II-16 EPSON S1C62N82 TECHNICAL SOFTWARE
CHAPTER 3: PERIPHERAL CIRCUITS (Oscillation Circuit)
PERIPHERAL CIRCUITS
Details on how to control the S1C62N82 peripheral circuit is
given in this chapter.
Oscillation Circuit
S1C62N82 has two built-in oscillation circuits (OSC1 and
OSC3).
When processing of S1C62A82 requires high-speed opera-
tions, the CPU's operating clock should be switched from
OSC1 to OSC3.
CHAPTER 3
3.1
Oscillation circuit
memory map
Table 3.1.1 I/O memory map
Address Comment
Register
D3 D2 D1 D0 Name SR 1 0
0FCH
CLKCHG OSCC 0 IOC CLKCHG
OSCC
0
IOC
0
0
0
CPU clock switch
OSC3 oscillator ON/OFF
I/O port P00–P03 Input/Output
OSC3
ON
Output
OSC1
OFF
Input
R/WR/W R
*5
*1 Initial value following initial reset
*2 Not set in the circuit
*3 Undefined
*4 Reset (0) immediately after being read
*5 Always 0 when being read
*6 Refer to main manual
S1C62N82 TECHNICAL SOFTWARE EPSON II-17
CHAPTER 3: PERIPHERAL CIRCUITS (Oscillation Circuit)
– It takes at least 5 ms from the time the OSC3 oscillation circuit
goes ON until the oscillation stabilizes. Consequently, when
switching the CPU operation clock from OSC1 to OSC3, do this
after a minimum of 5 ms have elapsed since the OSC3 oscilla-
tion went ON.
Further, the oscillation stabilization time varies depending on
the external oscillator characteristics and conditions of use, so
allow ample margin when setting the wait time.
– When switching the clock from OSC3 to OSC1, use a separate
instruction for switching the OSC3 oscillation OFF.
– To lessen current consumption, keep OSC3 oscillation OFF
except when the CPU must be run at high speed. Also, with
S1C62N82/62L82, keep OSCC fixed to "0".
Note
Examples of oscilla-
tion circuit control
program
• Switching from OSC1 to OSC3 (At fosc1 = 32.768 kHz)
Label Mnemonic/operand Comment
OS3: LD X,0FCH ;Set OSC3 to ON
OR MX,0100B
;LD A,0EH ;Delay of 5.28 ms: preparation
OS3DLP:ADD A,0FH ;Loop for delay
JP NZ,OS3DLP ;
;OR MX,1000B ;Switch the CPU clock to OSC3
RET ;Return to parent routine
This subroutine first sets OSC3 to ON, and then, after about
5 ms, switches the CPU clock to OSC3.
A 5.28 ms delay is specified before switching to OSC3, to allow
time for the oscillation circuit to stabilize.
Note
II-18 EPSON S1C62N82 TECHNICAL SOFTWARE
CHAPTER 3: PERIPHERAL CIRCUITS (Oscillation Circuit)
Note
• Switching from OSC3 to OSC1
Label Mnemonic/operand Comment
OS1: LD X,0FCH ;Switch the CPU clock to OSC1
AND MX,0111B ;
;AND MX,1011B ;Set OSC3 to OFF
RET ;Return to parent routine
This subroutine switches the CPU clock to OSC1, and then
sets OSC3 to OFF.
To prevent an error, first switch OSC1, and then set OSC3 to OFF
in the next step.
S1C62N82 TECHNICAL SOFTWARE EPSON II-19
CHAPTER 3: PERIPHERAL CIRCUITS (Input Ports)
Input Ports3.2
Input port memory
map
Table 3.2.1 (a) I/O memory map
Address Comment
Register
D3 D2 D1 D0 Name SR *1 10
0E0H
0E1H
K03 K02 K01 K00
0 0 0 K10
R
R
K03
K02
K01
K00
–
–
–
–
0
0
0
K10 –
Input port (K10)
Input port (K00–K03)
High
High
High
High
Low
Low
Low
Low
High Low
*5
*5
*5
*2
*2
*2
*2
*2
0E5H
0E6H
KCP03 KCP02 KCP01 KCP00
0 0 0 KCP10
R
R/W
KCP03
KCP02
KCP01
KCP00
0
0
0
0
Input comparison register (K03)
Input comparison register (K02)
Input comparison register (K01)
Input comparison register (K00)
0
0
0
KCP10 0
Input comparison register (K10)
Falling
Falling
Falling
Falling
Rising
Rising
Rising
Rising
Falling Rising
*5
*5
*5
R/W
*1 Initial value following initial reset
*2 Not set in the circuit
*3 Undefined
*4 Reset (0) immediately after being read
*5 Always 0 when being read
*6 Refer to main manual
II-20 EPSON S1C62N82 TECHNICAL SOFTWARE
CHAPTER 3: PERIPHERAL CIRCUITS (Input Ports)
Control of
the input port
Table 3.2.1 (b) I/O memory map
Address Comment
Register
D3 D2 D1 D0 Name SR
*1
10
0E8H
0E9H
EIK03 EIK02 EIK01 EIK00
0 0 0 EIK10
R
R/W
EIK03
EIK02
EIK01
EIK00
0
0
0
0
0
0
0
EIK10 0
Interrupt mask register (K10)
Interrupt mask register (K03)
Interrupt mask register (K02)
Interrupt mask register (K01)
Interrupt mask register (K00)
Enable
Enable
Enable
Enable
Mask
Mask
Mask
Mask
Enable Mask
R/W
*5
*5
*5
0EDH
00IK1IK0
R
0
0
IK1
IK0
0
0
Interrupt factor flag (K10)
Interrupt factor flag (K00–K03)
Yes
Yes
No
No
*5
*5
*4
*4
*1 Initial value following initial reset
*2 Not set in the circuit
*3 Undefined
*4 Reset (0) immediately after being read
*5 Always 0 when being read
*6 Refer to main manual
The S1C62N82 has one 4-bit input port (K00–K03) and one
1-bit input port (K10). Input port data can be read as a 4-bit
unit (K00–K03, K10).
The state of the input ports can be obtained by reading the
data (bits D3, D2, D1, D0) of address 0E0H and the data (bit
D0) of address 0E1H. The input ports can be used to send
an interrupt request to the CPU via the input interrupt
condition flag. See Section 3.12 "Interrupt and Halt", for
details.
S1C62N82 TECHNICAL SOFTWARE EPSON II-21
CHAPTER 3: PERIPHERAL CIRCUITS (Input Ports)
• Loading K00–K03 into the A register
Label Mnemonic/operand Comment
LD Y,0E0H ;Set address of port
LD A,MY ;A register ← K00–K03
As shown in Figure 3.2.1, the two instruction steps above
load the data of the input port into the A register.
Examples of input
port control
program
D3
K03
D2
K02
D1
K01
D0
K00
A register
Fig. 3.2.1
Loading the A register
The data of the input port can be loaded into the B register
or MX instead of the A register.
• Bit-unit checking of input ports
Label Mnemonic/operand Comment
DI ;Disable interrupt
LD Y,0E0H ;Set address of port
INPUT1: FAN MY,0010B ;
JP NZ,INPUT1 ;Loop until K01 becomes "0"
INPUT2: FAN MY,0010B ;
JP Z,INPUT2 ;Loop until K01 becomes "1"
This program loopes until a rising edge is input to input port
K01.
The input port can be addressed using the X register instead
of the Y register.
When the input port is changed from high level to low level with a
pull-down resistor, the signal falls following a certain delay caused
by the time constants of the pull-down resistance and the input
gate capacitance. It is therefore necessary to observe a proper
wait time before the input port data is read.
Note
II-22 EPSON S1C62N82 TECHNICAL SOFTWARE
CHAPTER 3: PERIPHERAL CIRCUITS (Output Ports)
Output Ports3.3
Output port
memory map
Table 3.3.1 I/O memory map
Control of
the output port
The S1C62N82 Series have 7 bits for general output ports
(R00–R03 and R10–R12). The output port is a read/write
register, output pins provide the contents of the register.
The states of the output ports (R00–R03) are decided by the
data of address 0F3H and R10 to R12 are decided by the
data of address 0F4H. Output ports can also be read, and
output control is possible using the operation instructions
(AND, OR, etc.). The output ports are all initialized to low
level (0) after an initial reset.
*1 Initial value following initial reset
*2 Not set in the circuit
*3 Undefined
*4 Reset (0) immediately after being read
*5 Always 0 when being read
*6 Refer to main manual
Address Comment
Register
D3 D2 D1 D0 Name SR 1 0
0F3H
R03 R02 R01 R00 R03
R02
R01
R00
0
0
0
0
High
High
High
High
Low
Low
Low
Low
Output port data (R00–R03)
R/W
0F4H
R12
MO
ENV
R11 R10
FOUT
R/W
MELD
R12
MO
ENV
R11
R10
FOUT
Melody output mask
Output port data (R12)
Inverting melody output
Melody envelope control
Output port data (R11)
Output port data (R10)
Frequency output
Disable
High
–
–
High
High
ON
Enable
Low
–
–
Low
Low
OFF
0
0
–
Hz
0
0
MELD
*6
S1C62N82 TECHNICAL SOFTWARE EPSON II-23
CHAPTER 3: PERIPHERAL CIRCUITS (Output Ports)
Examples of output
port control
program
• Loading B register data into R00–R03
Label Mnemonic/operand Comment
LD Y,0F3H ;Set address of port
LD MY,B ;R00–R03 ← B register
As shown in Figure 3.3.1, the two instruction steps above
load the data of the B register into the output ports.
The output data can be taken from the A register, MX, or
immediate data instead of the B register.
• Bit-unit operation of output ports
Label Mnemonic/operand Comment
LD Y,0F3H ;Set address of port
OR MY,0010B ;Set R01 to 1
AND MY,1011B ;Set R02 to 0
The three instruction steps above cause the output port to
be set, as shown in Figure 3.3.2.
R03 R02 R01 R00
No change
Sets "1"
Sets "0"
No change
Address 0F3H D3 D2 D1 D0
Fig. 3.3.1
Control of the output port
Fig. 3.3.2
Setting of the output port
D3 D2 D1 D0
Data register R00
Data register R01
Data register R02
Data register R03
B register
II-24 EPSON S1C62N82 TECHNICAL SOFTWARE
CHAPTER 3: PERIPHERAL CIRCUITS (Special Use Output Ports)
Special use output
port memory map
Table 3.4.1 I/O memory map
*1 Initial value following initial reset
*2 Not set in the circuit
*3 Undefined
*4 Reset (0) immediately after being read
*5 Always 0 when being read
*6 Refer to main manual
Special Use Output Ports3.4
Address Comment
Register
D3 D2 D1 D0 Name SR 1 0
0F4H
R12
MO
ENV
R11 R10
FOUT
R/W
MELD
R12
MO
ENV
R11
R10
FOUT
Melody output mask
Output port data (R12)
Inverting melody output
Melody envelope control
Output port data (R11)
Output port data (R10)
Frequency output
Disable
High
–
–
High
High
ON
Enable
Low
–
–
Low
Low
OFF
0
0
–
Hz
0
0
MELD
*6
S1C62N82 TECHNICAL SOFTWARE EPSON II-25
CHAPTER 3: PERIPHERAL CIRCUITS (Special Use Output Ports)
In addition to the regular DC, special output can be selected
for output ports R10–R12, as shown in Table 3.4.2. Figure
3.4.1 shows the structure of output ports R10–R12 and MO.
Pin Name When Special Output is Selected
R12 MO or ENV
R10 FOUT
Control of the spe-
cial use output port
Address
(0F4H)
FOUT
Data bus
R10
R11
R12
Mask option
Register
(R12)
Register
(R11)
Register
(R10)
MO
or ENV
MO
Register
(MELD)
Melody data
Fig. 3.4.1
Structure of output ports
R10–R12, MO
Table 3.4.2
Special output
II-26 EPSON S1C62N82 TECHNICAL SOFTWARE
CHAPTER 3: PERIPHERAL CIRCUITS (Special Use Output Ports)
• Melody output MO, MO or envelope output (R12)
MO and MO (or ENV) are the melody signal output pins for
driving a piezo or speaker through an amplifying transistor.
Refer to 3.11, "Melody Generator".
• FOUT (R10)
When output port R10 is set for FOUT, it outputs the fosc3
clock or the divided fosc1. The clock frequencies listed in
Table 3.4.3 selectable by mask option.
Example of special
use output port
control program
fosc1 / 1
fosc1 / 2
fosc1 / 4
fosc1 / 8
fosc1 / 16
fosc1 / 32
fosc1 / 64
fosc1 / 128
32,768
16,384
8,192
4,096
2,048
1,024
512
256
Setting Value Clock Frequency (Hz)
fosc3 1,000,000 (Typ.)
Table 3.4.3
Selectable by mask option
Label Mnemonic/operand Comment
LD Y,0F4H ;Set address of port
OR MY,0001B ;Turn on FOUT
AND MY,1110B ;Turn off FOUT
S1C62N82 TECHNICAL SOFTWARE EPSON II-27
CHAPTER 3: PERIPHERAL CIRCUITS (I/O Ports)
3.5 I/O Ports
I/O port memory
map
Table 3.5.1 I/O memory map
Address Comment
Register
D3 D2 D1 D0 Name SR 1 0
0F6H
P03 P02 P01 P00 P03
P02
P01
P00
–
–
–
–
I/O port (P00–P03)
High
High
High
High
Low
Low
Low
Low
R/W
0FCH
CLKCHG OSCC 0 IOC CLKCHG
OSCC
0
IOC
0
0
0
CPU clock switch
OSC3 oscillator ON/OFF
I/O port P00–P03 Input/Output
OSC3
ON
Output
OSC1
OFF
Input
R/W
R/W R
*5
*1 Initial value following initial reset
*2 Not set in the circuit
*3 Undefined
*4 Reset (0) immediately after being read
*5 Always 0 when being read
*6 Refer to main manual
II-28 EPSON S1C62N82 TECHNICAL SOFTWARE
CHAPTER 3: PERIPHERAL CIRCUITS (I/O Ports)
The S1C62N82 contains a 4-bit general I/O port (4 bits × 1).
This port can be used as an input port or an output port,
according to I/O port control register IOC. When IOC is "0",
the port is set for input, when it is "1", the port is set for
output.
• How to set an input port
Set "0" in the I/O port control register (D0 of address 0FCH),
and the I/O port is set as an input port. The state of the I/O
port (P00–P03) is decided by the data of address 0F6H. (In
the input mode, the port level is read directly.)
• How to set an output port
Set "1" in the I/O port control register, and the I/O port is
set as an output port. The state of the I/O port is decided by
the data of address 0F6H. This data is held by the register,
and can be set regardless of the contents of the I/O control
register. (The data can be set whether P00 to P03 ports are
input ports or output ports.)
The I/O control registers are cleared to "0" (input/output
ports are set as input ports), and the data registers are also
cleared to "0" after an initial reset.
• Loading P00–P03 input data into A register
Label Mnemonic/operand Comment
LD Y,0FCH ;Set address of I/O control port
AND MY,1110B ;Set port as input port
LD Y,0F6H ;Set address of port
LD A,MY ;A register ← P00–P03
Control of
the I/O port
Examples of I/O port
control
program
S1C62N82 TECHNICAL SOFTWARE EPSON II-29
CHAPTER 3: PERIPHERAL CIRCUITS (I/O Ports)
As shown in Figure 3.5.1, the four instruction steps above
load the data of the I/O ports into the A register.
• Loading P00–P03 output data into A register
Label Mnemonic/operand Comment
LD Y,0FCH ;Set the address of input/output
;port control register
OR MY,0001B ;Set as output port
LD Y,0F6H ;Set the address of port
LD A,MY ;A register ← P00–P03
As shown in Figure 3.5.2, the four instruction steps above
load the data of the I/O ports into the A register.
D3
P03
D2
P02
D1
P01
D0
P00
A register
P03 P02 P01 P00
Data register P00
Data register P01
Data register P02
Data register P03
A register D3 D2 D1 D0
Data can be loaded from the I/O port into the B register or
MX instead of the A register.
Fig. 3.5.2
Control of I/O port (input)
Fig. 3.5.1
Loading into the A register
II-30 EPSON S1C62N82 TECHNICAL SOFTWARE
CHAPTER 3: PERIPHERAL CIRCUITS (I/O Ports)
• Loading contents of B register into P00–P03
Label Mnemonic/operand Comment
LD Y,0FCH ;Set the address of input/output
;port control register
OR MY,0001B ;Set port as output port
LD Y,0F6H ;Set the address of port
LD MY,B ;P00–P03 ← B register
As shown in Figure 3.5.3, the four instruction steps above
load the data of the B register into the I/O ports.
D3 D2 D1 D0
Data register P00
Data register P01
Data register P02
Data register P03
B register
Fig. 3.5.3
Control of the I/O port (output)
The output data can be taken from the A register, MX, or
immediate data instead of the B register.
Bit-unit operation for the I/O port is identical to that for the
input ports (K00–K03, K10) or output ports (R00–R03).
S1C62N82 TECHNICAL SOFTWARE EPSON II-31
CHAPTER 3: PERIPHERAL CIRCUITS (LCD Driver)
LCD Driver3.6
Address 0123456789ABCDEF
090
0A0
0B0
0C0
0D0
Display memory (R/W)
80 words x 4 bits
LCD driver memory
map
Table 3.6.1 I/O memory map
Address Comment
Register
D3 D2 D1 D0 Name SR
*1
10
0FBH
CSDC 0 CMPDT CMPON
R
0
1
0
LCD drive switch
Analog comparator ON/OFF
Static
+ > -
ON
Dynamic
- > +
OFF
*5
R/W R/W
CSDC
0
CMPDT
CMPON
Comparator's voltage condition:
1 = CMPP(+)input > CMPM(-)input,
0 = CMPM(-)input > CMPP(+)input
*1 Initial value following initial reset
*2 Not set in the circuit
*3 Undefined
*4 Reset (0) immediately after being read
*5 Always 0 when being read
*6 Refer to main manual
Fig. 3.6.1
Display memory map
II-32 EPSON S1C62N82 TECHNICAL SOFTWARE
CHAPTER 3: PERIPHERAL CIRCUITS (LCD Driver)
The S1C62N82 contains 320 bits of display memory in
addresses 090H to 0DFH of the data memory. Each display
memory can be assigned to any 304 bits of the 320 bits for
the LCD driver (38 SEG × 8 COM) or 168 bits of the 320 bits
(42 SEG × 4 COM) by using a mask option. The remaining
16 bits or 152 bits of display memory are not connected to
the LCD driver, and are not output even when data is writ-
ten. The memory which is not assigned may be used as
general-purpose RAM. An LCD segment is on with "1" set in
the display memory, and off with "0" set in the display
memory.
The contents of the display memory is indefinite during initial reset
and until the display memory is initialized (i.e., through memory
clearing process from the CPU, etc.), the data of the memory and
the contents of LCD display will not match.
Perform display memory initialization through initializing processes.
• LCD drive control register (CSDC)
The LCD drive control register (CSDC: address 0FBH, D3)
can be set either for dynamic drive or for static drive. Set "0"
in CSDC for 1/8 duty or 1/4 duty (time-shared) dynamic
drive. Set "1" in CSDC and the same value in the display
memories corresponding to COM0 to COM7 for static drive.
Figure 3.6.2 is the static drive control of the LCD, and
Figure 3.6.3 is an example of the 7-segment LCD assign-
ment.
In Figure 3.6.2 segment option set for 4 commons (COM0–
COM3), segment can use from SEG0–SEG41. If option set
for 8 commons (COM0–COM7), then segment can use from
SEG0–SEG37 only.
Even in case 1/4 duty were selected, when SEG terminal is set to
static driving, set the same values on all the display memories
corresponding to COM0–COM7.
Control of the LCD
driver
Note
Note
S1C62N82 TECHNICAL SOFTWARE EPSON II-33
CHAPTER 3: PERIPHERAL CIRCUITS (LCD Driver)
Fig. 3.6.2
LCD static drive control
Fig. 3.6.3
7-segment LCD assignment
In the assignment shown in Figure 3.6.3, the 7-segment
display pattern is controlled by writing data to display
memory addresses 090H and 091H.
SEG
0–41
COM
0–3
Frame frequency
LCD lighting status
COM0
COM1
COM2
COM3
SEG0–41
-V
-V
-V
-V
-V
-V
-V
-V
-V
-V
-V
-V
Not lit Lit
DD
L1
L2
L3
DD
L1
L2
L3
DD
L1
L2
L3
g f e
091H
dcba
090H D3 D2 D1 D0
Address Register
a
g
fb
ec
d
II-34 EPSON S1C62N82 TECHNICAL SOFTWARE
CHAPTER 3: PERIPHERAL CIRCUITS (LCD Driver)
• Displaying 7-segment (for 4 commons)
The LCD display routine using the assignment of Figure
3.6.3 can be programmed as follows.
Label Mnemonic/operand Comment
ORG 000H
RETD 3FH ;0 is displayed
RETD 06H ;1 is displayed
RETD 5BH ;2 is displayed
RETD 4FH ;3 is displayed
RETD 66H ;4 is displayed
RETD 6DH ;5 is displayed
RETD 7DH ;6 is displayed
RETD 27H ;7 is displayed
RETD 7FH ;8 is displayed
RETD 6FH ;9 is displayed
SEVENS: LD B,0 ;Set the address of jump
LD X,090H ;Set address of display memory
JPBA
When the above routine is called (by the CALL or CALZ
instruction) with any number from "0" to "9" set in the A
register for the assignment of Figure 3.6.4, seven segments
are displayed according to the contents of the A register.
Examples of
LCD driver control
program
0
1
DisplayA resister
2
3
DisplayA resister
4
5
DisplayA resister
6
7
DisplayA resister
8
9
DisplayA resister
Fig. 3.6.4
Data set in A register and
displayed patterns
The RETD instruction can be used to write data to the
display memory only if it is addressed using the X register.
(Addressing using the Y register is invalid.)
Note that the stack pointer must be set to a proper value
before the CALL (CALZ) instruction is executed.
S1C62N82 TECHNICAL SOFTWARE EPSON II-35
CHAPTER 3: PERIPHERAL CIRCUITS (LCD Driver)
SEG0 SEG1 SEG2 SEG3 SEG37
COM0 ■■D0 ■■D0 ■■D0 ■■D0 ■■D0
COM1 ■■D1 ■■D1 ■■D1 ■■D1 ■■D1
COM2 ■■D2 ■■D2 ■■D2 ■■D2 ■■D2
COM3 ■■D3 ■■D3 ■■D3 ■■D3 ■■D3
COM4 ■■D0 ■■D0 ■■D0 ■■D0 ■■D0
COM5 ■■D1 ■■D1 ■■D1 ■■D1 ■■D1
COM6 ■■D2 ■■D2 ■■D2 ■■D2 ■■D2
COM7 ■■D3 ■■D3 ■■D3 ■■D3 ■■D3
Memory address Data bit
• Bit-unit operation of the display memory
The LCD display routine using the assignment of Figure
3.6.5 can be programmed as follows.
Label Mnemonic/operand Comment
LD Y,090H ;Set address display memory
LD MY,3 ;SEG-A, B ON (●, ▲)
AND MY,1110B ;SEG-A OFF (●●, ▲)
AND MY,1101B ;SEG-B OFF (●●, ▲▲)
For manipulation of the display memory in bit-units for the
assignment of Figure 3.6.5, because the LCD RAM can be
read and written, so data can be changed directly using an
ALU instruction (for example, AND or OR).
• Displaying dot matrix LCD (for 8 commons)
The dot matrix LCD display routine using the assignment of
Figure 3.6.6 can be programmed as follows.
▲●
090H D3 D2 D1 D0
Address Data
▲
●: SEG - A
: SEG - B
Fig. 3.6.5
Example of segment
assignment
DBH
DAH
91H
90H
93H
92H
95H
94H 96H .........
97H .........
↑↑
Fig. 3.6.6 Dot matrix LCD assignment
II-36 EPSON S1C62N82 TECHNICAL SOFTWARE
CHAPTER 3: PERIPHERAL CIRCUITS (LCD Driver)
Label Mnemonic/operand Comment
YCOLUM EQU 20H
;
NUMLCD:
;* DISPLAY NUMERAL ON THE LCD PANEL
;LD Y,YCOLUM
LD MY,1 ;Select 1st column
LD A,0 ;Display "0"
CALL DSPLCD
;LD MY,2 ;Select 2nd column
LD A,5 ;Display "5"
CALL DSPLCD
LD MY,2 ;Show the cursor on 2nd column
CALL SHCRSR
:
:
DSPLCD:
;* DISPLAY ONE NUMERAL
RDF
LD X,90H
DSPLC1:ADD MY,0FH ;Set address of display memory
CP MY,0
JP Z,DSPLC2
;RCF
ADC XL,0AH
ADC XH,00H
JP DSPLC1
DSPLC2:PUSH YL
PUSH YH
LD M0,A
LD B,0
RCF
RLC A
RLC B
RCF
S1C62N82 TECHNICAL SOFTWARE EPSON II-37
CHAPTER 3: PERIPHERAL CIRCUITS (LCD Driver)
RLC A
RLC B
LD Y,0
ADD A,MY ;Set address of display pattern table
ADC B,0
POP YH
POP YL
PSET 03H
JPBA
;
;
SHCRSR:
;* SHOW THE CURSOR ON THE CHARACTER
RDF
LD X,91H
SHCRS1:ADD MY,0FH ;Set address of display memory
CP MY,0
JP Z,SHCRS2
;RCF
ADC XL,0AH
ADC XH,00H
JP SHCRS1
SHCRS2:OR MX,8H ;Display of underline
INC X
INC X
OR MX,8H
INC X
INC X
OR MX,8H
INC X
INC X
OR MX,8H
INC X
INC X
OR MX,8H
RET
;ORG 0300H
II-38 EPSON S1C62N82 TECHNICAL SOFTWARE
CHAPTER 3: PERIPHERAL CIRCUITS (LCD Driver)
;
NUM0: LBPX MX,3EH ;Display pattern for "0"
LBPX MX,51H
LBPX MX,49H
LBPX MX,45H
RETD 3EH
:
:
ORG 319H
;
NUM5: LBPX MX,27H ;Display pattern for "5"
LBPX MX,45H
LBPX MX,45H
LBPX MX,45H
RETD 39H
:
:
The display characters for example are shown as following:
1ST COLUMN
1
2
3
4
5
6
7
SEG0
1
2
3
4
2ND COLUMN
5
6
7
8
9
COM0
Fig. 3.6.7
Example of dot matrix LCD
display assignment
S1C62N82 TECHNICAL SOFTWARE EPSON II-39
CHAPTER 3: PERIPHERAL CIRCUITS (Timer)
3.7 Timer
Timer memory map
Table 3.7.1 I/O memory map
Address Comment
Register
D3 D2 D1 D0 Name SR *1 10
0E4H
TM3 TM2 TM1 TM0
R
TM3
TM2
TM1
TM0
–
–
–
–
Timer data (clock timer 2 Hz)
Timer data (clock timer 4 Hz)
Timer data (clock timer 8 Hz)
Timer data (clock timer 16 Hz)
High
High
High
High
Low
Low
Low
Low
0EBH
0 EIT2 EIT8 EIT32
R
0
EIT2
EIT8
EIT32
0
0
0
Enable
Enable
Enable
Mask
Mask
Mask
Interrupt mask register (clock timer 2 Hz)
Interrupt mask register (clock timer 8 Hz)
Interrupt mask register (clock timer 32 Hz)
R/W
*5
0EFH
0 IT2 IT8 IT32 0
IT2
IT8
IT32
0
0
0
Yes
Yes
Yes
No
No
No
Interrupt factor flag (clock timer 2 Hz)
Interrupt factor flag (clock timer 8 Hz)
Interrupt factor flag (clock timer 32 Hz)
R
*5
*4
*4
*4
0F9H
0 TMRST SWRUN SWRST
W
0
TMRST
SWRUN
SWRST
Reset
0
Reset
Clock timer reset
Stopwatch timer RUN/STOP
Stopwatch timer reset
Reset
Run
Reset
–
Stop
–
R/W WR
*5
*5
*5
*1 Initial value following initial reset
*2 Not set in the circuit
*3 Undefined
*4 Reset (0) immediately after being read
*5 Always 0 when being read
*6 Refer to main manual
II-40 EPSON S1C62N82 TECHNICAL SOFTWARE
CHAPTER 3: PERIPHERAL CIRCUITS (Timer)
The S1C62N82 contains a timer with a basic oscillation of
32.768 kHz (typical). This timer is a 4-bit binary counter,
and the counter data can be read as necessary. The counter
data of the 16 Hz clock can be read by reading TM3 to TM0
(address 0E4H, D3 to D0). ("1" to "0" are set in TM3 to TM0,
corresponding to the high-low levels of the 2 Hz, 4 Hz, 8 Hz,
and 16 Hz 50 % duty waveform. See Figure 3.7.1.) The
timer can also interrupt the CPU on the falling edges of the
32 Hz, 8 Hz, and 2 Hz signals. For details, see Section 3.12,
"Interrupt and Halt".
Control of the timer
The timer is reset by setting "1" in TMRST (address 0F9H,
D2).
The 128 Hz to 2 Hz of the internal divider is initialized by resetting
the timer, and 128 Hz to 1 Hz of the internal divider is reset by
resetting the stopwatch timer.
The dividers of the timer and stopwatch timers are individ-
ual circuits, so resetting one circuit does not affect the
other.
Clock timer timing chart
Frequency
Register
bit
Address
0E4H
D0 16 Hz
D1
D2
D3
8 Hz
4 Hz
2 Hz
Occurrence of
32 Hz interrupt request
Occurrence of
8 Hz interrupt request
Occurrence of
2 Hz interrupt request
Fig. 3.7.1
Output waveform of
timer and interrupt timing
Note
S1C62N82 TECHNICAL SOFTWARE EPSON II-41
CHAPTER 3: PERIPHERAL CIRCUITS (Timer)
• Initializing the timer
Label Mnemonic/operand Comment
LD Y,0F9H ;Set address of the timer
;reset register
OR MY,0100B ;Reset the timer
The two instruction steps above are used to reset (clear
TM0–TM3 to 0) and restart the timer. The TMRST register is
cleared to "0" by hardware 1 clock after it is set to "1".
• Loading the timer
Label Mnemonic/operand Comment
LD Y,0E4H ;Set address of
;the timer data (TM0 to TM3)
LD A,MY ;Load the data of
;TM0 to TM3 into A register
As shown in Table 3.7.2, the two instruction steps load the
data of TM0 to TM3 into the A register.
TM3 (2 Hz)
D3
TM2 (4 Hz)
D2
TM1 (8 Hz)
D1
TM0 (16 Hz)
D0
A register
Table 3.7.2
Loading the timer data
Examples of timer
control program
II-42 EPSON S1C62N82 TECHNICAL SOFTWARE
CHAPTER 3: PERIPHERAL CIRCUITS (Timer)
• Checking timer edge
Label Mnemonic/operand Comment
LD X,TMSTAT ;Set address of the timer edge counter
CP MX,0 ;Check whether the timer edge
;counter is "0"
JP Z,RETURN ;Jump if "0" (Z-flag is "1")
LD Y,0E4H ;Set address of the timer
LD A,MY ;Read the data of TM0 to TM3
;into A register
LD Y,TMDTBF ;Set address of the timer data buffer
XOR MY,A ;Did the count on the timer
;change?
FAN MY,0100B ;Check bit D2 of the timer data buffer
LD MY,A ;Set the data of A register into
;the timer data buffer
JP Z,RETURN ;Jump, if the Z-flag is "1"
ADD MX,0FH ;Decrement the timer edge counter
;
RETURN: RET ;Return
This program takes a subroutine form. It is called at short
intervals, and decrements the data at address TMSTAT every
125 ms until the data reaches "0". The timing chart is
shown in Figure 3.7.2. The timer can be addressed using
the X register instead of the Y register.
TMSTAT and TMDTBF may be any address in RAM and not
involve a hardware function.
125 ms
Timer edge counter (TMSTAT) decrementing timing
TM2
Note
Fig. 3.7.2
Timing of the timer
edge counter
S1C62N82 TECHNICAL SOFTWARE EPSON II-43
CHAPTER 3: PERIPHERAL CIRCUITS (Stopwatch Timer)
3.8 Stopwatch Timer
Stopwatch timer
memory map
Table 3.8.1 I/O memory map
Address Comment
Register
D3 D2 D1 D0 Name SR
*1
10
0E2H
0E3H
SWL3 SWL2 SWL1 SWL0
SWH3 SWH2 SWH1 SWH0
R
R
SWL3
SWL2
SWL1
SWL0
0
0
0
0
SWH3
SWH2
SWH1
SWH0
0
0
0
0
MSB
Stopwatch timer
1/100 sec (BCD)
LSB
MSB
Stopwatch timer
1/10 sec (BCD)
LSB
0EAH
0 0 EISW1 EISW0
R
0
0
EISW1
EISW0
0
0
Interrupt mask register (stopwatch 1 Hz)
Interrupt mask register (stopwatch 10 Hz)
Enable
Enable
Mask
Mask
*5
*5
R/W
0EEH
0 0 ISW1 ISW0
R
0
0
ISW1
ISW0
0
0
Interrupt factor flag (stopwatch 1 Hz)
Interrupt factor flag (stopwatch 10 Hz)
Yes
Yes
No
No
*5
*5
*4
*4
0F9H
0 TMRST SWRUN SWRST
W
0
TMRST
SWRUN
SWRST
Reset
0
Reset
Clock timer reset
Stopwatch timer RUN/STOP
Stopwatch timer reset
Reset
Run
Reset
–
Stop
–
R/W WR
*5
*5
*5
*1 Initial value following initial reset
*2 Not set in the circuit
*3 Undefined
*4 Reset (0) immediately after being read
*5 Always 0 when being read
*6 Refer to main manual
II-44 EPSON S1C62N82 TECHNICAL SOFTWARE
CHAPTER 3: PERIPHERAL CIRCUITS (Stopwatch Timer)
The S1C62N82 contains 1/100 sec and 1/10 sec stopwatch
timers.
This timer can be loaded in 4-bit units. Starting, stopping,
and resetting the timer can be controlled by register.
Figure 3.8.1 shows the operation of the stopwatch timer.
Control of the stop-
watch timer
Fig. 3.8.1
Stopwatch timer
operating timing
Address
Address
Register bit Stopwatch timer (SWL) timing chart
Stopwatch timer (SWH) timing chart
Occurrence of
10 Hz interrupt request
Occurrence of
1 Hz interrupt request
0E3H
(1/10 sec BCD)
0E2H
(1/100 sec BCD)
D0
D1
D2
D3
D0
D1
D2
D3
Register bit
S1C62N82 TECHNICAL SOFTWARE EPSON II-45
CHAPTER 3: PERIPHERAL CIRCUITS (Stopwatch Timer)
• Initializing the stopwatch timer
Label Mnemonic/operand Comment
LD Y,0F9H ;Set address of the SWRST register
OR MY,0001B ;Reset the stopwatch timer
The two instruction steps above reset the stopwatch timer.
(SWL3 to SWL0, SWH3 to SWH0 are all cleared to "0".)
The stopwatch timer is reset by setting "1" in the SWRST register.
However, the SWRST register is cleared to "0" by hardware 1
clock after it is set to "1".
• Starting the stopwatch timer
Label Mnemonic/operand Comment
LD Y,0F9H ;Set address of SWRUN register
OR MY,0010B ;Start the stopwatch timer
The two instruction steps above run the stopwatch timer of
SWL0 to SWL3, and SWH0 to SWH3 (addresses 0E2H and
0E3H, respectively).
• Stopping the stopwatch timer
Label Mnemonic/operand Comment
LD Y,0F9H ;Set address of SWRUN register
AND MY,1101B ;Stop the stopwatch timer
The two instruction steps above stop the stopwatch timer of
SWL0 to SWL3, and SWH0 to SWH3 (addresses 0E2H and
0E3H, respectively).
Note
Examples of stop-
watch timer control
program
II-46 EPSON S1C62N82 TECHNICAL SOFTWARE
CHAPTER 3: PERIPHERAL CIRCUITS (Stopwatch Timer)
• Loading the stopwatch timer
Label Mnemonic/operand Comment
LD Y,0E2H ;Set address of the SWL of
;the stopwatch
LDPY A,MY ;Read the data of SWL0 to SWL3
;into A register
LD B,MY ;Read the data of SWH0 to SWH3
;into B register
The three instruction steps above reads the contents of the
stopwatch timer into A register and B register. (Also see
Table 3.8.2.)
Table 3.8.2
Data load into A register
and B register
SWH3 SWH2 SWH1 SWH0
B register
SWL3 SWL2 SWL1 SWL0
A register D3 D2 D1 D0
A read-in error caused by a carry from the SWL is not taken into
account in this program. You are recommended to add a handling
routine in your application.
Note
S1C62N82 TECHNICAL SOFTWARE EPSON II-47
CHAPTER 3: PERIPHERAL CIRCUITS (SVD Circuit and Heavy Load Protection Function)
3.9 Supply Voltage Detection (SVD) Circuit and
Heavy Load Protection Function
The S1C62N82 Series has built-in supply voltage detection
circuit and drop in power supply voltage may be detected by
controlling the register on the I/O memory. Criteria voltages
are as follows:
Model Criteria Voltage
S1C62N82/62A82 2.4 V ± 0.15 V
S1C62L82 1.2 V ± 0.10 V
Moreover, when the battery load becomes heavy, such as
during external piezo buzzer driving or external lamp light-
ing, heavy load protection function is built-in in case the
supply voltage drops. S1C62L82 operates at 0.9 V due to the
SVD circuit and heavy load protection function.
SVD circuit and
heavy load protec-
tion function mem-
ory map
Table 3.9.1 I/O memory map
Address Comment
Register
D3 D2 D1 D0 Name SR 1 0
0FAH
HLMOD 0 SVDDT SVDON HLMOD
0
SVDDT
SVDON
0
0
0 ON OFF
Heavy load protection mode register
Supply voltage detector data
Supply voltage detector ON/OFF
RR/W R/W
Heavy
load
Supply
voltage
low
Normal
load
Supply
voltage
normal
*5
*1 Initial value following initial reset
*2 Not set in the circuit
*3 Undefined
*4 Reset (0) immediately after being read
*5 Always 0 when being read
*6 Refer to main manual
II-48 EPSON S1C62N82 TECHNICAL SOFTWARE
CHAPTER 3: PERIPHERAL CIRCUITS (SVD Circuit and Heavy Load Protection Function)
Control of the SVD
circuit
The SVD circuit will turn ON by writing "1" on the SVDON
register (address 0FAH, D0, R/W) and supply voltage detec-
tion will be performed. By writing "0" on the SVDON register,
the detection result is stored in the SVDDT register. How-
ever, in order to obtain a stable detection result, it is neces-
sary to turn the SVD circuit ON for at least 100 µs. Accord-
ingly, reading out the detection result from the SVDDT
register is performed through the following procedures:
➀Set the SVDON register to "1".
➁Provide at least 100 µs waiting time.
➂Set the SVDON register to "0".
➃Read-out from the SVDDT register.
Note, however, that when S1C62N82 is to be used with the
OSC1 system clock at fosc1 = 32.768 kHz, there is no need
for the waiting time stated in the above procedure ➁ since 1
instruction cycle will take longer than 100 µs. When system
clock change to OSC3, it must delay some instructions.
Because the power current consumption of the IC becomes
large when the SVD circuit is operated, turn the SVD circuit
OFF when not in use. The operation timing chart is shown
in Figure 3.9.1.
Label Mnemonic/Operand Comment
LD X,0FAH ;Sets the address of SVDON
OR MX,0001B ;Sets SVDON to "1"
AND MX,1110B ;Sets SVDON to "0"
LD A,MX ;Loads the detection result
;into the A register
Example of SVD
circuit control
program
(At fosc1 = 32.768 kHz)
Supply voltage
Criteria voltage
SVDON register
SVD circuit
SVDDT register
HLMOD register
100 µs or more
Fig. 3.9.1
Timing chart of supply
voltage detection operation
through the SVDON
register
S1C62N82 TECHNICAL SOFTWARE EPSON II-49
CHAPTER 3: PERIPHERAL CIRCUITS (SVD Circuit and Heavy Load Protection Function)
Heavy load protec-
tion function
There are two ways to operate the heavy load protection
function:
• Operation through the HLMOD register
The heavy load protection function may be operated by
writing "1" on the HLMOD register (address 0FAH, D3, R/
W). Simultaneously, the SVD circuit will turn ON and
supply voltage detection by hardware every 2 Hz (0.5 sec)
will automatically be performed.
Operation through the HLMOD register is useful when
heavy load can be anticipated such as when S1C62N82
drives the piezo buzzer. The operation timing chart is
shown in Figure 3.9.2.
Supply voltage
Criteria voltage
HLMOD register
Heavy load
protection mode
2 Hz clock
SVD circuit
SVDDT
SVDON register
Fig. 3.9.2
Timing chart of supply
voltage detection opera-
tion through the HLMOD
register
• Operation through the SVDON register
The SVD circuit will turn ON by writing "1" on the
SVDON register (address 0FAH, D0, R/W) and supply
voltage detection will be performed. By writing "0" on the
SVDON register, the detection result is stored in the
SVDDT register. If this results in the supply voltage being
lower than the criteria voltage, the heavy load protection
function will operate. In other words, the SVD circuit in
this case serves as a sensor for detecting the operational
state of the heavy load protection function.
II-50 EPSON S1C62N82 TECHNICAL SOFTWARE
CHAPTER 3: PERIPHERAL CIRCUITS (SVD Circuit and Heavy Load Protection Function)
Operation through the SVDON circuit is useful as a
measure against unforeseen circumstances, such as drop
in supply voltage due to expiring battery life, by way of
promptly operating the heavy load protection function.
The following procedures for controlling the SVD circuit
by the software are the same as those described in "Con-
trol of the SVDON circuit":
➀Set the SVDON register to "1".
➁Provide at least 100 µs waiting time.
➂Set the SVDON register to "0".
➃Read-out from the SVDDT register.
If the supply voltage is lower than the criteria voltage, the
heavy load protection function will automatically start
operating after the above procedure ➂ has been per-
formed.
Because supply voltage detection by hardware every 2 Hz
(0.5 sec) will automatically be performed when the heavy
load protection function operates, refrain from operating
the SVD circuit with the software in order to minimize
power current consumption. The operation timing chart
is shown in Figure 3.9.3.
100 µs or more
Supply voltage
Criteria voltage
SVDON register
2 Hz clock
SVD circuit
SVDDT register
Heavy load
protection mode
HLMOD register
Fig. 3.9.3
Timing chart of heavy
load protection
function operation
through the SVDON
register
S1C62N82 TECHNICAL SOFTWARE EPSON II-51
CHAPTER 3: PERIPHERAL CIRCUITS (SVD Circuit and Heavy Load Protection Function)
Examples of heavy
load protection
function control
program
• Operation through the HLMOD register
This is a sample program when lamp is driven with the
R00 terminal during performance of heavy load protec-
tion.
Label Mnemonic/Operand Comment
LD X,0FAH ;Sets the address of HLMOD
OR MX,1000B ;Sets to the heavy protection mode
LD Y,0F3H ;Sets the address of R0n port
OR MY,0001B ;Turns lamp ON
:
:
LD Y,0F3H ;Sets the R0n port address
AND MY,1110B ;Turns the lamp on
CALL WT1S ;1 second waiting time (software timer)
AND MX,0111B ;Cancels the heavy load protection mode
In the above program, the heavy load protection mode is
canceled after 1 sec waiting time provided as the time for
the supply voltage to stabilize after the lamp is turned off;
however, since this time varies according to the nature of
the battery, time setting must be done in accordance with
the actual application.
II-52 EPSON S1C62N82 TECHNICAL SOFTWARE
CHAPTER 3: PERIPHERAL CIRCUITS (SVD Circuit and Heavy Load Protection Function)
• Operation through the SVDON register
Label Mnemonic/Operand Comment
LD X,0FAH ;Sets the HLMOD/SVDDT address
FAN MX,1010B ;Checks the HLMOD/SVDDT bits
JP NZ,HLMOD ;Heavy load protection mode
OR MX,0001B ;Sets the SVDON to "1"
AND MX,1110B ;Sets the SVDON to "0"
FAN MX,0010B ;Checks the SVDDT bit
JP Z,HLMOD ;Shifts the mode to
;the heavy load protection mode
LD Y,FLAG
AND MY,0 ;Resets the flag to "0"
RET
;
HLMOD: LD Y,FLAG
OR MY,1 ;Sets the flag to "1"
RET
The above program operates the heavy load protection
function by using the SVDON register. In the normal
operation mode, supply voltage detection is done from the
SVDON register and when the supply voltage drops below
the criteria voltage, the mode shifts to the heavy load
protection mode. In the heavy load protection mode,
supply voltage detection by the hardware is done every 2
Hz and the detection result is stored in the SVDDT regis-
ter. Because of this, the SVDDT register will be "1" during
the heavy load protection mode. Moreover, in the above
program, supply voltage detection by the SVDON is
halted during the heavy load protection mode. If the
supply voltage become grater than the criteria voltage,
the SVDDT register value will become "0" and hence,
supply voltage detection through the SVDON register will
resume after checking the SVDDT register value. When
used as a sub-routine, the above program will enable the
user to determine whether the present operation mode is
the normal operation mode (flag = "0") or the heavy load
protection mode (flag = "1").
The flow chart for the above program is shown in the next
page.
S1C62N82 TECHNICAL SOFTWARE EPSON II-53
CHAPTER 3: PERIPHERAL CIRCUITS (SVD Circuit and Heavy Load Protection Function)
Start
RET
FLAG←0
HLMOD?
SVDDT?
SVDDT?
SVDON←1
SVDON←0
FLAG←1
=1
=0
=1
=0
=1
=0
Fig. 3.9.4
Flow chart of operation
through the SVDON register
II-54 EPSON S1C62N82 TECHNICAL SOFTWARE
CHAPTER 3: PERIPHERAL CIRCUITS (Analog Comparator)
3.10 Analog Comparator
The S1C62N82 contains an analog comparator (CMP) the
data of which can be read by software. This circuit can be
turned on and off to save power. The CMPON bit controls
analog comparator (CMP) power on/off. At initial reset, the
CMP circuit is off. While the circuit is not in use, keep this
bit set to "0" to save power.
The output data of the analog comparator appears in
CMPDT, this bit is "1" when CMPP > CMPM, and "0" when
CMPP < CMPM. If the CMPON bit is "0", the CMPDT bit is
fixed at "1".
Analog comparator
memory map
Table 3.10.1 I/O memory map
*1 Initial value following initial reset
*2 Not set in the circuit
*3 Undefined
*4 Reset (0) immediately after being read
*5 Always 0 when being read
*6 Refer to main manual
Address Comment
Register
D3 D2 D1 D0 Name SR *1 10
0FBH
CSDC 0 CMPDT CMPON
R
0
1
0
LCD drive switch
Analog comparator ON/OFF
Static
+ > -
ON
Dynamic
- > +
OFF
*5
R/W R/W
CSDC
0
CMPDT
CMPON
Comparator's voltage condition:
1 = CMPP(+)input > CMPM(-)input,
0 = CMPM(-)input > CMPP(+)input
S1C62N82 TECHNICAL SOFTWARE EPSON II-55
CHAPTER 3: PERIPHERAL CIRCUITS (Analog Comparator)
Example of CMP
control program
(At fosc1 = 32.768 kHz)
Label Mnemonic/operand Comment
LD X,0FBH ;Set CMP circuit address
OR MX,0001B ;CMP circuit on
LD A,08H ;
LOOP: ADD A,01H ; Wait about 1 ms
JP NZ,LOOP ;
LD A,MX ;A register ← CMPDT
AND MX,1110B ;CMP circuit off
Execution of the above program loads CMP output data
CMPDT into D1 of the A register.
It takes about 1 ms for the CMP output to become stable
when the circuit is turned on. Therefore, the program must
include a wait time of at least 1 ms before the output data is
loaded after the CMP circuit has been turned on.
II-56 EPSON S1C62N82 TECHNICAL SOFTWARE
CHAPTER 3: PERIPHERAL CIRCUITS (Melody Generator)
3.11 Melody Generator
Melody generator
memory map
Table 3.11.1 I/O memory map
Address Comment
Register
D3 D2 D1 D0 Name SR 1 0
0E7H
0 0 0 EIMEL
R
0
0
0
EIMEL 0 Enable Mask
Interrupt mask register (melody)
R/W
0ECH
0 0 0 IMEL
R
0
0
0
IMEL 0
Interrupt factor flag (melody)
Yes No
0F0H
0F1H
0F2H
MAD3 MAD2 MAD1 MAD0
0 MAD6 MAD5 MAD4
CLKC1 CLKC0 TEMPC MELC
R/W
R
R/W
MAD3
MAD2
MAD1
MAD0
0
0
0
0
0
MAD6
MAD5
MAD4
0
0
0
Melody ROM address (AD6, MSB)
Melody ROM address (AD5)
Melody ROM address (AD4)
CLKC1
CLKC0
TEMPC
MELC
0
0
0
0
CLKC1(0)&CLKC0(0) : melody speed 1
CLKC1(0)&CLKC0(1) : melody speed 8
CLKC1(1)&CLKC0(0) : melody speed 16
CLKC1(1)&CLKC0(1) : melody speed 32
Tempo change control
Melody control ON/OFF
Melody ROM address (AD3)
Melody ROM address (AD2)
Melody ROM address (AD1)
Melody ROM address (AD0, LSB)
High
High
High
High
Low
Low
Low
Low
High
High
High
Low
Low
Low
High
High
High
ON
Low
Low
Low
OFF
R/W
×
×
×
×
0F4H
R12
MO
ENV
R11 R10
FOUT
R/W
MELD
R12
MO
ENV
R11
R10
FOUT
Melody output mask
Output port data (R12)
Inverting melody output
Melody envelope control
Output port data (R11)
Output port data (R10)
Frequency output
Disable
High
–
–
High
High
ON
Enable
Low
–
–
Low
Low
OFF
0
0
–
Hz
0
0
MELD
*5
*5
*5
*5
*5
*5
*4
*5
*6
*1 Initial value following initial reset *4 Reset (0) immediately after being read
*2 Not set in the circuit *5 Always 0 when being read
*3 Undefined *6 Refer to main manual
S1C62N82 TECHNICAL SOFTWARE EPSON II-57
CHAPTER 3: PERIPHERAL CIRCUITS (Melody Generator)
There are 7 bits for melody start address setting.
The user programmable area is from 00H to 07FH (128 words).
Address 0F2H (4 bits) is for melody control.
MELC: (1)Melody start when this bit is set to "1".
(2)Melody stop when this bit is set to "0" and there is
an end bit come from melody ROM.
TEMPC: Selection of tempo (TEMPC0 or TEMPC1); chosen
by mask option. Two tempos (TEMPC0 and
TEMPC1) can be chosen out of 16 tempos.
0: TEMPC0
1: TEMPC1
(See S1C62N82 Technical Hardwar, 4.11, "Playing
tempo".)
CLKC1, CLKC0: These two bits are combined to set the play
speed.
Note
Fig. 3.11.1
Set of melody ROM
address
–MSB
↓
MAD6
AD5
↓
MAD5
AD4
↓
MAD4
0F1H AD3
↓
MAD3
AD2
↓
MAD2
AD1
↓
MAD1
LSB
↓
MAD0
0F0H
Description
Table 3.11.2
Set of play speed
0
0
1
1
0
1
0
1
CLKC1 CLKC0 Play as normal speed
Play as normal speed 8
Play as normal speed 16
Play as normal speed 32
Play Speed
×
×
×
Address 0F4H, D3 is for melody output control.
MELD = "1": Melody sound is disable output
MELD = "0": Melody sound is enable output
Address setting
(Addresses 0F0H and
0F1H)
Play mode control
II-58 EPSON S1C62N82 TECHNICAL SOFTWARE
CHAPTER 3: PERIPHERAL CIRCUITS (Melody Generator)
(1)One shot
In this mode, only one melody is played.
The control procedure is as follow:
Play mode
Set melody address
Set MELD bit to "0"
Set MELC bit to "0"
Set melody interrupt
mask enable
Jump to
melody subroutine
Melody end
interrupt
10AH
Melody subroutine
Read interrupt flag
to clear
EI
RET
Set MELC bit to "1"
Fig. 3.11.2
Control procedure of
one shot mode
When the MELC bit is set to "1", it makes the melody
play. The user's program should set this bit to "0" before
the end bit from the melody ROM. If not, the function will
be like the level hold mode (see next function).
MELC
MO Playing
Interrupt generate by END data setting
S1C62N82 TECHNICAL SOFTWARE EPSON II-59
CHAPTER 3: PERIPHERAL CIRCUITS (Melody Generator)
(2)Level hold
In this mode, after one melody has been played, the user
can change the next play to any other melody. If there is
no change, the melody is played repeatedly. The control
procedure is as follows:
Fig. 3.11.3
Control procedure of level
hold mode
MELC
MO Melody 1
Interrupt generate
Melody 2 Melody N - 1 Melody N
Set melody1 address
Set MELC bit to "1"
Set melody 2 address
Enable interrupt
Jump to
melody subroutine
Melody 1 end
interrupt
10AH
INC n
Set MELC bit to "0"
Read interrupt factor
flag to clear
Set MELD bit to "0"
Melody 2 end
interrupt
Melody 3 end
interrupt
Melody 4 end
interrupt
n = ?
n = N - 1
Set melody 3 address
Select tempo
n = 1
EI
RET
Set melody 4 address
Select tempo
n = 2 N
Set counter n = 0
II-60 EPSON S1C62N82 TECHNICAL SOFTWARE
CHAPTER 3: PERIPHERAL CIRCUITS (Melody Generator)
(3)Retrigger play
In this mode, the melody can be stopped anywhere dur-
ing playing, and it can be set to any another melody. The
control procedure is as follows:
With this function, the user can force the melody to stop
if there is a rest note with the End data = "1" in the
melody ROM (See melody ROM data setting).
MELC
MO Melody 1
Melody 1 stopped mid-way Interrupt generate by END data setting
Melody n
Fig. 3.11.4
Control procedure of
retriggrer play mode
Set melody n address
Set MELC bit to "1"
Set MELC bit to "0"
Jump to
melody subroutine
Melody n end
interrupt
10AH
Melody subroutine
EI
RET
Set MELD bit to "0"
Set MELC bit to "1"
Set MELC bit to "0"
Enable interrupt
Mid-way of
melody 1
Start of
melody n
Set melody address
S1C62N82 TECHNICAL SOFTWARE EPSON II-61
CHAPTER 3: PERIPHERAL CIRCUITS (Melody Generator)
(1)Tempo
Tempo selection is asigned to address 0F2H bit D1
(TEMPC).
This bit should be set at the same time that the MELC bit
is set to "1". During playing, this bit will have no function
for the melody playing. But in the level hold mode, when
the next melody is loading, TEMPC will also be loaded.
The tempo will then be changed. The control procedure is
as follows:
Tempo and speed control
Set TEMPC bit to "1"
Set melody 2 address
Enable interrupt
Jump to
melody subroutine
Melody 1 end
interrupt
10AH
Melody subroutine
EI
RET
Set TEMPC
bit to "0"
Set MELC bit to "1"
Melody 2 end
interrupt
Set MELD bit to "0"
Set melody 1 address
MELC
MO Melody 1 with tempo 0
Interrupt generate by END data setting
Melody 2 with tempo 1
Fig. 3.11.5
Control procedure of tempo
II-62 EPSON S1C62N82 TECHNICAL SOFTWARE
CHAPTER 3: PERIPHERAL CIRCUITS (Melody Generator)
(2)Speed
Speed control is asigned to address 0F2H, bits D2 and
D3 (CLKC0 and CLKC1). These two bits are controlled
independently. The user can change the speed during
playing, or start with a different speed. The control proce-
dure is as follows:
0F2H D3 D2 D1 D0
0001→Melody start with TEMPC0, speed normal
0101→Melody start with TEMPC0, speed × 8
1001→Melody start with TEMPC0, speed × 16
1101→Melody start with TEMPC0, speed × 32
0011→Melody start with TEMPC1, speed normal
0111→Melody start with TEMPC1, speed × 8
1011→Melody start with TEMPC1, speed × 16
1111→Melody start with TEMPC1, speed × 32
S1C62N82 TECHNICAL SOFTWARE EPSON II-63
CHAPTER 3: PERIPHERAL CIRCUITS (Melody Generator)
Example of changing speed during playing:
Set MELC bit to "0"
Enable interrupt
Set 0F2H to "4"
CLKC1
MO Normal speed
Set MELD bit to "0"
Set MELC bit to "1"
Interrupt generate by END data setting
CLKC0
MELC
Speed x 8
One melody
Set melody 1 address
Fig. 3.11.6
Control procedure of play
speed
II-64 EPSON S1C62N82 TECHNICAL SOFTWARE
CHAPTER 3: PERIPHERAL CIRCUITS (Melody Generator)
A melody interrupt occurs when the melody ROM data is
read out with the end bit set to "1". This indicates the end of
melody playing.
0E7H, D0: Interrupt mask bit
D0: 1Enable interrupt at the end of melody play.
D0: 0Interrupt cannot be generated even if play
is ending.
0ECH, D0: Interrupt factor flag
This bit will be reset to "0" when the user reads it.
D0: 1Interrupt has occured already, and pro-
gram will jump to interrupt vector 10AH.
Because the melody interrupt has the
highest priority, the interrupt service will
finish first, and this flag should be read to
be cleared.
D0: 0Interrupt has not been generated yet.
Volume: 00H–7FH (128 words)
Word: 10 bits/word
Refer to data setting as below:
Melody interrupt
Table 3.11.3
Melody ROM data
Fig. 3.11.7
End data
D8 D7 D6 D5 D4 D3 D2 D1 D0
Note data Scale data
End
data
D9
Attack
data
D0: End Data
Melody play will stop after the note playing when this data is
set to "1".
End data
(D0)
Read
MO 1 note play 1 note play 1 note play
0 0 1
Interrupt
Melody ROM
S1C62N82 TECHNICAL SOFTWARE EPSON II-65
CHAPTER 3: PERIPHERAL CIRCUITS (Melody Generator)
D1–D5: Scale Address Data (Scale ROM address)
What pitch is used depends on the address point of the
scale ROM and the scale data contained. (See scale ROM
data setting.)
D6–D8: Note Data
Note data table as below:
Table 3.11.4
Note data
D8
Note
10101010
+
D7 11001100
D6 11110000
D9: ATK Data
There will be a short break (≈12 ms) before the note playing
if this data is set to "1". Usually, two notes of the same pitch
are separated with this function, otherwise the two notes
will play continuously without any break.
In each melody first word, set this data to "1". Otherwise,
there will be no melody play even if the user starts play.
Next, according to the user's definition it can set to "1" or
"0". If the hardware mask option selects the R12 envelope
function, this data also controls the note output by enve-
lope.
ATK data
(D9)
MO
1 1 1 0
Note 1 pla
y
Note 2 pla
y
Note 3 pla
y
Note 4 pla
y
Envelope
Fig. 3.11.8
Waveform of envelope
II-66 EPSON S1C62N82 TECHNICAL SOFTWARE
CHAPTER 3: PERIPHERAL CIRCUITS (Melody Generator)
Volume: 00H–1FH (32 words)
Word: 8 bits/word
Address 1FH is set to a rest note. The data contained is not
connected with the scale. The scale may be selected accord-
ing to the definition of the scale ROM address, which is
defined by melody ROM data D5–D1. The scale data defini-
tion is as the table on the next page. The user has the
choice of 31 types of scale from this table.
Melody ROM
(D5–D1) Scale ROM data C major
00H 04H →C4 (Do)
01H 20H →D4 (Re)
02H 3BH →E4 (Mi)
03H 44H →F4 (Fa)
::
1EH C4H →C6 (Do)
1FH FFH →Rest
For level hold
Label Mnemonic/operand Comment
ORG 10AH
PSET 004H
JP 000H
:
LD A,00H ;Set counter (melody point)
LD M0,A
LD X,0F0H ;Set first melody address (00)
LD MX,00H
INC X
LD MX,00H
LD X,0F4H ;Enable melody output
AND MX,0111B
LD Y,0F2H ;Start melody with TEMPC0
LD MY,01H
LD X,0F0H ;Set second melody address (06)
Scale ROM
Examples of
melody control
program
S1C62N82 TECHNICAL SOFTWARE EPSON II-67
CHAPTER 3: PERIPHERAL CIRCUITS (Melody Generator)
LD MX,06H
INC X
LD MX,00H
LD Y,0E7H ;Enable melody interrupt mask
LD MY,01H
EI ;Enable interrupt
:
:
ORG 400H
PUSH XL
PUSH XH
PUSH YL
PUSH YH
PUSH A
INC M0 ;Melody pointer increment
LD A,M0 ;Decide which melody
CP A,01H
JP Z,MELDY3
CP A,02H
JP Z,MELDY4
CP A,03H
JP Z,MELDY5
CP A,04H
JP Z,MELDY6
CP A,05H
JP Z,MELSTP
JP MELEND
MELDY3 LD X,0F0H ;Set MEL3 address (0A)
LD MX,0AH
INC X
LD MX,00H
JP MELEND
MELDY4 LD X,0F0H ;Set MEL4 address (12)
LD MX,02H
INC X
LD MX,01H
JP MELEND
MELDY5 LD X,0F0H ;Set MEL5 address (28)
LD MX,08H
INC X
II-68 EPSON S1C62N82 TECHNICAL SOFTWARE
CHAPTER 3: PERIPHERAL CIRCUITS (Melody Generator)
LD MX,02H
LD Y,0F2H ;Set TEMPC1 for MEL5, 6
LD MY,03H
JP MELEND
MELDY6 LD X,0F0H ;Set MEL6 address (30)
LD MX,00H
INC X
LD MX,03H
JP MELEND
MELSTP LD Y,0F2H ;Melody stop after end
LD MY,00H
MELEND LD Y,0ECH ;Read clear interrupt factor flag
LD A,MY
POP A
POP YH
POP YL
POP XH
POP XL
EI
RET
For one shot
Labe Mnemonic/operand Comment
:
LD X,0F0H ;Set melody address
LD MX,00H
INC X
LD MX,00H
LD X,0F4H ;Enable melody output
AND MX,0111B
LD Y,0F2H ;Set melody start
LD MY,01H
LD MY,00H ;Set MELC to "0"
LD X,0E7H ;Enable melody interrupt mask
LD MX,01H
EI ;Enable interrupt
:
S1C62N82 TECHNICAL SOFTWARE EPSON II-69
CHAPTER 3: PERIPHERAL CIRCUITS (Melody Generator)
For retrigger
Label Mnemonic/operand Comment
:
LD X,0F0H ;Set melody 1 address
LD MX,00H
INC X
LD MX,00H
LD X,0F4H ;Enable melody output
AND MX,0111B
LD Y,0F2H ;Set melody start
LD MY,01H
LD MY,00H ;Set MELC to "0" ← Start of melody 1
LD X,0E7H ;Enable melody
LD MX,01H ;Interrupt mask
EI ;Enable interrupt
:
:
LD X,0F0H ;Set melody n address
LD MX,04H
INC X
LD MX,02H
LD Y,0F2H ;Retrigger melody with
LD MY,07H ;TEMPC1, speed × 8 ← Mid-way through melody 1
LD MY,06H ;Set MELC to "0" ← Start of melody n
:
:
II-70 EPSON S1C62N82 TECHNICAL SOFTWARE
CHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt)
3.12 Interrupt and Halt
Table 3.12.1 (a) I/O memory map
Interrupt memory
map
Address Comment
Register
D3 D2 D1 D0 Name SR *1 10
0E5H
0E6H
0E7H
KCP03 KCP02 KCP01 KCP00
0 0 0 KCP10
0 0 0 EIMEL
R
R
R/W
KCP03
KCP02
KCP01
KCP00
0
0
0
0
Input comparison register (K03)
Input comparison register (K02)
Input comparison register (K01)
Input comparison register (K00)
0
0
0
KCP10 0
0
0
0
EIMEL 0 Enable Mask
Input comparison register (K10)
Falling
Falling
Falling
Falling
Rising
Rising
Rising
Rising
Interrupt mask register (melody)
Falling Rising
*5
*5
*5
R/W
*5
*5
*5
R/W
0E8H
EIK03 EIK02 EIK01 EIK00
R/W
EIK03
EIK02
EIK01
EIK00
0
0
0
0
Interrupt mask register (K03)
Interrupt mask register (K02)
Interrupt mask register (K01)
Interrupt mask register (K00)
Enable
Enable
Enable
Enable
Mask
Mask
Mask
Mask
*1 Initial value following initial reset
*2 Not set in the circuit
*3 Undefined
*4 Reset (0) immediately after being read
*5 Always 0 when being read
*6 Refer to main manual
S1C62N82 TECHNICAL SOFTWARE EPSON II-71
CHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt)
Table 3.12.1 (b) I/O memory map
Address Comment
Register
D3 D2 D1 D0 Name SR
*1
10
0E9H
0EAH
0EBH
0 0 0 EIK10
0 0 EISW1 EISW0
0 EIT2 EIT8 EIT32
R
R
R
0
0
0
EIK10 0
Interrupt mask register (K10)
0
0
EISW1
EISW0
0
0
0
EIT2
EIT8
EIT32
0
0
0
Enable
Enable
Enable
Mask
Mask
Mask
Interrupt mask register (stopwatch 1 Hz)
Interrupt mask register (stopwatch 10 Hz)
Enable Mask
Interrupt mask register (clock timer 2 Hz)
Interrupt mask register (clock timer 8 Hz)
Interrupt mask register (clock timer 32 Hz)
Enable
Enable
Mask
Mask
*5
*5
R/W
*5
R/W
R/W
*5
*5
*5
0ECH
0 0 0 IMEL
R
0
0
0
IMEL 0
Interrupt factor flag (melody)
Yes No
*5
*5
*5
*4
*1 Initial value following initial reset
*2 Not set in the circuit
*3 Undefined
*4 Reset (0) immediately after being read
*5 Always 0 when being read
*6 Refer to main manual
II-72 EPSON S1C62N82 TECHNICAL SOFTWARE
CHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt)
Table 3.12.1 (c) I/O memory map
Address Comment
Register
D3 D2 D1 D0 Name SR *1 10
0EDH
0EEH
0EFH
00IK1IK0
0 0 ISW1 ISW0
0 IT2 IT8 IT32
R
R
0
0
IK1
IK0
0
0
Interrupt factor flag (K10)
Interrupt factor flag (K00–K03)
0
0
ISW1
ISW0
0
0
0
IT2
IT8
IT32
0
0
0
Yes
Yes
Yes
No
No
No
Interrupt factor flag (stopwatch 1 Hz)
Interrupt factor flag (stopwatch 10 Hz)
Yes
Yes
No
No
Interrupt factor flag (clock timer 2 Hz)
Interrupt factor flag (clock timer 8 Hz)
Interrupt factor flag (clock timer 32 Hz)
Yes
Yes
No
No
*5
*5
*4
*4
R
*5
*4
*4
*4
*5
*5
*4
*4
*1 Initial value following initial reset
*2 Not set in the circuit
*3 Undefined
*4 Reset (0) immediately after being read
*5 Always 0 when being read
*6 Refer to main manual
S1C62N82 TECHNICAL SOFTWARE EPSON II-73
CHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt)
The S1C62N82 supports four types of a total of 11 inter-
rupts. There are three timer interrupts (2 Hz, 8 Hz, 32 Hz),
two stopwatch interrupts (1 Hz, 10 Hz), five input interrupts
(K00–K03, K10) and one melody interrupt.
The 11 interrupts are individually enabled or masked (dis-
abled) by interrupt mask registers. The EI and DI instruc-
tions can be used to set or reset the interrupt flag (I), which
enables or disables all the interrupts at the same time.
Individual vector addresses are assigned to the four types of
interrupt. The priority of the interrupts is determined by the
hardware. The priority of the 2 Hz, 8 Hz, and 32 Hz timer
interrupts where the vector address is the same is deter-
mined by the software. The priority of the stopwatch inter-
rupts between 1 Hz and 10 Hz is also determined by soft-
ware.
When an interrupt is accepted, the interrupt flag (I) is reset,
and cannot accepts any other interrupts (DI state).
Restart from the halt state created by the HALT instruction,
is done by interrupt.
Control of interrupts
and halt
II-74 EPSON S1C62N82 TECHNICAL SOFTWARE
CHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt)
• Interrupt factor flags
This flag is set when any of the K00 to K03 input interrupts
occurs. The interrupt factor flag (IK0) is set to "1" when the
contents of the input (K00–K03) and the input comparison
register (KCP00–KCP03) do not match and the data of the
corresponding interrupt mask register (EIK00–EIK03) is "1".
The contents of the IK0 flag can be loaded by software to
determine whether the K00–K03 input interrupts have
occured.
The flag is reset when loaded by software. (See Figure
3.12.1.)
IK0
D0
D1
D2
D3
Address 0E5H
D0
D1
D2
D3
Address 0E8H
Input interrupt mask register
(EIK00–EIK03)
Input interrupt factor
flag register (IK0)
INT
(Interrupt request)
Interrupt flag (I)
FF
K03
K02
K01
K00
Input comparison
register (KCP00–KCP03) Address 0E0H
Data bus
Data bus
Fig. 3.12.1
K00–K03
input interrupt circuit
S1C62N82 TECHNICAL SOFTWARE EPSON II-75
CHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt)
This flag is set when the K10 input interrupt occurs.
The interrupt factor flag (IK1) is set to "1" when the contents
of the input (K10) and the interrupt differential register
(KCP10) do not match, and the corresponding interrupt
mask register (EIK10) is "1".
The contents of the IK1 flag can be loaded by software to
determine whether K10 input interrupt has occured.
The flag is reset when loaded by software. (See Figure
3.12.2.)
IK1
D0
Address 0E9H
Input interrupt mask register
(EIK10)
Input interrupt factor
flag register (IK1)
INT
(Interrupt request)
Interrupt flag (I)
FF
K10
Input comparison
register (KCP10)
Address 0E1H
Data bus
Data bus
D0
Address 0E6H
D0
Fig. 3.12.2
K10 input interrupt circuit
II-76 EPSON S1C62N82 TECHNICAL SOFTWARE
CHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt)
This flag is set to "1" when a falling edge is detected in the
timer TM1 (32 Hz) signal.
The contents of the IT32 flag can be loaded by software to
determine whether a 32 Hz timer interrupt has occured.
The flag is reset, when it is loaded by software. (See Figure
3.12.3.)
This flag is set to "1" when a falling edge is detected in the
timer TM1 (8 Hz) signal.
The contents of the IT8 flag can be loaded by software to
determine whether an 8 Hz timer interrupt has occured.
The flag is reset, when it is loaded by software. (See Figure
3.12.3.)
This flag is set to "1" when a falling edge is detected in the
timer TM1 (2 Hz) signal.
The contents of the IT2 flag can be loaded by software to
determine whether a 2 Hz timer interrupt has occured.
The flag is reset, when it is loaded by software. (See Figure
3.12.3.)
IT8
IT32
IT2
D0
D1
D2
Address 0EFH
D0
D1
D2
Address 0EBH
Timer interrupt
mask register (EIT)
Timer interrupt
factor flag (IT)
INT
(Interrupt request)
Interrupt flag (I)
Data bus
Data bus Basic clock counter
32 Hz
8 Hz
2 Hz
Fig. 3.12.3
Timer interrupt circuit
S1C62N82 TECHNICAL SOFTWARE EPSON II-77
CHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt)
This flag is set to "1" when a falling edge is detected in the
stopwatch timer (SWH, 1 Hz).
The contents of the ISW1 flag can be loaded by software to
determine whether a 1 Hz stopwatch interrupt has occured.
The flag is reset, when it is loaded by software. (See Figure
3.12.4.)
This flag is set to "1" when a falling edge is detected in the
stopwatch timer (SWH, 10 Hz).
The contents of the ISW0 flag can be loaded by software to
determine whether a 10 Hz stopwatch interrupt has
occured.
The flag is reset, when it is loaded by software. (See Figure
3.12.4.)
ISW1
ISW0
Reading of interrupt factor flags is available at EI, but be careful in
the following cases.
If the interrupt mask register value corresponding to the interrupt
factor flags to be read is set to 1, an interrupt request will be
generated by the interrupt factor flags set timing, or an interrupt
request will not be generated.
Be very careful when interrupt factor flags are in the same address.
Note
Fig. 3.12.4
Stopwatch interrupt
D0
D1
D0
D1
Address 0EAH
Stopwatch interrupt
mask register (EISW)
Stopwatch interrupt
factor flag (ISW)
INT
(Interrupt request)
Interrupt flag (I)
Data bus
Data bus Stopwatch
timer
10 Hz
1 Hz
Address 0EEH
II-78 EPSON S1C62N82 TECHNICAL SOFTWARE
CHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt)
• Interrupt mask registers
The interrupt mask registers are registers that individually
specify whether to enable or mask the timer interrupt (2 Hz,
8 Hz, 32 Hz), stopwatch timer interrupt (1 Hz, 10 Hz), or
input interrupt (K00–K03, K10).
The following are descriptions of the interrupt mask regis-
ters.
This register enables or masks the K00–K03 input interrupt.
The interrupt condition flag (IK0) is set to "1" when the
contents of the input (K00–K03) and the interrupt differen-
tial register (KCP00–KCP03) do not match and the data of
the corresponding interrupt mask register (EIK00–EIK03) is
"1". The CPU is interrupted if it is in the EI state (interrupt
flag [I] = "1"). (See Figure 3.12.1.)
This register enables or masks the K10 input interrupt. The
interrupt condition flag (IK1) is set to "1" when the contents
of the input (K10) and the interrupt differential register
(KCP10) do not match and the data of the corresponding
interrupt mask register (EIK10) is "1". The CPU is inter-
rupted if it is in the EI state (interrupt flag [I] = "0"). (See
Figure 3.12.2.)
EIK00 to EIK03
EIK10
<Input interrupt programing related precautions>
When the content of the mask register is rewritten, while the port K
input is in the active status. The input interrupt factor flags are set at
➀ and ➁, ➀ being the interrupt due to the falling edge and ➁ the
interrupt due to the rising edge.
Fig. 3.12.5
Input interrupt timing
Port K input
Factor flag set Not set
➁
Factor flag set
Input comparison
register
Mask register
Active status Active status
Rising edge interrupt
➀
Falling edge interrupt
S1C62N82 TECHNICAL SOFTWARE EPSON II-79
CHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt)
When using an input interrupt, if you rewrite the content
of the mask register, when the value of the input terminal
which becomes the interrupt input is in the active status,
the factor flag for input interrupt may be set. Therefore,
when using the input interrupt, the active status of the
input terminal implies
input terminal = Low status, when the falling edge
interrupt is effected and
input terminal = High status, when the rising edge
interrupt is effected.
When an interrupt is triggered at the falling edge of an
input terminal, a factor flag is set with the timing of ➀
shown in Figure 3.12.5. However, when clearing the
content of the mask register with the input terminal kept
in the LOW status and then setting it, the factor flag of
the input interrupt is again set at the timing that has
been set.
Consequently, when the input terminal is in the active
status (Low status), do not rewrite the mask register
(clearing, then setting the mask register), so that a factor
flag will only set at the falling edge in this case. When
clearing, then setting the mask register, set the mask
register, when the input terminal is not in the active
status (High status).
When an interrupt is triggered at the rising edge of the
input terminal, a factor flag will be set at the timing of ➁
shown in Figure 3.12.5. In this case, when the mask
registers cleared, then set, you should set the mask
register, when the input terminal is in the Low status.
In addition, when the mask register = "1" and the content
of the input comparison register is rewritten in the input
terminal active status, an input interrupt factor flag may
be set. Thus, you should rewrite the content of the input
comparison register in the mask register = "0" status.
II-80 EPSON S1C62N82 TECHNICAL SOFTWARE
CHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt)
This register enables or masks the 32 Hz timer interrupt.
The CPU is interrupted if it is in the EI state when the
interrupt mask register (EIT32) is set to "1" and the inter-
rupt condition flag (IT32) is "1". (See Figure 3.12.3.)
This register enables or masks the 8 Hz timer interrupt. The
CPU is interrupted if it is in the EI state when the interrupt
mask register (EIT8) is set to "1" and the interrupt condition
flag (IT8) is "1". (See Figure 3.12.3.)
This register enables or masks the 2 Hz timer interrupt. The
CPU is intterrupted if it is in the EI state when the interrupt
mask register (EIT2) is set to "1" and the interrupt condition
flag (IT2) is "1". (See Figure 3.12.3.)
This register enables or masks the 1 Hz stopwatch interrupt.
The CPU is interrupted if it is in the EI state when the
interrupt mask register (EISW1) is set to "1", and also the
interrupt condition flag (ISW1) is "1". (See Figure 3.12.4.)
This register enables or masks the 10 Hz stopwatch inter-
rupt. The CPU is interrupted if it is in the EI state when the
interrupt mask register (EISW0) is set to "1", and the inter-
rupt condition flag (ISW0) is "1". (See Figure 3.12.4.)
Write to the interrupt mask registers (EIT32, EIT8, EIT2) in DI
states only (interrupt flag [I] = "0").
EISW1
EIT2
EIT8
Note
EISW0
EIT32
S1C62N82 TECHNICAL SOFTWARE EPSON II-81
CHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt)
• Interrupt control registers
The data of the input comparison registers (KCP00–KCP03)
is compared with the data of the corresponding input ports
(K00–K03). If the data does not match and the correspond-
ing input mask register (EIK00–EIK03) is "1", the interrupt
factor flag (IK0) is set to "1".
These registers are used to determine the change in the
input (K01–K03) level. (See Figure 3.12.1.)
The data of the input comparison register (KCP10) is com-
pared with the data of the corresponding input port (K10). If
the data does not match and the corresponding input mask
register (EIK10) is "1", the interrupt factor flag (IK1) is set to
"1".
This register is used to determine the change in the input
(K10) level. (See Figure 3.12.2.)
The input comparison register can effectively be used to
determine the on/off state of the input.
However, as shown in Figure 3.12.1, the result of compari-
son of the input (K00–K03) is collected in the interrupt
factor flag (IK0), so the input comparison register cannot be
used to determine the on/off state of the key matrix.
KCP00 to KCP03
KCP10
II-82 EPSON S1C62N82 TECHNICAL SOFTWARE
CHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt)
• Interrupt vector address
The S1C62N82 interrupt vector address is made up of the
low-order 4 bits of the program counter (12 bits), each of
which is assigned a specific function as shown in Table
3.12.2.
Table 3.12.2 Assignment of the interrupt vector address
As shown in Table 3.12.2, the lower order 4 bits of the
program counter are set according to which of the interrupts
occurs. In other words, the interrupt vector address is set at
page 1, steps 02H, 04H, 06H, 08H, 0AH.
Note that all of the three timer interrupts have the same
vector address, and software must be used to judge whether
or not a given timer interrupt has occurred. For instance,
when the 32 Hz timer interrupt and the 8 Hz timer interrupt
are enabled at the same time, the accepted timer interrupt
must be identified by software. (Similarly, the K00–K03
input interrupts and the 10 Hz/1 Hz stopwatch interrupts
must be identified by software.)
When an interrupt is generated, the hardware resets the
interrupt flag (I) to enter the DI state. Execute the EI in-
struction as necessary to recover the EI state after interrupt
processing.
0
0
0
0
0
PCP3 0
0
0
0
0
PCP2 0
0
0
0
0
PCP1 1
1
1
1
1
PCP0 0
0
0
0
0
PCS7 0
0
0
0
0
PCS6 0
0
0
0
0
PCS5 0
0
0
0
0
PCS4 1
1
0
0
0
PCS3 0
0
1
1
0
PCS2 1
0
1
0
1
PCS1 0
0
0
0
0
PCS0Interrupt Item
Melody
K10
K03–K00
Stopwatch
Timer
10A
108
106
104
102
Interrupt
Vector Address Highest
Lowest
Priority
S1C62N82 TECHNICAL SOFTWARE EPSON II-83
CHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt)
Set the EI state at the start of the interrupt processing
routine to allow nesting of the interrupts. Then the priority
of the interrupt or the nesting level is determined and set by
hardware.
The interrupt factor flags must always be reset before set-
ting the EI status in the corresponding interrupt processing
routine. (The flag is reset when the interrupt condition flag
is read by software.)
If the EI instruction is executed without resetting the inter-
rupt factor flag after generating the timer interrupt or the
stopwatch timer interrupt or melody, and if the correspond-
ing interrupt mask register is still "1", the same interrupt is
generated once more. (See Figure 3.12.6.)
If the EI state is set without resetting the interrupt condition
flag after generating the input interrupt (K00–K03, K10), the
same interrupt is generated once more. (See Figure 3.12.6.)
Reading of interrupt factor flags is available at EI, but be
careful in the following cases.
If the interrupt mask register value corresponding to the
interrupt factor flags to be read is set to 1, an interrupt
request will be generated by the interrupt factor flags set
timing, or an interrupt request will not be generated.
Be very careful when interrupt factor flags are in the same
address.
The timer interrupt factor flags (IT32, IT8, IT2) and the
stopwatch interrupt factor flags (ISW1, ISW0) are set
whether the corresponding interrupt mask register is set or
not.
The input interrupt factor flags (IK0, IK1) are allowed to be
set in the condition when the corresponding interrupt mask
register (EIK00–EIK03, EIK10) is set to "1" (interrupt is
enabled). (See Figure 3.12.6.)
II-84 EPSON S1C62N82 TECHNICAL SOFTWARE
CHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt)
IMEL
EIMEL
KCP10
EIK10
K10
KCP00
EIK00
K00
KCP01
EIK01
K01
KCP02
EIK02
K02
KCP03
EIK03
K03
ISW0
EISW0
ISW1
EISW1
IT2
EIT2
IT8
EIT8
IT32
EIT32
IK1
IK0
(MSB)
(LSB)
Program
counter
Interrupt vector
(low-order 4 bits)
Priority detection circuit
Fig. 3.12.6
Internal interrupt circuit
S1C62N82 TECHNICAL SOFTWARE EPSON II-85
CHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt)
• Restart from halt state by interrupt
Main routine
Label Mnemonic/operand Comment
LD X,0E8H ;Set address of K00 to K03
;interrupt mask register
OR MX,1111B ;Enable K00 to K03
;input interrupt
;LD X,0EAH ;Set address of stopwatch
;interrupt mask register
OR MX,0010B ;Enable 1 Hz stopwatch interrupt
;LD X,0EBH ;Set address of timer interrupt
;mask register
OR MX,0111B ;Enable timer interrupt
;(32 Hz, 8 Hz, 2 Hz)
LD X,E7H ;Set address of melody interrupt
;mask register
OR MX,0001B ;Enable melody interrupt
MAIN: EI ;Set interrupt flag (EI state is set)
HALT ;Halt mode
JP MAIN ;Jump to MAIN
Examples of interrupt
and halt control
program
II-86 EPSON S1C62N82 TECHNICAL SOFTWARE
CHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt)
Interruption vector routine
Label Mnemonic/operand Comment
ORG 100H
JP INIT ;Jump to initial routine
HALT
JP TIINT ;Jump to timer interrupt routine
HALT
JP SWINT ;Jump to stopwatch interrupt routine
HALT
JP K0INT ;Jump to K0 input interrupt routine
HALT
JP K1INT ;Jump to K1 input interrupt routine
HALT
JP MELINT ;Jump to melody interrupt routine
MELINT LD Y,0ECH ;Address of melody interrupt
;factor flag
LD A,MY ;Reset melody interrupt
;factor flag
RETURN EI
RET
K1INT LD Y,0EDH ;Address of K10 input port interrupt
;factor flag
LD A,MY ;Reset K10 input port interrupt
;factor flag
JP RETURN
K0INT LD Y,0EDH ;Address of K0n input port interrupt
;factor flag
LD A,MY ;Reset K0n input port interrupt
;factor flag
JP RETURN
SWINT LD Y,0EEH ;Address of stopwatch interrupt
;factor flag
LD X,SWFSTK ;Address of stopwatch interrupt
;factor flag buffer
LD MX,MY ;Store stopwatch interrupt
;factor flag in buffer
FAN MX,0010B ;Check stopwatch 1 Hz
;factor flag
JP Z,SW10RQ ;Jump if not the 1 Hz request
;interrupt
CALL SW1IN ;Stopwatch 1 Hz interrupt
;service routine
SW10RQ LD X,SWFSTK ;Address of stopwatch interrupt
;factor flag buffer
S1C62N82 TECHNICAL SOFTWARE EPSON II-87
CHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt)
FAN MX,0001B ;Check stopwatch 10 Hz
;factor flag
JP Z,RETURN ;Return
CALL SW10IN ;Stopwatch 10 Hz interrupt
;service routine
JP RETURN
TIINT LD Y,0EFH ;Address of timer interrupt
;factor flag
LD X,TMFSK ;Address of timer interrupt
;factor flag buffer
LD MX,MY ;Store timer interrupt factor
;flag in buffer
FAN MX,0100B ;Check 2 Hz timer interrupt
;factor flag
CALL TINT2 ;Call 2 Hz timer interrupt
;service routine
JP RETURN ;Return
TI8RQ LD X,TMFSK ;Address of timer interrupt factor
;flag buffer
FAN MX,0010B ;Check 8 Hz timer interrupt
;factor flag
JP Z,TI32RQ ;Don't request interrupt
CALL TINT8 ;Call 8 Hz timer interrupt
;service routine
TI32RQ LD X,TMFSK ;Address of timer interrupt factor
;flag buffer
FAN MX,0001B ;Check 32 Hz timer interrupt
;factor flag
JP Z,RETURN ;Don't request interrupt
CALL TINT32 ;Call 32 Hz timer interrupt
;service routine
JP RETURN
The above program is normally used to restart the CPU
when in the halt state by interrupt and to return it to the
halt state again after the interrupt processing is completed.
The processing proceeds by repeating the → halt interrupt
→ halt → interrupt cycle.
II-88 EPSON S1C62N82 TECHNICAL SOFTWARE
CHAPTER 3: PERIPHERAL CIRCUITS (Interrupt and Halt)
All interrupts are enabled, and the priority when all inter-
rupts are generated simultaneously is determined by hard-
ware as follows:
(highest priority) Melody interrupt → K10 interrupt → K00–
K03 interrupt → stopwatch interrupt → timer interrupt
(lowest priority)
The two stopwatch interrupts (1 Hz, 10 Hz) have the same
vector address (104H). The priority is decided by software;
the stopwatch interrupt service routine first checks the 1 Hz
interrupt factor flag, so the priority is (high priority) stop-
watch 1 Hz interrupt → stopwatch 10 Hz interrupt (low
priority).
The three timer interrupts (2 Hz, 8 Hz, 32 Hz) have the same
vector address (102H). The priority is decided by software;
the timer interrupt service routine first checks the 2 Hz
interrupt factor flag, then 8 Hz, and finally 32 Hz, so the
priority is (first priority) timer 2 Hz interrupt → (second
priority) timer 8 Hz interrupt → (third priority) timer 32 Hz
interrupt.
Reading of interrupt factor flags is available at EI, but be
careful in the following cases.
If the interrupt mask register value corresponding to the
interrupt factor flags to be read is set to 1, an interrupt
request will be generated by the interrupt factor flags set
timing, or an interrupt request will not be generated.
Be very careful when interrupt factor flags are in the same
address.
S1C62N82 TECHNICAL SOFTWARE EPSON II-89
CHAPTER 4: SUMMARY OF PROGRAMMING POINTS
CHAPTER 4 SUMMARY OF PROGRAMMING
POINTS
• Core CPU After the system reset, only the program counter (PC),
new page pointer (NPP) and interrupt flag (I) are initial-
ized by the hardware. The other internal circuits whose
settings are undefined must be initialized with the pro-
gram.
• Power Supply External load driving through the output voltage of con-
stant voltage circuit or booster circuit is not permitted.
• Data Memory – Since some portions of the RAM are also used as stack
area during sub-routine call or register saving, see to it
that the data area and the stack area do not overlap.
– The stack area consumes 3 words during a sub-routine
call or interrupt.
– Address 00H–0FH in the RAM is the memory register area
addressed by the register pointer RP.
– Memory is not mounted in unused area within the mem-
ory map and in memory area not indicated in this man-
ual. For this reason, normal operation cannot be assured
for programs that have been prepared with access to
these areas.
• Initial Reset When utilizing the simultaneous high input reset func-
tion of the input ports (K00–K03), take care not to make
the ports specified during normal operation to go high
simultaneously.
– It takes at least 5 ms from the time the OSC3 oscillation
circuit goes ON until the oscillation stabilizes. Conse-
quently, when switching the CPU operation clock from
OSC1 to OSC3, do this after a minimum of 5 ms have
elapsed since the OSC3 oscillation went ON.
Further, the oscillation stabilization time varies depend-
ing on the external oscillator characteristics and condi-
tions of use, so allow ample margin when setting the wait
time.
• Oscillation Circuit
II-90 EPSON S1C62N82 TECHNICAL SOFTWARE
CHAPTER 4: SUMMARY OF PROGRAMMING POINTS
– When switching the clock from OSC3 to OSC1, use a
separate instruction for switching the OSC3 oscillation
OFF.
– To lessen current consumption, keep OSC3 oscillation
OFF except when the CPU must be run at high speed.
Also, with S1C62N82/62L82, keep OSCC fixed to "0".
• Input Port – When modifying the input port from high level to low level
with pull-down resistance, a delay will occur at the rise of
the waveform due to time constant of the pull-down
resistance and input gate capacities. Provide appropriate
waiting time in the program when performing input port
reading.
– Input interrupt programing related precautions
When the content of the mask register is rewritten, while the port K
input is in the active status. The input interrupt factor flags are set at
➀ and ➁, ➀ being the interrupt due to the falling edge and ➁ the
interrupt due to the rising edge.
Fig. 4.1
Input interrupt timing
When using an input interrupt, if you rewrite the content
of the mask register, when the value of the input terminal
which becomes the interrupt input is in the active status,
the factor flag for input interrupt may be set. Therefore,
when using the input interrupt, the active status of the
input terminal implies
input terminal = Low status, when the falling edge
interrupt is effected and
input terminal = High status, when the rising edge
interrupt is effected.
When an interrupt is triggered at the falling edge of an
input terminal, a factor flag is set with the timing of ➀
shown in Figure 4.1.
Port K input
Factor flag set Not set ➁Factor flag set
Input comparison
register
Mask register
Active status Active status
Rising edge interrupt
➀
Falling edge interrupt
S1C62N82 TECHNICAL SOFTWARE EPSON II-91
CHAPTER 4: SUMMARY OF PROGRAMMING POINTS
However, when clearing the content of the mask register
with the input terminal kept in the LOW status and then
setting it, the factor flag of the input interrupt is again set
at the timing that has been set.
Consequently, when the input terminal is in the active
status (Low status), do not rewrite the mask register
(clearing, then setting the mask register), so that a factor
flag will only set at the falling edge in this case. When
clearing, then setting the mask register, set the mask
register, when the input terminal is not in the active
status (High status).
When an interrupt is triggered at the rising edge of the
input terminal, a factor flag will be set at the timing of ➁
shown in Figure 4.1. In this case, when the mask regis-
ters cleared, then set, you should set the mask register,
when the input terminal is in the Low status.
In addition, when the mask register = "1" and the content
of the input comparison register is rewritten in the input
terminal active status, an input interrupt factor flag may
be set. Thus, you should rewrite the content of the input
comparison register in the mask register = "0" status.
• Output Port The FOUT output signal may produce hazards when the
output port R10 is turned on or off.
• I/O Port – When the I/O port is set to the output mode and a low-
impedance load is connected to the port pin, the data
written to the register may differ from the data read.
– When the I/O port is set to the input mode and a low-
level voltage (VSS) is input by the built-in pull-down
resistance, an erroneous input results if the time con-
stant of the capacitive load of the input line and the built-
in pull-down resistance load is greater than the read-out
time. When the input data is being read, the time that the
input line is pulled down is equivalent to 0.5 cycles of the
CPU system clock.
Hence, the electric potential of the pins must settle within
0.5 cycles. If this condition cannot be met, some measure
must be devised, such as arranging a pull-down resis-
tance externally, or performing multiple read-outs.
II-92 EPSON S1C62N82 TECHNICAL SOFTWARE
CHAPTER 4: SUMMARY OF PROGRAMMING POINTS
• LCD Driver – Becase the LCD RAM can be read and written, so data
can be changed directly using an ALU instruction (for
example, AND or OR).
– Because at initial reset, the contens of segment data
memory are undefined, there are need to initialize by
software.
– Even in case 1/4 duty were selected, when SEG terminal
is set to static driving, set the same values on all the
display memories corresponding to COM0–COM7.
• Analog Comparator Data in the CMPDT register becomes "1" when CMPON is
"0" (analog comparator circuit is off), and undefined when
the CMPP and/or CMPM input is disconnected. Avoid
reading operation under those conditions.
• Supply Voltage Detec-
tion (SVD) Circuit Since supply voltage detection is automatically performed
by the hardware every 2 Hz (0.5 sec) when the heavy load
protection function operates, do not permit the operation
of the SVD circuit by the software in order to minimize
power current consumption.
In the heavy load protection function (heavy load protec-
tion mode flag = "1"), supply voltage detection through
the SVDON register is not permitted in order to minimize
power current consumption.
• Heavy Load Protec-
tion Function
– Even when the contents of the input data and input
comparator register change from an unmatched state to
another unmatched state or to a matched state, no
interrupt will occur.
– Re-start from the HALT state is performed by the inter-
rupt. The return address after completion of the interrupt
processing in this case will be the address following the
HALT instruction.
– When interrupt occurs, the interrupt flag will be reset by
the hardware and it will become DI state. After comple-
tion of the interrupt processing, set to the EI state
through the software as needed.
Moreover, the nesting level may be set to be program-
mable by setting to the EI state at the beginning of the
interrupt processing routine.
• Interrupt
S1C62N82 TECHNICAL SOFTWARE EPSON II-93
CHAPTER 4: SUMMARY OF PROGRAMMING POINTS
– Be sure to reset the interrupt factor flag before setting to
the EI state on the interrupt processing routine. The
interrupt factor flag is reset by reading through the
software. Not resetting the interrupt factor flag and
interrupt mask register being "1", will cause the same
interrupt to occur again.
– The interrupt factor flag will be reset by reading through
the software. Because of this, when multiple interrupt
factor flags are to be assigned to the same address,
perform the flag check after the contents of the address
has been stored in the RAM. Direct checking with the
FAN instruction will cause all the interrupt factor flag to
be reset.
– Reading of interrupt factor flags is available at EI, but be
careful in the following cases. If the interrupt mask
register value corresponding to the interrupt factor flags
to be read is set to 1, an interrupt request will be gener-
ated by the interrupt factor flags set timing, or an inter-
rupt request will not be generated. Be very careful when
interrupt factor flags are in the same address.
– Be sure to perform the interrupt mask register writing
while in the DI (interrupt flag = "0") state. Writing while in
the EI (interrupt flag = "1") state may cause mis-opera-
tion.
– In case multiple interrupts occur simultaneously, inter-
rupt processing will be done in the order of high priority
first.
• Vacant Register and
Read/Write Writing data into the addresses where read/write bits
and read only bits are mixed in 1 word (4 bits) does not
affect the read only bits.
II-94 EPSON S1C62N82 TECHNICAL SOFTWARE
APPENDIX A: TABLE OF INSTRUCTIONS
APPENDIX A Table of Instructions
B
1
0
0
0
0
0
1
0
0
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
A
1
0
0
0
1
1
1
1
1
1
1
0
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
0
0
0
0
9
1
0
1
1
1
1
1
0
0
1
1
0
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
8
0
0
0
1
0
1
1
0
1
1
1
1
1
1
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
7
0
s7
s7
s7
s7
s7
1
s7
s7
1
1
l7
1
1
1
1
1
x7
y7
1
1
1
1
1
1
1
1
0
0
0
0
6
1
s6
s6
s6
s6
s6
1
s6
s6
1
1
l6
1
1
1
1
1
x6
y6
0
0
0
0
0
0
0
0
0
0
0
0
5
0
s5
s5
s5
s5
s5
1
s5
s5
0
0
l5
1
1
1
1
1
x5
y5
0
0
0
0
1
1
1
1
0
0
1
1
4
p4
s4
s4
s4
s4
s4
0
s4
s4
1
1
l4
1
1
1
0
1
x4
y4
0
0
1
1
0
0
1
1
0
1
0
1
3
p3
s3
s3
s3
s3
s3
1
s3
s3
1
1
l3
1
1
1
0
0
x3
y3
0
1
0
1
0
1
0
1
i3
i3
i3
i3
2
p2
s2
s2
s2
s2
s2
0
s2
s2
1
1
l2
0
1
0
0
0
x2
y2
1
0
1
0
1
0
1
0
i2
i2
i2
i2
1
p1
s1
s1
s1
s1
s1
0
s1
s1
1
1
l1
1
1
0
0
0
x1
y1
r1
r1
r1
r1
r1
r1
r1
r1
i1
i1
i1
i1
0
p0
s0
s0
s0
s0
s0
0
s0
s0
1
0
l0
1
1
0
0
0
x0
y0
r0
r0
r0
r0
r0
r0
r0
r0
i0
i0
i0
i0
p
s
C, s
NC, s
Z, s
NZ, s
s
s
l
X
Y
X, x
Y, y
XH, r
XL, r
YH, r
YL, r
r, XH
r, XL
r, YH
r, YL
XH, i
XL, i
YH, i
YL, i
PSET
JP
JPBA
CALL
CALZ
RET
RETS
RETD
NOP5
NOP7
HALT
INC
LD
ADC
Branch
instructions
System
control
instructions
Index
operation
instructions
Classification Operand
IDZC
↑
↑
↑
↑
↑
↑
↑
↑
5
5
5
5
5
5
5
7
7
7
12
12
5
7
5
5
5
5
5
5
5
5
5
5
5
5
5
7
7
7
7
Clock
Operation Code Flag
NBP p4, NPP p3~p0
PCB NBP, PCP NPP, PCS s7~s0
PCB NBP, PCP NPP, PCS s7~s0 if C=1
PCB NBP, PCP NPP, PCS s7~s0 if C=0
PCB NBP, PCP NPP, PCS s7~s0 if Z=1
PCB NBP, PCP NPP, PCS s7~s0 if Z=0
←
←
←
←
←
←
←
←←
←
←
←
←
←
←
←
←
←
←
PCB NBP, PCP NPP, PCSH B, PCSL A
M(SP-1) PCP, M(SP-2) PCSH, M(SP-3) PCSL+1
SP SP-3, PCP NPP, PCS s7~s0
M(SP-1) PCP, M(SP-2) PCSH, M(SP-3) PCSL+1
SP SP-3, PCP 0, PCS s7~s0
PCSL M(SP), PCSH M(SP+1), PCP M(SP+2)
SP SP+3
PCSL M(SP), PCSH M(SP+1), PCP M(SP+2)
SP SP+3, PC PC+1
PCSL M(SP), PCSH M(SP+1), PCP M(SP+2)
SP SP+3, M(X) i3~i0, M(X+1) l7~l4, X X+2
No operation (5 clock cycles)
No operation (7 clock cycles)
Halt (stop clock)
X X+1
Y Y+1
XH x7~x4, XL x3~x0
YH y7~y4, YL y3~y0
XH
XL
YH
YL
r XH
r XL
r YH
r YL
XH
XL
YH
YL
←←
←←←
←←← ←←←
←←←
←←←
←←← ←
←← ←← ←
←←←←
←
←
←
←←
←
←
←
←
←
←
←
←
←←
←
←
←
Mne-
monic Operation
r
r
r
r
XH+i3~i0+C
XL+i3~i0+C
YH+i3~i0+C
YL+i3~i0+C
↓
↓
↓
↓
↓
↓
↓
↓
S1C62N82 TECHNICAL SOFTWARE EPSON II-95
APPENDIX A: TABLE OF INSTRUCTIONS
B
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
A
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
9
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
8
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
7
0
0
0
0
0
1
1
1
1
1
0
1
0
1
l7
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
6
1
1
1
1
0
1
0
0
0
0
1
1
1
1
l6
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
5
0
0
1
1
r1
0
1
1
0
0
1
1
1
1
l5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
4
0
1
0
1
r0
0
0
1
0
1
0
0
1
1
l4
0
1
0
1
0
1
0
1
0
1
1
0
0
0
0
0
0
0
1
1
1
3
i3
i3
i3
i3
i3
r1
n3
n3
n3
n3
i3
r1
i3
r1
l3
i3
i3
0
1
0
1
0
1
1
0
1
1
0
0
0
1
1
1
0
0
0
2
i2
i2
i2
i2
i2
r0
n2
n2
n2
n2
i2
r0
i2
r0
l2
i2
i2
0
1
0
1
1
0
0
1
0
0
0
1
1
0
0
0
0
1
1
1
i1
i1
i1
i1
i1
q1
n1
n1
n1
n1
i1
q1
i1
q1
l1
i1
i1
0
1
1
0
0
1
0
1
1
1
r1
0
1
0
0
1
r1
0
1
0
i0
i0
i0
i0
i0
q0
n0
n0
n0
n0
i0
q0
i0
q0
l0
i0
i0
1
0
0
1
0
1
0
1
1
1
r0
1
0
0
1
0
r0
1
0
XH, i
XL, i
YH, i
YL, i
r, i
r, q
A, Mn
B, Mn
Mn, A
Mn, B
MX, i
r, q
MY, i
r, q
MX, l
F, i
F, i
SP
SP
r
XH
XL
YH
YL
F
r
XH
XL
CP
LD
LDPX
LDPY
LBPX
SET
RST
SCF
RCF
SZF
RZF
SDF
RDF
EI
DI
INC
DEC
PUSH
POP
Index
operation
instructions
Data
transfer
instructions
Flag
operation
instructions
Stack
operation
instructions
Classification Operand
IDZC
↑
↓
↑
↓
↑
↑
↑
↑
↑
↓
↑
↓
↑
↑
↑
↑
↑
↓
↑
↓
7
7
7
7
5
5
5
5
5
5
5
5
5
5
5
7
7
7
7
7
7
7
7
7
7
5
5
5
5
5
5
5
5
5
5
5
Clock
Operation Code Flag
XH-i3~i0
XL-i3~i0
YH-i3~i0
YL-i3~i0
r i3~i0
r q
A
B
M(n3~n0) A
M(n3~n0) B
M(X) i3~i0, X X+1
r q, X X+1
M(Y) i3~i0, Y Y+1
r q, Y Y+1
M(X) l3~l0, M(X+1) l7~l4, X X+2
←
←
F
F
C
C
Z
Z
D
D
I
I
←←
←
←
←← ←←
Mne-
monic Operation
↓
↓
↓
↓
↑
↓
↑
↓
↓
↓
↓
↓
SP SP+1
SP SP-1
SP SP-1, M(SP) r
SP SP-1, M(SP) XH
SP SP-1, M(SP) XL
SP SP-1, M(SP) YH
SP SP-1, M(SP) YL
SP SP-1, M(SP) F
r M(SP), SP SP+1
XH
XL
←
←
M(n3~n0)
M(n3~n0)
←
←←
←
←
←
←
←
←
←
←
←
←
←
←
F i3~i0
F i3~i0
1
0
1
0
1 (Decimal Adjuster ON)
0 (Decimal Adjuster OFF)
1 (Enables Interrupt)
0 (Disables Interrupt)
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←←
←
←
M(SP), SP SP+1
M(SP), SP SP+1
←
←
II-96 EPSON S1C62N82 TECHNICAL SOFTWARE
APPENDIX A: TABLE OF INSTRUCTIONS
d3 d2, d2 d1, d1 d0, d0 C, C d3
d3 C, d2 d3, d1 d2, d0 d1, C d0
M(n3~n0) M(n3~n0)+1
M(n3~n0) M(n3~n0)-1
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
B
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
A
1
1
1
1
1
1
1
1
0
1
0
0
1
0
1
0
1
0
1
0
1
1
1
1
0
1
1
1
1
1
1
1
1
9
1
1
1
1
1
1
1
0
1
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
0
8
1
1
1
1
1
1
1
0
0
0
0
0
1
0
0
0
0
0
1
0
1
1
1
1
0
0
1
1
1
1
1
1
1
7
1
1
1
1
1
1
1
0
1
0
1
1
0
1
1
1
1
1
0
1
1
0
1
0
1
1
0
0
0
0
0
0
0
6
1
1
1
1
1
1
1
0
0
1
0
0
1
0
0
1
1
1
0
1
1
0
0
0
1
0
1
1
0
0
0
0
0
5
0
0
0
1
1
1
1
r1
0
r1
0
1
r1
1
r1
0
r1
0
r1
1
r1
0
r1
0
1
0
1
1
1
1
1
1
r1
4
1
1
1
0
1
0
1
r0
0
r0
1
0
r0
1
r0
0
r0
1
r0
0
r0
0
r0
1
1
0
0
1
0
0
1
1
r0
3
1
1
1
0
0
0
0
i3
r1
i3
r1
r1
i3
r1
i3
r1
i3
r1
i3
r1
i3
r1
i3
r1
r1
1
n3
n3
1
1
1
1
1
2
0
0
0
0
0
1
1
i2
r0
i2
r0
r0
i2
r0
i2
r0
i2
r0
i2
r0
i2
r0
i2
r0
r0
1
n2
n2
0
1
0
1
1
1
0
0
1
r1
r1
r1
r1
i1
q1
i1
q1
q1
i1
q1
i1
q1
i1
q1
i1
q1
i1
q1
i1
q1
r1
r1
n1
n1
r1
r1
r1
r1
1
0
0
1
0
r0
r0
r0
r0
i0
q0
i0
q0
q0
i0
q0
i0
q0
i0
q0
i0
q0
i0
q0
i0
q0
r0
r0
n0
n0
r0
r0
r0
r0
1
YH
YL
F
SPH, r
SPL, r
r, SPH
r, SPL
r, i
r, q
r, i
r, q
r, q
r, i
r, q
r, i
r, q
r, i
r, q
r, i
r, q
r, i
r, q
r, i
r, q
r
r
Mn
Mn
MX, r
MY, r
MX, r
MY, r
r
POP
LD
ADD
ADC
SUB
SBC
AND
OR
XOR
CP
FAN
RLC
RRC
INC
DEC
ACPX
ACPY
SCPX
SCPY
NOT
Stack
operation
instructions
Arithmetic
instructions
Classification Operand
IDZC
↑↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
5
5
5
5
5
5
5
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
5
7
7
7
7
7
7
7
Clock
Operation Code Flag
YH
YL
F M(SP), SP SP+1
SPH
SPL
r SPH
r SPL
←
←
←
Mne-
monic Operation
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↑
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
↓↓
★
★
★
★
★
★
★
★
★
★
★
r r+i3~i0
r r+q
r r+i3~i0+C
r r+q+C
r r-q
r r-i3~i0-C
r r-q-C
r r i3~i0
r r q
r r i3~i0
r r q
r r i3~i0
r r q
r-i3~i0
r-q
r i3~i0
r q
M(X) M(X)+r+C, X X+1
M(Y) M(Y)+r+C, Y Y+1
M(X) M(X)-r-C, X X+1
M(Y) M(Y)-r-C, Y Y+1
r r
M(SP), SP SP+1
M(SP), SP SP+1
←
←
←←
←
←
r
r
←←← ←
←← ← ←←
←
←
←
←
←
←
←
←
←
←
←
S1C62N82 TECHNICAL SOFTWARE EPSON II-97
APPENDIX A: TABLE OF INSTRUCTIONS
Abbreviations used in the explanations have the following
meanings.
A .............. A register
B .............. B register
X .............. XHL register (low order eight bits of index register
IX)
Y .............. YHL register (low order eight bits of index
register IY)
XH ........... XH register (high order four bits of XHL register)
XL ............ XL register (low order four bits of XHL register)
YH............ YH register (high order four bits of YHL register)
YL ............ YL register (low order four bits of YHL register)
XP ............ XP register (high order four bits of index
register IX)
YP ............ YP register (high order four bits of index
register IY)
SP ............ Stack pointer SP
SPH.......... High-order four bits of stack pointer SP
SPL .......... Low-order four bits of stack pointer SP
MX, M(X) .. Data memory whose address is specified with
index register IX
MY, M(Y)... Data memory whose address is specified with
index register IY
Mn, M(n) .. Data memory address 000H–00FH (address
specified with immediate data n of 00H–0FH)
M(SP) ....... Data memory whose address is specified with
stack pointer SP
r, q ........... Two-bit register code
r, q is two-bit immediate data; according to the
contents of these bits, they indicate registers A,
B, and MX and MY (data memory whose ad-
dresses are specified with index registers IX and
IY) rq
r1 r0 q1 q0
0000 A
0101 B
1010 MX
1111 MY
Registers specified
Symbols associated with
registers and memory
II-98 EPSON S1C62N82 TECHNICAL SOFTWARE
APPENDIX A: TABLE OF INSTRUCTIONS
NBP..... New bank pointer
NPP ..... New page pointer
PCB..... Program counter bank
PCP ..... Program counter page
PCS ..... Program counter step
PCSH .. Four high order bits of PCS
PCSL ... Four low order bits of PCS
F ......... Flag register (I, D, Z, C)
C ......... Carry flag
Z ......... Zero flag
D......... Decimal flag
I .......... Interrupt flag
↓............. Flag reset
↑............. Flag set
↕......... Flag set or reset
p ......... Five-bit immediate data or label 00H–1FH
s.......... Eight-bit immediate data or label 00H–0FFH
l .......... Eight-bit immediate data 00H–0FFH
i .......... Four-bit immediate data 00H–0FH
+ ......... Add
- .......... Subtract
∧............. Logical AND
∨............. Logical OR
∀ ............ Exclusive-OR
★......... Add-subtract instruction for decimal operation
when the D flag is set
Symbols associated with
program counter
Symbols associated with
flags
Associated with
immediate data
Associated with
arithmetic and other
operations
S1C62N82 TECHNICAL SOFTWARE EPSON II-99
APPENDIX B: THE S1C62N82 I/O MEMORY MAP
APPENDIX B The S1C62N82 I/O Memory Map
K03
K02
K01
K00
–
–
–
–
HIGH
HIGH
HIGH
HIGH
LOW
LOW
LOW
LOW
INPORT DATA K03
INPORT DATA K02
INPORT DATA K01
INPORT DATA K00
K00
R
K01
R
K02
R
K03
R
E0
0
0
0
K10
–
–
–
–
–
–
–
HIGH
–
–
–
LOW INPORT DATA K10
K10
R
0
R
0
R
0
R
E1
SWL3
SWL2
SWL1
SWL0
0
0
0
0
–
–
–
–
–
–
–
–
STOPWATCH TIMER DATA 3 (1/100) MSB
STOPWATCH TIMER DATA 2 (1/100)
STOPWATCH TIMER DATA 1 (1/100)
STOPWATCH TIMER DATA 0 (1/100) LSB
SWL0
R
SWL1
R
SWL2
R
SWL3
R
E2
SWH3
SWH2
SWH1
SWH0
0
0
0
0
–
–
–
–
–
–
–
–
STOPWATCH TIMER DATA 3 (1/10) MSB
STOPWATCH TIMER DATA 2 (1/10)
STOPWATCH TIMER DATA 1 (1/10)
STOPWATCH TIMER DATA 0 (1/10) LSB
SWH0
R
SWH1
R
SWH2
R
SWH3
R
E3
TM3
TM2
TM1
TM0
0
0
0
0
HIGH
HIGH
HIGH
HIGH
LOW
LOW
LOW
LOW
CLOCK TIMER DATA 2Hz
CLOCK TIMER DATA 4Hz
CLOCK TIMER DATA 8Hz
CLOCK TIMER DATA 16Hz
TM0
R
TM1
R
TM2
R
TM3
R
E4
KCP03
KCP02
KCP01
KCP00
0
0
0
0
FALLING
FALLING
FALLING
FALLING
RISING
RISING
RISING
RISING
K03 INPUT COMPARISON REGISTER
K02 INPUT COMPARISON REGISTER
K01 INPUT COMPARISON REGISTER
K00 INPUT COMPARISON REGISTER
KCP00
R/W
KCP01
R/W
KCP02
R/W
KCP03
R/W
E5
0
0
0
KCP10
–
–
–
0
–
–
–
FALLING
–
–
–
RISING K10 INPUT COMPARISON REGISTER
KCP10
R/W
0
R
0
R
0
R
E6
0
0
0
EIMEL
–
–
–
0
–
–
–
ENABLE
–
–
–
MASK MELODY INTERRUPT MASK REGISTER
EIMEL
R/W
0
R
0
R
0
R
E7
EIK03
EIK02
EIK01
EIK00
0
0
0
0
ENABLE
ENABLE
ENABLE
ENABLE
MASK
MASK
MASK
MASK
K03 INTERRUPT MASK REGISTER
K02 INTERRUPT MASK REGISTER
K01 INTERRUPT MASK REGISTER
K00 INTERRUPT MASK REGISTER
EIK00
R/W
EIK01
R/W
EIK02
R/W
EIK03
R/W
E8
0
0
0
EIK10
–
–
–
0
–
–
–
ENABLE MASK K10 INTERRUPT MASK REGISTER
EIK10
R/W
0
R
0
R
0
R
E9
0
0
EISW1
EISW0
–
–
0
0
–
–
ENABLE
ENABLE
–
–
MASK
MASK S/W INTERRUPT MASK REGISTER 1Hz
S/W INTERRUPT MASK REGISTER 10Hz
EISW0
R/W
EISW1
R/W
0
R
0
R
EA
0
EIT2
EIT8
EIT32
–
0
0
0
–
ENABLE
ENABLE
ENABLE
–
MASK
MASK
MASK
TIMER INTERRUPT MASK REGISTER 2Hz
TIMER INTERRUPT MASK REGISTER 8Hz
TIMER INTERRUPT MASK REGISTER 32Hz
EIT32
R/W
EIT8
R/W
EIT2
R/W
0
R
EB
0
0
0
IMEL
–
–
–
0
–
–
–
YES
–
–
–
NO MELODY INTERRUPT FACTOR FLAG
IMEL
R
0
R
0
R
0
R
EC
0
0
IK1
IK0
–
–
0
0
–
–
YES
YES
–
–
NO
NO K10 INTERRUPT FACTOR FLAG
K00–K03 INTERRUPT FACTOR FLAG
IK0
R
IK1
R
0
R
0
R
ED
0
0
ISW1
ISW0
–
–
0
0
–
–
YES
YES
–
–
NO
NO S/W INTERRUPT FACTOR FLAG 1Hz
S/W INTERRUPT FACTOR FLAG 10Hz
ISW0
R
ISW1
R
0
R
0
R
EE
0
IT2
IT8
IT32
–
0
0
0
–
YES
YES
YES
–
NO
NO
NO
TIMER INTERRUPT FACTOR FLAG 2Hz
TIMER INTERRUPT FACTOR FLAG 8Hz
TIMER INTERRUPT FACTOR FLAG 32Hz
IT32
R
IT8
R
IT2
R
0
R
EF
AD-
DRESS D0D1D2D3 01SRNAME COMMENT
DATA
II-100 EPSON S1C62N82 TECHNICAL SOFTWARE
APPENDIX B: THE S1C62N82 I/O MEMORY MAP
MAD3
MAD2
MAD1
MAD0
0
0
0
0
HIGH
HIGH
HIGH
HIGH
LOW
LOW
LOW
LOW
MEL. ROM ADDR. SETTING REG. AD3
MEL. ROM ADDR. SETTING REG. AD2
MEL. ROM ADDR. SETTING REG. AD1
MEL. ROM ADDR. SETTING REG. LSB
MAD0
R/W
MAD1
R/W
MAD2
R/W
MAD3
R/W
F0
0
MAD6
MAD5
MAD4
–
0
0
0
–
HIGH
HIGH
HIGH
–
LOW
LOW
LOW
MEL. ROM ADDR. SETTING REG. MSB
MEL. ROM ADDR. SETTING REG. AD5
MEL. ROM ADDR. SETTING REG. AD4
MAD4
R/W
MAD5
R/W
MAD6
R/W
0
R
F1
CLK1
CLK0
TEMPC
MELC
0
0
0
0
HIGH
HIGH
HIGH
ON
LOW
LOW
LOW
OFF
REG. TO CHANGE MELODY CLOCK
REG. TO CHANGE MELODY CLOCK
REG. TO CHANGE TWO KINDS OF TEMPO
MELODY ON/OFF CONTROL REGISTER
MELC
R/W
TEMPC
R/W
CLKC0
R/W
CLKC1
R/W
F2
R03
R02
R01
R00
0
0
0
0
HIGH
HIGH
HIGH
HIGH
LOW
LOW
LOW
LOW
R03 OUT PORT DATA
R02 OUT PORT DATA
R01 OUT PORT DATA
R00 OUT PORT DATA
R00
R/W
R01
R/W
R02
R/W
R03
R/W
F3
MELD
R12
MO
ENV
R11
R10
FOUT
0
0
–
Hz
0
0
DISABLE
HIGH
–
–
HIGH
HIGH
ON
ENABLE
LOW
–
–
LOW
LOW
OFF
MELODY OUTPUT MASK
R12 OUT PORT DATA
MELODY INVERTED OUTPUT
MELODY ENVELOPE CONTROL
R11 OUT PORT DATA
R10 OUT PORT DATA
FREQUENCY OUTPUT
R10
FOUT
R/W
R11
R/W
R12
MO
ENV
R/W
MELD
R/W
F4
P03
P02
P01
P00
–
–
–
–
HIGH
HIGH
HIGH
HIGH
LOW
LOW
LOW
LOW
P03 I/O PORT DATA
P02 I/O PORT DATA
P01 I/O PORT DATA
P00 I/O PORT DATA
P00
R/W
P01
R/W
P02
R/W
P03
R/W
F6
0
TMRST
SWRUN
SWRST
–
RESET
0
RESET
–
RESET
RUN
RESET
–
–
STOP
–
TIMER RESET
STOPWATCH RUN/STOP CONTROL REG.
STOPWATCH RESET
SWRST
W
SWRUN
R/W
TMRST
W
0
R
F9
HLMOD
0
SVDDT
SVDON
0
–
0
0
HEAVY
–
LOW
ON
NORMAL
–
NORMAL
OFF
HEAVY LOAD PROTECTION MODE
SUPPLY VOLTAGE DETECTOR DATA
SUPPLY VOLTAGE DETECTOR ON/OFF
SVDON
R/W
SVDDT
R
0
R
HLMOD
R/W
FA
CSDC
0
CMPDT
CMPON
0
–
1
0
STATIC
–
+>-
ON
DYNAMIC
–
->+
OFF
LCD DRIVER CONTROL REG.
CMP DATA
COMPARATOR ON-OFF CONTROL REG.
CMPON
R/W
CMPDT
R
0
R
CSDC
R/W
FB
CLKCHG
OSCC
0
IOC
–
–
–
0
OSC3
ON
–
OUT
OSC1
OFF
–
IN
CPU CLOCK SWITCH
OSC3 OSCILLATOR ON/OFF
I/O IN-OUT CONTROL REG.
IOC
R/W
0
R
OSCC
R/W
CLKCHG
R/W
FC
AD-
DRESS
D0D1D2D3 01SRNAME COMMENT
DATA
S1C62N82 TECHNICAL SOFTWARE EPSON II-101
APPENDIX C: TABLE OF THE ICE COMMANDS
APPENDIX C Table of the ICE Commands
1
2
3
4
5
6
7
8
9
10
Assemble
Disassemble
Dump
Fill
Set
Run Mode
Trace
Break
Move
Data Set
Change CPU
Internal
Registers
#A,a
#L,a1,a2
#DP,a1,a2
#DD,a1,a2
#FP,a1,a2,d
#FD,a1,a2,d
#G,a
#TIM
#OTF
#T,a,n
#U,a,n
#BA,a
#BAR,a
#BD
#BDR
#BR
#BRR
#BM
#BMR
#BRES
#BC
#BE
#BSYN
#BT
#BRKSEL,REM
#MP,a1,a2,a3
#MD,a1,a2,a3
#SP,a
#SD,a
#DR
#SR
#I
#DXY
#SXY
Assemble command mnemonic code and store at address "a"
Contents of addresses a1 to a2 are disassembled and displayed
Contents of program area a1 to a2 are displayed
Content of data area a1 to a2 are displayed
Data d is set in addresses a1 to a2 (program area)
Data d is set in addresses a1 to a2 (data area)
Program is executed from the "a" address
Execution time and step counter selection
On-the-fly display selection
Executes program while displaying results of step instruction
from "a" address
Displays only the final step of #T,a,n
Sets Break at program address "a"
Breakpoint is canceled
Break condition is set for data RAM
Breakpoint is canceled
Break condition is set for Evaluation Board CPU internal registers
Breakpoint is canceled
Combined break conditions set for program data RAM address
and registers
Cancel combined break conditions for program data ROM
address and registers
All break conditions canceled
Break condition displayed
Enter break enable mode
Enter break disable mode
Set break stop/trace modes
Set BA condition clear/remain modes
Contents of program area addresses a1 to a2 are moved to
addresses a3 and after
Contents of data area addresses a1 to a2 are moved to addresses
a3 and after
Data from program area address "a" are written to memory
Data from data area address "a" are written to memory
Item No. Function Command Format Outline of Operation
Display Evaluation Board CPU internal registers
Set Evaluation Board CPU internal registers
Reset Evaluation Board CPU
Display X, Y, MX and MY
Set data for X and Y display and MX, MY
II-102 EPSON S1C62N82 TECHNICAL SOFTWARE
APPENDIX C: TABLE OF THE ICE COMMANDS
11
12
13
14
15
16
17
History
File
Coverage
ROM Access
Terminate
ICE
Command
Display
Self
Diagnosis
#H,p1,p2
#HB
#HG
#HP
#HPS,a
#HC,S/C/E
#HA,a1,a2
#HAR,a1,a2
#HAD
#HS,a
#HSW,a
#HSR,a
#RF,file
#RFD,file
#VF,file
#VFD,file
#WF,file
#WFD,file
#CL,file
#CS,file
#OPTLD,n,file
#CVD
#CVR
#RP
#VP
#ROM
#Q
#HELP
#CHK
Display history data for pointer 1 and pointer 2
Display upstream history data
Display 21 line history data
Display history pointer
Set history pointer
Sets up the history information acquisition before (S),
before/after (C) and after (E)
Sets up the history information acquisition from program area
a1 to a2
Sets up the prohibition of the history information acquisition
from program area a1 to a2
Indicates history acquisition program area
Retrieves and indicates the history information which executed
a program address "a"
Retrieves and indicates the history information which wrote or
read the data area address "a"
Save contents of memory to program file
Save contents of memory to data file
Load ICE set condition from file
Save ICE set condition to file
Load HEXA data flom file
Terminate ICE and return to operating system control
Display ICE instruction
Report results of ICE self diagnostic test
Move program file to memory
Move data file to memory
Compare program file and contents of memory
Compare data file and contents of memory
Indicates coverage information
Clears coverage information
Move contents of ROM to program memory
Compare contents of ROM with contents of program memory
Set ROM type
Item No. Function Command Format Outline of Operation
means press the RETURN key.
S1C62N82 TECHNICAL SOFTWARE EPSON II-103
APPENDIX D: CROSS-ASSEMBLER PSEUDO INSTRUCTION LIST
APPENDIX D Cross-assembler Pseudo Instruction List
Item No. Pseudo-instruction Meaning Example of Use
1
2
3
4
5
6
7
8
9
10
EQU
(Equation)
ORG
(Origin)
SET
(Set)
DW
(Define Word)
PAGE
(Page)
SECTION
(Section)
END
(End)
MACRO
(Macro)
LOCAL
(Local)
ENDM
(End Macro)
To allocate data to label
To define location counter
To allocate data to label
(data can be changed)
To define ROM data
To define boundary of page
To define boundary of section
To terminate assembly
To define macro
To make local specification of label
during macro definition
To end macro definition
ABC EQU 9
CHECK MACRO DATA
LOCAL LOOP
LOOP CP MX,DATA
JP NZ,LOOP
ENDM
CHECK 1
BCD EQU ABC+1
ORG 100H
ORG 256
ABC SET 0001H
ABC SET 0002H
ABC DW 'AB'
BCD DW 0FFBH
PAGE 1H
PAGE 15
SECTION
END
II-104 EPSON S1C62N82 TECHNICAL SOFTWARE
APPENDIX E: THE FORMAT OF MELODY SOURCE FILE
Contents of the source file, created with an editor such as
EDLIN, are configured from the S1C62N82 Series melody
codes and the pseudo-instructions described later.
Source File Name
The source file can be named with a maximum of any seven
characters. As a rule, keep to the following format.
C282YYY.MDT
Three alphanumerics are entered in the "YYY" part. Refer to
the model name from Seiko Epson. The extension must be
".MDT".
Statement (line)
Write each of the source file statements (lines) as follows:
APPENDIX E The Format of Melody Source File
Basic format:
Example: <attack> <note> <scale> <end bit> <comment>
.TEMPC0=5
.TEMPC1=8
.OCTAVE=32
;
1
0
0
0
0
1
1
0
;
ORG
;
1
0
0
1
0
0
1
1
4
4
2
3
7
5
6
10H
2
3
7
6
5
7
3
C3
D4
E4#
F5
G5#
A4
B4
A4#
C3#
$45
$E3
$97
C6
A5#
$42
1
1
;1st Melody
;2nd Melody
Attack field Note field Scale field End bit field Comment field
S1C62N82 TECHNICAL SOFTWARE EPSON II-105
APPENDIX E: THE FORMAT OF MELODY SOURCE FILE
The statement is made up of the five fields: attack field, note
field, scale field, end bit field, and comment field. Up to 80
characters can be written in the statement. The fields are
separated by one or more spaces or by inserting tabs.
The end bit fields and comment fields can be filled in on an
as-needed basis.
A blank line is also permitted for the CR (carriage return)
code only. However, it is not permitted on the last line.
Each of the fields can be started from any column.
Control of the attack output is written.
When "1" is written, attack output is performed. When "0"
is written, attack output is not performed.
Eight notes can be specified with the melody ROM codes D6
through D8. Fill in the note field with numbers from 1 to 8.
Scale field
Attack field
Note field
No.
Note
12345678
The scale field can be filled in with any scale data (C3
through C6#).
When inputting the code directly, prefix the code with "$".
In this case, the input code range is 00H through FDH.
The instruction indicating the end of the melody is written
in the end bit field. When "1" is written, the melody finishes
with the melody ROM code of that address. Otherwise, write
"0", or omit it altogether.
Any comment, such as the program index or processing
details, can be written in the comment field, with no affect
on the object file created with the assembler.
The comment field is the area between the semicolon ";" and
the CR code at the end of the line.
A line can be made up of a comment field alone. However, if
the comment extends into two or more lines, each line must
be headed with a semicolon.
End bit field
Comment field
II-106 EPSON S1C62N82 TECHNICAL SOFTWARE
APPENDIX F: DIVIDING TABLE
APPENDIX F Dividing Table
Dividing table at no use of octave 32.768 kHz
Scale
Data Scale ROM Code
S7
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
S6
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
S5
0
0
1
1
1
0
0
0
1
1
1
1
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
S4
0
1
0
0
1
0
1
1
0
0
1
1
0
0
1
1
1
0
0
1
1
1
1
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
S3
0
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
1
0
1
0
0
1
1
0
0
1
1
1
0
0
1
1
1
1
0
0
0
0
S2
1
0
0
1
0
1
0
0
1
1
1
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
1
0
1
0
0
1
1
0
0
1
1
S1
0
1
0
1
1
0
0
1
0
0
0
0
0
0
1
0
1
0
1
0
0
0
0
0
0
0
0
1
1
0
0
1
0
1
0
1
0
1
S0
0
0
0
1
1
0
1
1
1
0
0
0
0
1
0
0
0
0
1
1
1
0
0
0
0
0
1
0
1
0
1
1
0
0
0
0
0
0
Hex.
Frequency
(Hz) Dividing
Ratio Absolute
Error (%) Standard
Frequency (Hz)
C3
C3#
D3
D3#
E3
F3
F3#
G3
G3#
A3
A3#
B3
C4
C4#
D4
D4#
E4
F4
F4#
G4
G4#
A4
A4#
B4
C5
C5#
D5
D5#
E5
F5
F5#
G5
G5#
A5
A5#
B5
C6
C6#
128
135.405
143.719
152.409
161.419
170.667
181.039
191.626
203.528
215.579
227.556
240.941
256
270.810
287.439
303.407
321.255
341.333
360.088
385.506
404.543
431.158
455.111
481.882
512
546.133
574.877
606.815
642.510
682.667
728.178
762.047
819.200
862.316
910.222
963.765
1024
1092.267
04
12
20
2F
3B
44
51
5B
65
6C
74
7C
84
8D
92
98
9E
A4
AB
B1
B5
B8
BC
C0
C4
C8
CD
CE
D3
D4
D9
DB
DC
DE
E0
E2
E4
E6
1/128
1/121
1/114
1/107
1/101
1/96
1/90
1/85
1/80
1/76
1/72
1/68
1/64
1/60
1/57
1/54
1/51
1/48
1/45
1/42
1/40
1/38
1/36
1/34
1/32
1/30
1/28
1/27
1/25
1/24
1/22
1/21
1/20
1/19
1/18
1/17
1/16
1/15
1/2
1/2
1/2
103
102
1/2
91
86
81
1/2
1/2
1/2
1/2
61
1/2
1/2
1/2
1/2
46
43
41
1/2
1/2
1/2
1/2
1/2
29
1/2
26
1/2
23
22
1/2
1/2
1/2
1/2
1/2
1/2
x
x
x
+
+
x
+
+
+
x
x
x
x
+
x
x
x
x
+
+
+
x
x
x
x
x
+
x
+
x
+
+
x
x
x
x
x
x
0
-0.152
0.031
0.024
0.092
-0.113
0.010
-0.030
0.167
0.143
-0.226
-0.287
0
-0.153
0.031
-0.339
-0.400
-0.113
-0.542
0.503
-0.453
0.144
-0.226
-0.287
0
0.675
0.031
-0.339
-0.400
-0.113
0.563
-0.668
0.787
0.144
-0.226
-0.287
0
0.675
128
135.611
143.675
152.218
161.270
170.860
181.019
191.783
203.187
215.270
228.070
241.632
256
271.222
287.350
304.436
322.540
341.720
362.038
383.566
406.374
430.540
456.140
483.264
512
542.444
574.700
608.872
645.080
683.440
724.076
767.132
812.748
861.080
912.280
966.528
1024
1084.888
S1C62N82 TECHNICAL SOFTWARE EPSON II-107
APPENDIX F: DIVIDING TABLE
Dividing table at no use of octave 65.536 kHz
Scale
Data Scale ROM Code
S7
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
S6
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
S5
0
0
1
1
1
0
0
0
1
1
1
1
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
S4
0
1
0
0
1
0
1
1
0
0
1
1
0
0
1
1
1
0
0
1
1
1
1
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
S3
0
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
1
0
1
0
0
1
1
0
0
1
1
1
0
0
1
1
1
1
0
0
0
0
S2
1
0
0
1
0
1
0
0
1
1
1
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
1
0
1
0
0
1
1
0
0
1
1
S1
0
1
0
1
1
0
0
1
0
0
0
0
0
0
1
0
1
0
1
0
0
0
0
0
0
0
0
1
1
0
0
1
0
1
0
1
0
1
S0
0
0
0
1
1
0
1
1
1
0
0
0
0
1
0
0
0
0
1
1
1
0
0
0
0
0
1
0
1
0
1
1
0
0
0
0
0
0
Hex.
Frequency
(Hz) Dividing
Ratio Absolute
Error (%) Standard
Frequency (Hz)
C4
C4#
D4
D4#
E4
F4
F4#
G4
G4#
A4
A4#
B4
C5
C5#
D5
D5#
E5
F5
F5#
G5
G5#
A5
A5#
B5
C6
C6#
D6
D6#
E6
F6
F6#
G6
G6#
A6
A6#
B6
C7
C7#
256
270.810
287.439
304.819
322.837
341.333
362.077
383.251
407.056
431.158
455.111
481.882
512
541.620
574.877
606.815
642.510
682.667
720.176
771.012
809.086
862.316
910.222
963.765
1024
1092.267
1149.754
1213.630
1285.020
1365.333
1456.356
1524.093
1638.400
1724.632
1820.444
1927.529
2048
2194.533
04
12
20
2F
3B
44
51
5B
65
6C
74
7C
84
8D
92
98
9E
A4
AB
B1
B5
B8
BC
C0
C4
C8
CD
CE
D3
D4
D9
DB
DC
DE
E0
E2
E4
E6
1/128
1/121
1/114
1/107
1/101
1/96
1/90
1/85
1/80
1/76
1/72
1/68
1/64
1/60
1/57
1/54
1/51
1/48
1/45
1/42
1/40
1/38
1/36
1/34
1/32
1/30
1/28
1/27
1/25
1/24
1/22
1/21
1/20
1/19
1/18
1/17
1/16
1/15
1/2
1/2
1/2
103
102
1/2
91
86
81
1/2
1/2
1/2
1/2
61
1/2
1/2
1/2
1/2
46
43
41
1/2
1/2
1/2
1/2
1/2
29
1/2
26
1/2
23
22
1/2
1/2
1/2
1/2
1/2
1/2
x
x
x
+
+
x
+
+
+
x
x
x
x
+
x
x
x
x
+
+
+
x
x
x
x
x
+
x
+
x
+
+
x
x
x
x
x
x
0
-0.152
0.031
2.448
0.092
-0.113
0.011
-0.082
0.168
0.143
-0.226
-0.287
0
-0.152
0.031
-0.339
-0.400
-0.113
-0.541
0.503
-0.453
0.143
-0.226
-0.287
0
0.676
0.031
-0.339
-0.399
-0.113
0.563
-0.667
0.788
0.143
-0.226
-0.287
0
0.676
256
271.222
287.350
304.436
322.540
341.720
362.038
383.566
406.374
430.540
456.140
483.264
512
542.444
574.700
608.872
645.080
683.440
724.076
767.132
812.748
861.080
912.280
966.528
1024
1084.888
1149.400
1217.748
1290.160
1366.880
1448.152
1534.264
1625.496
1722.160
1824.560
1933.056
2048
2169.776
II-108 EPSON S1C62N82 TECHNICAL SOFTWARE
APPENDIX G: RAM MAP
APPENDIX G RAM Map
PROGRAM NAME: C282_____ /
H
0
1
2
3
4
5
P
0L
MAME
MSB
LSB
MAME
MSB
LSB
MAME
MSB
LSB
MAME
MSB
LSB
MAME
MSB
LSB
MAME
MSB
LSB
0123456789ABCDEF
S1C62N82 TECHNICAL SOFTWARE EPSON II-109
APPENDIX G: RAM MAP
PROGRAM NAME: C282_____ /
H
9
A
E
F
P
0L
MAME
MSB
LSB
MAME
MSB
LSB
MAME
MSB
LSB
MAME
MSB
LSB
0123456789ABCDEF
—
ZK03
ZK02
ZK01
ZK00
—
ZMAD3
ZMAD2
ZMAD1
ZMAD0
—
—
—
—
ZK10
—
—
ZMAD6
ZMAD5
ZMAD4
—
ZSWL3
ZSWL2
ZSWL1
ZSWL0
—
ZCLKC1
ZCLKC0
ZTEMPC
ZMELC
—
ZSWH3
ZSWH2
ZSWH1
ZSWH0
—
ZR03
ZR02
ZR01
ZR00
—
ZTM3
ZTM2
ZTM1
ZTM0
—
ZMELD
ZR12
ZR11
ZR10
—
ZKCP03
ZKCP02
ZKCP01
ZKCP00
—
—
—
—
—
—
—
—
—
ZKCP10
—
ZP03
ZP02
ZP01
ZP00
—
—
—
—
ZEIMEL
—
—
—
—
—
—
—
—
—
ZEIK10
—
—
ZTMRST
ZSWRUN
ZSWRST
—
—
—
ZEISW1
ZEISW0
—
ZHLMOD
—
ZSVDDT
ZSVDON
—
—
ZEIT2
ZEIT8
ZEIT32
—
ZCSDC
—
ZCMPDT
ZCMPON
—
—
—
—
ZIMEL
—
ZOSCC
—
ZIOC
—
—
—
ZIK1
ZIK0
—
—
—
—
—
—
—
—
ZISW1
ZISW0
—
—
—
—
—
—
—
ZIT2
ZIT8
ZIT32
—
—
—
—
—
ZCLKCHG
—
ZEIK03
ZEIK02
ZEIK01
ZEIK00
—
—
—
—
—
AMERICA
EPSON ELECTRONICS AMERICA, INC.
- HEADQUARTERS -
1960 E. Grand Avenue
EI Segundo, CA 90245, U.S.A.
Phone: +1-310-955-5300 Fax: +1-310-955-5400
- SALES OFFICES -
West
150 River Oaks Parkway
San Jose, CA 95134, U.S.A.
Phone: +1-408-922-0200 Fax: +1-408-922-0238
Central
101 Virginia Street, Suite 290
Crystal Lake, IL 60014, U.S.A.
Phone: +1-815-455-7630 Fax: +1-815-455-7633
Northeast
301 Edgewater Place, Suite 120
Wakefield, MA 01880, U.S.A.
Phone: +1-781-246-3600 Fax: +1-781-246-5443
Southeast
3010 Royal Blvd. South, Suite 170
Alpharetta, GA 30005, U.S.A.
Phone: +1-877-EEA-0020 Fax: +1-770-777-2637
EUROPE
EPSON EUROPE ELECTRONICS GmbH
- HEADQUARTERS -
Riesstrasse 15
80992 Munich, GERMANY
Phone: +49-(0)89-14005-0 Fax: +49-(0)89-14005-110
SALES OFFICE
Altstadtstrasse 176
51379 Leverkusen, GERMANY
Phone: +49-(0)2171-5045-0 Fax: +49-(0)2171-5045-10
UK BRANCH OFFICE
Unit 2.4, Doncastle House, Doncastle Road
Bracknell, Berkshire RG12 8PE, ENGLAND
Phone: +44-(0)1344-381700 Fax: +44-(0)1344-381701
FRENCH BRANCH OFFICE
1 Avenue de l' Atlantique, LP 915 Les Conquerants
Z.A. de Courtaboeuf 2, F-91976 Les Ulis Cedex, FRANCE
Phone: +33-(0)1-64862350 Fax: +33-(0)1-64862355
BARCELONA BRANCH OFFICE
Barcelona Design Center
Edificio Prima Sant Cugat
Avda. Alcalde Barrils num. 64-68
E-08190 Sant Cugat del Vallès, SPAIN
Phone: +34-93-544-2490 Fax: +34-93-544-2491
ASIA
EPSON (CHINA) CO., LTD.
28F, Beijing Silver Tower 2# North RD DongSanHuan
ChaoYang District, Beijing, CHINA
Phone: 64106655 Fax: 64107319
SHANGHAI BRANCH
4F, Bldg., 27, No. 69, Gui Jing Road
Caohejing, Shanghai, CHINA
Phone: 21-6485-5552 Fax: 21-6485-0775
EPSON HONG KONG LTD.
20/F., Harbour Centre, 25 Harbour Road
Wanchai, Hong Kong
Phone: +852-2585-4600 Fax: +852-2827-4346
Telex: 65542 EPSCO HX
EPSON TAIWAN TECHNOLOGY & TRADING LTD.
10F, No. 287, Nanking East Road, Sec. 3
Taipei
Phone: 02-2717-7360 Fax: 02-2712-9164
Telex: 24444 EPSONTB
HSINCHU OFFICE
13F-3, No. 295, Kuang-Fu Road, Sec. 2
HsinChu 300
Phone: 03-573-9900 Fax: 03-573-9169
EPSON SINGAPORE PTE., LTD.
No. 1 Temasek Avenue, #36-00
Millenia Tower, SINGAPORE 039192
Phone: +65-337-7911 Fax: +65-334-2716
SEIKO EPSON CORPORATION KOREA OFFICE
50F, KLI 63 Bldg., 60 Yoido-dong
Youngdeungpo-Ku, Seoul, 150-763, KOREA
Phone: 02-784-6027 Fax: 02-767-3677
SEIKO EPSON CORPORATION
ELECTRONIC DEVICES MARKETING DIVISION
Electronic Device Marketing Department
IC Marketing & Engineering Group
421-8, Hino, Hino-shi, Tokyo 191-8501, JAPAN
Phone: +81-(0)42-587-5816 Fax: +81-(0)42-587-5624
ED International Marketing Department Europe & U.S.A.
421-8, Hino, Hino-shi, Tokyo 191-8501, JAPAN
Phone: +81-(0)42-587-5812 Fax: +81-(0)42-587-5564
ED International Marketing Department Asia
421-8, Hino, Hino-shi, Tokyo 191-8501, JAPAN
Phone: +81-(0)42-587-5814 Fax: +81-(0)42-587-5110
International Sales Operations
In pursuit of “Saving” Technology, Epson electronic devices.
Our lineup of semiconductors, liquid crystal displays and quartz devices
assists in creating the products of our customers’ dreams.
Epson IS energy savings.
http://www.epson.co.jp/device/
Technical Manual
S1C62N82
EPSON Electronic Devices Website
ELECTRONIC DEVICES MARKETING DIVISION
First issue November, 1991
Printed March, 2001 in Japan B
M
