VTM®Current Multiplier Rev 1.3 vicorpower.com
Page 1 of 18 07/2015 800 927.9474
High Efficiency, Sine Amplitude Converter™
VTM Current Multiplier
S
NRTL
CUS
320 009 A00 yE
48
VTM x
FEATURES
• 48 Vdc to 32 Vdc 9.4 A current multiplier
- Operating from standard 48 V or 24 V PRM®Regulators
•High efficiency (> 96 %) reduces system power
consumption
•High density ( 32 A /in3)
•“ Full Chip ” VI Chip®package enables surface mount,
low impedance interconnect to system board
•Contains built-in protection features against:
- Overvoltage Lockout
- Overcurrent
- Short Circuit
- Overtemperature
•Provides enable / disable control,
internal temperature monitoring
•ZVS / ZCS resonant Sine Amplitude Converter topology
•Less than 50ºC temperature rise at full load
in typical applications
TYPICAL APPLICATIONS
• High End Computing Systems
• Automated Test Equipment
• High Density Power Supplies
• Communications Systems
DESCRIPTION
The VI Chip®current multiplier is a high efficiency (> 96 %)
Sine Amplitude Converter™ (SAC) operating from a
26 to 55 Vdc primary bus to deliver an isolated output. The
Sine Amplitude Converter offers a low AC impedance beyond
the bandwidth of most downstream regulators; therefore
capacitance normally at the load can be located at the input to
the Sine Amplitude Converter. Since the K factor of the
VTM48EF320T009A00 is 2/3 , the capacitance value can be
reduced by a factor of 2.25 , resulting in savings of board area,
materials and total system cost.
The VTM48EF320T009A00 is provided in a VI Chip package
compatible with standard pick-and-place and surface mount
assembly processes. The co-molded VI Chip package provides
enhanced thermal management due to a large thermal
interface area and superior thermal conductivity. The high
conversion efficiency of the VTM48EF320T009A00 increases
overall system efficiency and lowers operating costs compared
to conventional approaches.
The VTM48EF320T009A00 enables the utilization of Factorized
Power Architecture™ which provides efficiency and size
benefits by lowering conversion and distribution losses and
promoting high density point of load conversion.
VIN = 26 to 55 V
VOUT = 17.3 to 36.7 V(NO LOAD)
IOUT = 9.4 A(NOM)
K = 2/3
VIN
L
O
A
D
PR
PC
VC
TM
IL
OS
SG
PRM®
Regulator
CD
-Out
+Out
-In
+In
PC
VC
TM
-Out
+Out
-In
+In
Regulator Voltage Transformer
Factorized Power ArchitectureTM
VTM®
Transformer
(See Application Note AN:024)
PART NUMBER PACKAGE STYLE PRODUCT GRADE
F= J-Lead T= -40 to 125°C
T= Through hole M= -55 to 125°C
PART NUMBERING
For Storage and Operating Temperatures see Section 6.0 General Characteristics
320
xy 009
A00
E
48 VTM
TYPICAL APPLICATION
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ATTRIBUTE SYMBOL CONDITIONS / NOTES MIN TYP MAX UNIT
Input voltage range VIN No external VC applied 26 55 VDC
VC applied 0 55
VIN slew rate dVIN /dt 1 V/µs
VIN UV turn off VIN_UV Module latched shutdown, 24 26 V
No external VC applied, IOUT = 9.4 A
No Load power dissipation PNL
VIN = 48 V 2 8.0
W
VIN = 26 V to 55 V 8.5
VIN = 48 V, TC= 25 ºC 3.5 5
VIN = 26 V to 55 V, TC= 2 ºC 5.5
Inrush current peak IINRP VC enable, VIN = 48 V, COUT = 100 µF, 9 25 A
RLOAD = 3307 mΩ
DC input current IIN_DC 8.2 A
Transfer ratio K K = VOUT /V
IN, IOUT = 0 A 2/3 V/V
Output voltage VOUT VOUT = VIN •K - IOUT •ROUT, Section 11 V
Output current (average) IOUT_AVG 9.4 A
Output current (peak) IOUT_PK TPEAK < 10 ms, IOUT_AVG ≤ 9.4 A 11.8 A
Output power (average) POUT_AVG IOUT_AVG ≤ 9.4 A 300 W
VIN = 48 V, IOUT = 9.4 A 95.0 96.2
Efficiency (ambient) hAMB VIN = 26 V to 55 V, IOUT = 9.4 A 93.0 %
VIN = 48 V, IOUT = 4.7 A
95.0 96.4
Efficiency (hot) hHOT VIN = 48 V, TC= 100°C, IOUT = 9.4 A
95.0 96.2 %
Efficiency (over load range) h20% 1.88 A < IOUT < 9.4 A 87.0 %
Output resistance (cold) ROUT_COLD TC= -40°C, IOUT = 9.4 A
35.0 70.0 87.0 mΩ
Output resistance (ambient) ROUT_AMB TC= 25°C, IOUT = 9.4 A 53 97.4 120.0 mΩ
Output resistance (hot) ROUT_HOT TC= 100°C, IOUT = 9.4 A 75.0 113.5 140.0 mΩ
Switching frequency FSW 1.57 1.60 1.63 MHz
Output ripple frequency FSW_RP 3.14 3.20 3.26 MHz
Output voltage ripple VOUT_PP COUT = 0 F, IOUT = 9.4 A, VIN = 48 V, 310 500 mV
20 MHz BW, Section 12
Output inductance (parasitic) LOUT_PAR Frequency up to 30 MHz, 600 pH
Simulated J-lead model
Output capacitance (internal) COUT_INT Effective Value at 32 VOUT 4.2 µF
Output capacitance (external) COUT_EXT VTM Standalone Operation. 100 µF
VIN pre-applied, VC enable
PROTECTION
Overvoltage lockout VIN_OVLO+Module latched shutdown 55.1 59 60.0 V
Overvoltage lockout TOVLO Effective internal RC filter 8 µs
response time constant
Output overcurrent trip IOCP 11 14 19.5 A
Short circuit protection trip current ISCP 20 A
Output overcurrent TOCP Effective internal RC filter (Integrative). 3.8 ms
response time constant
Short circuit protection response time TSCP From detection to cessation 1 µs
of switching (Instantaneous)
Thermal shutdown setpoint TJ_OTP 125 130 135 ºC
Reverse inrush current protection Reverse Inrush protection disabled for this product.
1.0 ABSOLUTE MAXIMUM VOLTAGE RATINGS
The absolute maximum ratings below are stress ratings only. Operation at or beyond these maximum ratings can cause permanent
damage to the device.
2.0 ELECTRICAL CHARACTERISTICS
Specifications apply over all line and load conditions unless otherwise noted; Boldface specifications apply over the temperature
range of -40°C < TJ< 125 °C (T-Grade); All other specifications are at TJ= 25ºC unless otherwise noted.
MIN MAX UNIT
+ IN to - IN . . . . . . . . . . . . . . . . . . . . . . . -1.0 60 VDC
PC to - IN . . . . . . . . . . . . . . . . . . . . . . . . -0.3 20 VDC
TM to -IN . . . . . . . . . . . . . . . . . . . . . . . . -0.3 7 VDC
MIN MAX UNIT
VC to - IN . . . . . . . . . . . . . . . . . . . . . . . . -0.3 20 VDC
+ IN / - IN to + OUT / - OUT (hipot) . . . 2250 VDC
+ OUT to - OUT....................................... 0.0 60 VDC
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SIGNAL TYPE STATE ATTRIBUTE SYMBOL CONDITIONS / NOTES MIN TYP MAX UNIT
External VC voltage VVC_EXT Required for start up, and operation
11.5 16.5 V
below 26 V. See Section 7.
VC = 11.5 V, VIN = 0 V 150 200
VC current draw IVC
VC = 11.5 V, VIN > 26 V 0 mA
VC = 16.5 V, VIN > 26 V 0
Steady Fault mode. VC > 11.5 V 60
ANALOG
VC internal diode rating DVC_INT 100 V
INPUT
VC internal resistor RVC-INT 0.51 kΩ
VC internal resistor TVC_COEFF 900 ppm/°C
temperature coefficient
Start Up
VC start up pulse VVC_SP Tpeak <18 ms 20 V
VC slew rate dVC/dt Required for proper start up; 0.02 0.25 V/µs
VC inrush current IINR_VC VC = 16.5 V, dVC/dt = 0.25 V/µs 1 A
VC to VOUT turn-on delay TON VIN pre-applied, PC floating, 500 µs
VC enable, CPC = 0 µF
Transitional VC to PC delay Tvc_pc VC = 11.5 V to PC high, VIN = 0 V, 75 125 µs
dVC/dt = 0.25 V/µs
Internal VC capacitance CVC_INT VC = 0 V 3.2 µF
• Used to wake up powertrain circuit.
• A minimum of 11.5 V must be applied indefinitely for VIN < 26 V
to ensure normal operation.
• VC slew rate must be within range for a succesful start.
•PRM
®VC can be used as valid wake-up signal source.
• Internal Resistance used in “Adaptive Loop” compensation
• VC voltage may be continuously applied
VTM CONTROL : VC
3.0 SIGNAL CHARACTERISTICS
Specifications apply over all line and load conditions unless otherwise noted; Boldface specifications apply over the
temperaturerange of -40°C < TJ< 125°C (T-Grade); All other specifications are at TJ= 25°C unless otherwise noted.
SIGNAL TYPE STATE ATTRIBUTE SYMBOL CONDITIONS / NOTES MIN TYP MAX UNIT
PC voltage VPC 4.7 5.0 5.3 V
ANALOG Steady PC source current IPC_OP 2 mA
OUTPUT PC resistance (internal) RPC_INT Internal pull down resistor 50 150 400 kΩ
Start Up
PC source current IPC_EN 50 100 300 µA
PC capacitance (internal) CPC_INT Section 7 1000 pF
PC resistance (external) RPC_S 60 kΩ
Enable PC voltage VPC_EN 2 2.5 3 V
DIGITAL Disable PC voltage (disable) VPC_DIS 2 V
INPUT / OUPUT
PC pull down current IPC_PD 5.1 mA
Transitional PC disable time TPC_DIS_T 5 µs
PC fault response time TFR_PC From fault to PC = 2 V 100 µs
• The PC pin enables and disables the VTM.
When held below 2 V, the VTM will be disabled.
• PC pin outputs 5 V during normal operation. PC pin is equal to 2.5 V
during fault mode given VIN > 26 V or VC > 11.5 V.
• After successful start up and under no fault condition, PC can be used as
a 5 V regulated voltage source with a 2 mA maximum current.
• Module will shutdown when pulled low with an impedance
less than 400 Ω.
• In an array of VTMs, connect PC pin to synchronize start up.
• PC pin cannot sink current and will not disable other modules
during fault mode.
PRIMARY CONTROL : PC
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SIGNAL TYPE STATE ATTRIBUTE SYMBOL CONDITIONS / NOTES MIN TYP MAX UNIT
TM voltage VTM_AMB TJcontroller = 27°C 2.95 3.00 3.05 V
ANALOG TM source current ITM 100 µA
OUTPUT Steady TM gain ATM 10 mV/°C
TM voltage ripple VTM_PP CTM = 0 F, VIN = 48 V, 120 200 mV
IOUT = 9.4 A
Disable TM voltage VTM_DIS 0 V
DIGITAL OUTPUT TM resistance (internal) RTM_INT Internal pull down resistor 25 40 50 kΩ
Transitional TM capacitance (external) CTM_EXT 50 pF
(FAULT FLAG) TM fault response time TFR_TM From fault to TM = 1.5 V 10 µs
• The TM pin monitors the internal temperature of the VTM controller IC
within an accuracy of ±5°C.
• Can be used as a "Power Good" flag to verify that the VTM is operating.
• The TM pin has a room temperature setpoint of 3 V
and approximate gain of 10 mV/°C.
• Output drives Temperature Shutdown comparator
TEMPERATURE MONITOR : TM
4.0 TIMING DIAGRAM
12
7
VPRI
1. Initiated VC pulse
2. Controller start
3. VPRI ramp up
4. VPRI = VOVLO
5. VPRI ramp down no VC pulse
6. Overcurrent, Secondary
7. Start up on short circuit
8. PC driven low
VSEC
PC
3 V
VC
NL
5 V
VOVLO
TM
VTM-AMB
c
Notes:
– Timing and voltage is not to scale
– Error pulse width is load dependent
a: VC slew rate (dVC/dt)
b: Minimum VC pulse rate
c: TOVLO_PIN
d: TOCP_SEC
e: Secondary turn on delay (TON)
f: PC disable time (TPC_DIS_T)
g: VC to PC delay (TVC_PC)
d
ISEC
ISEC
ISEC
VVC-EXT
345
6
a
b
8
g
ef
≥ 26 V
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5.0 APPLICATION CHARACTERISTICS
The following values, typical of an application environment, are collected at TC= 25ºC unless otherwise noted. See associated figures
for general trend data.
ATTRIBUTE SYMBOL CONDITIONS / NOTES TYP UNIT
No load power dissipation PNL VIN = 48 V, PC enabled 3.3 W
Efficiency (ambient) hAMB VIN = 48 V, IOUT = 9.4 A 96.2 %
Efficiency (hot) hHOT VIN = 48 V, IOUT = 9.4 A, TC= 100ºC 95.8 %
Output resistance (cold) ROUT_COLD VIN = 48 V, IOUT = 9.4 A, TC= -40ºC 72.3 mΩ
Output resistance (ambient) ROUT_AMB VIN = 48 V, IOUT = 9.4 A 98.5 mΩ
Output resistance (hot) ROUT_HOT VIN = 48 V, IOUT = 9.4 A, TC= 100ºC 113.9 mΩ
Output voltage ripple VOUT_PP COUT = 0 F, IOUT = 9.4 A, VIN = 48 V,
329 mV
20 MHz BW, Section 12
VOUT transient (positive) VOUT_TRAN+IOUT_STEP = 0 A TO 9.4 A, VIN = 48 V,
500 mV
ISLEW = 12 A /us
VOUT transient (negative) VOUT_TRAN-IOUT_STEP = 9.4 A to 0 A, VIN = 48 V
200 mV
ISLEW = 31 A /us
Input Voltage (V)
Power Dissipation (W)
-40°C 25°C 100°C
T :
CASE
No Load Power Dissipation vs. Line
1
2
3
4
5
6
7
8
26 29 32 35 38 41 43 46 49 52 55
Full Load Efficiency vs. T
CASE
Case Temperature (C)
Full Load Efficiency (%)
26 V 48 V 55 V
V :
IN
-40 -20 0 20 40 60 80 100
92
93
94
95
96
97
98
Efficiency & Power Dissipation -40°C Case
Load Current (A)
Efficiency (%)
26 V 48 V 55 V
V :
IN 26 V 48 V 55 V
Power Dissipation (W)
0
3
6
9
12
15
18
21
24
27
80
82
84
86
88
90
92
94
96
98
0 1 2 3 4 5 6 7 8 9 10
P
D
Efficiency & Power Dissipation 25°C Case
Load Current (A)
Efficiency (%)
26 V 48 V 55 V
V :
IN 26 V 48 V 55 V
Power Dissipation (W)
0
3
6
9
12
15
18
21
24
27
80
82
84
86
88
90
92
94
96
98
0 1 2 3 4 5 6 7 8 9 10
P
D
Figure 1 — No load power dissipation vs. VIN Figure 2 — Full load efficiency vs. temperature
Figure 3 — Efficiency and power dissipation at –40°C Figure 4 — Efficiency and power dissipation at 25°C
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Figure 10 — Start up from application of VIN;
VC pre-applied COUT = 100 µF
Output Voltage (V)
Output Current (A)
Safe Operating Area
0
2
4
6
8
10
12
14
16
0 4 8 12 16 20 24 28 32 36 40
Continuous
10ms Max
Figure 8 — Safe operating area
Figure 9 — Full load ripple, 100 µF CIN; No external COUT.Board
mounted module, scope setting : 20 MHz analog BW
Load Current (A)
26 V 48 V 55 V
V :
IN
Output Voltage Ripple vs. Load
VRipple (mVPK-PK)
50
100
150
200
250
300
350
400
0 1 2 3 4 5 6 7 8 9 10
Figure 7 — VRIPPLE vs. IOUT ; No external COUT.Board mounted
module, scope setting : 20 MHz analog BW
Efficiency & Power Dissipation 100°C Case
Load Current (A)
26 V 48 V 55 V
V :
IN 26 V 48 V 55 V
Power Dissipation (W)
Efficiency
0
3
6
9
12
15
18
21
24
27
80
82
84
86
88
90
92
94
96
98
0 1 2 3 4 5 6 7 8 9 10
P
D
R
OUT
(mW)
)
Case Temperature (C)
R
OUT
vs. T
CASE
at V
IN
= 48 V
Full Load
30
54
78
102
126
150
-40 -20 0 20 40 60 80 100
Figure 5 — Efficiency and power dissipation at 100°C Figure 6 — ROUT vs. temperature
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Figure 13 — Full load – 0 A transient response:
CIN = 100 µF, no external COUT
Figure 12 – 0 A– Full load transient response:
CIN = 100 µF, no external COUT
Figure 11 — Start up from application of VC;
VIN pre-applied COUT = 100 µF
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ATTRIBUTE SYMBOL CONDITIONS / NOTES MIN TYP MAX UNIT
MECHANICAL
Length L 32.25 / [1.270] 32.5 / [1.280] 32.75 / [1.289] mm/[in]
Width W 21.75 / [0.856] 22.0 / [0.866] 22.25 / [0.876] mm/[in]
Height H 6.48 / [0.255] 6.73 / [0.265] 6.98 / [0.275] mm/[in]
Volume Vol No heat sink 4.81 / [0.294] cm3/[in3]
Weight W 15.0 / [0.53] g/[oz]
Nickel 0.51 2.03
Lead finish Palladium 0.02 0.15 µm
Gold 0.003 0.051
THERMAL
VTM48EF320T009A00 (T-Grade) -40 125 °C
Operating temperature TJ
VTM48EF320M009A00 (M-Grade) -55 125 °C
VTM48ET320T009A00 (T-Grade) -40 125 °C
VTM48ET320M009A00 (M-Grade) -55 125 °C
Thermal resistance fJC Isothermal heat sink and 1 °C/W
isothermal internal PCB
Thermal capacity 5 Ws/°C
ASSEMBLY
Peak compressive force Supported by J-lead only 6 lbs
applied to case (Z-axis) 5.41 lbs / in2
VTM48EF320T009A00 (T-Grade) -40 125 °C
Storage temperature TST VTM48EF320M009A00 (M-Grade) -65 125 °C
VTM48ET320T009A00 (T-Grade) -40 125 °C
VTM48ET320M009A00 ( M-Grade) -65 125 °C
ESDHBM 1000
ESD withstand
ESDCDM 400
VDC
SOLDERING
Peak temperature during reflow MSL 4 (Datecode 1528 and later) 245 °C
Peak time above 217°C 60 90 s
Peak heating rate during reflow 1.5 3 °C/s
Peak cooling rate post reflow 1.5 6 °C/s
SAFETY
Isolation voltage (hipot) VHIPOT 2250 VDC
Isolation capacitance CIN_OUT Unpowered unit 2500 3200 3800 pF
Isolation resistance RIN_OUT 10 MΩ
MTBF
MIL-HDBK-217 Plus Parts Count;
3.8 MHrs25ºC Ground Benign, Stationary,
Indoors / Computer Profile
Telcordia Issue 2 - Method I Case 1; 5.6 MHrs
Ground Benign, Controlled
cTUVus
Agency approvals / standards CE Marked for Low Voltage Directive and ROHS Recast Directive, as applicable
Human Body Model,
"JEDEC JESD 22-A114-F"
Charge Device Model,
"JEDEC JESD 22-C101-D"
6.0 GENERAL CHARACTERISTICS
Specifications apply over all line and load conditions unless otherwise noted; Boldface specifications apply over the temperature
range of -40ºC < TJ< 125ºC (T-Grade); All Other specifications are at TJ= 25°C unless otherwise noted.
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7.0 USING THE CONTROL SIGNALS VC, PC, TM, IM
The VTM Control (VC) pin is an input pin which powers the
internal VCC circuitry when within the specified voltage range
of 11.5 V to 16.5 V. This voltage is required for VTM current
multiplier start up and must be applied as long as the input is
below 26 V. In order to ensure a proper start, the slew rate of
the applied voltage must be within the specified range.
Some additional notes on the using the VC pin:
• In most applications, the VTM module will be powered by an
upstream PRM®regulator which provides a 10 ms
VC pulse during start up. In these applications the VC pins
of the PRM regulator and VTM current multiplier should be
tied together.
• The VC voltage can be applied indefinitely allowing for
continuous operation down to 0 VIN.
• The fault response of the VTM module is latching. A positive
edge on VC is required in order to restart the unit. If VC is
continuously applied the PC pin may be toggled to restart
the VTM module.
Primary Control (PC) pin can be used to accomplish the
following functions:
• Delayed start: Upon the application of VC, the PC pin will
source a constant 100 µA current to the internal RC
network. Adding an external capacitor will allow further
delay in reaching the 2.5 V threshold for module start.
• Auxiliary voltage source: Once enabled in regular
operational conditions (no fault), each VTM PC provides a
regulated 5 V, 2 mA voltage source.
• Output disable: PC pin can be actively pulled down in order
to disable the module. Pull down impedance shall be lower
than 400 Ω.
• Fault detection flag: The PC 5 V voltage source is internally
turned off as soon as a fault is detected. It is important to
notice that PC doesn’t have current sink capability. Therefore,
in an array, PC line will not be capable of disabling
neighboring modules if a fault is detected.
• Fault reset: PC may be toggled to restart the unit if VC
is continuously applied.
Temperature Monitor (TM) pin provides a voltage
proportional to the absolute temperature of the converter
control IC.
It can be used to accomplish the following functions:
• Monitor the control IC temperature: The temperature in
Kelvin is equal to the voltage on the TM pin scaled
by 100. (i.e. 3.0 V = 300 K = 27ºC). If a heat sink is applied,
TM can be used to thermally protect the system.
• Fault detection flag: The TM voltage source is internally
turned off as soon as a fault is detected. For system
monitoring purposes (microcontroller interface) faults are
detected on falling edges of TM signal.
8.0 START UP BEHAVIOR
Depending on the sequencing of the VC with respect to the
input voltage, the behavior during start up will vary as follows:
• Normal operation (VC applied prior to VIN): In this case the
controller is active prior to ramping the input. When the
input voltage is applied, the VTM module output voltage will
track the input (See Figure 10). The inrush current is
determined by the input voltage rate of rise and output
capacitance. If the VC voltage is removed prior to the input
reaching 26 V, the VTM may shut down.
• Stand-alone operation (VC applied after VIN): In this case the
VTM output will begin to rise upon the application of the
VC voltage (See Figure 11). The Adaptive Soft Start Circuit
(See Section 11) may vary the ouput rate of rise in order to
limit the inrush current to its maximum level. When starting
into high capacitance, or a short, the output current will be
limited for a maximum of 1200 µsec. After this period, the
Adaptive Soft Start Circuit will time out and the VTM module
may shut down. No restart will be attempted until VC is
re-applied or PC is toggled. The maximum output
capacitance is limited to 100 µF in this mode of operation
to ensure a sucessful start.
9.0 THERMAL CONSIDERATIONS
VI Chip®products are multi-chip modules whose temperature
distribution varies greatly for each part number as well as with
the input /output conditions, thermal management and
environmental conditions. Maintaining the top of the
VTM48EF320T009A00 case to less than 100ºC will keep all
junctions within the VI Chip module below 125ºC for most
applications.
The percent of total heat dissipated through the top surface
versus through the J-lead is entirely dependent on the
particular mechanical and thermal environment. The heat
dissipated through the top surface is typically 60%. The heat
dissipated through the J-lead onto the PCB board surface is
typically 40%. Use 100% top surface dissipation when
designing for a conservative cooling solution.
It is not recommended to use a VI Chip module for an
extended period of time at full load without proper
heat sinking.
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VTM x
-VOUT
+VINI
VREF
TM
PC
Temperature
Dependent
Voltage Source
-VIN
2.5 V
100 A
5 V
40 K
1000 pF
10.5 V
2.5 V
Dierential
Primary
Current Sensing
VREF
Enable
1.5 K
Synchronous
Rectication
Primary Stage &
Resonant Tank
PC Pull-Up
& Source
Overtemperature
Protection
Fast Current
Limit
VC
CIN
18 V
Power
Transformer
Q1
Q2
Q6
Primary
Gate
Drive
Secondary
Gate Drive
Fault Logic
Regulator
Supply
Enable
Adaptive
Soft Start
Enable
Q5
Cr Lr
0.01 F
1 K
2 mA
COUT
Modulator
Enable
150 K
VDD
VDD
VDD
+VOUT
Q3
Q4
Gate Drive
Supply
DVC_INT
RVC_INT
VIN
OVLO
UVLO
Slow Current
Limit
Over Current Protection
10.0 VTM MODULE BLOCK DIAGRAM
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11.0 SINE AMPLITUDE CONVERTERTM POINT OF LOAD CONVERSION
The Sine Amplitude Converter (SAC) uses a high frequency
resonant tank to move energy from input to output. (The
resonant tank is formed by Cr and leakage inductance Lr in the
power transformer windings as shown in the VTM module
Block Diagram. See Section 10). The resonant LC tank,
operated at high frequency, is amplitude modulated as a
function of input voltage and output current. A small amount
of capacitance embedded in the input and output stages of
the module is sufficient for full functionality and is key to
achieving power density.
The VTM48EF320T009A00 SAC can be simplified into the
following model:
At no load:
VOUT = VIN •K (1)
K represents the “turns ratio” of the SAC.
Rearranging Eq (1):
K= VOUT (2)
VIN
In the presence of load, VOUT is represented by:
VOUT = VIN •K – IOUT •ROUT (3)
and IOUT is represented by:
IOUT =IIN –I
Q(4)
K
ROUT represents the impedance of the SAC, and is a function of
the RDSON of the input and output MOSFETs and the winding
resistance of the power transformer. IQrepresents the
quiescent current of the SAC control and gate drive circuitry.
The use of DC voltage transformation provides additional
interesting attributes. Assuming that ROUT = 0 Ωand IQ= 0 A,
Eq. (3) now becomes Eq. (1) and is essentially load
independent, resistor R is now placed in series with VIN as
shown in Figure 15.
The relationship between VIN and VOUT becomes:
VOUT = (VIN –I
IN •R) •K (5)
Substituting the simplified version of Eq. (4)
(IQis assumed = 0 A) into Eq. (5) yields:
VOUT = VIN •K – IOUT •R •K2(6)
+
–
+
–
VOUT
COUT
VIN
V•I
K
+
–
+
–
CIN
IOUT
RCOUT
IQ
ROUT
RCIN
73 mA
2/3 • IOUT 2/3 • VIN
97.4 mΩ
RCIN
0.57 mΩ
8800 pH
0.5 ΩRCOUT
850 µΩ
4.2 µF
LOUT = 600 pH
2 µF
IQ
LIN = 5.8 nH IOUT ROUT
VIN VOUT
R
SAC
K = 1/32
Vin
Vout
+
–
VIN
VOUT
R
SAC™
K = 1/32
Figure 15 — K = 1/32 Sine Amplitude Converter™
with series input resistor
Figure 14 — VI Chip®module AC model
COUT
CIN
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VTM x
This is similar in form to Eq. (3), where ROUT is used to
represent the characteristic impedance of the SAC™. However,
in this case a real R on the input side of the SAC is effectively
scaled by K2with respect to the output.
Assuming that R = 1 Ω, the effective R as seen from the secondary
side is 0.98 mΩ, with K = 1/32 as shown in Figure 15.
A similar exercise should be performed with the additon of a
capacitor or shunt impedance at the input to the SAC. A
switch in series with VIN is added to the circuit. This is depicted
in Figure 16.
A change in VIN with the switch closed would result in a
change in capacitor current according to the following
equation:
IC(t) = C dVIN (7)
dt
Assume that with the capacitor charged to VIN, the switch is
opened and the capacitor is discharged through the idealized
SAC. In this case,
IC=I
OUT •K (8)
Substituting Eq. (1) and (8) into Eq. (7) reveals:
IOUT =C•dVOUT (9)
K2dt
The equation in terms of the output has yielded a K2scaling
factor for C, specified in the denominator of the equation.
A K factor less than unity, results in an effectively larger
capacitance on the output when expressed in terms of the
input. With a K=1/32 as shown in Figure 16,
C=1 µF would appear as C=1024 µF when viewed
from the output.
Low impedance is a key requirement for powering a high-
current, low voltage load efficiently. A switching regulation
stage should have minimal impedance while simultaneously
providing appropriate filtering for any switched current. The
use of a SAC between the regulation stage and the point of
load provides a dual benefit of scaling down series impedance
leading back to the source and scaling up shunt capacitance or
energy storage as a function of its K factor squared. However,
the benefits are not useful if the series impedance of the SAC
is too high. The impedance of the SAC must be low, i.e. well
beyond the crossover frequency of the system.
A solution for keeping the impedance of the SAC low involves
switching at a high frequency. This enables small magnetic
components because magnetizing currents remain low. Small
magnetics mean small path lengths for turns. Use of low loss
core material at high frequencies also reduces core losses.
The two main terms of power loss in the VTM module are:
-No load power dissipation (PNL): defined as the power
used to power up the module with an enabled powertrain
at no load.
-Resistive loss (ROUT): refers to the power loss across
the VTM modeled as pure resistive impedance.
PDISSIPATED = PNL + PROUT (10)
Therefore,
POUT = PIN –P
DISSIPATED = PIN –P
NL –P
ROUT (11)
The above relations can be combined to calculate the overall
module efficiency:
h=POUT =PIN –P
NL –P
ROUT (12)
PIN PIN
=VIN •IIN –P
NL –(I
OUT)2•ROUT
VIN •IIN
=1 –
(
PNL + (IOUT)2•ROUT
)
VIN •IIN
C
S
SAC
K = 1/32
Vin
Vout
+
–
VIN VOUT
C
SAC™
K = 1/32
Figure 16 — Sine Amplitude Converter™ with input capacitor
S
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VTM x
12.0 INPUT AND OUTPUT FILTER DESIGN
A major advantage of a SAC system versus a conventional
PWM converter is that the former does not require large
functional filters. The resonant LC tank, operated at extreme
high frequency, is amplitude modulated as a function of input
voltage and output current and efficiently transfers charge
through the isolation transformer. A small amount of
capacitance embedded in the input and output stages of the
module is sufficient for full functionality and is key to achieving
high power density.
This paradigm shift requires system design to carefully evaluate
external filters in order to:
1.Guarantee low source impedance.
To take full advantage of the VTM module dynamic
response, the impedance presented to its input terminals
must be low from DC to approximately 5 MHz. Input
capacitance may be added to improve transient
performance or compensate for high source impedance.
2.Further reduce input and /or output voltage ripple without
sacrificing dynamic response.
Given the wide bandwidth of the VTM module, the source
response is generally the limiting factor in the overall
system response. Anomalies in the response of the source
will appear at the output of the VTM module multiplied
by its K factor.
3.Protect the module from overvoltage transients imposed
by the system that would exceed maximum ratings and
cause failures.
The VI Chip®module input/output voltage ranges must
not be exceeded. An internal overvoltage lockout function
prevents operation outside of the normal operating input
range. Even during this condition, the powertrain is
exposed to the applied voltage and power MOSFETs must
withstand it.
13.0 CAPACITIVE FILTERING CONSIDERATIONS
FOR A SINE AMPLITUDE CONVERTER™
It is important to consider the impact of adding input and
output capacitance to a Sine Amplitude Converter on the
system as a whole. Both the capacitance value and the
effective impedance of the capacitor must be considered.
A Sine Amplitude Converter has a DC ROUT value which has
already been discussed in section 11. The AC ROUT of the
SAC contains several terms:
• Resonant tank impedance
• Input lead inductance and internal capacitance
• Output lead inductance and internal capacitance
The values of these terms are shown in the behavioral model in
section 11. It is important to note on which side of the
transformer these impedances appear and how they reflect
across the transformer given the K factor.
The overall AC impedance varies from model to model. For
most models it is dominated by DC ROUT value from DC to
beyond 500 KHz. The behavioral model in section 11 should be
used to approximate the AC impedance of the specific model.
Any capacitors placed at the output of the VTM module reflect
back to the input of the module by the square of the K factor
(Eq. 9) with the impedance of the module appearing in series.
It is very important to keep this in mind when using a PRM®
regulator to power the VTM module. Most PRM modules have
a limit on the maximum amount of capacitance that can be
applied to the output. This capacitance includes both the PRM
output capacitance and the VTM module output capacitance
reflected back to the input. In PRM module remote sense
applications, it is important to consider the reflected value of
VTM module output capacitance when designing and
compensating the PRM module control loop.
Capacitance placed at the input of the VTM module appear to
the load reflected by the K factor with the impedance of the
VTM module in series. In step-down ratios, the effective
capacitance is increased by the K factor. The effective ESR of
the capacitor is decreased by the square of the K factor, but
the impedance of the module appears in series. Still, in most
step-down VTM modules an electrolytic capacitor placed at the
input of the module will have a lower effective impedance
compared to an electrolytic capacitor placed at the output. This
is important to consider when placing capacitors at the output
of the module. Even though the capacitor may be placed at
the output, the majority of the AC current will be sourced from
the lower impedance, which in most cases will be the module.
This should be studied carefully in any system design using a
module. In most cases, it should be clear that electrolytic
output capacitors are not necessary to design a stable,
well-bypassed system.
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VTM x
VIN VOUT
+
–DC
ZIN_EQ1
ZIN_EQ2
ZOUT_EQ1
ZOUT_EQ2
Load
VTM®1
RO_1
VTM®2
RO_2
VTM®n
RO_n
ZOUT_EQn
ZIN_EQn
Figure 17 — VTM module array
14.0 CURRENT SHARING
The SAC topology bases its performance on efficient transfer
of energy through a transformer without the need of closed
loop control. For this reason, the transfer characteristic can be
approximated by an ideal transformer with some resistive drop
and positive temperature coefficient.
This type of characteristic is close to the impedance
characteristic of a DC power distribution system, both in
behavior (AC dynamic) and absolute value (DC dynamic).
When connected in an array with the same K factor, the VTM
module will inherently share the load current (typically 5%)
with parallel units according to the equivalent impedance
divider that the system implements from the power source to
the point of load.
Some general recommendations to achieve matched array
impedances:
• Dedicate common copper planes within the PCB
to deliver and return the current to the modules.
• Provide the PCB layout as symmetric as possible.
• Apply same input / output filters (if present) to each unit.
For further details see AN:016 Using BCM® Bus Converters
in High Power Arrays.
15.0 FUSE SELECTION
In order to provide flexibility in configuring power systems
VI Chip®products are not internally fused. Input line fusing
of VI Chip products is recommended at system level to provide
thermal protection in case of catastrophic failure.
The fuse shall be selected by closely matching system
requirements with the following characteristics:
• Current rating
(usually greater than maximum current of VTM module)
• Maximum voltage rating
(usually greater than the maximum possible input voltage)
• Ambient temperature
• Nominal melting I2t
16.0 REVERSE OPERATION
The VTM48EF320T009A00 is capable of reverse operation.
If a voltage is present at the output which satisfies the
condition VOUT > VIN •K at the time the VC voltage is applied,
or after the unit has started, then energy will be transferred
from secondary to primary. The input to output ratio will be
maintained. The VTM48EF320T009A00 will continue to
operate in reverse as long as the input and output are within
the specified limits. The VTM48EF320T009A00 has not been
qualified for continuous operation (>10 ms) in the reverse
direction.
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VTM x
inch
mm
NOTES:
.
DIMENSIONS ARE .
2.
UNLESS OTHERWISE SPECIFIED, TOLERANCES ARE:
.X / [.XX] = +/-0.25 / [.01]; .XX / [.XXX] = +/-0.13 / [.005]
3.
PRODUCT MARKING ON TOP SURFACE
DXF and PDF files are available on vicorpower.com
4
inch
mm .
DIMENSIONS ARE .
2.
UNLESS OTHERWISE SPECIFIED, TOLERANCES ARE:
.X / [.XX] = +/-0.25 / [.01]; .XX / [.XXX] = +/-0.13 / [.005]
3.
PRODUCT MARKING ON TOP SURFACE
DXF and PDF files are available on vicorpower.com
4
17.2 J-LEAD PACKAGE RECOMMENDED LAND PATTERN
mm
(inch)
17.1 J-LEAD PACKAGE MECHANICAL DRAWING
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VTM x
inch
mm
NOTES:
.
DIMENSIONS ARE .
2.
UNLESS OTHERWISE SPECIFIED, TOLERANCES ARE:
.X / [.XX] = +/-0.25 / [.01]; .XX / [.XXX] = +/-0.13 / [.005]
3.
PRODUCT MARKING ON TOP SURFACE
DXF and PDF files are available on vicorpower.com
4
inch
mm .
DIMENSIONS ARE .
2.
UNLESS OTHERWISE SPECIFIED, TOLERANCES ARE:
.X / [.XX] = +/-0.25 / [.01]; .XX / [.XXX] = +/-0.13 / [.005]
3.
PRODUCT MARKING ON TOP SURFACE
DXF and PDF files are available on vicorpower.com
4
17.4 THROUGH-HOLE PACKAGE RECOMMENDED LAND PATTERN
mm
(inch)
17.3 THROUGH-HOLE PACKAGE MECHANICAL DRAWING
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VTM x
Notes:
1. Maintain 3.50 (0.138) Dia. keep-out zone
free of copper, all PCB layers.
2. (A) Minimum recommended pitch is 39.50 (1.555).
This provides 7.00 (0.275) component
edge-to-edge spacing, and 0.50 (0.020)
clearance between Vicor heat sinks.
(B) Minimum recommended pitch is 41.00 (1.614).
This provides 8.50 (0.334) component
edge-to-edge spacing, and 2.00 (0.079)
clearance between Vicor heat sinks.
3. VI Chip® module land pattern shown for reference
only; actual land pattern may differ.
Dimensions from edges of land pattern
to push–pin holes will be the same for
all full-size VI Chip® products.
4. RoHS compliant per CST–0001 latest revision.
(NO GROUNDING CLIPS) (WITH GROUNDING CLIPS)
5. Unless otherwise specified:
Dimensions are mm (inches)
tolerances are:
x.x (x.xx) = ±0.3 (0.01)
x.xx (x.xxx) = ±0.13 (0.005)
6. Plated through holes for grounding clips (33855)
shown for reference, heat sink orientation and
device pitch will dictate final grounding solution.
17.5 RECOMMENDED HEAT SINK PUSH PIN LOCATION
-In
PC
VC
TM
+In
-Out
+Out
-Out
+Out
Bottom View
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
4 3 2 1
A
B
C
D
E
H
J
K
L
M
N
P
R
T
17.6 VTM MODULE PIN CONFIGURATION
Signal Name Pin Designation
+In A1-E1, A2-E2
–In L1-T1, L2-T2
TM H1, H2
VC J1, J2
PC K1, K2
+Out A3-D3, A4-D4, J3-M3, J4-M4
–Out E3-H3, E4-H4, N3-T3, N4-T4
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VTM x
Vicor’s comprehensive line of power solutions includes high density AC-DC and DC-DC modules and
accessory components, fully configurable AC-DC and DC-DC power supplies, and complete custom
power systems.
Information furnished by Vicor is believed to be accurate and reliable. However, no responsibility is assumed by Vicor for its use. Vicor makes no
representations or warranties with respect to the accuracy or completeness of the contents of this publication. Vicor reserves the right to make
changes to any products, specifications, and product descriptions at any time without notice. Information published by Vicor has been checked and
is believed to be accurate at the time it was printed; however, Vicor assumes no responsibility for inaccuracies. Testing and other quality controls are
used to the extent Vicor deems necessary to support Vicor’s product warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
Specifications are subject to change without notice.
Vicor’s Standard Terms and Conditions
All sales are subject to Vicor’s Standard Terms and Conditions of Sale, which are available on Vicor’s webpage or upon request.
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“Express Limited Warranty”). This warranty is extended only to the original Buyer for the period expiring two (2) years after the date of shipment
and is not transferable.
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Vicor will repair or replace defective products in accordance with its own best judgment. For service under this warranty, the buyer must contact
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VICOR’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS
PRIOR WRITTEN APPROVAL OF THE CHIEF EXECUTIVE OFFICER AND GENERAL COUNSEL OF VICOR CORPORATION. As used herein, life support
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when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the
user. A critical component is any component in a life support device or system whose failure to perform can be reasonably expected to cause the
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products described in this data sheet. No license, whether express, implied, or arising by estoppel or otherwise, to any intellectual property rights is
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The products described on this data sheet are protected by the following U.S. Patents Numbers:
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