APRIL 2012
DSC-6450/1
1
©2012 Integrated Device Technology, Inc.
Features
◆128K x 36, 256K x 18 memory configurations
◆◆
◆◆
◆Supports fast access times:
Commercial:
– 6.5ns up to 133MHz clock frequency (TQFP package only)
Commercial and Industrial:
– 7.5ns up to 117MHz clock frequency
– 8.0ns up to 100MHz clock frequency
– 8.5ns up to 87MHz clock frequency
◆LBO input selects interleaved or linear burst mode
◆◆
◆◆
◆Self-timed write cycle with global write control (GW), byte write
enable (BWE), and byte writes (BWx)
◆◆
◆◆
◆3.3V core power supply
◆◆
◆◆
◆Power down controlled by ZZ input
◆◆
◆◆
◆3.3V I/O
◆◆
◆◆
◆Optional - Boundary Scan JTAG Interface (IEEE 1149.1
compliant)
◆◆
◆◆
◆Packaged in a JEDEC Standard 100-pin plastic thin quad
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch ball
grid array
Pin Description Summary
NOTE:
1. BW3 and BW4 are not applicable for the IDT71V3579.
Description
The IDT71V3577/79 are high-speed SRAMs organized as
128K x 36/256K x 18. The IDT71V3577/79 SRAMs contain write, data,
address and control registers. There are no registers in the data output
path (flow-through architecture). Internal logic allows the SRAM to gen-
erate a self-timed write based upon a decision which can be left until the
end of the write cycle.
The burst mode feature offers the highest level of performance to the
system designer, as the IDT71V3577/79 can provide four cycles of data
for a single address presented to the SRAM. An internal burst address
counter accepts the first cycle address from the processor, initiating the
access sequence. The first cycle of output data will flow-through from the
array after a clock-to-data access time delay from the rising clock edge of
the same cycle. If burst mode operation is selected (ADV=LOW), the
subsequent three cycles of output data will be available to the user on the
next three rising clock edges. The order of these three addresses are
defined by the internal burst counter and the LBO input pin.
The IDT71V3577/79 SRAMs utilize IDT’s latest high-performance
CMOS process and are packaged in a JEDEC standard 14mm x 20mm
100-pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid array
(BGA) and a 165 fine pitch ball grid array (fBGA).
A
0
-A
17
Address Inputs Input Synchronous
CE Chip Enab le Input Sy nchro nous
CS
0
, CS
1
Chip Se le cts Input Sy nchrono us
OE Outp ut E nab le Inp ut A sy nchro no us
GW Glo bal Write Enab le Input Sy nchrono us
BWE Byte Write Enable Input Sy nchro nous
BW
1
, BW
2
, BW
3
, BW
4
(1)
Indi vidual Byte Write Se le c ts Input Sy nchrono us
CLK Clock Input N/A
ADV Burst Add ress Adv ance Input Sy nchronous
ADSC Ad dre ss S tatus (Cac he Contro ller) Input Sy nchrono us
ADSP Address Status (Processor) Input Synchronous
LBO Line ar / Interle ave d Burst Ord er Input DC
TMS Test Mode Select Input Synchronous
TDI Test Data Input Input Sy nchrono us
TCK Test Clock Input N/A
TDO Test Data Outp ut Output Sy nchrono us
TRST JTAG Re se t (Optional) Input Asy nc hro nous
ZZ Sleep Mode Input Asynchronous
I/O
0
-I/O
31
, I/O
P1
-I/O
P4
Data Inp ut / Outp ut I/ O Sy nc hro no us
V
DD
, V
DDQ
Co re Power, I/O Power Supp ly N/A
V
SS
Ground Supply N/A
6 450 tb l 01
128K X 36, 256K X 18
3.3V Synchronous SRAMs
3.3V I/O, Flow-Through Outputs
Burst Counter, Single Cycle Deselect
IDT71V3577S
IDT71V3579S
IDT71V3577SA
IDT71V3579SA
6.42
2
IDT71V3577S_79S, IDT71V3577SA_79SA, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges
Pin Definitions(1)
NOTE:
1. All synchronous inputs must meet specified setup and hold times with respect to CLK.
Symbol Pin Function I/O Active Description
A
0
-A
17
Address Inputs I N/A Synchronous Address inputs. The address register is triggered by a combi-nation of the rising edge of CLK
and ADSC Low or ADSP Lo w and CE Low.
ADSC Address Status
(Cache Co ntrolle r) I LOW S y nchronous A ddress Status from Cache Contro l l er. ADSC is an activ e LOW inp ut that is use d to lo ad the
address registers with new addresses.
ADSP Address Status
(Processor) I LOW Synchronous Address Status from Processor. ADSP is an active LOW input that is use d to lo ad the addre ss
registers with new addresses. ADSP is gated by CE.
ADV Burst Address
Advance I LOW Synchronous Address Advance. ADV i s an active LOW inp ut that is use d to advance the internal b urs t co unte r,
co ntrolling burst acc ess after the i nitial address is lo aded. When the input is HIGH the burst counter is not
incremented; that is, there is no address advance.
BWE Byte Write Enable I LOW Synchronous byte write enable gates the byte write inputs BW
1
-BW
4
. If BWE is LOW at the rising edge of CLK
then BWx inputs are passed to the next stage in the circuit. If BWE is HIGH the n the b y te write inp uts are
blocked and only GW can initiate a write cycle.
BW
1
-BW
4
Indi vi d u al B y te
Write Enable s I LOW Sync hrono us by te wri te e nab le s. BW
1
controls I/O
0-7
, I/O
P1
, BW
2
controls I/O
8-15
, I/O
P2
, etc. Any active byte
write causes all outputs to be disabled.
CE Chip Enable I LOW Synchronous chip enab le. CE is used with CS
0
and CS
1
to enab le the IDT71V3577/79. CE also gates ADSP.
CLK Clo c k I N/ A This i s the c lo c k inp ut. A ll timi ng re fe re nce s fo r the d e vice are mad e wi th re s p ec t to this inp ut.
CS
0
Chip Select 0 I HIGH Synchronous active HIGH chip select. CS
0
is used with CE and CS
1
to e nab l e the chip .
CS
1
Chip Select 1 I LOW Synchronous active LOW chip select. CS
1
is used with CE and CS
0
to e nab l e the c hip .
GW Glo bal Write
Enable I LOW Synchronous global write enable. This input will write all four 9-bit data bytes when LOW on the rising edge of
CLK. GW supersedes individual byte write enables.
I/O
0
-I/O
31
I/O
P1
-I/O
P4
Data Input/Output I/O N/A Synchronous data inp ut/output (I/O) pins. The data input path is registered, triggered by the rising edge of
CLK. The data o utput path is flow-through (no output register).
LBO Line ar Burst Ord e r I LOW Async hro nous burst o rder se lectio n input. When LBO is HIGH, the inter-leaved burst sequence is selected.
When LBO is LOW the Linear burst sequence is selected. LBO is a static input and mus t no t c hange state
while the device is operating.
OE Output Enable I LOW Async hrono us output e nable . Whe n OE is LOW the data output drivers are enabled on the I/O pins if the chip
is also selected. When OE is HIGH the I/O pins are in a high-impedance state.
TMS Test ModeSelect I N/A Gives input command for TAP controller. Sampled on rising edge of TDK. This pin has an internal pullup.
TDI Te s t Data Inp ut I N/A Serial input of registers placed between TDI and TDO. Sampled on rising edge of TCK. This pin has an
internal pullup.
TCK Test Clock I N/A Clock input of TAP controller. Each TAP event is clocked. Test inputs are captured on rising edge of TCK,
while test outputs are driven from the falling edge of TCK. This pin has an internal p ullup .
TDO Te s t DataO utp ut O N/ A Serial output of registers placed be tween TDI and TDO. This output is active depending on the state of the
TAP controller.
TRST JTAG Reset
(Optional) ILOW
Op tio nal Asynchro nous J TA G rese t. Can b e us ed to re se t the TAP c ontroll er, b ut no t re quire d. J TAG re se t
occurs automatically at power up and also resets using TMS and TCK per IEEE 1149.1. If not used TRST can
be left floating. This pin has an internal pullup. Only available in BGA package.
ZZ Sleep Mode I HIGH Asynchro nous sleep m od e input. ZZ HIGH will g ate the CLK internally and po wer down the IDT71V3577/79 to
its lowest power consumption level. Data retention is guaranteed in Sleep Mode.This pin has an internal pull
down.
V
DD
Power Supply N/A N/A 3.3V core power supply.
V
DDQ
Power Supply N/A N/A 3.3V I/O Sup ply.
V
SS
Ground N/A N/A Ground.
NC No Connect N/A N/A NC pins are not electrically connected to the device.
6450 tbl 02
6.42
3
IDT71V3577S_79S, IDT71V3577SA_79SA, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges
Functional Block Diagram
A
0-
A
16/17
ADDRESS
REGISTER
CLR
A1*
A0*
17/18
2
17/18
A
2-
A
17
128K x 36/
256K x 18-
BIT
MEMORY
ARRAY
INTERNAL
ADDRESS
A
0
,A
1
BW
4
BW
3
BW
2
BW
1
Byte 1
Write Register
36/18 36/18
ADSP
ADV
CLK
ADSC
CS
0
CS
1
Byte 1
Write Driver
Byte 2
Write Driver
Byte 3
Write Driver
Byte 4
Write Driver
Byte 2
Write Register
Byte 3
Write Register
Byte 4
Write Register
9
9
9
9
GW
CE
BWE
LBO
I/O
0
- I/O
31
I/O
P1
-I/O
P4
OE
DATA INPUT
REGISTER
36/18
OUTPUT
BUFFER
DQ
Enable
Register
OE
Burst
Sequence
CEN
CLK EN
CLK EN
Q1
Q0
2
Burst
Logic
Binary
Counter
6450 drw 01
ZZ
Powerdown
,
JTAG
(SA Version)
TMS
TDI
TCK
TRST
(Optional)
TDO
6.42
4
IDT71V3577S_79S, IDT71V3577SA_79SA, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges
100 Pin TQFP Capacitance
(TA = +25° C, f = 1.0mhz)
Recommended Operating
Temperature Supply Voltage
Absolute Maximum Ratings(1)
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VDD terminals only.
3. VDDQ terminals only.
4. Input terminals only.
5. I/O terminals only.
6 . This is a steady-state DC parameter that applies after the power supplies have
ramped up. Power supply sequencing is not necessary; however, the voltage
on any input or I/O pin cannot exceed VDDQ during power supply ramp up.
7. TA is the "instant on" case temperature.
Recommended DC Operating
Conditions
NOTES:
1. VIH (max) = VDDQ + 1.0V for pulse width less than tCYC/2, once per cycle.
2. VIL (min) = -1.0V for pulse width less than tCYC/2, once per cycle.
NOTE:
1. This parameter is guaranteed by device characterization, but not production tested.
Symbol Rating Commercial &
Industrial Values Unit
V
TERM
(2)
Terminal Voltage with
Re s p e c t to GND -0.5 to +4.6 V
V
TERM
(3,6)
Terminal Voltage with
Re s p e c t to GND -0.5 to V
DD
V
V
TERM
(4,6)
Terminal Voltage with
Re s p e c t to GND -0. 5 to V
DD
+0.5 V
V
TERM
(5,6)
Terminal Voltage with
Re s p e c t to GND -0.5 to V
DDQ
+0.5 V
T
A
(7)
Commercial
Operating Temperature -0 to +70
o
C
Industrial
Operating Temperature -40 to +85
o
C
T
BIAS
Temperature
Under Bias -55 to +125
o
C
T
STG
Storage
Temperature -55 to +125
o
C
P
T
Power Dissipatio n 2.0 W
I
OUT
DC Outp ut Curre nt 50 mA
6 450 t bl 03
Grade Temperature
(1)
V
SS
V
DD
V
DDQ
Commercial 0° C to +70° C 0V 3.3V± 5% 3.3V± 5%
Ind ustri al -40° C to +85° C 0V 3. 3V± 5% 3.3V±5%
6 450 t bl 04
Symbol Parameter Min. Typ. Max. Uni
t
V
DD
Core Sup p ly Voltag e 3. 135 3.3 3.465 V
V
DDQ
I/O Supply Vo ltage 3.135 3.3 3.465 V
V
SS
Supply Voltage 0 0 0 V
V
IH
Inp ut Hig h Vo ltag e - Inp uts 2. 0
____
V
DD
+0.3 V
V
IH
Input High Voltage - I/O 2.0
____
V
DDQ
+0.3
(1)
V
V
IL
Inp ut Lo w Vo ltag e -0. 3
(2)
____
0.8 V
6450 tbl 06
Symbol Parameter
(1)
Conditions Max. Unit
C
IN
Inp ut Cap ac itance V
IN
= 3dV 5 pF
C
I/O
I/O Capac itanc e V
OUT
= 3dV 7 pF
6450 tb l 07
NOTES:
1. TA is the "instant on" case temperature.
119 BGA Capacitance
(TA = +25° C, f = 1.0mhz)
Symbol Parameter
(1)
Conditions Max. Unit
C
IN
Inp ut Cap ac itanc e V
IN
= 3dV 7 pF
C
I/O
I/O Capacitance V
OUT
= 3dV 7 pF
6450 t bl 07a
165 fBGA Capacitance
(TA = +25° C, f = 1.0mhz)
Symbol Parameter
(1)
Conditions Max. Unit
C
IN
Inp ut Cap ac itance V
IN
= 3dV 7 pF
C
I/O
I/O Capac itanc e V
OUT
= 3dV 7 pF
6450 tbl 07b
6.42
5
IDT71V3577S_79S, IDT71V3577SA_79SA, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges
Pin Configuration – 128K x 36
100 TQFP
Top View
NOTES:
1. Pin 14 does not have to be directly connected to VSS as long as the input voltage is < VIL.
2. Pin 64 can be left unconnected and the device will always remain in active mode.
10099989796959493929190 8786858483828189 88
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
A
6
A
7
CE
CS
0
BW
4
BW
3
BW
2
BW
1
CS
1
V
DD
V
SS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
8
A
9
NC
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A
16
NC
LBO
A
14
A
13
A
12
A
11
A
10
V
DD
V
SS
A
0
A
1
A
2
A
3
A
4
A
5
I/O
P4
I/O
31
I/O
30
V
DDQ
V
SS
I/O
29
I/O
28
I/O
27
I/O
26
V
SS
V
DDQ
I/O
25
I/O
24
V
SS
(1)
V
DD
I/O
23
I/O
22
V
DDQ
V
SS
I/O
21
I/O
20
I/O
19
I/O
18
V
SS
V
DDQ
I/O
17
I/O
16
I/O
P3 80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
I/O
P2
I/O
14
V
DDQ
V
SS
I/O
13
I/O
12
I/O
11
I/O
10
V
SS
V
DDQ
I/O
9
I/O
8
V
SS
NC
V
DD
ZZ
(2)
I/O
7
I/O
6
V
DDQ
V
SS
I/O
5
I/O
4
I/O
3
I/O
2
V
SS
V
DDQ
I/O
1
I/O
0
I/O
P1
V
SS
I/O
15
A
15
6450 drw 02a
,
NC
NC
NC
6.42
6
IDT71V3577S_79S, IDT71V3577SA_79SA, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges
Pin Configuration – 256K x 18
100 TQFP
Top View
NOTES:
1. Pin 14 does not have to be directly connected to VSS as long as the input voltage is < VIL.
2. Pin 64 can be left unconnected and the device will always remain in active mode.
10099989796959493929190 8786858483828189 88
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
A
6
A
7
CE
CS
0
NC
NC
BW
2
BW
1
CS
1
V
DD
V
SS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
8
A
9
NC
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A
17
NC
NC
LBO
A
15
A
14
A
13
A
12
A
11
V
DD
V
SS
A
0
A
1
A
2
A
3
A
4
A
5
NC
NC
NC
V
DDQ
V
SS
NC
I/O
P2
I/O
15
I/O
14
V
SS
V
DDQ
I/O
13
I/O
12
V
SS
V
DD
I/O
11
I/O
10
V
DDQ
V
SS
I/O
9
I/O
8
NC
NC
V
SS
V
DDQ
NC
NC
NC
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A
10
NC
V
DDQ
V
SS
NC
I/O
P1
I/O
7
I/O
6
V
SS
V
DDQ
I/O
5
I/O
4
V
SS
NC
V
DD
ZZ
(2)
I/O
3
I/O
2
V
DDQ
V
SS
I/O
1
I/O
0
NC
NC
V
SS
V
DDQ
NC
NC
NC
V
SS
(1)
NC
A
16
6450 drw 02b
,
NC
NC
6.42
7
IDT71V3577S_79S, IDT71V3577SA_79SA, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges
1234567
AV
DDQ
A
6
A
4
ADSP A
8
A
16
V
DDQ
BNC CS
0
A
3
ADSC A
9
CS
1
NC
CA
7
A
2
V
DD
A
13
A
17
NC
DI/O
8
NC V
SS
NC V
SS
I/O
P1
NC
ENC I/O
9
V
SS
CE V
SS
NC I/O
7
FV
DDQ
NC V
SS
OE V
SS
I/O
6
V
DDQ
GNC I/O
10
ADVBW
2
NC I/O
5
HI/O
11
NC V
SS
GW V
SS
I/O
4
NC
JV
DDQ
V
DD
NC V
DD
NC V
DD
V
DDQ
KNC I/O
12
V
SS
CLK V
SS
NC I/O
3
LI/O
13
NC NC BW
1
I/O
2
NC
MV
DDQ
I/O
14
V
SS
BWE V
SS
NC V
DDQ
NI/O
15
NC V
SS
A
1
V
SS
I/O
0
NC
PNC I/O
P2
V
SS
A
0
V
SS
NC I/O
1
RNC A
5
LBO V
DD
NCA
12
V
SS
TNC A
10
A
15
NC A
14
A
11
ZZ
(3)
UV
DDQ
V
DDQ
6450 drw 02d
NC
V
SS
V
SS
,
NC/TMS
(2)
NC/TDI
(2)
NC/TCK
(2)
NC/TDO
(2)
NC/TRST
(2,4)
Pin Configuration – 256K x 18, 119 BGA
Pin Configuration – 128K x 36, 119 BGA
Top View
Top View
NOTES:
1. R5 does not have to be directly connected to VSS as long as the input voltage is < VIL.
2. These pins are NC for the "S" version or the JTAG signal listed for the "SA" version. Note: If NC, these pins can either be tied to VSS, VDD or left floating.
3. T7 can be left unconnected and the device will always remain in active mode.
4. TRST is offered as an optional JTAG Reset if required in the application. If not needed, can be left floating and will internally be pulled to VDD.
1234567
AV
DDQ
A
6
A
4
ADSP A
8
A
16
V
DDQ
BNC CS
0
A
3
ADSC A
9
CS
1
NC
CA
7
A
2
V
DD
A
12
A
15
NC
DI/O
16
I/O
P3
V
SS
NC V
SS
I/O
P2
I/O
15
EI/O
17
I/O
18
V
SS
CE V
SS
I/O
13
I/O
14
FV
DDQ
I/O
19
V
SS
OE V
SS
I/O
12
V
DDQ
GI/O
20
I/O
21
BW
3
ADV BW
2
I/O
11
I/O
10
HI/O
22
I/O
23
V
SS
GW V
SS
I/O
9
I/O
8
JV
DDQ
V
DD
NC V
DD
NC V
DD
V
DDQ
KI/O
24
I/O
26
V
SS
CLK V
SS
I/O
6
I/O
7
LI/O
25
I/O
27
BW
4
NC BW
1
I/O
4
I/O
5
MV
DDQ
I/O
28
V
SS
BWE V
SS
I/O
3
V
DDQ
NI/O
29
I/O
30
V
SS
A
1
V
SS
I/O
2
I/O
1
PI/O
31
I/O
P4
V
SS
A
0
V
SS
I/O
0
I/O
P1
RNC A
5
LBO V
DD
NCA
13
TNC NC A
10
A
11
A
14
NC ZZ
(3)
UV
DDQ
V
DDQ
NC
V
SS
6450 drw 02c
NC/TMS
(2)
NC/TDI
(2)
NC/TCK
(2)
NC/TDO
(2)
NC/TRST
(2,4)
6.42
8
IDT71V3577S_79S, IDT71V3577SA_79SA, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges
Pin Configuration – 256K x 18, 165 fBGA
Pin Configuration – 128K x 36, 165 fBGA
NOTES:
1. H1 does not have to be directly VSS as long as input voltage is < VIL
2. These pins are NC for the "S" version or the JTAG signal listed for the "SA" version. Note: If NC, these pins can either be tied to VSS, VDD or left floating.
3. H11 can be left unconnected and the device will always remain in active mode.
4. Pins P11, N6, B11, A1, R2 and P2 are reserved for 9M, 18M, 36M, 72M, 144M and 288M respectively.
5. TRST is offered as an optional JTAG Reset if required in the application. If not needed, can be left floating and will internally be pulled to VDD.
1234567891011
ANC
(4)
A
7
CE
1
BW
3
BW
2
CS
1
BWE ADSC ADV A
8
NC
BNC A
6
CS
0
BW
4
BW
1
CLK GW OE ADSP A
9
NC
(4)
CI/O
P3
NC V
DDQ
V
SS
V
SS
V
SS
V
SS
V
SS
V
DDQ
NC I/O
P2
DI/O
17
I/O
16
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
I/O
15
I/O
14
EI/O
19
I/O
18
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
I/O
13
I/O
12
FI/O
21
I/O
20
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
I/O
11
I/O
10
GI/O
23
I/O
22
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
I/O
9
I/O
8
HV
SS
(1)
NC NC V
DD
V
SS
V
SS
V
SS
V
DD
NC NC ZZ
(3)
JI/O
25
I/O
24
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
I/O
7
I/O
6
KI/O
27
I/O
26
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
I/O
5
I/O
4
LI/O
29
I/O
28
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
I/O
3
I/O
2
MI/O
31
I/O
30
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
I/O
1
I/O
0
NI/O
P4
NC V
DDQ
V
SS NC/TRST
(2,5)
NC
(4)
NC V
SS
V
DDQ
NC I/O
P1
PNCNC
(4)
A
5
A
2
NC/TDI
(2)
A
1
NC/TDO
(2)
A
10
A
13
A
14
NC
(4)
RLBO NC
(4)
A
4
A
3
NC/TMS
(2)
A
0
NC/TCK
(2)
A
11
A
12
A
15
A
16
6450 tb l 17
1234567891011
ANC
(4)
A
7
CE
1
BW
2
NC CS
1
BWE ADSC ADV A
8
A
10
BNC A
6
CS
0
NC BW
1
CLK GW OE ADSP A
9
NC
(4)
CNC NCV
DDQ
V
SS
V
SS
V
SS
V
SS
V
SS
V
DDQ
NC I/O
P1
DNC I/O
8
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
NC I/O
7
ENC I/O
9
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
NC I/O
6
FNCI/O
10
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
NC I/O
5
GNC I/O
11
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
NC I/O
4
HV
SS
(1)
NC NC V
DD
V
SS
V
SS
V
SS
V
DD
NC NC ZZ
(3)
JI/O
12
NC V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
I/O
3
NC
KI/O
13
NC V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
I/O
2
NC
LI/O
14
NC V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
I/O
1
NC
MI/O
15
NC V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
I/O
0
NC
NI/O
P2
NC V
DDQ
V
SS NC/TRST
(2,5)
NC
(4)
NC V
SS
V
DDQ
NC NC
PNC NC
(4)
A
5
A
2
NC/TDI
(2)
A
1
NC/TDO
(2)
A
11
A
14
A
15
NC
(4)
RLBO NC
(4)
A
4
A
3
NC/TMS
(2)
A
0
NC/TCK
(2)
A
12
A
13
A
16
A
17
6450 tb l 17a
6.42
9
IDT71V3577S_79S, IDT71V3577SA_79SA, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (1)
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VDD = 3.3V ± 5%)
Figure 2. Lumped Capacitive Load, Typical Derating
Figure 1. AC Test Load
AC Test LoadAC Test Conditions
(VDDQ = 3.3V)
NOTE:
1. The LBO, TMS, TDI, TCK and TRST pins will be internally pulled to VDD and the ZZ in will be internally pulled to VSS if they are not actively driven in the application.
NOTES:
1. All values are maximum guaranteed values.
2. At f = fMAX, inputs are cycling at the maximum frequency of read cycles of 1/tCYC while ADSC = LOW; f=0 means no input lines are changing.
3. For I/Os VHD = VDDQ - 0.2V, VLD = 0.2V. For other inputs VHD = VDD - 0.2V, VLD = 0.2V.
V
DDQ
/2
50Ω
I/O Z
0
=50Ω
6450 drw 03
,
Symbol Parameter Test Conditions Min. Max. Unit
|I
LI
| Input Leakage Curre nt V
DD
= Max., V
IN
= 0V to V
DD
___
5µA
|I
LI
|ZZ , LBO and JTAG Input Leakage Current
(1)
V
DD
= Max., V
IN
= 0V to V
DD
___
30 µA
|I
LO
| Output Le akage Current V
OUT
= 0V to V
DDQ
, Device Deselected
___
5µA
V
OL
Output Lo w Vo ltag e I
OL
= +8mA, V
DD
= Min.
___
0.4 V
V
OH
Output Hig h Vo ltag e I
OH
= -8mA, V
DD
= Min. 2.4
___
V
6450 t bl 08
Symbol Parameter Test Conditions
6.5ns 7.5ns 8ns 8.5ns
UnitCom'l Only Com'l Ind Com'l Ind Com'l Ind
I
DD
Operating Powe r Sup ply Curre nt Device Selected, Outputs Open, V
DD
= Max.,
V
DDQ
= Max., V
IN
> V
IH
or < V
IL
, f = f
MAX
(2)
300 255 265 200 210 180 190 mA
I
SB1
CMOS Standby Power
S up p ly Current Device De selected, Outputs Open, V
DD
= Max.,
V
DDQ
= Max., V
IN
> V
HD
or < V
LD
, f = 0
(2,3)
30 30 35 30 35 30 35 mA
I
SB2
Clock Running Power
S up p ly Current Device De selected, Outputs Open, V
DD
= Max.,
V
DDQ
= Max., V
IN
> V
HD
or < V
LD
, f = f
MAX
(2,.3)
110 90 100 85 95 80 90 mA
I
ZZ
Full Sle ep Mo de S up ply Curre nt ZZ > V
HD,
V
DD
= Max . 30 30 35 30 35 30 35 mA
6450 tb l 09a
Inp ut P uls e Le v e ls
Inp ut Ri se / Fall Ti me s
Inp ut Timi ng Re fe re nc e Le ve ls
Outp ut Timing Re fe re nce Le ve ls
AC Te s t Lo ad
0 to 3V
2ns
1.5V
1.5V
See Figure 1
6 450 t bl 10
1
2
3
4
20 30 50 100 200
∆tCD
(Typical, ns)
Capacitance (pF)
80
5
6
6450 drw 05
,
6.42
10
IDT71V3577S_79S, IDT71V3577SA_79SA, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges
Synchronous Truth Table (1,3)
NOTES:
1 . L = VIL, H = VIH, X = Don’t Care.
2. OE is an asynchronous input.
3. ZZ - low for the table.
Operation Address
Used
CE CS0CS1ADSP ADSC ADV GW BWE BWxOE
(2)
CLK I/O
Deselected Cycle, Power Down None HXXX LXXXXX↑HI-Z
Deselected Cycle, Power Down None L XHL XXXXXX↑HI-Z
Deselected Cycle, Power Down None LLX L XXXXXX↑HI-Z
Deselected Cycle, Power Down None L XH X LXXXXX↑HI-Z
Deselected Cycle, Power Down None LLXX LXXXXX↑HI-Z
Read Cycle, Begin Burst ExternalL HL L XXXXX L↑DOUT
Read Cycle, Begin Burst ExternalL HL L XXXXXH↑HI-Z
Read Cycle, Begin Burst External L H L H L X H H X L ↑DOUT
Read Cycle, Begin Burst External L H L H L X H L H L ↑DOUT
Read Cycle, Begin Burst External L H L H L X H L H H ↑HI-Z
Write Cycle, Begin Burst External L H L H L X H L L X ↑DIN
Write Cycle, Begin Burst External L H L H L X L X X X ↑DIN
Re ad Cy cl e , Co ntinue B urs t Ne x t X X X H H L H H X L ↑DOUT
Re ad Cy cl e , Co ntinue B urs t Ne x t X X X H H L H H X H ↑HI-Z
Re ad Cy cl e , Co ntinue B urs t Ne x t X X X H H L H X H L ↑DOUT
Re ad Cy cl e , Co ntinue B urs t Ne x t X X X H H L H X H H ↑HI-Z
Re ad Cy cl e , Co ntinue B urs t Ne x t H X X X H L H H X L ↑DOUT
Re ad Cy cl e , Co ntinue B urs t Ne x t H X X X H L H H X H ↑HI-Z
Re ad Cy cl e , Co ntinue B urs t Ne x t H X X X H L H X H L ↑DOUT
Re ad Cy cl e , Co ntinue B urs t Ne x t H X X X H L H X H H ↑HI-Z
Write Cycle, Continue Burst Next X X X H H L H L L X ↑DIN
Write Cycle, Continue Burst Next X X X H H L L X X X ↑DIN
Write Cycle, Continue Burst Next H X X X H L H L L X ↑DIN
Write Cycle, Continue Burst Next H X X X H L L X X X ↑DIN
Read Cycle, Suspend Burst Current X X X H H H H H X L ↑DOUT
Read Cycle, Suspend Burst Current X X X H H H H H X H ↑HI-Z
Read Cycle, Suspend Burst Current X X X H H H H X H L ↑DOUT
Read Cycle, Suspend Burst Current X X X H H H H X H H ↑HI-Z
Read Cycle, Suspend Burst Current H X X X H H H H X L ↑DOUT
Read Cycle, Suspend Burst Current H X X X H H H H X H ↑HI-Z
Read Cycle, Suspend Burst Current H X X X H H H X H L ↑DOUT
Read Cycle, Suspend Burst Current H X X X H H H X H H ↑HI-Z
Write Cycle, Suspend Burst Current X X X H H H H L L X ↑DIN
Write Cycle, Suspend Burst Current X X X H H H L X X X ↑DIN
Write Cycle, Suspend Burst Current H X X X H H H L L X ↑DIN
Write Cycle, Suspend Burst Current H X X X H H L X X X ↑DIN
6450 tbl 11
6.42
11
IDT71V3577S_79S, IDT71V3577SA_79SA, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges
Linear Burst Sequence Table ( LBO=VSS)
Synchronous Write Function Truth Table (1, 2)
Asynchronous Truth Table (1)
Interleaved Burst Sequence Table ( LBO=VDD)
NOTES:
1 . L = VIL, H = VIH, X = Don’t Care.
2. BW3 and BW4 are not applicable for the IDT71V3579.
3. Multiple bytes may be selected during the same cycle.
NOTES:
1 . L = VIL, H = VIH, X = Don’t Care.
2. Synchronous function pins must be biased appropriately to satisfy operation requirements.
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state.
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state.
Operation GW BWE BW
1
BW
2
BW
3
BW
4
Read HHXXXX
Read HLHHHH
Write all Bytes L XXXXX
Write all Bytes HLLLLL
Write B yte 1
(3)
HLLHHH
Write B yte 2
(3)
HLHLHH
Write B yte 3
(3)
HLHHLH
Write B yte 4
(3)
HLHHHL
6450 tbl 12
Operation
(2)
OE ZZ I/O Status Power
Re ad L L Data Out Ac tiv e
Read H L High-Z Active
Wri te X L Hi g h-Z – Data In A cti v e
Deselected X L High-Z Standby
Sleep Mode X H High-Z Sleep
6450 tbl 13
Seq uence 1 Sequence 2 Sequence 3 Sequence 4
A1 A0 A1 A0 A1 A0 A1 A0
First Address 0 0 0 1 1 0 1 1
Second Address 0 1 0 0 1 1 1 0
Third Address 1 0 1 1 0 0 0 1
Fourth Address
(1)
11100100
6450 tbl 14
Seq uence 1 Sequence 2 Sequence 3 Seq uence 4
A1 A0 A1 A0 A1 A0 A1 A0
First Address 0 0 0 1 1 0 1 1
Second Address 0 1 1 0 1 1 0 0
Third Address 1 0 1 1 0 0 0 1
Fourth Address
(1)
11000110
6450 tbl 15
6.42
12
IDT71V3577S_79S, IDT71V3577SA_79SA, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges
AC Electrical Characteristics
(VDD = 3.3V ±5%, Commercial and Industrial Temperature Ranges)
6.5ns
(5)
7.5ns 8ns 8.5ns
Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Unit
Cl ock P aram eter
t
CYC
Clock Cycle Time 7.5
____
8.5
____
10
____
11.5
____
ns
t
CH
(1)
Clo c k Hi g h Pulse Wid th 2. 5
____
3
____
4
____
4.5
____
ns
t
CL
(1)
Clo c k Low P uls e Wid th 2. 5
____
3
____
4
____
4.5
____
ns
Outpu t Parameters
t
CD
Clo c k Hi g h to Val id Data
____
6.5
____
7.5
____
8
____
8.5 ns
t
CDC
Clock High to Data Change 2
____
2
____
2
____
2
____
ns
t
CLZ
(2)
Cl o c k Hig h to Outp u t Ac tiv e 0
____
0
____
0
____
0
____
ns
t
CHZ
(2)
Clo ck Hig h to Data Hi gh-Z 2 3. 5 2 3. 5 2 3. 5 2 3. 5 ns
t
OE
Output Enable Access Time
____
3.5
____
3.5
____
3.5
____
3.5 ns
t
OLZ
(2)
Outp ut E nab le Lo w to Output Ac tiv e 0
____
0
____
0
____
0
____
ns
t
OHZ
(2)
Outp ut E na b le Hi g h to Outp ut Hig h-Z
____
3.5
____
3.5
____
3.5
____
3.5 ns
Set Up Times
t
SA
Address Setup Time 1.5
____
1.5
____
2
____
2
____
ns
t
SS
Address Status Setup Time 1.5
____
1.5
____
2
____
2
____
ns
t
SD
Data In Se tup Time 1. 5
____
1.5
____
2
____
2
____
ns
t
SW
Write Setup Time 1.5
____
1.5
____
2
____
2
____
ns
t
SAV
Address Ad vance Setup Time 1.5
____
1.5
____
2
____
2
____
ns
t
SC
Chip E nable /Se le ct Se tup Time 1.5
____
1.5
____
2
____
2
____
ns
Hol d Ti m es
t
HA
Address Hold Time 0.5
____
0.5
____
0.5
____
0.5
____
ns
t
HS
Address Status Hold Time 0.5
____
0.5
____
0.5
____
0.5
____
ns
t
HD
Data In Ho l d Tim e 0. 5
____
0.5
____
0.5
____
0.5
____
ns
t
HW
Write Ho ld Tim e 0.5
____
0.5
____
0.5
____
0.5
____
ns
t
HAV
Address Advance Hold Time 0.5
____
0.5
____
0.5
____
0.5
____
ns
t
HC
Chip E nable /Se le ct Hold Time 0.5
____
0.5
____
0.5
____
0.5
____
ns
Sl eep Mode and Configuration Parameters
t
ZZPW
ZZ Pu l se W i dt h 1 0 0
____
100
____
100
____
100
____
ns
t
ZZR
(3)
ZZ Reco very Time 100
____
100
____
100
____
100
____
ns
t
CFG
(4)
Config uratio n Se t-up Time 30
____
34
____
40
____
50
____
ns
6450 tb l 16
NOTES:
1. Measured as HIGH above VIH and LOW below VIL.
2. Transition is measured ±200mV from steady-state.
3. Device must be deselected when powered-up from sleep mode.
4. tCFG is the minimum time required to configure the device based on the LBO input. LBO is a static input and must not change during normal operation.
5. 6.5ns speed only available in TQFP package and in commercial temp range.
6.42
13
IDT71V3577S_79S, IDT71V3577SA_79SA, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges
NOTES:
1. O1 (Ax) represents the first output from the external address Ax. O1 (Ay) represents the first output from the external address Ay; O2 (Ay) represents the next output data in the burst sequence
of the base address Ay, etc. where A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input.
2. ZZ input is LOW and LBO is Don't Care for this cycle.
3. CS0 timing transitions are identical but inverted to the CE and CS1 signals. For example, when CE and CS1 are LOW on this waveform, CS0 is HIGH.
Timing Waveform of Flow-Through Read Cycle (1,2)
t
CHZ
t
SA
t
SC
t
HS
G
W,BWE,BWx
t
SW
t
CL
t
SAV
t
HW
t
HAV
CLK
ADSP
ADSC
(1)
ADDRESS
t
CYC
t
CH
t
HA
t
HC
t
OE
t
OHZ
OEt
CD
t
OLZ
O1(Ax)
DATA
OUT
t
CDC
O1(Ay)O2(Ay)
O2(Ay)
ADV
CE,CS
1
(Note3)
Flow-through
Read
BurstFlow-throughRead
Output
Disabled
AxAy
t
SS
O1(Ay)
O4(Ay)
O3(Ay)
(Burstwrapsaround
toitsinitialstate)
6450drw06
ADVHIGHsuspendsburst
,
6.42
14
IDT71V3577S_79S, IDT71V3577SA_79SA, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges
O1(Az)
CLK
ADSP
ADDRESS
GW
ADV
OE
DATA
OUT
t
CYC
t
CH
t
CL
t
HA
t
SW
t
HW
t
CLZ
AxAyAz
t
HS
I1(Ay)
t
SD
t
HD
t
OLZ
t
CD
t
CDC
DATA
IN
(2)
t
OE
O1(Az)
SingleReadFlow-throughBurstRead
Write
t
OHZ
t
SS
t
SA
O3(Az)
O2(Az)O4(Az)
O1(Ax)
6450drw07
t
CD
,
NOTES:
1. Device is selected through entire cycle; CE and CS1 are LOW, CS0 is HIGH.
2. ZZ input is LOW and LBO is Don't Care for this cycle.
3. O1 (Ax) represents the first output from the external address Ax. I1 (Ay) represents the first input from the external address Ay; O1 (Az) represents the first output from the external address Az; O2 (Az) represents
the next output data in the burst sequence of the base address Az, etc. where A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input.
Timing Waveform of Combined Flow-Through Read and Write Cycles (1,2,3)
6.42
15
IDT71V3577S_79S, IDT71V3577SA_79SA, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges
Timing Wa v eform of Write Cyc le No. 1 - GW Controlled (1,2,3)
A
DDRESS
CLK
ADSP
ADSC
t
CYC
t
SS
t
HS
t
CH
t
CL
t
HA
t
SA
AxAyAz
ADV
DATA
OUT
OE
t
HC
t
SD
I1(Ax)I1(Az)
I2(Ay)
tHD
t
OHZ
DATA
IN
t
HAV
O4(Aw)
CE,CS
1
t
HW
GW
t
SW
(Note3)
I2(Az)I3(Az)
I4(Ay)
I3(Ay)
I2(Ay)
t
SAV
(ADVsuspendsburst)
I1(Ay)
t
SC
(1)
(2)
O3(Aw)
6450drw08
GWisignoredwhenADSPinitiatesacycleandissampledonthenextcyclerisingedge
,
NOTES:
1. ZZ input is LOW, BWE is HIGH and LBO is Don't Care for this cycle.
2. O4 (Aw) represents the final output data in the burst sequence of the base address Aw. I1 (Ax) represents the first input from the external address Ax. I1 (Ay) represents the first input from the external
address Ay; I2 (Ay) represents the next input data in the burst sequence of the base address Ay, etc. where A0 and A1 are advancing for the four word burst in the sequence defined by the state of the
LBO input. In the case of input I2 (Ay) this data is valid for two cycles because ADV is high and has suspended the burst.
3. CS0 timing transitions are identical but inverted to the CE and CS1 signals. For example, when CE and CS1 are LOW on this waveform, CS0 is HIGH.
6.42
16
IDT71V3577S_79S, IDT71V3577SA_79SA, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges
Timing Wa v eform of Write Cyc le No. 2 - Byte Controlled (1,2,3)
A
DDRESS
CLK
ADSP
ADSC
t
CYC
t
SS
t
HS
t
CH
t
CL
t
HA
t
SA
AxAy
t
HW
BWx
ADV
DATA
OUT
OE
t
HC
t
SD
Single
WriteBurstWrite
I1(Ax)I2(Ay)I2(Ay)I2(Az)
tHD
Burst
ReadExtended
BurstWrite
t
OHZ
DATA
IN
t
SAV
t
SW
O4(Aw)
CE,CS
1
t
HW
BWE
t
SW
(Note3)
I1(Az)
Az
I4(Ay)
I1(Ay)I4(Ay)
I3(Ay)
t
SC
BWEisignoredwhenADSPinitiatesacycleandissampledonthenextcyclerisingedge
BWxisignoredwhenADSPinitiatesacycleandissampledonthenextclockrisingedge
I3(Az)
O3(Aw)
6450drw09
(ADVHIGHsuspendsburst)
,
NOTES:
1. ZZ input is LOW, GW is HIGH and LBO is Don't Care for this cycle.
2. O4 (Aw) represents the final output data in the burst sequence of the base address Aw. I1 (Ax) represents the first input from the external address Ax. I1 (Ay) represents the first input from the external
address Ay; I2 (Ay) represents the next input data in the burst sequence of the base address Ay, etc. where A0 and A1 are advancing for the four word burst in the sequence defined by the state of the
LBO input. In the case of input I2 (Ay) this data is valid for two cycles because ADV is high and has suspended the burst.
3. CS0 timing transitions are identical but inverted to the CE and CS1 signals. For example, when CE and CS1 are LOW on this waveform, CS0 is HIGH.
6.42
17
IDT71V3577S_79S, IDT71V3577SA_79SA, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges
t
CYC
t
SS
t
CL
t
CH
t
HA
t
SA
t
SC
t
HC
t
OE
t
OLZ
t
HS
CLK
ADSP
ADSC
A
DDRESS
GW
CE,CS
1
ADV
DATA
OUT
OE
ZZ
SingleReadSnoozeMode
tZZPW
6450drw13
O1(Ax)
Ax
(Note4)
tZZR
Az
,
NOTES:
1. Device must power up in deselected Mode.
2. LBO is Don't Care for this cycle.
3. It is not necessary to retain the state of the input registers throughout the Power-down cycle.
4. CS0 timing transitions are identical but inverted to the CE and CS1 signaals. For example, when CE and CS1 are LOW on this waveform, CS0 is HIGH.
Timing Waveform of Sleep (ZZ) and Power-Down Modes (1,2,3)
6.42
18
IDT71V3577S_79S, IDT71V3577SA_79SA, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges
NOTES:
1. ZZ input is LOW, ADV is HIGH and LBO is Don't Care for this cycle.
2. (Ax) represents the data for address Ax, etc.
3. For read cycles, ADSP and ADSC function identically and are therefore interchangable.
Non-Burst Read Cycle Timing Waveform
CLK
ADSP
GW,BWE,BWx
CE,CS
1
CS
0
ADDRESS
ADSC
DATA
OUT
OE
Av Aw Ax Ay Az
(Av) (Aw) (Ax) (Ay)
6450 drw 10
,
Non-Burst Write Cycle Timing Waveform
CLK
ADSP
GW
CE,CS
1
CS
0
ADDRESS
ADSC
DATA
IN
Av Aw Ax AzAy
(Av) (Aw) (Ax) (Az)(Ay)
6450 drw 11
,
NOTES:
1. ZZ input is LOW, ADV and OE are HIGH, and LBO is Don't Care for this cycle.
2. (Ax) represents the data for address Ax, etc.
3. Although only GW writes are shown, the functionality of BWE and BWx together is the same as GW.
4. For write cycles, ADSP and ADSC have different limitations.
6.42
19
IDT71V3577S_79S, IDT71V3577SA_79SA, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges
JTAG Interface Specification (SA Version only)
TCK
Device Inputs
(1)
/
TDI/TMS
Device Outputs
(2)
/
TDO
TRST
(3)
t
JCD
t
JDC
t
JRST
t
JS
t
JH
t
JCYC
t
JRSR
t
JF
t
JCL
t
JR
t
JCH
M6450 drw 01
x
Symbol Parameter Min. Max. Units
t
JCYC
JTAG Clock Input Period 100
____
ns
t
JCH
JTAG Clock HIGH 40
____
ns
t
JCL
JTAG Clock Low 40
____
ns
t
JR
JTAG Clock Rise Time
____
5
(1)
ns
t
JF
JTAG Clock Fall Time
____
5
(1)
ns
t
JRST
JTAG Reset 50
____
ns
t
JRSR
JTAG Reset Recovery 50
____
ns
t
JCD
J TAG Data O utp ut
____
20 ns
t
JDC
J TA G Data Outp ut Ho ld 0
____
ns
t
JS
JTAG Setup 25
____
ns
t
JH
JTAG Hold 25
____
ns
I6450 tbl 01
Regi ster Name Bi t Si ze
Instruc tio n (IR) 4
Bypass (BYR) 1
J TAG Id e ntific atio n (J IDR) 32
Boundary Scan (BSR) Note (1)
I6 4 50 tbl 03
NOTES:
1. Device inputs = All device inputs except TDI, TMS and TRST.
2. Device outputs = All device outputs except TDO.
3. During power up, TRST could be driven low or not be used since the JTAG circuit resets automatically. TRST is an optional JTAG reset.
NOTE:
1. The Boundary Scan Descriptive Language (BSDL) file for this device is available
by contacting your local IDT sales representative.
JT AG AC Electrical
Characteristics(1,2,3,4)
Scan Register Sizes
NOTES:
1. Guaranteed by design.
2. AC Test Load (Fig. 1) on external output signals.
3. Refer to AC Test Conditions stated earlier in this document.
4. JTAG operations occur at one speed (10MHz). The base device may run at any speed specified in this datasheet.
6.42
20
IDT71V3577S_79S, IDT71V3577SA_79SA, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges
NOTES:
1. Device outputs = All device outputs except TDO.
2. Device inputs = All device inputs except TDI, TMS, and TRST.
Instruction Field Value Description
Revision Number (31:28) 0x2 Reserved for version number.
IDT De vic e ID (27:12) 0x 22C, 0x22E De fine s IDT p art numb e r 71V 3577YSA and 71V 3579YSA, re sp e ctiv ely.
IDT JEDEC ID (11:1) 0x33 Allows unique identification of device vendor as IDT.
ID Register Indicator Bit (Bit 0) 1 Indicates the presenc e of an ID register.
I6 4 50 tb l 02
JTAG Identification Register Definitions (SA Version only)
Instruction Description OPCODE
EXTEST Forces contents of the bound ary scan cells onto the device outputs
(1)
.
Places the boundary scan register (BSR) between TDI and TDO. 0000
SAMPLE/PRELOAD
Places the boundary scan register (BSR) between TDI and TDO.
SAMPLE allows data from device inputs
(2)
and outputs
(1)
to be captured
in the b oundary sc an ce lls and shifte d se rially thro ug h TDO. PRELOAD
al lo w s d ata to b e inp ut se ri all y into the b oun dary sc an c e lls via the TDI.
0001
DEVICE_ID Loads the JTAG ID register (JIDR) with the vendor ID code and places
the register between TDI and TDO. 0010
HIGHZ Places the bypass register (BYR) be tween TDI and TDO. Forces all
device o utput drivers to a High-Z state. 0011
RESERVED
Several combinations are reserved. Do not use codes other than those
ide ntified for EXTEST, SAMPLE/PRELOAD, DEVICE_ID, HIGHZ, CLAMP,
VALIDATE and BYPASS instructions.
0100
RESERVED 0101
RESERVED 0110
RESERVED 0111
CLAMP Uses BYR. Forces contents of the bound ary scan cells onto the device
outputs. Places the bypass register (BYR) between TDI and TDO. 1000
RESERVED
Same as ab ove .
1001
RESERVED 1010
RESERVED 1011
RESERVED 1100
VALIDATE Automatically loaded into the instruction register whenever the TAP
co ntro lle r passe s thro ugh the CAPTURE-IR s tate . The lo we r two bits '01'
are mandate d b y the IE EE std. 1149. 1 sp e cific atio n. 1101
RESERVED Same as above. 1110
BYPASS The BYPASS instruction is used to truncate the boundary scan register
as a s ing le b it in le ngth. 1111
I6450 tbl 04
Available JTAG Instructions
6.42
21
IDT71V3577S_79S, IDT71V3577SA_79SA, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges
Ordering Information
100-pin Plastic Thin Quad Flatpack (TQFP)
119BallGridArray(BGA)
165 Fine Pitch Ball Grid Array (fBGA)
S
Power
X
Speed
XX
Package
PF**
BG
BQ
XXX
65*
75
80
85
Access Time in Tenths of Nanoseconds
6450 drw 12
Device
Type
71V3577
71V3579
128K x 36 Flow-Through Burst Synchronous SRAM with 3.3V I/O
256K x 18 Flow-Through Burst Synchronous SRAM with 3.3V I/O
,
X
Process/
Temperature
Range
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
Blank
I
*6.5ns speed only available in TQFP package and commercial temp range.
**JTAG (SA version) is not available with 100 pin TQFP package.
S
SA
Standard Power
Standard Power with JTAG Interface
X
GGreen
X
Blank
8
Tube or Tray
Tape and Reel
Package Information
100 Pin Thin Quad Plastic Flatpack (TQFP)
119 Ball Grid Array (BGA)
165 Fine Pitch Ball Grid Array (fBGA)
Information available on the IDT website
6.42
22
IDT71V3577S_79S, IDT71V3577SA_79SA, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
Datasheet Document History
01/30/04 Released Y generation die step datasheet
04/17/06 Pg. 21 Added green (Restricted hazardous substance device) to the datasheet.
04/02/12 Pg. 9 Added Industrial temp range values to the 7.5ns speed in the DC chars table
Pg. 21 Removed die step indicator from the ordering information.
Added tape and reel and green to the ordering information.
Removed IDT from the ordering information.
Pg. 1, 12 & 21 Added 6.5ns speed only available in TQFP package and in commercial temp range.
CORPORATE HEADQUARTERS for SALES: for Tech Support:
6024 Silver Creek Valley Road 800-345-7015 or sramhelp@idt.com
San Jose, CA 95138 408-284-8200 408-284-4532
fax: 408-284-2775
www.idt.com
