HEF4014BT,652 - NXP - Datasheet.Live

1. General description

The HEF4014B is a fully synchronous edge-triggered 8-bit static shift register with eight

synchronous parallel inputs (D0 to D7), a synchronous serial data input (DS), a

synchronous parallel enable input (PE), a LOW-to-HIGH edge-triggered clock input (CP)

and buffered parallel outputs from the last three stages (Q5 to Q7).

Operation is synchronous and the device is edge-triggered on the LOW-to-HIGH

transition of CP. Each register st age is of a D-type master-s lave flip-flop type. When PE is

HIGH, data is loaded into the register fr om D0 to D7 on the LOW -to-HIGH transition of CP.

When PE is LOW, data is shifted to the first position from DS, and all the data in the

input’s Schmitt trigger action makes it highly tolerant of slower clock rise and fall times.

It operates over a recommended VDD power supply range of 3 V to 15 V referenced to V SS

(usually ground). Unused inputs must be connected to VDD, VSS, or another input.

2. Features and benefits

Tolerant of slow clock rise and fall times

Fully static operation

5 V, 10 V, and 15 V parametric ratings

Standardized symmetrical output characteristics

Specified from 40 C to +85 C

Complies with JEDEC standard JESD 13-B

3. Applications

Parallel-to-serial converter

Serial data queueing

General purpose register

4. Ordering information

HEF4014B

8-bit static shift register

Rev. 8 — 21 November 2011 Product data sheet

Table 1. Ordering information

All types operate from





C to +85



Type number Package

Name Description Version

HEF4014BP DIP16 plastic dual in-line package; 16-leads (300 mil) SOT38-4

HEF4014BT SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1

Product data sheet Rev. 8 — 21 November 2011 2 of 14

NXP Semiconductors HEF4014B

8-bit static shift register

5. Functional diagram

Fig 1. Functional di agram

Fig 2. Logic diag ram

001aae556

10 CP SHIFT REGISTER

8 BITS

Q5 Q6 Q7

0D 1D 2D 3D 4D 5D 6D 7D

D5 D6 D7

001aae558

Q6 Q7

D0 D5 D6 D7PE

FF 0

FF 5

FF 6

FF 7

Product data sheet Rev. 8 — 21 November 2011 3 of 14

NXP Semiconductors HEF4014B

8-bit static shift register

6. Pinning information

6.1 Pinning

6.2 Pin description

Fig 3. Pin configuratio n DIP16 and SO16

HEF4014B

D7 VDD

Q5 D6

Q7 D5

D3 D4

D2 Q6

D1 DS

D0 CP

VSS PE

001aae557

Table 2. Pin description

Symbol Pin Description

Q5 to Q7 2, 12, 3 output

D0 to D7 7, 6, 5, 4, 13, 14, 15, 1 parallel data input

VSS 8 ground supply voltage

PE 9 parallel enable input

CP 10 clock input (LOW-to-HIGH edge-triggered)

DS 11 serial data input

VDD 16 supply voltage

Product data sheet Rev. 8 — 21 November 2011 4 of 14

NXP Semiconductors HEF4014B

8-bit static shift register

7. Functional description

[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; nD = HIGH or LOW;

 = LOW-to-HIGH clock transition;  = HIGH-to-LOW clock transition;

8. Limiting values

[1] For DIP16 package: Ptot derates linearly with 12 mW/K above 70 C.

[2] For SO16 package: Ptot derates linearly with 8 mW/K above 70 C.

Table 3. Function table[1]

Number of clock

transitions Inputs Outputs

CP DS PE Q5 Q6 Q7

Serial operation

11DLXXX

22DLXXX

33DLXXX

6XL1DXX

7XL2D1DX

8X L 3D 2D 1D

X X no change no change no change

Parallel operation

1X H D5 D6 D7

X X no change no change no change

Table 4. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter Conditions Min Max Unit

VDD supply voltage 0.5 +18 V

IIK input clamping current VI<0.5 V or VI>V

DD + 0.5 V - 10 mA

VIinput voltage 0.5 VDD + 0.5 V

IOK output clamping current VO<0.5 V or VO>V

DD + 0.5 V - 10 mA

II/O input/output current - 10 mA

IDD supply current - 50 mA

Tstg storage temperature 65 +150 C

Tamb ambient temperature 40 +85 C

Ptot total power dissipation Tamb = 40 C to +85 C

DIP16 package [1] - 750 mW

SO16 package [2] - 500 mW

P power dissipation per output - 100 mW

Product data sheet Rev. 8 — 21 November 2011 5 of 14

NXP Semiconductors HEF4014B

8-bit static shift register

9. Recommended operating conditions

10. Static characteristics

Table 5. Recommended operating con ditions

Symbol Parameter Conditions Min Typ Max Unit

VDD supply voltage 3 - 15 V

VIinput voltage 0 - VDD V

Tamb ambient temperature in free air 40 - +85 C

t/V input transition rise and fall rate VDD = 5 V --3.75s/V

VDD = 10 V --0.5s/V

VDD = 15 V --0.08s/V

Table 6. Static characteristics

VSS = 0 V; VI = VSS or VDD unless otherwise specified.

Symbol Parameter Conditions VDD Tamb = 40 C Tamb = +25 C Tamb = +85 CUnit

Min Max Min Max Min Max

VIH HIGH-level input voltage IO < 1 A 5 V 3.5 - 3.5 - 3.5 - V

10 V 7.0 - 7.0 - 7.0 - V

15 V 11.0 - 11.0 - 11.0 - V

VIL LOW-level input voltage IO < 1 A 5 V -1.5-1.5-1.5V

10 V - 3.0 - 3.0 - 3.0 V

15 V - 4.0 - 4.0 - 4.0 V

VOH HIGH-level output voltage IO < 1 A 5 V 4.95 - 4.95 - 4.95 - V

10 V 9.95 - 9.95 - 9.95 - V

15 V 14.95 - 14.95 - 14.9 5 - V

VOL LOW-level output voltage |IO < 1 A 5 V - 0.05 - 0.05 - 0.05 V

10 V - 0 .0 5 - 0.05 - 0.05 V

15 V - 0 .0 5 - 0.05 - 0.05 V

IOH HIGH-level output current VO = 2.5 V 5 V - 1.7 - 1.4 - 1.1 mA

VO = 4.6 V 5 V -0.52 - 0.44 - 0.36 mA

VO = 9.5 V 10 V - 1.3 - 1.1 - 0.9 mA

VO = 13.5 V 15 V - 3.6 - 3.0 - 2.4 mA

IOL LOW-level output current VO = 0.4 V 5 V 0.52 - 0.44 - 0.36 - mA

VO = 0.5 V 10 V 1.3 - 1.1 - 0.9 - mA

VO = 1.5 V 15 V 3.6 - 3.0 - 2.4 - mA

IIinput leakage current 15 V - 0.3 - 0.3 - 1.0 A

IDD supply current IO = 0 A 5 V - 20 - 20 - 150 A

10 V - 40 - 40 - 300 A

15 V - 80 - 80 - 600 A

CIinput capacitance - - - - 7.5 - - pF

Product data sheet Rev. 8 — 21 November 2011 6 of 14

NXP Semiconductors HEF4014B

8-bit static shift register

11. Dynamic characteristics

[1] The typical values of the propagation delay and transition times are calculated from the extrapolation formulas shown (CL in pF).

[2] tt is the same as tTHL and tTLH.

Table 7. Dynamic characteristics

Tamb = 25



C; VSS = 0 V.

Symbol Parameter Conditions VDD Extrapolation formula[1] Min Typ Max Unit

tPHL HIGH to LOW

propagation delay CP to Qn;

see Figure 4 5 V 103 ns + (0.55 ns/pF)CL- 130 260 ns

10 V 44 ns + (0.23 ns/pF)CL-55110ns

15 V 32 ns + (0.16 ns/pF)CL-4080ns

tPLH LOW to HIGH

propagation delay CP to Qn;

see Figure 4 5 V 88 ns + (0.55 ns/pF)CL- 115 230 ns

10 V 39 ns + (0.23 ns/pF)CL- 50 100 ns

15 V 32 ns + (0.16 ns/pF)CL-4080ns

tttransition time Qn output;

see Figure 4 5 V [2] 10 ns + (1.00 ns/pF)CL- 60 120 ns

10 V 9 ns + (0.42 ns/pF)CL-3060ns

15 V 6 ns + (0.28 ns/pF)CL-2040ns

tWpulse width CP input;

minimum width;

see Figure 5

5 V 70 35 - ns

10 V 30 15 - ns

15 V 24 12 - ns

tsu set-up time PE CP;

see Figure 5 5 V 40 10 - ns

10 V 25 5 - ns

15 V 15 0 - ns

DS  CP;

see Figure 5 5 V +35 5- ns

10 V +25 5- ns

15 V 25 0 - ns

Dn  CP;

see Figure 5 5 V +35 5- ns

10 V +25 5- ns

15 V 25 0 - ns

thhold time PE CP;

see Figure 5 5 V +25 5- ns

10 V 20 0 - ns

15 V 15 0 - ns

DS  CP;

see Figure 5 5 V 30 15 - ns

10 V 20 10 - ns

15 V 15 7 - ns

Dn  CP;

see Figure 5 5 V 30 15 - ns

10 V 20 10 - ns

15 V 15 7 - ns

fclk(max) maximum clock

frequency see Figure 5 5 V 6 13 - MHz

10 V 15 30 - MHz

15 V 20 40 - MHz

Product data sheet Rev. 8 — 21 November 2011 7 of 14

NXP Semiconductors HEF4014B

8-bit static shift register

12. Waveforms

Table 8. Dynamic power dissipation PD

PD can be calculated from the formulas shown. VSS = 0 V; tr = tf



20 ns; Tamb = 25



Symbol Parameter VDD Typical formul a for PD (W) Where:

PDdynamic power

dissipation 5V P

D = 900  fi + (fo  CL)  VDD2fi = input frequency in MHz;

fo = output frequency in MHz;

CL = output load capacitance in pF;

VDD = supply voltage in V;

(CL  fo) = sum of the outputs.

10 V PD = 4300  fi + (fo  CL)  VDD2

15 V PD = 12000 fi + (fo  CL)  VDD2

Measurement points are given in Table 9.

Fig 4. CP to Qn propagation delays and output transition times

The shaded areas indicate where change is permitted for predictable output performance.

Set-up and hold times are shown as positive values but may be specified as negative values.

Measurement points are given in Table 9.

Fig 5. Minimum clock pulse width, and set-up and hold times for PE to CP, DS to CP, and D to CP

001aaj456

tPHL

tttt

CP input

Qn output

VSS

VOH

VOL

90 %

10 %

tPLH

001aae559

CP input

D input

PE input

DS input

50 %

50 % 50 % 50 %

clk(max)

50 % 50 %

50 %

Product data sheet Rev. 8 — 21 November 2011 8 of 14

NXP Semiconductors HEF4014B

8-bit static shift register

Table 9. Measurement points

Supply voltage Input Output

VDD VMVM

5 V to 15 V 0.5VDD 0.5VDD

Test data is given in Table 10;

Definitions for test circuit:

DUT = Device Under Test.

CL= load capacitance including jig and probe capacitance.

RT= termination resistance should be equal to the output impedance Zo of the pulse generator.

Fig 6. Test circuit

VDD

VIVO

001aag182

DUT

Table 10. Test data

Supply voltage Input Load

VDD VItr, tfCL

5 V to 15 V VSS or VDD 20 ns 50 pF

Product data sheet Rev. 8 — 21 November 2011 9 of 14

NXP Semiconductors HEF4014B

8-bit static shift register

13. Package outline

Fig 7. Package outline SOT38-4 (DIP16)

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

SOT38-4 95-01-14

03-02-13

(e )

seating plane

pin 1 index

0 5 10 mm

scale

Note

1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.

UNIT A

max. 12 b1(1) (1) (1)

b2cD E e M Z

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

min. A

max. bmax.

1.73

1.30 0.53

0.38 0.36

0.23 19.50

18.55 6.48

6.20 3.60

3.05 0.2542.54 7.62 8.25

7.80 10.0

8.3 0.764.2 0.51 3.2

inches 0.068

0.051 0.021

0.015 0.014

0.009

1.25

0.85

0.049

0.033 0.77

0.73 0.26

0.24 0.14

0.12 0.010.1 0.3 0.32

0.31 0.39

0.33 0.030.17 0.02 0.13

DIP16: plastic dual in-line package; 16 leads (300 mil) SOT38-4

Product data sheet Rev. 8 — 21 November 2011 10 of 14

NXP Semiconductors HEF4014B

8-bit static shift register

Fig 8. Package outline SOT109-1 (SO16)

detail X

vMA

(A )

pin 1 index

UNIT A

max. A1A2A3bpcD

(1) E(1) (1)

ELL

pQZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

inches

1.75 0.25

0.10 1.45

1.25 0.25 0.49

0.36 0.25

0.19 10.0

9.8 4.0

3.8 1.27 6.2

5.8 0.7

0.6 0.7

0.3 8

0.25 0.1

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

Note

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

1.0

0.4

SOT109-1 99-12-27

03-02-19

076E07 MS-012

0.069 0.010

0.004 0.057

0.049 0.01 0.019

0.014 0.0100

0.0075 0.39

0.38 0.16

0.15 0.05

1.05

0.041

0.244

0.228 0.028

0.020 0.028

0.012

0.01

0.25

0.01 0.004

0.039

0.016

0 2.5 5 mm

scale

SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1

Product data sheet Rev. 8 — 21 November 2011 11 of 14

NXP Semiconductors HEF4014B

8-bit static shift register

14. Revision history

Table 11. Revision history

Document ID Release date Data sheet status Change notice Supersedes

HEF4014B v.8 20111121 Product data sheet - HEF4014B v.7

Modifications: •Legal pages updated.

•Changes in “General description” and “Features and benefits”.

HEF4014B v.7 20110914 Product data sheet - HEF4014B v.6

HEF4014B v.6 20091102 Product data sheet - HEF4014B v.5

HEF4014B v.5 20090624 Product data sheet - HEF4014B v.4

HEF4014B v.4 20090122 Product data sheet - HEF4014B_CNV v.3

HEF4014B_CNV v.3 19950101 Product specification - HEF4014B_CNV v.2

HEF4014B_CNV v.2 19950101 Product specification - -

Product data sheet Rev. 8 — 21 November 2011 12 of 14

NXP Semiconductors HEF4014B

8-bit static shift register

15. Legal information

15.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Definitions”.

[3] The product status of de vice(s) descr ibed in th is docume nt may have cha nged since this docume nt was publis hed and ma y dif fer in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

15.2 Definitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

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Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and tit le. A short data sh eet is intended

for quick reference only and shou ld not be rel ied u pon to cont ain det ailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall pre vail.

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data sheet shall define the specification of the product as agreed between

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Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanent ly and irreversibly affect

the quality and reliability of the device.

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products are sold subject to the general terms and conditions of commercial

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Document status[1][2] Product status[3] Definition

Objective [short] data sheet Development This document contains data from the objective specification for product development.

Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.

Product [short] dat a sheet Production This document contains the product specifica tion.

Product data sheet Rev. 8 — 21 November 2011 13 of 14

NXP Semiconductors HEF4014B

8-bit static shift register

Non-automotive qualified products — Unless this data sheet expressly

states that this specific NXP Semiconductors product is automotive qualified,

the product is not suitable for aut omotive use. It i s neither qua lified nor test ed

in accordance with automotive testing or application requirements. NXP

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In the event that customer uses the product for design-in and use in

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use of the product for automotive applications beyond NXP Semiconductors’

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15.4 Trademarks

Notice: All referenced b rands, produc t names, service names and trademarks

are the property of their respect i ve ow ners.

16. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

NXP Semiconductors HEF4014B

8-bit static shift register

For more information, please visit: http://www.nxp.co m

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of rele ase: 21 November 2011

Document iden tifier: HEF4014B

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

17. Contents

1 General description. . . . . . . . . . . . . . . . . . . . . . 1

2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1

3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

4 Ordering information. . . . . . . . . . . . . . . . . . . . . 1

5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2

6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 3

6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3

7 Functional description . . . . . . . . . . . . . . . . . . . 4

8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4

9 Recommended operating conditions. . . . . . . . 5

10 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5

11 Dynamic characteristics . . . . . . . . . . . . . . . . . . 6

12 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9

14 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 11

15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 12

15.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 12

15.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

15.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 12

15.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 13

16 Contact information. . . . . . . . . . . . . . . . . . . . . 13

17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14