LT6557
1
6557fa
500MHz, 2200V/µs Gain of 2,
Single Supply Triple Video
Amplifi er with Input Bias Control
The LT®6557 is a high speed triple video amplifi er with an
internal fi xed gain of 2 and a programmable DC input bias
voltage. This amplifi er features a 400MHz 2VP-P signal
bandwidth, 2200V/µs slew rate and a unique ability to
drive heavy output loads to 0.8V of the supply rails, mak-
ing the LT6557 ideal for a single 5V supply, wideband video
application. With just one resistor, the inputs of all three
amplifi ers can be programmed to a common voltage level,
simplifying and reducing the need for external circuitry in
the AC-coupled applications. Without the programmable
resistor, the input bias circuit becomes inactive, allowing the
use of an external clamp circuit or direct coupled input.
The LT6557 has separate power supply and ground pins for
each amplifi er to improve channel separation and to ease
power supply bypassing. The LT6557 provides uncom-
promised performance in many high speed applications
where a low voltage, single supply is required.
The LT6557 is available in 16-lead SSOP and 5mm × 3mm
DFN packages.
■ LCD Video Projectors
■ RGB HD Video Amplifi ers
■ Coaxial Cable Drivers
■ Low Supply ADC Drivers
■ –3dB Small-Signal Bandwidth: 500MHz
■ –3dB 2VP-P Large-Signal Bandwidth: 400MHz
■ Slew Rate: 2200V/µs
■ Fixed Gain of 2, No External Resistors Required
■ AC Coupling with Programmable DC Input Bias
■ Output Swings to 0.8V of Supply Rails
■ Full Video Swing with 5V Single Supply
■ Diff Gain: 0.02%
■ Diff Phase: 0.05°
■ Enable/Shutdown Pin
■ High Output Current: ±100mA
■ Supply Range: 3V to 7.5V
■ Operating Temperature Range: –40°C to 85°C
■ Available in 16-Lead SSOP and 5mm × 3mm DFN
Packages
AC-Coupled Triple Video Driver
+
–
500Ω
IN R
GND
EN
IN R OUT R
V+
V+ R
V+ G
V+ B
BCV
LT6557
GND R
75Ω75Ω
412Ω
5V
5V
5V
5V
6557 TA01a
22µF
500Ω
75Ω220µF
+
–
500Ω
IN G
IN G OUT G
GND G
75Ω75Ω
22µF
500Ω
75Ω220µF
+
–
500Ω
IN B
IN B OUT B
GND B
75Ω75Ω
22µF
500Ω
75Ω220µF
Fast Large-Signal Transient Response
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
TYPICAL APPLICATION
FEATURES
APPLICATIONS
DESCRIPTION
LT6557
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ELECTRICAL CHARACTERISTICS
Total Supply Voltage (VS+ to GND) ...........................7.5V
Input Current ........................................................±10mA
Output Current (Note 2) .......................................±70mA
Output Short-Circuit Duration (Note 2) ............ Indefi nite
Operating Temperature Range (Note 3) ... –40°C to 85°C
Specifi ed Temperature Range (Note 4) .... –40°C to 85°C
The ● denotes the specifi cations which apply over the full operating
temperature range, otherwise specifi cations are at TA = 25°C. VS = 5V, RL = 150Ω to VS/2, VEN = 0.4V, RBCV = open, unless
otherwise noted.
GN PACKAGE
16-LEAD PLASTIC SSOP
1
2
3
4
5
6
7
8
TOP VIEW
16
15
14
13
12
11
10
9
EN
GND
IN R
GND R
IN G
GND G
IN B
GND B
BCV
V+
OUT R
V+ R
OUT G
V+ G
OUT B
V+ B
G = +2
G = +2
G = +2
TJMAX = 150°C, θJA = 110°C/W
16
15
14
13
12
11
10
9
17
1
2
3
4
5
6
7
8
BCV
V+
OUT R
V+ R
OUT G
V+ G
OUT B
V+ B
EN
GND
IN R
GND R
IN G
GND G
IN B
GND B
TOP VIEW
DHC PACKAGE
16-LEAD (5mm × 3mm) PLASTIC DFN
G = +2
G = +2
G = +2
TJMAX = 125°C, θJA = 40°C/W
EXPOSED PAD (PIN 17) IS GND, MUST BE SOLDERED TO PCB
ORDER PART NUMBER GN PART MARKING ORDER PART NUMBER DHC PART MARKING*
LT6557CGN
LT6557IGN
6557
6557I
LT6557CDHC
LT6557IDHC
6557
6557
Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
Consult LTC Marketing for parts specifi ed with wider operating temperature ranges. *The temperature grade is identifi ed by a label on the shipping container.
Junction Temperature
SSOP ................................................................ 150°C
DFN ................................................................... 125°C
Storage Temperature Range
SSOP ................................................. –65°C to 150°C
DFN .................................................... –65°C to 125°C
Lead Temperature (Soldering, 10 sec)
SSOP ................................................................ 300°C
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VOS Input Offset Voltage VIN = 1.25V
●
12
15
40
50
mV
mV
IIN Input Current VIN = 1.25V
●
35
45
70
100
µA
µA
RIN Input Resistance VIN = 0.75V to 1.75V, BCV (Pin 6) Open
●
90
50
200
150
kΩ
kΩ
CIN Input Capacitance f = 1MHz 1.5 pF
ABSOLUTE MAXIMUM RATINGS
(Note 1)
PACKAGE/ORDER INFORMATION
LT6557
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The ● denotes the specifi cations which apply over the full operating
temperature range, otherwise specifi cations are at TA = 25°C. VS = 5V, RL = 150Ω to VS/2, VEN = 0.4V, RBCV = open, unless
otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
AV ERR Gain Error VIN = 0.75V to 1.75V
●
±0.5
±0.5
±2.5
±3.0
%
%
AV MATCH Gain Match Between Channels VIN = 0.75V to 1.75V
●
±0.4
±0.4
±2.75
±3.25
%
%
VIN(DC) Input Voltage Bias RBCV = 348Ω
●
1.0
0.8
1.25
1.10
1.5
1.7
V
V
PSRR Power Supply Rejection Ratio VS = 4V to 6V, VIN = 1.25V
●
42
38
50
47
dB
dB
VOL Output Voltage Swing Low
●
0.8
0.9
0.9
1.0
V
V
VOH Output Voltage Swing High
●
4.1
4.0
4.2
4.1
V
V
ISSupply Current per Amplifi er VEN = 0.4V, RL = ∞, Includes IS of V+
(Pin 15) ●
22.5
25.0
25
29
mA
mA
Total Supply Current (Disabled) VEN = Open, RL = ∞
●
10
10
450
1000
µA
µA
IEN Enable Pin Current VEN = 0.4V
●
–250
–300
–125
–150
µA
µA
ISC Short-Circuit Current
●
±70
±40
±100
±90
mA
mA
SR Slew Rate VOUT = 1.25V to 3.75V (Note 5) 1400 2200 V/µs
–3dB BW –3dB Bandwidth VOUT = 2VP-P 400 MHz
VOUT = 0.2VP-P 500 MHz
0.1dB BW Gain Flatness ±0.1dB Bandwidth VOUT = 2VP-P 120 MHz
FPBW Full Power Bandwidth VOUT = 2VP-P (Note 6) 220 350 MHz
XTalk All Hostile Crosstalk f = 10MHz, VOUT = 2VP-P
f = 100MHz, VOUT = 2VP-P
–80
–55
dB
dB
tSSettling Time To 1%, VOUT = 1.5V to 3.5V
To 0.1%
4
7
ns
ns
tr, tfRise Time, Fall Time 10% to 90%, VOUT = 1.5V to 3.5V 875 ps
ΔG Differential Gain NTSC Signal 0.02 %
ΔΦ Differential Phase NTSC Signal 0.05 Deg
HD2 2nd Harmonic Distortion f = 10MHz, VOUT = 2VP-P –68 dBc
HD3 3rd Harmonic Distortion f = 10MHz, VOUT = 2VP-P –75 dBc
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: A heat sink may be required to keep the junction temperature
below the Absolute Maximum Rating.
Note 3: The LT6557C is guaranteed functional over the temperature range
of –40°C and 85°C.
Note 4: The LT6557C is guaranteed to meet specifi ed performance from
0°C to 70°C. The LT6557C is designed, characterized and expected to
meet specifi ed performance from –40°C to 85°C but is not tested or
QA sampled at these temperatures.The LT6557I is guaranteed to meet
specifi ed performance from –40°C to 85°C.
Note 5: Slew rate is 100% production tested on the R channel and
measured on the rising edge of the output signal. The slew rate of the
falling edge and of the G and B channels is guaranteed through design and
characterization.
Note 6: Large-signal bandwidth is calculated from slew rate:
FPBW = SR/(π • VP-P)
ELECTRICAL CHARACTERISTICS
LT6557
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Gain Error Distribution Gain Error Matching Distribution Voltage Gain vs Temperature
Supply Current per Ampifi er
vs Supply Voltage
Supply Current per Ampifi er
vs EN Voltage
EN Pin Current vs EN Pin Voltage
Input Referred Offset Voltage
vs Temperature
Input Bias Current
vs Input Voltage
SUPPLY VOLTAGE (V)
0
SUPPLY CURRENT (mA)
30
40
50
8
6557 G04
20
10
25
35
45
15
5
021 43 67
5
VOUT = VS/2
Supply Current per Ampifi er
vs Temperature
TYPICAL PERFORMANCE CHARACTERISTICS
LT6557
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Output Voltage vs Input Voltage
Output Voltage Swing
vs Load Current (Output High)
Input Bias Voltage vs Resistance
at BCV Pin Input Bias Voltage vs Temperature
Bias Control Voltage
vs Temperature
Frequency Response of Three
Amplifi ers Gain Flatness vs Frequency
Output Voltage Swing
vs Load Current (Output Low)
Frequency Response
TYPICAL PERFORMANCE CHARACTERISTICS
LT6557
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Crosstalk Between Amplifi ers
vs Frequency
Output Impedance vs Frequency Input Impedance vs Frequency PSRR vs Frequency
Distortion vs Frequency Distortion vs Frequency
TYPICAL PERFORMANCE CHARACTERISTICS
Frequency Response with
Capacitive Loads Large-Signal Group Delay
Input Referred Noise Spectral
Density
LT6557
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Overdriven Output Recovery Enable/Disable Response
Large-Signal Transient Response
EN (Pin 1): Enable Control Pin. The part is enabled when
this pin is pulled low. An internal pull-up resistor of 40k
will turn the part off if this pin is unconnected.
GND (Pin 2): Ground Reference for Enable Pin (Pin 1)
and Bias Control Voltage Pin (Pin 16). This pin must be
connected externally to ground.
IN R (Pin 3): Red Channel Input. This pin has a nominal
impedance of 200kΩ with input bias circuit inactive,
Pin 16 open.
GND R (Pin 4): Ground of Red Channel Amplifi er. This pin
is not internally connected to other ground pins and must
be connected externally to ground.
IN G (Pin 5): Green Channel Input. This pin has a nomi-
nal impedance of 200kΩ with input bias circuit inactive,
Pin 16 open.
GND G (Pin 6): Ground of Green Channel Amplifi er. This
pin is not internally connected to other ground pins and
must be connected externally to ground.
IN B (Pin 7): Blue Channel Input. This pin has a nominal
impedance of 200kΩ with input bias circuit inactive,
Pin 16 open.
GND B (Pin 8): Ground of Blue Channel Amplifi er. This
pin is not internally connected to other ground pins and
must be connected externally to ground.
TYPICAL PERFORMANCE CHARACTERISTICS
TIME (ns)
0
VIN = 0.5V/DIV, VOUT = 1V/DIV
3
4
5
200
6557 G28
2
1
025 50 75 100 125 150 175 225 250
VIN
VOUT
VS = 5V
VIN = 2.4VP-P
RL = 150
9
TIME (
m
s)
0
0
–1
VOLTAGE (V)
1
3
4
5
0.2 1.0 1.4
6557 G29
2
6
0.8 1.8 2.22.0
0.4 0.6 1.2 1.6
VEN(DISABLE)
VEN(ENABLE)
VOUT
VS = 5V
VOUT = 2VP-P
AC COUPLED
RL = 150
W
Small-Signal Transient Response
TIME (ns)
0
OUTPUT (V)
2.60
24
6557 G31
2.45 48
12 16 20
2610
14 18 22
2.65 VS = 5V
VIN = 50mVP-P
RL = 150
9
2.55
2.50
PIN FUNCTIONS
LT6557
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V+ B (Pin 9): Positive Supply Voltage of Blue Channel
Amplifi er. This pin is not internally connected to other
supply voltage pins and must be externally connected to
the supply voltage bus with proper bypassing for best
performance, see Power Supply Considerations.
OUT B (Pin 10): Blue Channel Output.
V+ G (Pin 11): Positive Supply Voltage of Green Channel
Amplifi er. This pin is not internally connected to other
supply voltage pins and must be externally connected to
the supply voltage bus with proper bypassing for best
performance, see Power Supply Considerations.
OUT G (Pin 12): Green Channel Output.
V+ R (Pin 13): Positive Supply Voltage of Red Channel
Amplifi er. This pin is not internally connected to other
supply voltage pins and must be externally connected to
Power Supply Considerations
The LT6557 is optimized to provide full video signal swing
output when operated from a standard 5V single supply.
Due to the supply current involved in ultrahigh slew rate
amplifi ers like the LT6557, selection of the lowest workable
supply voltage is recommended to minimize heat genera-
tion and simplify thermal management. Temperature rise
at the internal devices (TJ) must be kept below 150°C
(SSOP package) or 125°C (DFN package), and can be
estimated from the ambient temperature (TA) and power
dissipation (PD) as follows:
T
J = TA + PD • 40°C/W for DFN package
or
T
J = TA + PD • 110°C/W for SSOP package
where PD = (IS + 0.5 • IO) • VS(TOTAL)
The latter equation assumes (conservatively) that the output
swing is small relative to the supply and RMS load current
(IO) is bidirectional (as with AC coupling).
the supply voltage bus with proper bypassing for best
performance, see Power Supply Considerations.
OUT R (Pin 14): Red Channel Output.
V+ (Pin 15): Positive Supply Voltage of Control Circuitry.
This pin is not internally connected to other supply voltage
pins and must be externally connected to supply voltage
bus with proper bypassing for best performance, see
Power Supply Considerations.
BCV (Pin 16): Bias Control Voltage. A resistor connected
between Pin 16 and Pin 2 (GND) will generate a DC voltage
bias at the inputs of the three amplifi ers for AC coupling
application, see Programmable Input Bias.
Exposed Pad (Pin 17, DFN Package): Ground. This pad
must be soldered to PCB and is internally connected to
GND (Pin 2).
The grounds are separately pinned for each amplifi er to
minimize crosstalk.
Operation from split supplies can be accomplished by
connecting the LT6557 ground pins to the negative rail.
Since the amplifi er gain is referenced to its ground pins,
the actual signals are referenced to the negative rail, in
this case, and DC coupled applications need to take this
into consideration. With dual supplies, recommended
voltages range from nominal ±2.5V to ±3.3V.
The ultrahigh frequency (UHF) operating range of the
LT6557 requires that careful printed circuit layout prac-
tices be followed to obtain maximum performance. Trace
lengths between power pins and bypass capacitors should
be minimized (<0.1 inch) and one or more dedicated
ground planes should be employed to minimize parasitic
inductance. Poor layout or breadboarding methods can
seriously impact amplifi er stability, frequency response
and crosstalk performance. A 2.2µF and a 10µF bypass
capacitor is recommended for the LT6557supply bus, plus
a 10nF high frequency bypass capacitor at each individual
power pin.
PIN FUNCTIONS
APPLICATIONS INFORMATION
LT6557
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V+
IN
2.5k
9.1k
6557 F01
I = VPIN16
RSET
Figure 1. Simplifi ed Programmable Input Bias Circuit Diagram
no-signal amplifi er input bias condition according to the
following relationship:
VVk
R
BIAS IN PIN
SET
()
•.
=16 91
where VPIN16 = 0.048V typical.
For single 5V supply operation, a 400Ω programming
resistor is generally optimal. In applications that demand
maximum amplifi er linearity, or if external biasing is
preferred (in DC-coupled applications, for example), the
internal biasing circuitry may be disabled by leaving Pin
16 open. With Pin 16 open, input loading is approximately
200kΩ.
Shutdown Control
The LT6557 may be placed into a shutdown mode, where
all three amplifi er sections are deactivated and power sup-
ply draw is reduced to approximately 10µA. When the EN
pin is left open, an internal 40k pull-up resistor brings the
pin to V+ and the part enters the shutdown mode. Pulling
the pin more than approximately 1.5V below V+ will en-
able the LT6557 (see Figure 2 for equivalent circuit). The
pull-down current required to activate the part is typically
125µA. In most applications, the EN pin is simply con-
nected to ground (for continuous operation) or driven
directly by a CMOS-level logic gate (see Figure 3 for
examples). Response time is typically 50ns for enabling,
and 1µs for shutdown. In shutdown mode, the feedback
resistors remain connected between the output pins and
the individual ground (or V– connected) pins.
V+
40k
BIAS
CIRCUITRY
EN
Figure 2. Simplifi ed Shutdown Circuit Diagram
LT6557
V+V+
2
(3a) Open Drain or Open Collector
1
EN
DISABLE
LT6557
2
6557 F03
(3b) CMOS Gate with Shared Supply
1
EN
DISABLE
Figure 3. Suitable Shutdown Pin Drive Circuits
Programmable Input Bias
The LT6557 contains circuitry that provides a user-pro-
grammed bias voltage to the inputs of all three amplifi er
sections. The internal biasing feature is designed to mini-
mize external component count in AC-coupled applica-
tions, but may be defeated if external biasing is desired.
Figure 1 shows the simplifi ed equivalent circuit feeding
the noninverting input of each amplifi er. A programming
resistor from Pin 16 to GND (Pin 2) establishes the nominal
APPLICATIONS INFORMATION
LT6557
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6557fa
GN Package
16-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
GN16 (SSOP) 0204
12
345678
.229 – .244
(5.817 – 6.198)
.150 – .157**
(3.810 – 3.988)
16 15 14 13
.189 – .196*
(4.801 – 4.978)
12 11 10 9
.016 – .050
(0.406 – 1.270)
.015 ± .004
(0.38 ± 0.10) × 45°
0° – 8° TYP
.007 – .0098
(0.178 – 0.249)
.0532 – .0688
(1.35 – 1.75)
.008 – .012
(0.203 – 0.305)
TYP
.004 – .0098
(0.102 – 0.249)
.0250
(0.635)
BSC
.009
(0.229)
REF
.254 MIN
RECOMMENDED SOLDER PAD LAYOUT
.150 – .165
.0250 BSC.0165 ±.0015
.045 ±.005
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
INCHES
(MILLIMETERS)
NOTE:
1. CONTROLLING DIMENSION: INCHES
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
BIAS
V+
EN
IN
OUT
6557 SS
500Ω
500Ω
SIMPLIFIED SCHEMATIC
PACKAGE DESCRIPTION
LT6557
11
6557fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
DHC Package
16-Lead Plastic DFN (5mm × 3mm)
(Reference LTC DWG # 05-08-1706)
3.00 ±0.10
(2 SIDES)
5.00 ±0.10
(2 SIDES)
NOTE:
1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WJED-1) IN JEDEC
PACKAGE OUTLINE MO-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
0.40 ± 0.10
BOTTOM VIEW—EXPOSED PAD
1.65 ± 0.10
(2 SIDES)
0.75 ±0.05
R = 0.115
TYP
R = 0.20
TYP
4.40 ±0.10
(2 SIDES)
18
169
PIN 1
TOP MARK
(SEE NOTE 6)
0.200 REF
0.00 – 0.05
(DHC16) DFN 1103
0.25 ± 0.05
PIN 1
NOTCH
0.50 BSC
4.40 ±0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
1.65 ±0.05
(2 SIDES)2.20 ±0.05
0.50 BSC
0.65 ±0.05
3.50 ±0.05
PACKAGE
OUTLINE
0.25 ± 0.05
PACKAGE DESCRIPTION
LT6557
12
6557fa
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2006
LT/LWI 0606 • REV A • PRINTED IN USA
Split Supply Operation with DC Bias Servo
TYPICAL APPLICATION
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