LT1976/LT1976B
1
1976bfg
■
High Voltage Power Conversion
■
14V and 42V Automotive Systems
■
Industrial Power Systems
■
Distributed Power Systems
■
Battery-Powered Systems
■
Wide Input Range: 3.3V to 60V
■
1.5A Peak Switch Current (LT1976)
■
100μA Quiescent Current (LT1976)**
■
1.6mA Quiescent Current (LT1976B)
■
Low Shutdown Current: I
Q
< 1μA
■
Power Good Flag with Programmable Threshold
■
Load Dump Protection to 60V
■
200kHz Switching Frequency
■
Saturating Switch Design: 0.2Ω On-Resistance
■
Peak Switch Current Maintained Over
Full Duty Cycle Range*
■
1.25V Feedback Reference Voltage
■
Easily Synchronizable
■
Soft-Start Capability
■
Small 16-Pin Thermally Enhanced TSSOP Package
High Voltage 1.5A, 200kHz
Step-Down Switching Regulator
with 100μA Quiescent Current
*Protected by U.S. Patents, including 6498466
**See Burst Mode Operation section for conditions
The LT
®
1976/LT1976B are 200kHz monolithic step-down
switching regulators that accept input voltages up to 60V.
A high efficiency 1.5A, 0.2Ω switch is included on the die
along with all the necessary oscillator, control and logic
circuitry. Current mode topology is used for fast transient
response and good loop stability.
Innovative design techniques along with a new high volt-
age process achieve high efficiency over a wide input
range. Efficiency is maintained over a wide output current
range by employing Burst Mode operation at low currents,
utilizing the output to bias the internal circuitry, and by
using a supply boost capacitor to fully saturate the power
switch. The LT1976B does not shift into Burst Mode
operation at low currents, eliminating low frequency out-
put ripple at the expense of efficiency. Patented circuitry
maintains peak switch current over the full duty cycle
range.* Shutdown reduces input supply current to less
than 1μA. External synchronization can be implemented
by driving the SYNC pin with logic-level inputs. A single
capacitor from the C
SS
pin to the output provides a
controlled output voltage ramp (soft-start). The devices
also have a power good flag with a programmable thresh-
old and time-out and thermal shutdown protection.
The LT1976/LT1976B are available in a 16-pin TSSOP
package with Exposed Pad leadframe for low thermal
resistance.
VIN
SHDN
VC
BOOST
VBIAS
FB
PGFB
PG
LT1976
4.7μF
100V
CER
330pF
0.33μF
0.1μF
33μH4148
1μFSYNC
CT
GND
100μF
6.3V
TANT
VOUT
3.3V
1A
VIN
3.3V TO 60V
10MQ60N
1500pF
10k
165k
1%
100k
1%
1976 TA01
47pF
SW
CSS
14V to 3.3V Step-Down Converter with
100μA No Load Quiescent Current
LT1976 Efficiency and Power
Loss vs Load Current
LOAD CURRENT (mA)
0.1
EFFICIENCY (%)
POWER LOSS (W)
50
75
5V
3.3V
1000
1976 TA02
25
0110 100 10000
100
0.1
1
0.01
0.001
10
EFFICIENCY
TYPICAL
POWER LOSS
LT1976 Supply Current vs
Input Voltage
INPUT VOLTAGE (V)
0
0
SUPPLY CURRENT (μA)
50
100
10 20 30 40
1976 F05
50
150
25
75
125
60
V
OUT
= 3.3V
T
A
= 25°C
DESCRIPTIO
U
FEATURES
APPLICATIO S
U
TYPICAL APPLICATIO
U
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
Burst Mode is a registered trademark of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
LT1976/LT1976B
2
1976bfg
Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
(Note 1)
V
IN
, SHDN, PG, BIAS .............................................. 60V
BOOST Pin Above SW ............................................ 35V
BOOST Pin Voltage ................................................. 68V
SYNC, C
SS
, PGFB, FB................................................ 6V
Operating JunctionTemperature Range
LT1976EFE/LT1976BEFE (Note 2) ... – 40°C to 125°C
LT1976IFE/LT1976BIFE (Note 2) ..... –40°C to 125°C
LT1976HFE (Note 2) ........................ –40°C to 140°C
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
ORDER PART
NUMBER
Consult LTC Marketing for parts specified with wider operating temperature ranges.
LT1976EFE
LT1976IFE
LT1976HFE
LT1976BEFE
LT1976BIFE
ABSOLUTE AXI U RATI GS
W
WW
U
PACKAGE/ORDER I FOR ATIO
UUW
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full –40°C to 125°C
operating temperature range, otherwise specifications are at TJ = 25°C. VIN = 12V, SHDN = 12V, BOOST = 15.3V, BIAS = 5V,
FB/PGFB = 1.25V, CSS/SYNC = 0V unless otherwise noted.
θ
JA
= 45°C/W, θ
JC(PAD)
= 10°C/W
EXPOSED PAD IS GND (PIN 17)
MUST BE SOLDERED TO GND (PIN 8)
FE PACKAGE
16-LEAD PLASTIC TSSOP
1
2
3
4
5
6
7
8
TOP VIEW
16
15
14
13
12
11
10
9
NC
SW
NC
V
IN
NC
BOOST
C
T
GND
PG
SHDN
SYNC
PGFB
FB
V
C
BIAS
C
SS
17
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
SHDN
SHDN Threshold ●1.2 1.3 1.4 V
I
SHDN
SHDN Input Current SHDN = 12V ●520 μA
Minimum Input Voltage (Note 3) ●2.4 3 V
I
VINS
Supply Shutdown Current SHDN = 0V, BOOST = 0V, FB/PGFB = 0V 0.1 2 μA
Supply Sleep Current (Note 4) (LT1976) BIAS = 0V, FB = 1.35V ●170 230 μA
FB = 1.35V ●45 75 μA
I
VIN
Supply Quiescent Current BIAS = 0V, FB = 1.15V, V
C
= 0.8V (V
C
= 0V LT1976B) 3.2 4.10 mA
BIAS = 5V, FB = 1.15V, V
C
= 0.8V (V
C
= 0V LT1976B) 2.6 3.25 mA
Minimum BIAS Voltage (Note 5) ●2.7 3 V
I
BIASS
BIAS Sleep Current (Note 4) (LT1976) ●110 180 μA
I
BIAS
BIAS Quiescent Current SYNC = 3.3V 700 800 μA
Minimum Boost Voltage (Note 6) I
SW
= 1.5A 1.8 2.5 V
Input Boost Current (Note 7) I
SW
= 1.5A 40 50 mA
V
REF
Reference Voltage (V
REF
) 3.3V < V
VIN
< 60V ●1.225 1.25 1.275 V
I
FB
FB Input Bias Current 75 200 nA
EA Voltage Gain (Note 8) 900 V/V
EA Voltage g
m
dI(V
C
)= ±10μA 400 650 800 μMho
EA Source Current FB = 1.15V 20 40 55 μA
EA Sink Current FB = 1.35V 15 30 40 μA
V
C
to SW g
m
3A/V
V
C
High Clamp 2.1 2.2 2.4 V
V
C
Switching Threshold (LT1976B) ●0.1 0.4 0.8 V
FE PART MARKING
1976EFE
1976IFE
1976HFE
1976BEFE
1976BIFE
LT1976/LT1976B
3
1976bfg
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
I
PK
SW Current Limit LT1976 ●1.5 2.4 3.5 A
LT1976B 1.2 2.5 4 A
Switch On Resistance (Note 9) ●0.2 0.4 Ω
Switching Frequency BOOST = OPEN ●180 200 230 kHz
Maximum Duty Cycle 90 92 %
Minimum SYNC Amplitude 1.5 2.0 V
SYNC Frequency Range 230 600 kHz
SYNC Input Impedance SYNC = 0.5V 100 kΩ
I
CSS
C
SS
Current Threshold (Note 10) FB = 0V 7 13 20 μA
I
PGFB
PGFB Input Current 25 100 nA
V
PGFB
PGFB Voltage Threshold (Note 11) ●88 90 92 %
I
CT
C
T
Source Current (Note 11) ●2 3.6 5.5 μA
C
T
Sink Current (Note 11) 1 2 mA
V
CT
C
T
Voltage Threshold (Note 11) 1.16 1.2 1.26 V
PG Leakage (Note 11) PG = 12V 0.1 1 μA
PG Sink Current (Note 11) PGFB = 1V, PG = 400mV 120 200 μA
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full –40°C to 125°C
operating temperature range, otherwise specifications are at TJ = 25°C. VIN = 12V, SHDN = 12V, BOOST = 15.3V, BIAS = 5V,
FB/PGFB = 1.25V, CSS/SYNC = 0V unless otherwise noted.
The ● denotes the specifications which apply over the full –40°C to 140°C operating temperature range, otherwise specifications are
at TJ = 25°C. VIN = 12V, SHDN = 12V, BOOST = 15.3V, BIAS = 5V, FB/PGFB = 1.25V, CSS/SYNC = 0V unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
SHDN
SHDN Threshold ●1.2 1.3 1.4 V
I
SHDN
SHDN Input Current SHDN = 12V ●520 μA
Minimum Input Voltage (Note 3) ●2.4 3 V
I
VINS
Supply Shutdown Current SHDN = 0V, BOOST = 0V, FB/PGFB = 0V 0.1 2 μA
Supply Sleep Current (Note 4) (LT1976) BIAS = 0V, FB = 1.35V ●170 300 μA
FB = 1.35V ●45 100 μA
I
VIN
Supply Quiescent Current BIAS = 0V, FB = 1.15V, V
C
= 0.8V 3.2 4.10 mA
BIAS = 5V, FB = 1.15V, V
C
= 0.8V 2.6 3.25 mA
Minimum BIAS Voltage (Note 5) ●2.7 3 V
I
BIASS
BIAS Sleep Current (Note 4) ●110 180 μA
I
BIAS
BIAS Quiescent Current SYNC = 3.3V 700 800 μA
Minimum Boost Voltage (Note 6) I
SW
= 1.5A 1.8 2.5 V
Input Boost Current (Note 7) I
SW
= 1.5A 40 50 mA
V
REF
Reference Voltage (V
REF
) 3.3V < V
VIN
< 60V ●1.212 1.25 1.288 V
I
FB
FB Input Bias Current 75 200 nA
EA Voltage Gain (Note 8) 900 V/V
EA Voltage g
m
dI(V
C
)= ±10μA 400 650 800 μMho
EA Source Current FB = 1.15V 20 40 55 μA
EA Sink Current FB = 1.35V 15 30 40 μA
V
C
to SW g
m
3A/V
V
C
High Clamp 2.1 2.2 2.4 V
LT1976/LT1976B
4
1976bfg
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LT1976EFE/LT1976BEFE are guaranteed to meet performance
specifications from 0°C to 125°C junction temperature. Specifications over
the –40°C to 125°C operating junction temperature range are assured by
design, characterization and correlation with statistical process controls.
The LT1976IFE/LT1976BIFE/LT1976HFE are guaranteed and tested over
the full –40°C to 125°C operating junction temperature range. The
LT1976HFE is also tested to the LT1976HFE electrical characteristics table
at 140°C operating junction temperature. High junction temperatures
degrade operating lifetimes.
Note 3: Minimum input voltage is defined as the voltage where switching
starts. Actual minimum input voltage to maintain a regulated output will
depend upon output voltage and load current. See Applications
Information.
Note 4: Supply input current is the quiescent current drawn by the input
pin. Its typical value depends on the voltage on the BIAS pin and operating
state of the LT1976. With the BIAS pin at 0V, all of the quiescent current
required to operate the LT1976 will be provided by the V
IN
pin. With the
BIAS voltage above its minimum input voltage, a portion of the total
quiescent current will be supplied by the BIAS pin. Supply sleep current
for the LT1976 is defined as the quiescent current during the “sleep”
portion of Burst Mode operation. See Applications Information for
determining application supply currents.
Note 5: Minimum BIAS voltage is the voltage on the BIAS pin when I
BIAS
is
sourced into the pin.
Note 6: This is the minimum voltage across the boost capacitor needed to
guarantee full saturation of the internal power switch.
Note 7: Boost current is the current flowing into the BOOST pin with the
pin held 3.3V above input voltage. It flows only during switch on time.
Note 8: Gain is measured with a V
C
swing from 1.15V to 750mV.
Note 9: Switch on resistance is calculated by dividing V
IN
to SW voltage by
the forced current (1.5A LT1976, 1.2A LT1976B). See Typical Performance
Characteristics for the graph of switch voltage at other currents.
Note 10: The C
SS
threshold is defined as the value of current sourced into
the C
SS
pin which results in an increase in sink current from the V
C
pin.
See the Soft-Start section in Applications Information.
Note 11: The PGFB threshold is defined as the percentage of V
REF
voltage
which causes the current source output of the C
T
pin to change from
sinking (below threshold) to sourcing current (above threshold). When
sourcing current, the voltage on the C
T
pin rises until it is clamped
internally. When the clamp is activated, the output of the PG pin will be set
to a high impedance state. When the C
T
clamp is inactive the PG pin will
be set active low with a current sink capability of 200μA.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
I
PK
SW Current Limit 2.4 A
Switch On Resistance (Note 9) ●0.2 0.6 Ω
Switching Frequency BOOST = OPEN ●150 200 260 kHz
Maximum Duty Cycle 90 92 %
Minimum SYNC Amplitude 1.5 2.0 V
SYNC Frequency Range 230 600 kHz
SYNC Input Impedance SYNC = 0.5V 85 kΩ
I
CSS
C
SS
Current Threshold (Note 10) 7 13 20 μA
I
PGFB
PGFB Input Current 25 100 nA
V
PGFB
PGFB Voltage Threshold (Note 11) ●87 90 93 %
I
CT
C
T
Source Current (Note 11) ●1.5 3.6 5.5 μA
C
T
Sink Current (Note 11) 1 2 mA
V
CT
C
T
Voltage Threshold (Note 11) 1.16 1.2 1.26 V
PG Leakage (Note 11) PG = 12V 0.1 1 μA
PG Sink Current (Note 11) PGFB = 1V, PG = 400mV 120 200 μA
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full –40°C to 140°C
operating temperature range, otherwise specifications are at TJ = 25°C. VIN = 12V, SHDN = 12V, BOOST = 15.3V, BIAS = 5V,
FB/PGFB = 1.25V, CSS/SYNC = 0V unless otherwise noted.
LT1976/LT1976B
5
1976bfg
TYPICAL PERFOR A CE CHARACTERISTICS
UW
LT1976 Efficiency and Power Loss
vs Load Current
Oscillator Frequency SHDN Threshold SHDN Pin Current
Shutdown Supply Current
LT1976 Sleep Mode Supply
Current LT1976 Bias Sleep Current
VOLTAGE (V)
1.35
1976 G03
1.20
1.10
1.05
1.00
1.40
1.30
1.25
0.15
TEMPERATURE (°C)
–50 0 50 75–25 25 100 150125
SHDN VOLTAGE (V)
0
0
CURRENT (μA)
1.5
2.5
3.5
10 20 30 40
1976 G04
50
4.5
5.5
1.0
2.0
3.0
4.0
5.0
60
TJ = 25°C
CURRENT (μA)
1976 G05
20
10
5
0
25
15
TEMPERATURE (°C)
–50 0 50 75
–25 25 100 150125
V
IN
= 60V
V
IN
= 42V V
IN
= 12V
CURRENT (μA)
1976 G06
160
80
40
0
200
220
240
120
140
60
20
180
100
V
BIAS
= 0V
V
BIAS
= 5V
TEMPERATURE (°C)
–50 0 50 75
–25 25 100 150125
CURRENT (μA)
1976 G07
160
80
40
0
200
120
140
60
20
180
100
TEMPERATURE (°C)
–50 0 50 75
–25 25 100 150125
LOAD CURRENT (mA)
0.1
EFFICIENCY (%)
POWER LOSS (W)
50
75
5V
3.3V
1000
1976 TA02
25
0110 100 10000
100
0.1
1
0.01
0.001
10
EFFICIENCY
TYPICAL
POWER LOSS
LT1976B Efficiency and Power
Loss vs Load Current
1.20
VOLTAGE (V)
1.21
1.23
1.24
1.25
1.30
1.27
1.22
1.28
1.29
1.26
TEMPERATURE (°C)
–50 0 50 75
1976 G01
–25 25 100 150125
FB Voltage
TEMPERATURE (°C)
–50
150
FREQUENCY (kHz)
160
180
190
200
250
220
050 75
1976 G02
170
230
240
210
–25 25 100 150125
LOAD CURRENT (mA)
0.1
EFFICIENCY (%)
POWER LOSS (W)
50
75
1000
1976 G25
25
0110 100 10000
100
0.1
1
0.01
0.001
10
5V
3.3V
TYPICAL
POWER LOSS
EFFICIENCY
LT1976/LT1976B
6
1976bfg
TYPICAL PERFOR A CE CHARACTERISTICS
UW
Switch Peak Current Limit
Soft-Start Current Threshold
vs FB Voltage
Oscillator Frequency
vs FB Voltage
TEMPERATURE (°C)
–50
1.5
PEAK SWITCH CURRENT (A)
2.0
2.5
3.0
3.5
–25 –0 25 50
1976 G10
75 100 150125
FB VOLTAGE (V)
0
0
CURRENT (μA)
10
20
30
0.2 0.4 0.6 0.8
1976 G11
1.0
40
50
5
15
25
35
45
1.2
SOFT-START
DEFEATED
TJ = 25°C
FB VOLTAGE (V)
0
0
FREQUENCY (kHz)
50
100
150
0.2 0.4 0.6 0.8
1976 G12
1.0
200
250
1.2
TJ = 25°C
Switch On Voltage (VCESAT)
LOAD CURRENT (A)
0
VOLTAGE (mV)
50
150
200
250
500
350
0.7 0.9
1976 G13
100
400
450
300
0.5 1.1 1.3 1.5
TJ = 125°C
TJ = 25°C
TJ = –50°C
INPUT VOLTAGE (V)
0
0
SUPPLY CURRENT (μA)
50
100
10 20 30 40
1976 F05
50
150
25
75
125
60
VOUT = 3.3V
TA = 25°C
LT1976 Supply Current
vs Input Voltage
LOAD CURRENT (mA)
0
INPUT VOLTAGE (V)
5.5
6.0
6.5
1600
1976 G19
5.0
4.5
3.0 400 800 1200
200 600 1000 1400
4.0
3.5
7.5
7.0
5V START
3.3V START
5V RUNNING
3.3V RUNNING
Minimum Input Voltage
LT1976 Burst Mode Threshold
vs Input Voltage
INPUT VOLTAGE (V)
5
LOAD CURRENT (mA)
120
160
200
21
1975 G20
80
40
100
140
180
60
20
097 1311 17 19 23
15 25
VOUT = 3.3V
L = 33μH
COUT = 100μF
PGFB Threshold
VOLTAGE (V)
1976 G08
1.16
1.08
1.04
1.00
1.20
1.12
1.14
1.06
1.02
1.18
1.10
TEMPERATURE (°C)
–50 0 50 75
–25 25 100 150125
PG Sink Current
CURRENT (μA)
1976 G08
200
100
50
0
250
150
TEMPERATURE (°C)
–50 0 50 75
–25 25 100 150125
LT1976/LT1976B
7
1976bfg
TYPICAL PERFOR A CE CHARACTERISTICS
UW
Dropout Operation
INPUT VOLTAGE (V)
2
OUTPUT VOLTAGE (V)
1.5
2.0
2.5
3.5 4.5
1976 G23
1.0
0.5
02.5 3 4
3.0
3.5
4.0 VOUT = 3.3V
BOOST DIODE = DIODES INC. B1100
LOAD CURRENT = 1.25A
LOAD CURRENT = 250mA
INPUT VOLTAGE (V)
2
0
OUTPUT VOLTAGE (V)
1
2
3
4
34 56
1976 G24
5
6
2.5 3.5 4.5 5.5
VOUT = 5V
BOOST DIODE = DIODES INC. B1100
LOAD CURRENT = 1.25A
LOAD CURRENT = 250mA
LT1976 No Load 1A
Step Response
V
OUT
100mV/DIV
I
OUT
500mA/DIV
V
IN
= 12V TIME (1ms/DIV) 1976 G17
V
OUT
= 3.3V
C
OUT
= 47μF
0A
1A
LT1976 Burst Mode Operation
LT1976 Burst Mode Operation
V
OUT
50mV/
DIV
I
SW
100mA/
DIV
V
IN
= 12V TIME (10μs/DIV) 1976 G15
V
OUT
= 3.3V
I
Q
= 100μA
0A
0A
Dropout Operation
Minimum On Time Boost Current vs Load Current
TEMPERATURE (°C)
–50
0
ON TIME (ns)
50
150
200
250
500
350
–10 30 50
1976 G21
100
400
450
300
–30 10 70 90 110
LOAD CURRENT = 0.5A
LOAD CURRENT = 1A
LOAD CURRENT (mA)
0
0
BOOST CURRENT (mA)
5
15
20
25
50
35
400 800 1000
1976 G22
10
40
45
30
200 600 1200 1400
TEMPERATURE (˚C)
–50
V
C
VOLTAGE (V)
400
500
600
70 90 110
1976 G26
300
200
–10 3010–30 50
100
0
700
LT1976B VC Switching Threshold
vs Temperature
V
OUT
50mV/DIV
AC
COUPLED
I
SW
100mA/DIV
V
IN
= 12V TIME (10μs/DIV) 1976 G27
V
OUT
= 3.3V
I
Q
= 1.6mA
LT1976B No Load Operation
(Pulse-Skipping Mode)
V
OUT
50mV/DIV
I
SW
100mA/DIV
V
IN
= 12V TIME (5ms/DIV) 1976 G14
V
OUT
= 3.3V
I
Q
= 100μA
0A
LT1976/LT1976B
8
1976bfg
NC (Pins 1, 3, 5): No Connection. Pins 1, 3, 5 are
electrically isolated from the LT1976. They may be con-
nected to PCB traces to aid in PCB layout.
SW (Pin 2): The SW pin is the emitter of the on-chip power
NPN switch. This pin is driven up to the input pin voltage
during switch on time. Inductor current drives the SW pin
negative during switch off time. Negative voltage is clamped
with the external Schottky catch diode to prevent exces-
sive negative voltages.
V
IN
(Pin 4): This is the collector of the on-chip power NPN
switch. V
IN
powers the internal control circuitry when a
voltage on the BIAS pin is not present. High di/dt edges
occur on this pin during switch turn on and off. Keep the
path short from the V
IN
pin through the input bypass
capacitor, through the catch diode back to SW. All trace
inductance on this path will create a voltage spike at switch
off, adding to the V
CE
voltage across the internal NPN.
BOOST (Pin 6): The BOOST pin is used to provide a drive
voltage, higher than the input voltage, to the internal
bipolar NPN power switch. Without this added voltage, the
typical switch voltage loss would be about 1.5V. The
additional BOOST voltage allows the switch to saturate
and its voltage loss approximates that of a 0.2Ω FET
structure, but with much smaller die area.
C
T
(Pin 7): A capacitor on the C
T
pin determines the amount
of delay time between the PGFB pin exceeding its thresh-
old (V
PGFB
) and the PG pin set to a high impedance state.
When the PGFB pin rises above V
PGFB
, current is sourced
from the C
T
pin into the external capacitor. When the volt-
age on the external capacitor reaches an internal clamp
(V
CT
), the PG pin becomes a high impedance node. The
resultant PG delay time is given by t = C
CT
• V
CT
/I
CT
. If the
voltage on the PGFB pin drops below V
PGFB
, C
CT
will be
discharged rapidly to 0V and PG will be active low with a
200μA sink capability. If the C
T
pin is clamped (Power Good
condition) during normal operation and SHDN is taken low,
the C
T
pin will be discharged and a delay period will occur
when SHDN is returned high. See the Power Good section
in Applications Information for details.
GND (Pins 8, 17): The GND pin connection acts as the
reference for the regulated output, so load regulation will
suffer if the “ground” end of the load is not at the same
voltage as the GND pin of the IC. This condition will occur
when load current or other currents flow through metal
paths between the GND pin and the load ground. Keep the
path between the GND pin and the load ground short and
use a ground plane when possible. The GND pin also acts
as a heat sink and should be soldered (along with the
exposed leadframe) to the copper ground plane to reduce
thermal resistance (see Applications Information).
UU
U
PI FU CTIO S
TYPICAL PERFOR A CE CHARACTERISTICS
UW
LT1976 Step Response
V
OUT
100mV/DIV
I
OUT
500mA/DIV
V
IN
= 12V TIME (1ms/DIV) 1976 G18
V
OUT
= 3.3V
C
OUT
= 47μF
I
DC
= 250mA
0A
1A
LT1976/LT1976B
9
1976bfg
UU
U
PI FU CTIO S
C
SS
(Pin 9): A capacitor from the C
SS
pin to the regulated
output voltage determines the output voltage ramp rate
during start-up. When the current through the C
SS
capaci-
tor exceeds the C
SS
threshold (I
CSS
), the voltage ramp of
the output is limited. The C
SS
threshold is proportional to
the FB voltage (see Typical Performance Characteristics)
and is defeated for FB voltage greater than 0.9V (typical).
See Soft-Start section in Applications Information for
details.
BIAS (Pin 10): The BIAS pin is used to improve efficiency
when operating at higher input voltages and light load
current. Connecting this pin to the regulated output volt-
age forces most of the internal circuitry to draw its
operating current from the output voltage rather than the
input supply. This architecture increases efficiency espe-
cially when the input voltage is much higher than the
output. Minimum output voltage setting for this mode of
operation is 3V.
V
C
(Pin 11): The V
C
pin is the output of the error amplifier
and the input of the peak switch current comparator. It is
normally used for frequency compensation, but can also
serve as a current clamp or control loop override. The V
C
pin sits about 0.45V for light loads and 2.2V at current
limit. The LT1976 clamps the V
C
pin slightly below the
burst threshold during sleep periods for better transient
response. Driving the V
C
pin to ground will disable switch-
ing and also place the LT1976 into sleep mode.
FB (Pin 12): The feedback pin is used to determine the
output voltage using an external voltage divider from the
output that generates 1.25V at the FB pin . When the FB pin
drops below 0.9V, switching frequency is reduced, the
SYNC function is disabled and output ramp rate control is
enabled via the C
SS
pin. See the Feedback section in
Applications Information for details.
PGFB (PIN 13): The PGFB pin is the positive input to a
comparator whose negative input is set at V
PGFB
. When
PGFB is taken above V
PGFB
, current (I
CSS
) is sourced into
the C
T
pin starting the PG delay period. When the voltage
on the PGFB pin drops below V
PGFB
, the C
T
pin is rapidly
discharged resetting the PG delay period. The PGFB volt-
age is typically generated by a resistive divider from the
regulated output or input supply. See Power Good section
in Applications Information for details.
SYNC (Pin 14): The SYNC pin is used to synchronize the
internal oscillator to an external signal. It is directly logic
compatible and can be driven with any signal between
20% and 80% duty cycle. The synchronizing range is
equal to maximum initial operating frequency up to 700kHz.
When the voltage on the FB pin is below 0.9V the SYNC
function is disabled. See the Synchronizing section in
Applications Information for details.
SHDN (Pin 15): The SHDN pin is used to turn off the
regulator and to reduce input current to less than 1μA. The
SHDN pin requires a voltage above 1.3V with a typical
source current of 5μA to take the IC out of the shutdown
state.
PG (Pin 16): The PG pin is functional only when the SHDN
pin is above its threshold, and is active low when the
internal clamp on the C
T
pin is below its clamp level and
high impedance when the clamp is active. The PG pin has
a typical sink capability of 200μA. See the Power Good
section in Applications Information for details.
LT1976/LT1976B
10
1976bfg
BLOCK DIAGRA
W
12 FB
VC
Σ
15
INTERNAL REF
UNDERVOLTAGE
LOCKOUT
THERMAL
SHUTDOWN
SOFT-START
FOLDBACK
DETECT
SLOPE
COMP
ANTISLOPE
COMP
1.2V CT
CLAMP
2.4V
–
+
1.3V
1.25V
SHDN
9CSS
14 SYNC
10 BIAS
4
VIN
SHDN
COMP
–
+
–
+
ERROR
AMP
11
13 PGFB
CT
1.12V –
+
PG
COMP
7
BURST MODE
DETECT
LT1976 ONLY
200kHz
OSCILLATOR
SWITCH
LATCH
CURRENT
COMP
DRIVER
CIRCUITRY
R
Q
SW
S
2
BOOST 6
PG 16
GND 17
PGND
1976 BD
8
VC
CLAMP
The LT1976 is a constant frequency, current mode buck
converter. This means that there is an internal clock and two
feedback loops that control the duty cycle of the power
switch. In addition to the normal error amplifier, there is a
current sense amplifier that monitors switch current on a
cycle-by-cycle basis. A switch cycle starts with an oscilla-
tor pulse which sets the RS latch to turn the switch on. When
switch current reaches a level set by the current compara-
tor the latch is reset and the switch turns off. Output volt-
age control is obtained by using the output of the error
amplifier to set the switch current trip point. This technique
means that the error amplifier commands current to be
delivered to the output rather than voltage. A voltage fed
system will have low phase shift up to the resonant fre-
quency of the inductor and output capacitor, then an abrupt
180° shift will occur. The current fed system will have 90°
phase shift at a much lower frequency, but will not have the
additional 90° shift until well beyond the LC resonant fre-
quency. This makes it much easier to frequency compen-
sate the feedback loop and also gives much quicker tran-
sient response.
Most of the circuitry of the LT1976 operates from an
internal 2.4V bias line. The bias regulator normally draws
Figure 1. LT1976/LT1976B Block Diagram
LT1976/LT1976B
11
1976bfg
BLOCK DIAGRA
W
power from the V
IN
pin, but if the BIAS pin is connected to
an external voltage higher than 3V bias power will be
drawn from the external source (typically the regulated
output voltage). This improves efficiency.
High switch efficiency is attained by using the BOOST pin
to provide a voltage to the switch driver which is higher
than the input voltage, allowing switch to be saturated.
This boosted voltage is generated with an external capaci-
tor and diode.
To further optimize efficiency, the LT1976 automatically
switches to Burst Mode operation in light load situations.
In Burst Mode operation, all circuitry associated with
controlling the output switch is shut down reducing the
input supply current to 45μA.
The only difference between the LT1976 and the LT1976B
is that the LT1976B does not shift into burst mode in light
load situations, eliminating low frequency output ripple at
the expense of light load efficiency.
The LT1976 contains a power good flag with a program-
mable threshold and delay time. A logic-level low on the
SHDN pin disables the IC and reduces input suppy current
to less than 1μA.
APPLICATIO S I FOR ATIO
WUUU
CHOOSING THE LT1976 OR LT1977
The LT1976/LT1976B and LT1977 are high voltage 1.5A
step-down switching regulators. The LT1976 and LT1977
contain circuitry which shifts into burst mode at light loads
reducing quiescent current to typically 100μA. The LT1976B
pulse skips in light load situations, eliminating low fre-
quency burst mode output ripple at the expense of light
load efficiency. The difference between the LT1976/
LT1976B and LT1977 is that the fixed switching frequency
of the LT1976/LT1976B is 200kHz versus 500kHz for the
LT1977. The switching frequency affects: inductor size,
input voltage range in continuous mode operation, effi-
ciency, thermal loss and EMI.
OUTPUT RIPPLE AND INDUCTOR SIZE
Output ripple current is determined by the input to output
voltage ratio, inductor value and switch frequency. Since
the switch frequency of the LT1977 is 2.5 times greater
than that of the LT1976/LT1976B, the inductance used in
the LT1977 application can be 2.5 times lower than the
LT1976/LT1976B while maintaining the same output ripple
current. The lower value used in the LT1977 application
allows the use of a physically smaller inductor.
INPUT VOLTAGE RANGE
The minimum on and off times for all versions of the ic are
equivalent. This results in a narrower range of continuous
mode operation for the LT1977. Typical minimum and
maximum duty cycles are 6% to 92% for the LT1976/
LT1976B and 15% to 90% for the LT1977. Both parts will
regulate up to an input voltage of 60V but the LT1977 will
transistion into pulse-skipping/Burst Mode operation when
the input voltage is above 30V for a 5V output. At outputs
above 10V the LT1977’s input range will be similar to the
LT1976/LT1976B. Lowering the input voltage below the
maximum duty cycle limitation will cause a dropout in
regulation.
Table 1. LT1976/LT1976B/LT1977 Comparison
PARAMETER ADVANTAGE
Minimum Duty Cycle LT1976/LT1976B
Maximum Duty Cycle LT1976/LT1976B
Inductor Size LT1977
Output Capacitor Size LT1977
Efficiency LT1976
EMI LT1976B
Input Range LT1976/LT1976B
Output Ripple LT1977
Light Load Output Ripple LT1976B
LT1976/LT1976B
12
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APPLICATIO S I FOR ATIO
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FEEDBACK PIN FUNCTIONS
The feedback (FB) pin on the LT1976 is used to set output
voltage and provide several overload protection features.
The first part of this section deals with selecting resistors
to set output voltage and the remaining part talks about
frequency foldback and soft-start features. Please read
both parts before committing to a final design.
Referring to Figure 2, the output voltage is determined by
a voltage divider from V
OUT
to ground which generates
1.25V at the FB pin. Since the output divider is a load on the
output care must be taken when choosing the resistor
divider values. For light load applications the resistor
values should be as large as possible to achieve peak
efficiency in Burst Mode operation. Extremely large values
for resistor R1 will cause an output voltage error due to the
50nA FB pin input current. The suggested value for the
output divider resistor (see Figure 2) from FB to ground
(R2) is 100k or less. A formula for R1 is shown below. A
table of standard 1% values is shown in Table 2 for
common output voltages.
RR V
RnA
OUT
12 125
125 2 50
=+
•–.
.•
For LT1976B aplications, the suggested value for R2 is 10k
or less, eliminating output voltage errors due to feedback
pin current and reducing noise susceptibility.
More Than Just Voltage Feedback
The FB pin is used for more than just output voltage
sensing. It also reduces switching frequency and con-
trols the soft-start voltage ramp rate when output voltage
is below the regulated level (see the Frequency Foldback
and Soft-Start Current graphs in Typical Performance
Characteristics).
Frequency foldback is done to control power dissipation in
both the IC and in the external diode and inductor during
short-circuit conditions. A shorted output requires the
switching regulator to operate at very low duty cycles. As
a result the average current through the diode and induc-
tor is equal to the short-circuit current limit of the switch
(typically 2.4A for the LT1976). Minimum switch on time
limitations would prevent the switcher from attaining a
sufficiently low duty cycle if switching frequency were
maintained at 200kHz, so frequency is reduced by about
4:1 when the FB pin voltage drops below 0.4V (see
Frequency Foldback graph). In addition, if the current in
the switch exceeds 1.5 times the current limitations speci-
fied by the V
C
pin, due to minimum switch on time, the
LT1976 will skip the next switch cycle. As the feedback
voltage rises, the switching frequency increases to 200kHz
with 0.95V on the FB pin. During frequency foldback,
external syncronization is disabled to prevent interference
with foldback operation. Frequency foldback does not
affect operation during normal load conditions.
In addition to lowering switching frequency the soft-start
ramp rate is also affected by the feedback voltage. Large
SOFT-START
FOLDBACK
DETECT
200kHz
OSCILLATOR
–
+
ERROR
AMP
1.25V
VC11
FB 12
CSS
VOUT
9
SW
LT1976
C1
R1
R2
1976 F02
2
Figure 2. Feedback Network
Table 2
OUTPUT R1 OUTPUT
VOLTAGE R2 NEAREST (1%) ERROR
(V) (kΩ, 1%) (kΩ)(%)
2.5 100 100 0
3 100 140 0
3.3 100 165 0.38
5 100 300 0
6 100 383 0.63
8 100 536 – 0.63
10 100 698 –0.25
12 100 866 0.63
LT1976/LT1976B
13
1976bfg
APPLICATIO S I FOR ATIO
WUUU
capacitive loads or high input voltages can cause a high
input current surge during start-up. The soft-start func-
tion reduces input current surge by regulating switch
current via the V
C
pin to maintain a constant voltage ramp
rate (dV/dt) at the output. A capacitor (C1 in Figure 2) from
the C
SS
pin to the output determines the maximum output
dV/dt. When the feedback voltage is below 0.4V, the V
C
pin
will rise, resulting in an increase in switch current and
output voltage. If the dV/dt of the output causes the current
through the C
SS
capacitor to exceed I
CSS
the V
C
voltage is
reduced resulting in a constant dV/dt at the output. As the
feedback voltage increases I
CSS
increases, resulting in an
increased dV/dt until the soft-start function is defeated
with 0.9V present at the FB pin. The soft-start function
does not affect operation during normal load conditions.
However, if a momentary short (brown out condition) is
present at the output which causes the FB voltage to drop
below 0.9V, the soft-start circuitry will become active.
INPUT CAPACITOR
Step-down regulators draw current from the input supply
in pulses. The rise and fall times of these pulses are very
fast. The input capacitor is required to reduce the voltage
ripple this causes at the input of LT1976 and force the
switching current into a tight local loop, thereby minimiz-
ing EMI. The RMS ripple current can be calculated from:
II
VVVV
RIPPLE RMS OUT
IN OUT IN OUT()
–=
()
Ceramic capacitors are ideal for input bypassing. At 200kHz
switching frequency input capacitor values in the range of
4.7μF to 20μF are suitable for most applications. If opera-
tion is required close to the minimum input required by the
LT1976 a larger value may be required. This is to prevent
excessive ripple causing dips below the minimum operat-
ing voltage resulting in erratic operation.
Input voltage transients caused by input voltage steps or
by hot plugging the LT1976 to a pre-powered source such
as a wall adapter can exceed maximum V
IN
ratings. The
sudden application of input voltage will cause a large
surge of current in the input leads that will store energy in
the parasitic inductance of the leads. This energy will
cause the input voltage to swing above the DC level of input
power source and it may exceed the maximum voltage
rating of the input capacitor and LT1976. All input voltage
transient sequences should be observed at the V
IN
pin of
the LT1976 to ensure that absolute maximum voltage
ratings are not violated.
The easiest way to suppress input voltage transients is to
add a small aluminum electrolytic capacitor in parallel with
the low ESR input capacitor. The selected capacitor needs
to have the right amount of ESR to critically damp the
resonant circuit formed by the input lead inductance and
the input capacitor. The typical values of ESR will fall in the
range of 0.5Ω to 2Ω and capacitance will fall in the range
of 5μF to 50μF.
If tantalum capacitors are used, values in the 22μF to
470μF range are generally needed to minimize ESR and
meet ripple current and surge ratings. Care should be
taken to ensure the ripple and surge ratings are not
exceeded. The AVX TPS and Kemet T495 series are surge
rated AVX recommends derating capacitor operating volt-
age by 2:1 for high surge applications.
OUTPUT CAPACITOR
The output capacitor is normally chosen by its effective
series resistance (ESR) because this is what determines
output ripple voltage. To get low ESR takes volume, so
physically smaller capacitors have higher ESR. The ESR
range for typical LT1976 applications is 0.05Ω to 0.2Ω. A
typical output capacitor is an AVX type TPS, 100μF at 10V,
with a guaranteed ESR less than 0.1Ω. This is a “D” size
surface mount solid tantalum capacitor. TPS capacitors
are specially constructed and tested for low ESR, so they
give the lowest ESR for a given volume. The value in
microfarads is not particularly critical and values from
22μF to greater than 500μF work well, but you cannot
cheat Mother Nature on ESR. If you find a tiny 22μF solid
tantalum capacitor, it will have high ESR and output ripple
voltage could be unacceptable. Table 3 shows some
typical solid tantalum surface mount capacitors.
LT1976/LT1976B
14
1976bfg
APPLICATIO S I FOR ATIO
WUUU
filter capacitor C
F
in parallel with the R
C
/C
C
network, along
with a small feedforward capacitor C
FB
, is suggested to
control possible ripple at the V
C
pin. The LT1976 can be
stabilized using a 47μF ceramic output capacitor and V
C
component values of C
C
= 0.047μF, R
C
= 12.5k, C
F
= 100pF
and C
FB
= 27pF.
OUTPUT RIPPLE VOLTAGE
Figure 3 shows a typical output ripple voltage waveform
for the LT1976. Ripple voltage is determined by the
impedance of the output capacitor and ripple current
through the inductor. Peak-to-peak ripple current through
the inductor into the output capacitor is:
IVVV
VLf
OUT IN OUT
IN
P-P
=
()
()()()
–
For high frequency switchers the ripple current slew rate
is also relevant and can be calculated from:
di
dt
V
L
IN
=
Peak-to-peak output ripple voltage is the sum of a triwave
created by peak-to-peak ripple current times ESR and a
square wave created by parasitic inductance (ESL) and
ripple current slew rate. Capacitive reactance is assumed
to be small compared to ESR or ESL.
V I ESR ESL di
dt
RIPPLE =
()( )
+
()
P-P
Figure 3. LT1976 Ripple Voltage Waveform
V
OUT
20mV/DIV
47μF TANTALUM
ESR 100mΩ
V
OUT
20mV/DIV
47μF CERAMIC
V
SW
5V/DIV
V
IN
= 12V 1μs/DIV 1976 F03
V
OUT
= 3.3V
I
LOAD
= 1A
L = 33μH
Table 3. Surface Mount Solid Tantalum Capacitor ESR
and Ripple Current
E CASE SIZE ESR MAX (Ω) RIPPLE CURRENT (A)
AVX TPS 0.1 to 0.3 0.7 to 1.1
D CASE SIZE
AVX TPS 0.1 to 0.3 0.7 to 1.1
C CASE SIZE
AVX TPS 0.2 0.5
Many engineers have heard that solid tantalum capacitors
are prone to failure if they undergo high surge currents.
This is historically true and type TPS capacitors are
specially tested for surge capability but surge ruggedness
is not a critical issue with the output capacitor. Solid
tantalum capacitors fail during very high turn-on surges
which do not occur at the output of regulators. High
discharge surges, such as when the regulator output is
dead shorted, do not harm the capacitors.
Unlike the input capacitor RMS, ripple current in the
output capacitor is normally low enough that ripple cur-
rent rating is not an issue. The current waveform is
triangular with a typical value of 200mA
RMS
. The formula
to calculate this is:
Output capacitor ripple current (RMS)
IVVV
LfV
RIPPLE RMS OUT IN OUT
IN
()
.–
=
()( )
()()( )
=
029
12
I
P-P
CERAMIC CAPACITORS
Higher value, lower cost ceramic capacitors are now
becoming available. They are generally chosen for their
good high frequency operation, small size and very low
ESR (effective series resistance). Low ESR reduces output
ripple voltage but also removes a useful zero in the loop
frequency response, common to tantalum capacitors. To
compensate for this a resistor R
C
can be placed in series
with the V
C
compensation capacitor C
C
(Figure 10). Care
must be taken however since this resistor sets the high
frequency gain of the error amplifier including the gain at
the switching frequency. If the gain of the error amplifier
is high enough at the switching frequency output ripple
voltage (although smaller for a ceramic output capacitor)
may still affect the proper operation of the regulator. A
LT1976/LT1976B
15
1976bfg
APPLICATIO S I FOR ATIO
WUUU
Example: with V
IN
= 12V, V
OUT
= 3.3V, L = 33μH, ESR =
0.08Ω, ESL = 10nH:
IP-P =
()( )
()
−
()()
=
==
33 12 33
12 33 6 200 3 0 362
12
33 5 363 5
.–. .
.– .
ee A
di
dt e e
V
RIPPLE
= (0.362A)(0.08) + (10e – 9)(363e3)
= 0.0289 + 0.003 = 32mV
P-P
MAXIMUM OUTPUT LOAD CURRENT
Maximum load current for a buck converter is limited by
the maximum switch current rating (I
PK
). The current
rating for the LT1976 is 1.5A. Unlike most current mode
converters, the LT1976 maximum switch current limit
does not fall off at high duty cycles. Most current mode
converters suffer a drop off of peak switch current for duty
cycles above 50%. This is due to the effects of slope
compensation required to prevent subharmonic oscilla-
tions in current mode converters. (For detailed analysis,
see Application Note 19.)
The LT1976 is able to maintain peak switch current limit
over the full duty cycle range by using patented circuitry to
cancel the effects of slope compensation on peak switch
current without affecting the frequency compensation it
provides.
Maximum load current would be equal to maximum
switch current for an infinitely large inductor, but with
finite inductor size, maximum load current is reduced by
one-half peak-to-peak inductor current. The following
formula assumes continuous mode operation, implying
that the term on the right (I
P-P
/2) is less than I
OUT
.
II
VVV
LfV II
OUT MAX PK OUT IN OUT
IN PK P
()
–––=
()( )
()()( )
=
2
-P
2
Discontinuous operation occurs when:
IVVV
LfV
OUT DIS OUT IN OUT
IN
()
–
()()( )
≤
()
2
For V
OUT
= 5V, V
IN
= 8V and L = 20μH:
Iee
A
OUT MAX()
.– –
–
.–. .
=
()( )
()()()
==
15 58 5
2 20 6 200 3 8
15 024 126
Note that there is less load current available at the higher
input voltage because inductor ripple current increases. At
V
IN
= 15V, duty cycle is 33% and for the same set of
conditions:
Iee
A
OUT MAX().– –
–
.–. .
=
()( )
()()()
==
15 515 5
2 20 6 200 3 15
15 042 108
To calculate actual peak switch current in continuous
mode with a given set of conditions, use:
II
VVV
LfV
SW PK OUT
OUT IN OUT
IN
()
–
=+
()
()()( )
2
If a small inductor is chosen which results in discontinous
mode operation over the entire load range, the maximum
load current is equal to:
IIfLV
VVV
OUT MAX PK IN
OUT IN OUT
() –
=
()()( )
()( )
22
2
CHOOSING THE INDUCTOR
For most applications the output inductor will fall in the
range of 15μH to 100μH. Lower values are chosen to
reduce physical size of the inductor. Higher values allow
more output current because they reduce peak current
seen by the LT1976 switch, which has a 1.5A limit. Higher
values also reduce output ripple voltage and reduce core
loss.
When choosing an inductor you might have to consider
maximum load current, core and copper losses, allow-
able component height, output voltage ripple, EMI, fault
current in the inductor, saturation and of course cost.
The following procedure is suggested as a way of han-
dling these somewhat complicated and conflicting
requirements.
LT1976/LT1976B
16
1976bfg
APPLICATIO S I FOR ATIO
WUUU
1. Choose a value in microhenries from the graph of
maximum load current. Choosing a small inductor with
lighter loads may result in discontinuous mode of
operation, but the LT1976 is designed to work well in
either mode.
Table 4. Inductor Selection Criteria
VENDOR/
PART NUMBER VALUE (μH) I
RMS
(A) DCR (Ω) HEIGHT (mm)
Coiltronics
UP2B-150 15 2.4 0.041 6
UP2B-330 33 1.7 0.062 6
UP2B-470 47 1.4 0.139 6
UP2B-680 68 1.2 0.179 6
UP2B-101 100 0.95 0.271 6
UP3B-150 15 3.9 0.032 6.8
UP3B-330 33 2.4 0.069 6.8
UP3B-470 47 1.9 0.101 6.8
UP3B-680 68 1.6 0.156 6.8
UP3B-101 100 1.4 0.205 6.8
Sumida
CDRH8D28-150M 15 2.2 0.053 3
CDRH124-150M 15 3.2 0.05 4.5
CDRH127-150M 15 4.5 0.02 8
CDRH8D28-330M 33 1.4 0.122 3
CDRH124-330M 33 2.7 0.97 4.5
CDRH127-330M 33 3.0 0.048 8
CDRH8D28-470M 47 1.25 0.150 3
CDRH125-470M 47 1.8 0.058 6
CDRH127-470M 47 2.5 0.076 8
CDRH124-680M 68 1.5 0.228 4.5
CDRH127-680M 68 2.1 0.1 8
CDRH124-101M 100 1.2 0.30 4.5
CDRH127-101M 100 1.7 0.17 8
Coilcraft
DT3308P-153 15 2.0 0.1 3
DT3308P-333 33 1.4 0.3 3
DT3308P-473 47 1 0.47 3
Assume that the average inductor current is equal to
load current and decide whether or not the inductor
must withstand continuous fault conditions. If maxi-
mum load current is 0.5A, for instance, a 0.5A inductor
may not survive a continuous 2A overload condition.
For applications with a duty cycle above 50%, the
inductor value should be chosen to obtain an inductor
ripple current of less than 40% of the peak switch
current.
2. Calculate peak inductor current at full load current to
ensure that the inductor will not saturate. Peak current
can be significantly higher than output current, especially
with smaller inductors and lighter loads, so don’t omit
this step. Powdered iron cores are forgiving because they
saturate softly, whereas ferrite cores saturate abruptly.
Other core materials fall somewhere in between. The
following formula assumes continuous mode of opera-
tion, but it errs only slightly on the high side for discon-
tinuous mode, so it can be used for all conditions.
II
VVV
fLV
PEAK OUT OUT IN OUT
IN
=+
()
()()( )
–
2
V
IN
= maximum input voltage
f = switching frequency, 200kHz
3. Decide if the design can tolerate an “open” core geom-
etry like a rod or barrel, which have high magnetic field
radiation, or whether it needs a closed core like a toroid
to prevent EMI problems. This is a tough decision
because the rods or barrels are temptingly cheap and
small and there are no helpful guidelines to calculate
when the magnetic field radiation will be a problem.
4. After making an initial choice, consider the secondary
things like output voltage ripple, second sourcing, etc.
Use the experts in the Linear Technology’s applications
department if you feel uncertain about the final choice.
They have experience with a wide range of inductor
types and can tell you about the latest developments in
low profile, surface mounting, etc.
LT1976/LT1976B
17
1976bfg
APPLICATIO S I FOR ATIO
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Short-Circuit Considerations
The LT1976 is a current mode controller. It uses the V
C
node voltage as an input to a current comparator which
turns off the output switch on a cycle-by-cycle basis as
this peak current is reached. The internal clamp on the V
C
node, nominally 2.2V, then acts as an output switch peak
current limit. This action becomes the switch current limit
specification. The maximum available output power is
then determined by the switch current limit.
A potential controllability prod}m could occur under short-
circuit conditions. If the power supply output is short
circuited, the feedback amplifier responds to the low
output voltage by raising the control voltage, V
C
, to its
peak current limit value. Ideally, the output switch would
be turned on, and then turned off as its current exceeded
the value indicated by V
C
. However, there is finite response
time involved in both the current comparator and turn-off
of the output switch. These result in a minimum on time
t
ON(MIN).
When combined with the large ratio of V
IN
to
(V
F
+ I • R), the diode forward voltage plus inductor I • R
voltage drop, the potential exists for a loss of control.
Expressed mathematically the requirement to maintain
control is:
ft VIR
V
ON F
IN
••
≤+
where:
f = switching frequency
t
ON
= switch on time
V
F
= diode forward voltage
V
IN
= Input voltage
I • R = inductor I • R voltage drop
If this condition is not observed, the current will not be
limited at I
PK
but will cycle-by-cycle ratchet up to some
higher value. Using the nominal LT1976 clock frequency
of 200kHz, a V
IN
of 40V and a (V
F
+ I • R) of say 0.7V, the
maximum t
ON
to maintain control would be approximately
90ns, an unacceptably short time.
The solution to this dilemma is to slow down the oscillator
to allow the current in the inductor to drop to a sufficiently
low value such that the current doesn’t continue to ratchet
higher. When the FB pin voltage is abnormally low thereby
indicating some sort of short-circuit condition, the oscil-
lator frequency will be reduced. Oscillator frequency is
reduced by a factor of 4 when the FB pin voltage is below
0.4V and increases linearly to its typical value of 200kHz at
a FB voltage of 0.95V (see Typical Performance Character-
istics). In addition, if the current in the switch exceeds 1.5
• I
PK
current demanded by the V
C
pin, the LT1976 will skip
the next on cycle effectively reducing the oscillator fre-
quency by a factor of 2. These oscillator frequency reduc-
tions during short-circuit conditions allow the LT1976 to
maintain current control.
SOFT-START
For applications where [V
IN
/(V
OUT
+ V
F
)] ratios > 10 or
large input surge currents can’t be tolerated, the LT1976
soft-start feature should be used to control the output
capacitor charge rate during start-up, or during recovery
from an output short circuit thereby adding additional
control over peak inductor current. The soft-start function
limits the switch current via the V
C
pin to maintain a
constant voltage ramp rate (dV/dt) at the output capacitor.
A capacitor (C1 in Figure 2) from the C
SS
pin to the
regulated output voltage determines the output voltage
ramp rate. When the current through the C
SS
capacitor
exceeds the C
SS
threshold (I
CSS
), the voltage ramp of the
output capacitor is limited by reducing the V
C
pin voltage.
The C
SS
threshold is proportional to the FB voltage (see
Typical Performance Characteristics) and is defeated for
FB voltages greater than 0.9V (typical). The output dV/dt
can be approximated by:
dV
dt
I
C
CSS
SS
=
but actual values will vary due to start-up load conditions,
compensation values and output capacitor selection.
LT1976/LT1976B
18
1976bfg
APPLICATIO S I FOR ATIO
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Burst Mode OPERATION (LT1976 ONLY)
To enhance efficiency at light loads, the LT1976 automati-
cally switches to Burst Mode operation which keeps the
output capacitor charged to the proper voltage while mini-
mizing the input quiescent current. During Burst Mode
operation, the LT1976 delivers short bursts of current to
the output capacitor followed by sleep periods where the
output power is delivered to the load by the output capaci-
tor. In addition, V
IN
and BIAS quiescent currents are re-
duced to typically 45μA and 125μA respectively during the
sleep time. As the load current decreases towards a no
load condition, the percentage of time that the LT1976
operates in sleep mode increases and the average input
current is greatly reduced resulting in higher efficiency.
The minimum average input current depends on the V
IN
to
V
OUT
ratio, V
C
frequency compensation, feedback divider
network and Schottky diode leakage. It can be approxi-
mated by the following equation:
IIIV
V
III
IN AVG VINS SHDN OUT
IN
BIASS FB S
()
≅+ +
⎛
⎝
⎜⎞
⎠
⎟++
()
()
η
where
I
VINS
= input pin current in sleep mode
V
OUT
= output voltage
V
IN
=
input voltage
I
BIASS
= BIAS pin current in sleep mode
I
FB
= feedback network current
I
S
= catch diode reverse leakage at V
OUT
η = low current efficiency (non Burst Mode operation)
Example: For V
OUT
= 3.3V, V
IN
= 12V
IAA AA
IN AVG()
..
=μ+μ+
⎛
⎝
⎜⎞
⎠
⎟μ+ μ+
45 5 33
12
125 12 5 0..
.
5
08
45 5 47 97
μ
()
()
=μ+μ+μ=μ
A
AA A A
During the sleep portion of the Burst Mode cycle, the V
C
pin voltage is held just below the level needed for normal
operation to improve transient response. See the Typical
Performance Characteristics section for burst and tran-
sient response waveforms.
If a no load condition can be anticipated, the supply current
can be further reduced by cycling the SHDN pin at a rate
higher than the natural no load burst frequency. Figure 6
shows Burst Mode operation with the SHDN pin. V
OUT
burst ripple is maintained while the average supply current
Figure 6. Burst Mode with Shutdown Pin
V
OUT
50mV/DIV
V
SHDN
2V/DIV
I
SW
500mA/DIV V
IN
= 12V TIME (50ms/DIV) 1976 G16
V
OUT
= 3.3V
I
Q
= 15μA
Figure 5. IQ vs VIN
INPUT VOLTAGE (V)
0
0
SUPPLY CURRENT (μA)
50
100
10 20 30 40
1976 F05
50
150
25
75
125
60
V
OUT
= 3.3V
T
A
= 25°C
Figure 4. VOUT dV/dt
V
OUT
0.5V/DIV
C
SS
= GND
C
SS
= 0.1μFC
SS
= 0.1μF
C
OUT
= 47μF TIME (1ms/DIV) 1976 F04
I
LOAD
= 200mA
V
IN
= 12V
LT1976/LT1976B
19
1976bfg
APPLICATIO S I FOR ATIO
WUUU
drops to 15μA. The PG pin will be active low during the
“on” portion of the SHDN waveform due to the C
T
capaci-
tor discharge when SHDN is taken low. See the Power
Good section for further information.
CATCH DIODE
The catch diode carries load current during the SW off
time. The average diode current is therefore dependent on
the switch duty cycle. At high input to output voltage ratios
the diode conducts most of the time. As the ratio ap-
proaches unity the diode conducts only a small fraction of
the time. The most stressful condition for the diode is
when the output is short circuited. Under this condition the
diode must safely handle I
PEAK
at maximum duty cycle.
To maximize high and low load current efficiency a fast
switching diode with low forward drop and low reverse
leakage should be used. Low reverse leakage is critical to
maximize low current efficiency since its value over tem-
perature can potentially exceed the magnitude of the
LT1976 supply current. Low forward drop is critical for
high current efficiency since the loss is proportional to
forward drop.
These requirements result in the use of a Schottky type
diode. DC switching losses are minimized due to its low
forward voltage drop and AC behavior is benign due to its
lack of a significant reverse recovery time. Schottky diodes
are generally available with reverse voltage ratings of 60V
and even 100V and are price competitive with other types.
The effect of reverse leakage and forward drop on effi-
ciency for various Schottky diodes is shown in Table 4. As
can be seen these are conflicting parameters and the user
must weigh the importance of each specification in choos-
ing the best diode for the application.
The use of so-called “ultrafast” recovery diodes is gener-
ally not recommended. When operating in continuous
mode, the reverse recovery time exhibited by “ultrafast”
diodes will result in a slingshot type effect. The power
internal switch will ramp up V
IN
current into the diode in an
attempt to get it to recover. Then, when the diode has
finally turned off, some tens of nanoseconds later, the V
SW
node voltage ramps up at an extremely high dV/dt, per-
haps 5V to even 10V/ns! With real world lead inductances
the V
SW
node can easily overshoot the V
IN
rail. This can
result in poor RFI behavior and, if the overshoot is severe
enough, damage the IC itself.
BOOST PIN
For most applications the boost components are a 0.33μF
capacitor and a MMSD914 diode. The anode is typically
connected to the regulated output voltage to generate a
voltage approximately V
OUT
above V
IN
to drive the output
stage (Figure 7a). However, the output stage discharges
the boost capacitor during the on time of the switch. The
output driver requires at least 2.5V of headroom through-
out this period to keep the switch fully saturated. If the
output voltage is less than 3.3V it is recommended that an
alternate boost supply is used. The boost diode can be
connected to the input (Figure 7b) but care must be taken
to prevent the boost voltage (V
BOOST
= V
IN
• 2) from
exceeding the BOOST pin absolute maximum rating. The
additional voltage across the switch driver also increases
power loss and reduces efficiency. If available, an inde-
pendent supply can be used to generate the required
BOOST voltage (Figure 7c). Tying BOOST to V
IN
or an
independent supply may reduce efficiency but it will re-
duce the minimum V
IN
required to start-up with light
loads. If the generated BOOST voltage dissipates too
much power at maximum load, the BOOST voltage the
LT1976 sees can be reduced by placing a Zener diode in
series with the BOOST diode (Figure 7a option).
Table 5. Catch Diode Selection Criteria
I
Q
at 125°C EFFICIENCY
LEAKAGE V
IN
=12V V
IN
=12V
V
OUT
= 3.3V V
F
AT 1A V
OUT
= 3.3 V
OUT
= 3.3V
DIODE 25°C 125°C25°C 125°CI
L
= 0A I
L
= 1A
IR 10BQ100 0.0μA59μA 0.72V 0.58V 125μA 74.1%
Diodes Inc. 0.1μA 242μA 0.48V 0.41V 215μA 82.8%
B260SMA
Diodes Inc. 0.2μA 440μA 0.45V 0.36V 270μA 83.6%
B360SMB
IR 1μA 1.81mA 0.42V 0.34V 821μA 83.7%
MBRS360TR
IR 30BQ100 1.7μA 2.64mA 0.40V 0.32V 1088μA 84.5%
LT1976/LT1976B
20
1976bfg
APPLICATIO S I FOR ATIO
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A 0.33μF boost capacitor is recommended for most appli-
cations. Almost any type of film or ceramic capacitor is
suitable but the ESR should be <1Ω to ensure it can be fully
recharged during the off time of the switch. The capacitor
value is derived from worst-case conditions of 4700ns on
time, 42mA boost current and 0.7V discharge ripple. The
boost capacitor value could be reduced under less de-
manding conditions but this will not improve circuit opera-
tion or efficiency. Under low input voltage and low load
conditions a higher value capacitor and Schottky boost
diode will reduce discharge ripple and improve start-up
and dropout operation.
SHUTDOWN FUNCTION AND UNDERVOLTAGE
LOCKOUT
The SHDN pin on the LT1976 controls the operation of the
IC. When the voltage on the SHDN pin is below the 1.2V
shutdown threshold the LT1976 is placed in a “zero”
supply current state. Driving the SHDN pin above the
shutdown threshold enables normal operation. The SHDN
pin has an internal sink current of 3μA.
In addition to the shutdown feature, the LT1976 has an
undervoltage lockout function. When the input voltage is
below 2.4V, switching will be disabled. The undervoltage
lockout threshold doesn’t have any hysteresis and is
mainly used to insure that all internal voltages are at the
correct level before switching is enabled. If an undervolt-
age lockout function with hysteresis is needed to limit
input current at low V
IN
to V
OUT
ratios refer to Figure 8 and
the following:
VR
V
R
V
RIV
VVR
R
UVLO SHDN SHDN SHDN SHDN
HYST OUT
=++
⎛
⎝
⎜⎞
⎠
⎟+
=
()
132
1
3
R1 should be chosen to minimize quiescent current during
normal operation by the following equation:
RVV
I
IN
SHDN MAX
12
15
=
()
()
–
.()
Example:
RAM
RMM
AM
k
112 2
155 13
3513
165
113
649
408
=μ
()
=Ω
=Ω
()
=Ω Ω
ΩμΩ
=
–
..
..
––.
.
(Nearest 1% 6.49M )
R2 = 1.3
7 – 1.3
1.3M
(Nearest 1% 412k)
BOOST
LT1976
VBOOST – VSW = VOUT
VBOOST(MAX) = VIN + VOUT
VIN VOUT
OPTIONAL
(7a)
VIN
SWGND
BOOST
LT1976
VBOOST – VSW = VDC
VBOOST(MAX) = VDC + VIN
VIN VDC
DSS
1976 F07
VOUT
(7c)
VIN
SWGND
BOOST
LT1976
VBOOST – VSW = VIN
VBOOST(MAX) = 2VIN
VIN
VOUT
(7b)
VIN
SWGND
Figure 7. BOOST Pin Configurations
LT1976/LT1976B
21
1976bfg
APPLICATIO S I FOR ATIO
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See the Typical Performance Characteristics section for
graphs of SHDN and V
IN
currents verses input voltage.
SYNCHRONIZING
Oscillator synchronization to an external input is achieved
by connecting a TTL logic-compatible square wave with a
duty cycle between 20% and 80% to the LT1976 SYNC
pin. The synchronizing range is equal to initial operating
frequency up to 700kHz. This means that minimum
practical sync frequency is equal to the worst-case high
self-oscillating frequency (230kHz), not the typical oper-
ating frequency of 200kHz. Caution should be used when
synchronizing above 230kHz because at higher sync
frequencies the amplitude of the internal slope compen-
sation used to prevent subharmonic switching is re-
duced. This type of subharmonic switching only occurs at
input voltages less than twice output voltage. Higher
inductor values will tend to eliminate this problem. See
Frequency Compensation section for a discussion of an
entirely different cause of subharmonic switching before
assuming that the cause is insufficient slope compensa-
tion. Application Note 19 has more details on the theory
of slope compensation.
If the FB pin voltage is below 0.9V (power-up or output
short-circuit conditions) the sync function is disabled.
This allows the frequency foldback to operate to avoid and
hazardous conditions for the SW pin.
If the synchronization signal is present during Burst Mode
operation, synchronization will occur during the burst
portion of the output waveform. Synchronizing the LT1976
during Burst Mode operation may alter the natural burst
frequency which can lead to jitter and increased ripple in
the burst waveform. Synchronizing the LT1976B during
pulse skip operation may also increase output ripple.
If no synchronization is required this pin should be con-
nected to ground.
POWER GOOD
The LT1976 contains a power good block which consists
of a comparator, delay timer and active low flag that allows
the user to generate a delayed signal after the power good
threshold is exceeded.
Referring to Figure 2, the PGFB pin is the positive input to
a comparator whose negative input is set at V
PGFB
. When
PGFB is taken above V
PGFB
, current (I
CSS
) is sourced into
the C
T
pin starting the delay period. When the voltage on
the PGFB pin drops below V
PGFB
the C
T
pin is rapidly
discharged resetting the delay period. The PGFB voltage is
typically generated by a resistive divider from the regu-
lated output or input supply.
The capacitor on the C
T
pin determines the amount of
delay time between the PGFB pin exceeding its threshold
(V
PGFB
) and the PG pin set to a high impedance state.
When the PGFB pin rises above V
PGFB
current is sourced
Figure 8. Undervoltage Lockout
ENABLE
1.3V
1976 F08
3μA
SHDN
R2
2.4V
–
+
SHDN
COMP
–
+
VIN
COMP
15
VIN
VOUT
LT1976
4
R1
R3
LT1976/LT1976B
22
1976bfg
APPLICATIO S I FOR ATIO
WUUU
V
IN
PG
PGFB
LT1976
PG at 80% VOUT with 100ms Delay
0.27μF
C
OUT
C
OUT
200k
V
OUT
= 3.3V
153k
12k
100k
FB
C
T
V
IN
PG
PGFB
LT1976
VOUT Disconnect at 80% VOUT
with 100ms Delay
0.27μF
200k
V
OUT
= 3.3V
153k
12k
100k
FB
C
T
V
IN
PG
PGFB
LT1976
PG at VIN > 4V with 100ms Delay
0.27μF
V
OUT
= 3.3V
200k
511k
200k
100k
165k
FB
C
T
V
IN
PG
PGFB
LT1976
VOUT Disconnect 3.3V Logic Signal
with 100μs Delay
270pF
200k
V
OUT
= 12V
1976 F10
866k
100k
FB
C
T
C
OUT
C
OUT
Figure 10. Power Good Circuits
Figure 9. Power Good
V
OUT
500mV/DIV
PG
100k TO V
IN
V
CT
500mV/DIV
V
SHDN
2V/DIV
TIME (10ms/DIV) 1976 F09
(I
CT
) from the C
T
pin into the external capacitor. When the
voltage on the external capacitor reaches an internal clamp
(V
CT
), the PG pin becomes a high impedance node. The
resultant PG delay time is given by t = C
CT
•(V
CT
)/(I
CT
). If
the voltage on the PGFB pin drops below its V
PGFB
, C
CT
will
be discharged rapidly and PG will be active low with a
200μA sink capability. If the SHDN pin is taken below its
threshold during normal operation, the C
T
pin will be
discharged and PG inactive, resulting in a non Power Good
cycle when SHDN is taken above its threshold. Figure 9
shows the power good operation with PGFB connected to
FB and the capacitance on C
T
= 0.1μF. The PGOOD pin has
a limited amount of drive capability and is susceptible to
noise during start-up and Burst Mode operation. If erratic
operation occurs during these conditions a small filter
capacitor from the PGOOD pin to ground will ensure
proper operation. Figure 10 shows several different con-
figurations for the LT1976 Power Good circuitry.
LT1976/LT1976B
23
1976bfg
APPLICATIO S I FOR ATIO
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Figure 12. Suggested Layout
NC
R2
C2
C5
R1
R3
C4
SW
NC
VIN
NC
BOOST
CT
GND
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
PG
SHDN
SYNC
PGFB
FB
VC
BIAS
CSS
1976 F12
C3
GND
GND
D1
L1
VOUT
C1
C2 D2
MINIMIZE
D1-C3
LOOP
VIN
KELVIN SENSE
FEEDBACK
TRACE AND
KEEP SEPARATE
FROM BIAS TRACE
CONNECT PIN 8 GND TO THE
PIN 17 EXPOSED PAD GND
PLACE VIA's UNDER EXPOSED
PAD TO A BOTTOM PLANE TO
ENHANCE THERMAL
CONDUCTIVITY
LT1976
Figure 11. High Speed Switching Path
C2 C1
1976 F11
D1
L1
VIN
LT1976 VOUT
VIN
SW
42
HIGH
FREQUENCY
CIRCULATION
PATH
+
LOAD
LAYOUT CONSIDERATIONS
As with all high frequency switchers, when considering
layout, care must be taken in order to achieve optimal
electrical, thermal and noise performance. For maximum
efficiency switch rise and fall times are typically in the
nanosecond range. To prevent noise both radiated and
conducted the high speed switching current path, shown
in Figure 11, must be kept as short as possible. This is
implemented in the suggested layout of Figure 12. Short-
ening this path will also reduce the parasitic trace induc-
tance of approximately 25nH/inch. At switch off, this
parasitic inductance produces a flyback spike across the
LT1976 switch. When operating at higher currents and
input voltages, with poor layout, this spike can generate
voltages across the LT1976 that may exceed its absolute
maximum rating. A ground plane should always be used
under the switcher circuitry to prevent interplane coupling
and overall noise.
The V
C
and FB components should be kept as far away as
possible from the switch and boost nodes. The LT1976
pinout has been designed to aid in this. The ground for
these components should be separated from the switch
current path. Failure to do so will result in poor stability or
subharmonic like oscillation.
LT1976/LT1976B
24
1976bfg
APPLICATIO S I FOR ATIO
WUUU
Board layout also has a significant effect on thermal
resistance. Pin 8 and the exposed die pad, Pin 17, are a
continuous copper plate that runs under the LT1976 die.
This is the best thermal path for heat out of the package.
Reducing the thermal resistance from Pin 8 and exposed
pad onto the board will reduce die temperature and in-
crease the power capability of the LT1976. This is achieved
by providing as much copper area as possible around the
exposed pad. Adding multiple solder filled feedthroughs
under and around this pad to an internal ground plane will
also help. Similar treatment to the catch diode and coil
terminations will reduce any additional heating effects.
THERMAL CALCULATIONS
Power dissipation in the LT1976 chip comes from four
sources: switch DC loss, switch AC loss, boost circuit
current, and input quiescent current. The following formu-
las show how to calculate each of these losses. These
formulas assume continuous mode operation, so they
should not be used for calculating efficiency at light load
currents.
Switch loss:
PRI V
VtIVf
SW SW OUT OUT
IN EFF OUT IN
=
()( )
+
()
()()()
2
12/
Boost current loss:
PVI
V
BOOST OUT OUT
IN
=
()
()
2
36/
Quiescent current loss: (LT1976)
P
Q
= V
IN
(0.0015) + V
OUT
(0.003)
R
SW
= switch resistance (≈0.3 when hot )
t
EFF
= effective switch current/voltage overlap time
(t
r
+ t
f
+ t
IR
+ t
IF
)
t
r
= (V
IN
/1.7)ns
t
f
= (V
IN
/1.2)ns
t
IR
= t
IF
= (I
OUT
/0.05)ns
f = switch frequency
Example: with V
IN
= 40V, V
OUT
= 5V and I
OUT
= 1A:
Pee
W
PW
PW
SW
BOOST
Q
=
()()()
+
()
()
()( )( )
+=
=
()
()
=
=
()
+
()
=
03 1 5
40 97 9 1 2 1 40 200 3
004 0388 043
5136
40 002
40 0 0015 5 0 003 0 08
2
2
.–/
.. .
/.
...
Total power dissipation is:
P
TOT
= 0.43 + 0.02 + 0.08 = 0.53W
Thermal resistance for the LT1976 package is influenced
by the presence of internal or backside planes. With a full
plane under the FE16 package, thermal resistance will be
about 45°C/W. No plane will increase resistance to about
150°C/W. To calculate die temperature, use the proper
thermal resistance number for the desired package and
add in worst-case ambient temperature:
T
J
= T
A
+ Q
JA
(P
TOT
)
With the FE16 package (Q
JA
= 45°C/W) at an ambient
temperature of 70°C:
T
J
= 70 + 45(0.53) = 94°C
If a more accurate die temperature is required, a measure-
ment of the SYNC pin resistance to ground can be used.
The SYNC pin resistance can be measured by forcing a
voltage no greater than 0.25V at the pin and monitoring the
pin current versus temperature in a controlled temperature
environment. The measurement should be done with
minimal device power dissipation (pull the V
C
pin to
ground for sleep mode) in order to calibrate the SYNC pin
resistance with the ambient temperature.
LT1976/LT1976B
25
1976bfg
HIGH TEMPERATURE OPERATION
Extreme care must be taken when designing LT1976
applications to operate at high ambient temperatures. The
LT1976H grade is designed to work at elevated tempera-
tures but erratic operation can occur due to external
components. Each passive component should be checked
for absolute value and voltage ratings to ensure loop
stability at temperature. Boost and Catch diode leakages,
as well as increased series resistance (Table 5), will
adversely affect efficiency and low quiescent current op-
eration. Junction temperature increase in the diodes due
to self heating (leakage) and power dissipation should be
measured to ensure their maximum temperature specifi-
cations are not violated.
Input Voltage vs Operating Frequency Considerations
The absolute maximum input supply voltage for the LT1976
is specified at 60V. This is based solely on internal semi-
conductor junction breakdown effects. Due to internal
power dissipation the actual maximum V
IN
achievable in a
particular application may be less than this.
A detailed theoretical basis for estimating internal power
loss is given in the section Thermal Considerations. Note
that AC switching loss is proportional to both operating
frequency and output current. The majority of AC switch-
ing loss is also proportional to the square of input voltage.
For example, while the combination of V
IN
= 40V, V
OUT
=
5V at 1A and f
OSC
= 200kHz may be easily achievable,
simultaneously raising V
IN
to 60V and f
OSC
to 700kHz is
not possible. Nevertheless, input voltage transients up to
60V can usually be accommodated, assuming the result-
ing increase in internal dissipation is of insufficient time
duration to raise die temperature significantly.
A second consideration is controllability. A potential limi-
tation occurs with a high step-down ratio of V
IN
to V
OUT
,
as this requires a correspondingly narrow minimum switch
on time. An approximate expression for this (assuming
continuous mode operation) is given as follows:
t
ON(MIN)
= V
OUT
+ V
F
/V
IN
(f
OSC
)
where:
V
IN
= input voltage
V
OUT
= output voltage
V
F
= Schottky diode forward drop
f
OSC
= switching frequency
A potential controllability problem arises if the LT1976 is
called upon to produce an on time shorter than it is able to
produce. Feedback loop action will lower then reduce the
V
C
control voltage to the point where some sort of cycle-
skipping or Burst Mode behavior is exhibited.
In summary:
1. Be aware that the simultaneous requirements of high
V
IN
, high I
OUT
and high f
OSC
may not be achievable in
practice due to internal dissipation. The Thermal Con-
siderations section offers a basis to estimate internal
power. In questionable cases a prototype supply should
be built and exercised to verify acceptable operation.
2. The simultaneous requirements of high V
IN
, low V
OUT
and high f
OSC
can result in an unacceptably short
minimum switch on time. Cycle-skipping and/or Burst
Mode behavior will result although correct output volt-
age is usually maintained.
FREQUENCY COMPENSATION
Before starting on the theoretical analysis of frequency
response the following should be remembered—the worse
the board layout, the more difficult the circuit will be to
stabilize. This is true of almost all high frequency analog
circuits. Read the Layout Considerations section first.
Common layout errors that appear as stability problems
are distant placement of input decoupling capacitor and/or
catch diode and connecting the V
C
compensation to a
ground track carrying significant switch current. In addi-
tion the theoretical analysis considers only first order non-
ideal component behavior. For these reasons, it is important
that a final stability check is made with production layout
and components.
APPLICATIO S I FOR ATIO
WUUU
LT1976/LT1976B
26
1976bfg
The LT1976 uses current mode control. This alleviates
many of the phase shift problems associated with the
inductor. The basic regulator loop is shown in Figure 12.
The LT1976 can be considered as two g
m
blocks, the error
amplifier and the power stage.
Figure 13 shows the overall loop response with a 330pF V
C
capacitor and a typical 100μF tantalum output capacitor.
The response is set by the following terms:
Error amplifier: DC gain is set by g
m
and R
O
:
EA Gain = 650μ • 1.5M = 975
Ω
The pole set by C
F
and R
L
:
EA Pole = 1/(2π • 1.5M • 330pF) = 322Hz
Unity gain frequency is set by C
F
and g
m
:
EA Unity Gain Frequency = 650μF/(2π • 330pF)
= 313kHz
Powerstage: DC gain is set by g
m
and R
L
(assume 10Ω):
PS DC Gain = 3 • 10 = 30
Pole set by C
OUT
and R
L
:
PS Pole = 1/(2π • 100μF • 10) = 159Hz
Unity gain set by C
OUT
and g
m
:
PS Unity Gain Freq = 3/(2π • 100μF) = 4.7kHz.
APPLICATIO S I FOR ATIO
WUUU
Tantalum output capacitor zero is set by C
OUT
and C
OUT
ESR
Output Capacitor Zero = 1/(2π • 100μF • 0.1) = 15.9kHz
The zero produced by the ESR of the tantalum output
capacitor is very useful in maintaining stability. If better
transient response is required, a zero can be added to the
loop using a resistor (R
C
) in series with the compensation
capacitor. As the value of R
C
is increased, transient
response will generally improve but two effects limit its
value. First, the combination of output capacitor ESR and
a large R
C
may stop loop gain rolling off altogether.
Second, if the loop gain is not rolled off sufficiently at the
switching frequency output ripple will perturb the V
C
pin
enough to cause unstable duty cycle switching similar to
subharmonic oscillation. This may not be apparent at the
output. Small-signal analysis will not show this since a
continuous time system is assumed. If needed, an addi-
tional capacitor (C
F
) can be added to form a pole at
typically one-fifth the switching frequency (if R
C
= 10k,
C
E
= 1500pF, C
F
= 330pF)
When checking loop stability the circuit should be oper-
ated over the application’s full voltage, current and tem-
perature range. Any transient loads should be applied and
the output voltage monitored for a well-damped behavior.
Figure 13. Model for Loop Response
–
+
CURRENT MODE
POWER STAGE
gm = 3
Ω
gm = 650μ
Ω
1.26V
VC
LT1976
ERROR
AMP
1.6MRC
R1
FB 12
11
SW 2
ESR
OUTPUT
R2
COUT
1976 F13
CFB
CF
CC
Figure 14. Overall Loop Response
FREQUENCY (Hz)
0
PHASE (DEG)
90
45
135
100
–50
GAIN (dB)
0
50
100
100 1k 10k 100k
1976 F14
1M10
VOUT = 3.3V
COUT = 100μF, 0.1Ω
CF = 330pF
RL/CL = NC
ILOAD = 330mA
LT1976/LT1976B
27
1976bfg
PACKAGE DESCRIPTIO
U
FE Package
16-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663)
Exposed Pad Variation BC
FE16 (BC) TSSOP 0204
0.09 – 0.20
(.0035 – .0079)
0° – 8°
0.25
REF
0.50 – 0.75
(.020 – .030)
4.30 – 4.50*
(.169 – .177)
134
5678
10 9
4.90 – 5.10*
(.193 – .201)
16 1514 13 12 11
1.10
(.0433)
MAX
0.05 – 0.15
(.002 – .006)
0.65
(.0256)
BSC
2.94
(.116)
0.195 – 0.30
(.0077 – .0118)
TYP
2
RECOMMENDED SOLDER PAD LAYOUT
0.45 ±0.05
0.65 BSC
4.50 ±0.10
6.60 ±0.10
1.05 ±0.10
2.94
(.116)
3.58
(.141)
3.58
(.141)
MILLIMETERS
(INCHES) *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
SEE NOTE 4
4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
6.40
(.252)
BSC
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
TYPICAL APPLICATIO
U
VIN
SHDN
VC
BOOST
VBIAS
FB
PGFB
PG
LT1976B
4.7μF
100V
CER
100pF
0.33μF
0.1μF
33μH4148
1μFSYNC
CT
GND
100μF
6.3V
TANT
VOUT
3.3V
1A
VIN
3.3V TO 60V
10MQ60N
4700pF
8.06k
16.5k
1%
10k
1%
1976 TA03
SW
CSS
14V to 3.3V Non Burst Mode Step-Down Converter
LT1976B Efficiency and Power
Loss vs Load Current
LOAD CURRENT (mA)
0.1
EFFICIENCY (%)
POWER LOSS (W)
50
75
1000
1976 G25
25
0110 100 10000
100
0.1
1
0.01
0.001
10
5V
3.3V
TYPICAL
POWER LOSS
EFFICIENCY
LT1976/LT1976B
28
1976bfg
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
●
FAX: (408) 434-0507
●
www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2003
LT/CGRAFX 0407 REV G PRINTED IN USA
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