LTC1473L
1
The LTC
®
1473L provides reliable and efficient switching
between two DC power sources. This device drives two
external sets of back-to-back N-channel MOSFET switches
to route power to the input of a low voltage system. An
internal boost regulator provides the voltage to fully en-
hance the logic-level N-channel MOSFET switches while
an internal undervoltage lock-out circuit keeps the system
alive down to 2.8V.
The LTC1473L senses current to limit inrush between the
batteries and the system supply capacitor during switch-
over transitions or during fault conditions. A user-pro-
grammable timer monitors the time the MOSFET switches
are in current limit and latches them off when the pro-
grammed time is exceeded.
A unique “2-diode” logic mode ensures system start-up
regardless of which input receives power first.
■
Portable Computers
■
Portable Instruments
■
Fault Tolerant Computers
■
Battery-Backup Systems
■
3.3V/5V Power Management
, LTC and LT are registered trademarks of Linear Technology Corporation.
■
Power Path Management for Systems
with Multiple DC Sources
■
Switches and Isolates Sources from 3.3V to 10V
■
All N-Channel Switching to Reduce Power Losses
and System Cost
■
Built-In Step-Up Regulator for N-Channel Gate Drive
■
Capacitor Inrush and Short-Circuit Current Limited
■
User-Programmable Timer Prevents Overdissipation
During Current Limiting
■
Undervoltage Lockout Prevents Operation with Low
Inputs
■
Small Footprint: 16-Pin Narrow SSOP
Dual Low Voltage
PowerPathTM Switch Driver
PowerPath is a trademark of Linear Technology Corporation.
3.3V to 4-Cell NiMH Backup Switch
IN1
IN2
DIODE
TIMER
V
+
V
GG
SW
GND
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
GA1
SAB1
GB1
SENSE
+
SENSE
–
GA2
SAB2
GB2
LTC1473L
C
OUT
R
SENSE
0.04Ω
1µF1mH*
Si9926DY
BAT54C
1473 TA01
DCIN
3.3V
V
BAT1
4× NiMH
LOGIC
DRIVEN
3.3V OR
V
BAT1
C
TIMER
2000pF
Si9926DY
1µF
+
* COILCRAFT 1812LS-105XKBC
APPLICATIO S
U
FEATURES
TYPICAL APPLICA TIO
U
DESCRIPTIO
U
LTC1473L
2
ABSOLUTE AXI U RATI GS
W
WW
U
PACKAGE/ORDER I FOR A TIO
UUW
(Note 1)
ELECTRICAL CHARACTERISTICS
ORDER PART
NUMBER
LTC1473LCGN
T
JMAX
= 125°C, θ
JA
= 150°C/W
Consult factory for Military and Industrial grade parts.
SENSE
+
, SENSE
–
, V
+
..................................–0.3 to 10V
GA1, GB1, GA2, GB2 ...................................–0.3 to 20V
SAB1, SAB2.................................................–0.3 to 10V
SW, V
GG
......................................................–0.3 to 20V
IN1, IN2, DIODE...........................................–0.3V to 7V
Junction Temperature (Note 2).............................125°C
Operating Temperature Range.....................0°C to 70°C
Storage Temperature Range................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec)..................300°C
GN PART MARKING
1473L
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
+
Supply Operating Range 2.8 9 V
I
S
Supply Current V
IN1
= V
DIODE
= 5V, V
IN2
= 0V, V
SENSE+
= V
SENSE–
= 5V ●100 200 µA
V
GS
V
GS
Gate Supply Voltage V
GS
= V
GG
– V
+
, 2.8V ≤ V
+
≤ 10V (Note 3) ●7.5 8.5 9.5 V
V
+UVLO
V
+
Undervoltage Lockout Threshold V
+
Ramping Down ●2.3 2.5 2.8 V
V
+UVLOHYS
V
+
Undervoltage Lockout Hysteresis 70 mV
V
HIDIGIN
Digital Input Logic High (Note 4) ●2 0.9 V
V
LODIGIN
Digital Input Logic Low (Note 4) ●0.6 0.4 V
I
IN
Input Current V
IN1
= V
IN2
= V
DIODE
= 5V ±1µA
V
GS(ON)
Gate-to-Source ON Voltage I
GA1
= I
GA2
= I
GB1
= I
GB2
= –1µA, V
SAB1
= V
SAB2
= 5V ●4.5 5.6 7.0 V
V
GS(OFF)
Gate-to-Source OFF Voltage I
GA1
= I
GA2
= I
GB1
= I
GB2
= 100µA, V
SAB1
= V
SAB2
= 5V ●0 0.4 V
I
BSENSE+
SENSE
+
Input Bias Current V
SENSE+
= V
SENSE–
= 10V (Note 3) ●24.510µA
V
SENSE+
= V
SENSE–
= 0V (Note 5) ●–300 –175 –75 µA
I
BSENSE–
SENSE
–
Input Bias Current V
SENSE+
= V
SENSE–
= 10V (Note 3) ●24.510µA
V
SENSE+
= V
SENSE–
= 0V (Note 5) ●–300 –175 –75 µA
V
SENSE
Inrush Current Limit Sense Voltage V
SENSE–
= 10V (V
SENSE+
– V
SENSE–
) (Note 3) 0.15 0.20 0.25 V
V
SENSE–
= 0V (V
SENSE+
– V
SENSE–
) 0.10 0.20 0.30 V
I
PDSAB
SAB1, SAB2 Pull-Down Current V
IN1
= V
IN2
= V
DIODE
= 0.4V, V
+
= 10V (Note 3) 5 20 35 µA
V
IN1
= V
IN2
= 0.4V, V
DIODE
= 2V 30 140 300 µA
I
TIMER
Timer Source Current V
IN1
= 0.4V, V
IN2
= V
DIODE
= 2V, V
TIMER
= 0V, ●369µA
V
SENSE+
– V
SENSE–
= 300mV
V
TIMER
Timer Latch Threshold Voltage V
IN1
= 0.4V, V
IN2
= V
DIODE
= 2V ●1.05 1.16 1.25 V
t
ON
Gate Drive Rise Time C
GS
= 1000pF, V
SAB1
= V
SAB2
= 0V (Note 6) 33 µs
t
OFF
Gate Drive Fall Time C
GS
= 1000pF, V
SAB1
= V
SAB2
= 5V (Note 6) 2 µs
t
D1
Gate Drive Turn-On Delay C
GS
= 1000pF, V
SAB1
= V
SAB2
= 0V (Note 6) 22 µs
t
D2
Gate Drive Turn-Off Delay C
GS
= 1000pF, V
SAB1
= V
SAB2
= 5V (Note 6) 1 µs
f
OVGG
V
GS
Regulator Operating Frequency 30 kHz
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. Test circuit, V+ = 5V, unless otherwise specified.
TOP VIEW
GN PACKAGE
16-LEAD NARROW PLASTIC SSOP
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
IN1
IN2
DIODE
TIMER
V
+
V
GG
SW
GND
GA1
SAB1
GB1
SENSE
+
SENSE
–
GA2
SAB2
GB2
LTC1473L
3
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: T
J
is calculated from the ambient temperature T
A
and power
dissipation P
D
according to the following formula:
T
J
= T
A
+ (P
D
)(150°C/W)
Note 3: Some tests are performed under more stringent conditions to
ensure reliable operation over the entire supply voltage range.
ELECTRICAL CHARACTERISTICS
Note 4: Digital inputs include: IN1, IN2 and DIODE.
Note 5: I
S
increases by the same amount as I
BSENSE+
+ I
BSENSE–
when
their common mode falls below 5V.
Note 6: Gate turn-on and turn-off times are measured with no inrush
current limiting, i.e., V
SENSE
= 0V. Gate rise times are measured from 1V to
4.5V and fall times are measured from 4.5V to 1V. Delay times are
measured from the input transition to when the gate voltage has risen or
fallen to 3V. Results are not tested, but guaranteed by design.
DC Supply Current
vs Supply Voltage
VGS Gate-to-Source ON Voltage
vs Temperature
DC Supply Current vs VSENSE
V
SENSE
COMMON MODE (V)
0
SUPPLY CURRENT (µA)
1473 G03
567 101234 89
400
350
300
250
200
150
100
50
0
V
+
= 5V
V
DIODE
= V
IN1
= 5V
V
IN2
= 0V
V
SENSE+
– V
SENSE–
= 0V
VGS Gate Supply Voltage
vs Temperature
TEMPERATURE (°C)
–60–40–20 204060800
5.1
V
GS
GATE-TO-SOURCE ON VOLTAGE (V)
5.2
5.4
5.5
5.6
6.0
1473 G04
5.3
100
5.7
5.8
5.9 V
+
= V
SAB
= 10V
SUPPLY VOLTAGE (V)
0
SUPPLY CURRENT (µA)
50
150
10
1473 G01
02 45678913
250
100
200
V
DIODE
= V
IN1
= 5V
V
IN2
= 0V
V
DIODE
= 5V
V
IN1
= V
IN2
= 0V
V
SENSE+
= V
SENSE–
= V
+
TEMPERATURE (°C)
–40–60
8.1
V
GS
GATE SUPPLY VOLTAGE (V)
8.2
8.4
8.5
8.6
0
9.0
1473 G06
8.3
–20 20406080100
8.7
8.8
8.9 V
+
= 5V
V
GS
= V
GG
– V
+
DC Supply Current
vs Temperature
Undervoltage Lockout Threshold (V+)
vs Temperature
TEMPERATURE (°C)
–50
50
SUPPLY CURRENT (µA)
60
80
90
100
0
140
1473 G02
70
–25 25 50 75 100
110
120
130 V
+
= 5V
V
DIODE
= V
IN1
= 5V
V
IN2
= 0V
TEMPERATURE (°C)
–60
2.25
UNDERVOLTAGE LOCKOUT THRESHOLD (V)
2.30
2.40
2.45
2.50
2.75
2.60
–20 20 40
1473 G05
2.35
2.65
2.70
2.55
–40 0 60 80 100
START-UP
THRESHOLD
SHUTDOWN
THRESHOLD
TYPICAL PERFOR A CE CHAR ACTERISTICS
UW
LTC1473L
4
TYPICAL PERFOR A CE CHAR ACTERISTICS
UW
Turn-Off Delay and Gate Fall Time
vs Temperature
TEMPERATURE (°C)
–40–60
0.4
TURN-OFF DELAY AND GATE FALL TIME (µs)
0.6
1.0
1.2
1.4
0
2.2
1473 G07
0.8
–20 20406080100
1.6
1.8
2.0
GATE FALL
TIME
V
+
= 5V
C
LOAD
= 1000pF
V
SAB
= 5V
TURN-OFF
DELAY
Rise and Fall Time
vs Gate Capacitive Loading
GATE CAPACITIVE LOADING (pF)
10
20
RISE AND FALL TIME (µs)
30
40
100 1000 10000
1473 G08
10
5
25
35
15
0
RISE TIME
V
SAB
= 0V
FALL TIME
V
SAB
= 5V
Turn-On Delay and Gate Rise Time
vs Temperature
TEMPERATURE (°C)
–60
0
TURN-ON DELAY AND GATE RISE TIME (µs)
5
15
20
25
0
45
1473 G08
10
–40 –20 20 40 60 80 100
30
35
40 GATE RISE
TIME
V
+
= 5V
C
LOAD
= 1000pF
V
SAB
= 0V
TURN-ON
DELAY
SENSE Pin Source Current
(IBSENSE) vs VSENSE
V
SENSE
(V)
SENSE PIN CURRENT (µA)
1473 G13
V
+
= 5V
V
DIODE
= V
IN1
= 5V
V
IN2
= 0V
V
SENSE+
– V
SENSE–
= 0V
0
300
250
200
150
100
50
0
–50 123456789
10
Timer Source Current
vs Temperature
TEMPERATURE (°C)
–50
4.0
TIMER SOURCE CURRENT (µA)
4.5
5.5
6.0
6.5
0
8.5
1473 G12
5.0
–25 25 50 75 100 125
7.0
7.5
8.0 V
+
= 5V
TIMER = 0V
TEMPERATURE (°C)
–50
1.10
TIMER LATCH THRESHOLD VOLTAGE (V)
1.12
1.16
1.18
1.20
0
1.28
1473 G11
1.14
–25 25 50 75 100 125
1.22
1.24
1.26 V
+
= 5V
Timer Latch Threshold Voltage
vs Temperature
Logic Input Threshold Voltage
vs Temperature
TEMPERATURE (°C)
–60
0
INPUT THRESHOLD VOLTAGE (V)
0.2
0.6
0.8
1.0
2.0
1.4
–20 20 40
1473 G10
0.4
1.6
1.8
1.2
–40 0 60 80 100
V
+
= 10V
V
+
= 2.8V
LTC1473L
5
PI FU CTIO S
UUU
SW (Pin 7): Open Drain of an Internal N-Channel MOSFET
Switch. This pin drives the bottom of the V
GG
switching
regulator inductor which is connected between this pin and
the V
+
pin.
GND (Pin 8): Ground.
GB2, GA2 (Pins 9, 11): Switch Gate Drivers. GA2 and GB2
drive the gates of the second back-to-back external
N-channel switches.
SAB2 (Pin 10): Source Return. The SAB2 pin is connected
to the sources of SW A2 and SW B2. A small pull-down
current source returns this node to 0V when the switches
are turned off.
SENSE
–
(Pin 12): Inrush Current Input. This pin should be
connected directly to the bottom (output side) of the low
valued resistor in series with the two input power selector
switch pairs, SW A1/B1 and SW A2/B2, for detecting and
controlling the inrush current into and out of the power
supply sources and the output capacitor.
SENSE
+
(Pin 13): Inrush Current Input. This pin should be
connected directly to the top (switch side) of the low
valued resistor in series with the two input power selector
switch pairs, SW A1/B1 and SW A2/B2, for detecting and
controlling the inrush current into and out of the power
supply sources and the output capacitor. Current limit is
invoked when (V
SENSE+
– V
SENSE–
) exceeds ±0.2V.
IN1 (Pin 1): Logic Input of Gate Drivers GA1 and GB1. IN1
is disabled when IN2 is high or DIODE is low. During
2-diode mode, asserting IN1 disables the fault timer
function.
IN2 (Pin 2): Logic Input of Gate Drivers GA2 and GB2. IN2
is disabled when IN1 is high or DIODE is low. During
2-diode mode, asserting IN2 disables the fault timer
function.
DIODE (Pin 3): “2-Diode Mode” Logic Input. Diode over-
rides IN1 and IN2 by forcing the two back-to-back
external N-channel MOSFET switches to mimic two di-
odes.
TIMER (Pin 4): Fault Timer. A capacitor connected from
this pin to GND programs the time the MOSFET switches
are allowed to be in current limit. To disable this function,
Pin 4 can be grounded.
V
+
(Pin 5): Power Supply. Bypass this pin with at least a
1µF capacitor.
V
GG
(Pin 6): Gate Driver Supply. This high voltage supply
is intended only for driving the internal micropower gate
drive circuitry.
Do not load this pin with any external
circuitry
. Bypass this pin with at least 1µF.
Pin Function Table NOMINAL (V) ABSOLUTE MAX (V)
PIN NAME DESCRIPTION MIN TYP MAX MIN MAX
1 IN1 Logic Input of Gate Drivers GA1 and GB1 0.4 1 2 –0.3 7
2 IN2 Logic Input of Gate Drivers GA2 and GB2 0.4 1 2 –0.3 7
3 DIODE “2-Diode Mode” Logic Input 0.4 1 2 –0.3 7
4 TIMER Fault Timer Programs Time in Current Limit 1.16 –0.3 5
5V
+
Power Supply 2.8 9 –0.3 10
6V
GG
Gate Driver Supply 10.2 20 –0.3 20
7 SW Switch Node of Internal Boost Switching Regulator 0 20 –0.3 20
8 GND Ground 0 0 0
9 GB2 Switch Gate Driver for Switch B2 0 17 –0.3 20
10 SAB2 Source Return of Switch 2 0 10 –0.3 10
11 GA2 Switch Gate Driver for Switch A2 0 17 –0.3 20
12 SENSE
–
Inrush Current Input, Low Side 0 10 –0.3 10
13 SENSE
+
Inrush Current Input, High Side 0 10 –0.3 10
14 GB1 Switch Gate Driver for Switch B1 0 17 –0.3 20
15 SAB1 Source Return of Switch 1 0 10 –0.3 10
16 GA1 Switch Gate Driver for Switch A1 0 17 –0.3 20
LTC1473L
6
PI FU CTIO S
UUU
FU CTIO AL DIAGRA
UU
W
GB1, GA1 (Pins 14, 16): Switch Gate Drivers. GA1 and GB1
drive the gates of the first back-to-back external N-channel
switches.
SAB1 (Pin 15): Source Return. The SAB1 pin is connected
to the sources of SW A1 and SW B1. A small pull-down
current source returns this node to 0V when the switches
are turned off.
GA1
SAB1
GB1
GA2
SAB2
GB2
1473 FD
SENSE+
SENSE–
IN1
IN2
DIODE
V+
TIMER
V+
SW
TO
GATE
DRIVERS
VGG
GND
1.16V
VGG
SWITCHING
REGULATOR
INRUSH
CURRENT
SENSE
900k
6µA
LATCH
R
S
–
+
SW A1/B1
GATE
DRIVERS
SW A2/B2
GATE
DRIVERS
16
15
14
13
12
11
10
9
8
6
5
4
3
2
1
7
LTC1473L
7
OPERATIO
U
The LTC1473L is responsible for low-loss switching and
isolation for a dual supply system, where during a power
backup situation, a battery pack can be connected or
disconnected seamlessly. Smooth switching between in-
put power sources is accomplished with the help of
low-loss N-channel switches. They are driven by special
gate drive circuitry which limits the inrush current in and
out of the battery packs and the system power supply
capacitors.
All N-Channel Switching
The LTC1473L drives external back-to-back N-channel
MOSFET switches to direct power from two sources: the
primary battery and the secondary battery, or a battery and
a DC power supply. (N-channel MOSFET switches are
more cost effective and provide lower voltage drops than
their P-channel counterparts.)
Gate Drive (V
GG
) Power Supply
The gate drive for the low-loss N-channel switches is
supplied by an internal micropower boost regulator which
is regulated at approximately 8.5V above V
+
, up to 20V
maximum. In a DC supply and backup battery system, the
LTC1473L V
+
pin is diode ORed through two external
Schottky diodes connected to the two main power sources,
DCIN and BAT1. Thus, V
GG
is regulated at 8.5V above the
higher power source and will provide the overdrive
required to fully enhance the MOSFET switches.
For maximum efficiency the input to the boost regulator
inductor is connected to V
+
as shown in Figure 1. C1
provides filtering to the input of the 1mH switched induc-
tor, L1, which is housed in a small surface mount package.
An internal diode directs the current from the 1mH induc-
tor to the V
GG
output capacitor C2.
Inrush and Short-Circuit Current Limiting
The LTC1473L uses an adaptive inrush current limiting
scheme to reduce current flowing in and out of the battery
and the following system’s input capacitor during switch-
over transitions. The voltage across a single small valued
resistor, R
SENSE
, is measured to ascertain the instanta-
neous current flowing through either of the two switch
pairs, SW A1/B1 and SW A2/B2, during the transitions.
Figure 2 shows a block diagram of a switch driver pair, SW
A1/B1. A bidirectional current sensing and limiting circuit
determines when the voltage drop across R
SENSE
reaches
±200mV. The gate-to-source voltage, V
GS
, of the appro-
priate switch is limited during the transition period until
the inrush current subsides.
This scheme allows capacitors and MOSFET switches of
differing sizes and current ratings to be used in the same
system without circuit modifications.
Figure 1. VGG Switching Regulator
Figure 2. SW A1/B1 Inrush Current Limiting
BAT1DCIN
V
+
SW
GND
1473 F01
V
GG
L1
1mH
C1
1µF
25V
C2
1µF
25V
TO GATE
DRIVERS
(8.5V + V
+
)
LTC1473L
V
GG
SWITCHING
REGULATOR
V
SENSE+
V
SENSE–
GA1 GB1
SAB1
SW A1 SW B1 R
SENSE
1473 F02
BAT1
+
OUTPUT
LOAD
C
OUT
V
GG
LTC1473L
6V 6V ± 200mV
THRESHOLD
SW A/B
GATE
DRIVERS
BIDIRECTIONAL
INRUSH CURRENT
SENSING AND
LIMITING
LTC1473L
8
After the transition period, the V
GS
of both MOSFETs in the
selected switch pair rises to approximately 5.6V. The gate
drive is set at 5.6V to provide ample overdrive for logic-
level MOSFET switches without exceeding their maximum
V
GS
rating.
In the event of a fault condition, the current limit loop limits
the inrush of current into the short. At the instant the
MOSFET switch is in current limit, i.e., when the voltage
drop across R
SENSE
is ±200mV, a fault timer starts timing.
It will continue to time as long as the MOSFET switch is in
current limit. Eventually the preset time will lapse and the
MOSFET switch will latch off. The latch is reset by dese-
lecting the gate drive input. Fault time-out is programmed
by an external capacitor connected between the TIMER pin
and ground.
POWER PATH SWITCHING CONCEPTS
Power Source Selection
The LTC1473L drives low-loss switches to direct power
from either the battery pack or the DC supply during power
backup situations.
Figure 3 is a conceptual block diagram that illustrates the
main features of an LTC1473L dual supply power manage-
ment system starting with a 4 NiMH battery pack and a 5V/
3.3V DC supply and ending with an uninterrupted output
load. Switches SW A1/B1 and SW A2/B2 direct power
from either the DC supply or the battery to the output load.
Each of the switches is controlled by a logic compatible
input that can interface directly with a digital pin.
Using Tantalum Capacitors
The inrush (and “outrush”) current of the load capacitor is
limited by the LTC1473L, i.e., the current flowing both in
and out of the capacitor during transitions from one input
power source to another is limited. In many applications,
this inrush current limiting makes it feasible to use lower
cost/size tantalum surface mount capacitors in place of
more expensive/larger aluminum electrolytics.
Note: The capacitor manufacturer should be consulted for
specific inrush current specifications and limitations and
some experimentation may be required to ensure compli-
ance with these limitations under all possible operating
conditions.
Back-to-Back Switch Topology
The simple SPST switches shown in Figure 3 actually
consist of two back-to-back N-channel switches. These
low-loss N-channel switch pairs are housed in 8-pin SO or
SSOP packaging and are available from a number of
manufacturers. The back-to-back topology eliminates the
problems associated with the inherent body diodes in
power MOSFET switches and allows each switch pair to
block current flow in either direction when the two switches
are turned off.
Figure 3. LTC1473L PowerPath Conceptual Diagram
DCIN
5V/3.3V
BAT1
4 NiMH
INRUSH
CURRENT
LIMITING
SW A1/B1
SW A2/B2 +
1473 F03
CLOAD
LTC1473L
APPLICA TIO S I FOR A TIO
WUUU
LTC1473L
9
The back-to-back topology also allows for independent
control of each half of the switch pair which facilitates
bidirectional inrush current limiting and the so-called
“2-diode mode” described in the following section.
The 2-Diode Mode
Under normal operating conditions, both halves of each
switch pair are turned on and off simultaneously. For
example, when the input power source is switched from
BAT1 to DCIN in Figure 4, both gates of switch pair SW
A1/B1 are normally turned off and both gates of switch pair
SW A2/B2 are turned on. The back-to-back body diodes in
switch pair, SW A1/B1, block current flow in or out of the
BAT1 input connector.
In the “2-diode mode,” only the first half of each power
path switch pair, i.e., SW A1 and SW A2, is turned on; and
the second half, i.e., SW B1 and SW B2, is turned off. These
two switch pairs now act simply as two diodes connected
to the two main input power sources as illustrated in
Figure 4. The power path diode with the highest input
voltage passes current through to the output load to
ensure that the output is powered even under start-up or
abnormal operating conditions. (An undervoltage lockout
circuit defeats this mode when the V
+
pin drops below
2.5V. The supply to V
+
comes from the main power
sources, DCIN and BAT1 through two common cathode
Schottky diodes as shown in Figure 1.)
The 2-diode mode is asserted by applying an active low to
the DIODE input.
COMPONENT SELECTION
N-Channel Switches
The LTC1473L adaptive inrush limiting circuitry permits
the use of a wide range of logic-level N-Channel MOSFET
switches. A number of dual low R
DS(ON)
N-channel switches
in 8-lead surface mount packages are available that are
well suited for LTC1473L applications.
The maximum allowable drain-source voltage, V
DS(MAX)
,
of the two switch pairs, SW A1/B1 and SW A2/B2 must be
high enough to withstand the maximum input DC supply
voltage. Since the DC supply is in the 3.3V to 10V range,
12V MOSFET switches will suffice.
As a general rule, select the switch with the lowest
R
DS(ON)
at the maximum allowable V
DS
. This will mini-
mize the heat dissipated in the switches while increasing
the overall system efficiency. Higher switch resistances
can be tolerated in some systems with lower current
requirements, but care should be taken to ensure that the
Figure 4. LTC1473L PowerPath Switches in 2-Diode Mode
BAT1
DCIN SW A2
SW B2
ON OFF
R
SENSE
1473 F04
OUTPUT
LOAD
+
C
IN
SW A1
SW B1
ON OFF
LTC1473L
APPLICA TIO S I FOR A TIO
WUUU
LTC1473L
10
power dissipated in the switches is never allowed to rise
above the manufacturers’ recommended level.
Inrush Current Sense Resistor, R
SENSE
A small valued sense resistor (current shunt) is used by
the two switch pair drivers to measure and limit the inrush
or short-circuit current flowing through the conducting
switch pair.
The inrush current limit should be set at approximately 2×
or 3× the maximum required output current. For example,
if the maximum current required by the DC/DC converter
is 2A, an inrush current limit of 6A is set by selecting a
0.033Ω sense resistor, R
SENSE
, using the following
formula:
R
SENSE
= (200mV)/I
INRUSH
Note that the voltage drop across the resistor in this
example is only 66mV under normal operating conditions.
Therefore, the power dissipated in the resistor is ex-
tremely small (132mW), and a small 1/4W surface mount
resistor can be used in this application (the resistor will
tolerate the higher power dissipation during current limit
for the duration of the fault time-out). A number of small
valued surface mount resistors are available that have
been specifically designed for high efficiency current
sensing applications.
Programmable Fault Timer Capacitor, C
TIMER
A fault timer capacitor, C
TIMER
, is used to program the time
duration the MOSFET switches are allowed to be in current
limit continuously. This feature can be disabled by either
grounding the TIMER pin or asserting DIODE low and
asserting either IN1 or IN2 high.
In the event of a fault condition, the MOSFET switch is
driven into current limit by the inrush current limit loop.
The MOSFET switch operating in current limit is in a high
dissipation mode and can fail catastrophically if not
promptly terminated.
The fault time delay is programmed with an external
capacitor connected between the TIMER pin and GND. At
the instant the MOSFET switch enters current limit, a 6µA
current source starts charging C
TIMER
through the TIMER
pin. When the voltage across C
TIMER
reaches 1.16V an
internal latch is set and the MOSFET switch is turned off.
To reset the latch, the logic input of the MOSFET gate
driver must be deselected.
The fault time delay should be programmed as large as
possible, at least 3× to 5× the maximum switching transi-
tion period, to avoid prematurely tripping the protection
circuit. Conversely, for the protection circuit to be effec-
tive, the fault time delay must be within the safe operating
area of the MOSFET switches as stated in the manufacturer’s
data sheet.
The maximum switching transition period happens during
a cold start, when a fully charged battery is connected to
an unpowered system. The inrush current charging up the
system supply capacitor to the battery voltage determines
the switching transition period.
The following example illustrates the calculation of C
TIMER.
Assume the maximum battery voltage is 10V, the system
supply capacitor is 100µF, the inrush current limit is 6A
and the maximum current required by the following sys-
tem is 2A. Then, the maximum switching transition period
is calculated using the following formula:
tVC
II
tF
AA s
SW MAX BAT MAX IN SYSTEM
INRUSH LOAD
SW MAX
() ()
()
=
()
()
−
=
()
µ
()
−=µ
()
10 100
62 250
Multiplying 3 by 250µs gives 0.75ms, the minimum fault
delay time. Make sure this delay time does not fall outside
of the safe operating area of the MOSFET switch dissipat-
ing 30W (6A • 10V/2). Using this delay time the C
TIMER
can
be calculated using the following formula:
Cms
A
VpF
ITMER
=µ
=075 6
116 3879. .
Therefore, C
TIMER
can be 3900pF.
APPLICA TIO S I FOR A TIO
WUUU
LTC1473L
11
V
GG
Regulator Inductor and Capacitors
The V
GG
regulator provides a power supply voltage signifi-
cantly higher than either of the two main power source
voltages to allow the control of N-channel MOSFET
switches. This micropower, step-up voltage regulator is
powered by the higher potential available from the two
main power sources for maximum regulator efficiency.
APPLICA TIO S I FOR A TIO
WUUU
Three external components are required by the V
GG
regu-
lator: L1, C1 and C2, as shown in Figure 5.
L1 is a small, low current, 1mH surface mount inductor. C1
provides filtering to the input of the 1mH switched induc-
tor and should be at least 1µF to filter switching transients.
The V
GG
output capacitor, C2, provides storage and filter-
ing for the V
GG
output and should be at least 1µF and rated
for 25V operation. C1 and C2 can be ceramic capacitors.
Figure 5. VGG Step-Up Switching Regulator
BAT1DCIN
VGG
SWITCHING
REGULATOR
V+
SW
GND
1473 F05
VGG
L1*
1mH
C1
1µF
25V
C2
1µF
25V
TO GATE
DRIVERS
(8.5V + V+)
LTC1473L
*COILCRAFT 1812LS-105 XKBC. (708) 639-6400
LTC1473L
12
LTC1473L with Battery Charger
TYPICAL APPLICA TIO S
U
IN1
IN2
DIODE
TIMER
V+
VGG
SW
GND
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
GA1
SAB1
GB1
SENSE+
SENSE–
GA2
SAB2
GB2
LTC1473L
COUT
RSENSE
0.04Ω
1µF
1mH
Si9926DY
BAT54C
100mA
D1
MBRS130LT3
1473 TA03
DCIN
3.3V
BAT1
4 NiMH
3.3V OR
VBAT1
CTIMER
2000pF
C1
22µF
25V
R1
47.55k
L1B*
L1A* C2**
22µF
R4
24Ω
C3
22µF
25V
C4
0.22µF
L1A, L1B ARE TWO 33µH WINDINGS ON A
SINGLE INDUCTOR: COILTRONICS CTX33-3
TOKIN CERAMIC 1E22ZY5U-C203-F
C5
0.1µF
SYNC
AND/OR
SHDN
*
**
Si9926DY
1µF
+
R2
12.45k
R5
1k R3
1Ω
VSW
VIN
FBS/S IFB
VC
GND
LT®1512
GND LOGIC
DRIVEN
LTC1473L
13
2-Cell Li-Ion to 5V/3.5A DC/DC Converter with Battery Charger and Automatic Switchover Between Battery and DCIN
TYPICAL APPLICA TIO S
U
R
SENSE
0.015Ω
M1
Si4412DY
C4
0.1µF
D1
CMDSH-3
C3
4.7µF
16V D2
MBRS140T3
C
IN
22µF
30V
OS-CON
C
OUT
100µF
10V
× 3
V
OUT
5V/3.5A
M2
Si4412DY
+
+
R1
105k
1%
L1*
10µH
SGND
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
C1
100pF C5
1000pF
C
SS
, 0.1µF
C
C2
, 220pF
C
OSC
51pF
R
C
, 33k
C
C
470pF
+
C6
100pF
C2, 0.1µF
R2
20k
1%
2600pF
C
TIMER
C7
1µFC8
1µF
GND
SW
BOOST
GND
GND
UV
GND
OVP
CLP
CLN
COMP1
SENSE
GND
GND
V
CC1
V
CC2
V
CC3
PROG
V
C
UVOUT
GND
COMP2
BAT
SPIN
LT1511
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
DCIN
OUT A
V
–
IN
+
A
IN
–
B
OUT B
V
+
REF
HYST
LTC1442
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
1
2
3
4
8
7
6
5
74C00
12
3
45
6
13
12
11
14
BAT54C
D5
MBRD340
C11
0.47µF
D6
MBR0540T
D4
MBRD340
L3***
20µH
2,3
1,4
C10
1µF
R13
5.1k
1%
R12
3k
1%
C16
220pF
R
SENSE
0.033Ω
R20
395k
0.1%
R21
164k
0.1%
C17
10µF
8.4V
Li-Ion
BATTERY
R19
200Ω
1%
R15
1kC15
0.33µF
R16
300Ω
C14
1µF
R17
4.93k
C12
10µF
C13
10µF
R
SENSE
0.033Ω
R14
510Ω
R6
900k
1%
R7
130k
1%
R9
113k
1%
R8
427k
1% R10
50k
1%
R11
1132k
1%
C9
0.1µF
R5
500k
7
L2**
1mH
R18, 200Ω, 1%
1473 TA04
*SUMIDA CDRH125-10
**COILCRAFT 1812LS-105XKBC
***COILTRONICS CTX20-4
10
9
8
Si9926DY
R
SENSE
0.033Ω
IN1
IN2
DIODE
TIMER
V
+
V
GG
SW
GND
GA1
SAB1
GB1
SENSE
+
SENSE
–
GA2
SAB2
GB2
LTC1473L
Si9926DY
D3
6.8V
TG
BOOST
SW
V
IN
INTV
CC
BG
PGND
EXTV
CC
C
OSC
RUN/SS
I
TH
SFB
SGND
V
OSENSE
SENSE
–
SENSE
+
LTC1735
8
+
5V
LTC1473L
14
TYPICAL APPLICA TIO S
U
Automatic PowerPath Switching for 3.3V Applications
3.3V or 5V, 6A, PowerPath Switch
IN1
IN2
DIODE
TIMER
V
+
V
GG
SW
GND
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
GA1
SAB1
GB1
SENSE
+
SENSE
–
GA2
SAB2
GB2
LTC1473L
C
OUT
R
SENSE
0.04Ω
1µF1mH*
Si4966DY
BAT54C
1473 TA05
DCIN
3.3V LTC1442
R1
1.65M
1%
BAT1
4 NiMH
3.3V OR
V
BAT1
C
TIMER
4700pF
Si4966DY
1µF
1.182V 2
8
4
5
6
3
1
7
+
–
+
–
+
R2
1.13M
1%
* COILCRAFT 18126S-105XKBC
IN1
IN2
DIODE
TIMER
V
+
V
GG
SW
GND
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
GA1
SAB1
GB1
SENSE
+
SENSE
–
GA2
SAB2
GB2
LTC1473L
C
OUT
R
SENSE
0.015Ω
1µF1mH
Si4966DY
BAT54C
1473 TA06
DCIN
3.3V
DCIN
5V
3.3V OR 5V
6A
C
TIMER
550pF
Si4966DY
1µF
+
LOGIC
DRIVEN
LTC1473L
15
TYPICAL APPLICA TIO S
U
GN Package
16-Lead Plastic SSOP (Narrow 0.150)
(LTC DWG # 05-08-1641)
Protected Hot Swap
TM
Switchover Between Two Supplies for Portable PC
PACKAGE DESCRIPTIO
U
Dimensions in inches (millimeters) unless otherwise noted.
Hot Swap is a trademark of Linear Technology Corporation
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
IN1
IN2
DIODE
TIMER
V+
VGG
SW
GND
GA1
SAB1
GB1
SENSE+
SENSE–
GA2
SAB2
GB2
LTC1473L
L1*, 1mH
C5
1µF
C7
1µF
100k
100k
C6
4700pF
SUPPLY V2
3.3V
SUPPLY V1
5V
D1
MMBD2838LT1
Q1
Si9926DY
Q2
Si9926DY
R3
0.1ΩOUT
5V
DOCKING
CONNECTOR
ON
LONG PIN
LONG PIN
SHORT PIN
*1812LS-105XKBC,
COILCRAFT
1473 • TA07
GN16 (SSOP) 1098
* DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
12345678
0.229 – 0.244
(5.817 – 6.198) 0.150 – 0.157**
(3.810 – 3.988)
16 15 14 13
0.189 – 0.196*
(4.801 – 4.978)
12 11 10 9
0.016 – 0.050
(0.406 – 1.270)
0.015 ± 0.004
(0.38 ± 0.10) × 45°
0° – 8° TYP
0.007 – 0.0098
(0.178 – 0.249)
0.053 – 0.068
(1.351 – 1.727)
0.008 – 0.012
(0.203 – 0.305)
0.004 – 0.0098
(0.102 – 0.249)
0.0250
(0.635)
BSC
0.009
(0.229)
REF
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
LTC1473L
16
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
●
FAX: (408) 434-0507
●
www.linear-tech.com
LINEAR TECHNOLOGY CORPORATION 1999
1473lf LT/TP 1099 4K • PRINTED IN USA
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16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
IN1
IN2
DIODE
TIMER
V
+
V
GG
SW
GND
GA1
SAB1
GB1
SENSE
+
SENSE
–
GA2
SAB2
GB2
LTC1473L
L1*, 1mH
C5
1µF
C7
1µF
C6
2600pF
–
+
5
6
7
–
+
3
2
1
8
4
1M
1M
10k
10k
1M
SUPPLY V2
SUPPLY V1
1M 1µF
5V 18
3
LT1121-5
BAT54C
Q1
Si9926DY
Q2
Si9926DY
R3
0.033ΩOUT
*1812LS-105XKBC, COILCRAFT
1473 • TA02
LT1490
