REVISIONS
LTR DESCRIPTION DATE (YR-MO-DA) APPROVED
A
Drawing updated to reflect current requirements. Removed
programming specifics from drawing. Editorial changes throughout.
gap
01-02-07 Raymond Monnin
B Boilerplate update and part of five year review. tcr 07-02-13 Joseph Rodenbeck
THE ORIGINAL FIRST PAGE OF THIS DRAWING HAS BEEN REPLACED.
REV
SHEET
REV
SHEET
REV STATUS REV B B B B B B B B B B B
OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11
PMIC N/A PREPARED BY
James E. Jamison
DEFENSE SUPPLY CENTER COLUMBUS
STANDARD
MICROCIRCUIT
DRAWING
CHECKED BY
Charles Reusing
COLUMBUS, OHIO 43218-3990
http://www.dscc.dla.mil
THIS DRAWING IS
AVAILABLE
FOR USE BY ALL
DEPARTMENTS
APPROVED BY
Michael A. Frye
MICROCIRCUIT, MEMORY, DIGITAL, CMOS,
2K X 8 REGISTERED UVEPROM, MONOLITHIC
SILICON
AND AGENCIES OF THE
DEPARTMENT OF DEFENSE
DRAWING APPROVAL DATE
91-12-30
AMSC N/A
REVISION LEVEL
B SIZE
A CAGE CODE
67268
5962-89815
SHEET
1 OF
11
DSCC FORM 2233
APR 97 5962-E261-07
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
5962-89815
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990 REVISION LEVEL
B SHEET 2
DSCC FORM 2234
APR 97
1. SCOPE
1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in
accordance with MIL-PRF-38535, appendix A.
1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following example:
5962-89815 01 K X
Drawing number Device type
(see 1.2.1) Case outline
(see 1.2.2) Lead finish
(see 1.2.3)
1.2.1 Device type(s). The device type(s) identify the circuit function as follows:
Device type Generic number Circuit function Setup time
01 7C245A-35 2K x 8 registered UV EPROM 35 ns
02 7C245A-25 2K x 8 registered UV EPROM 25 ns
03 7C245A-18 2K x 8 registered UV EPROM 18 ns
1.2.2 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows:
Outline letter Descriptive designator Terminals Package style
K GDFP2-F24 or CDFP3-F24 24 flat package 1/
L GDIP3-T24 or CDIP4-T24 24 dual-in-line package 1/
3 CQCC1-N28 28 square leadless chip carrier package 1/
1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A.
1.3 Absolute maximum ratings.
Supply voltage range (VCC) ............................................................ -0.5 V dc to +7.0 V dc
DC voltage applied to outputs in high Z state ................................ -0.5 V dc to +7.0 V dc
DC input voltage ............................................................................. -3.0 V dc to +7.0 V dc
DC program voltage ...................................................................... 13.0 V dc
Maximum power dissipation 2/ ..................................................... 1.0 W
Lead temperature (soldering, 10 seconds) .................................... +260°C
Thermal resistance, junction-to-case (θJC) ..................................... See MIL-STD-1835
Junction temperature (TJ) .............................................................. +175°C
Storage temperature range ........................................................... -65°C to +150°C
Temperature under bias ................................................................ -55°C to +125°C
Endurance ..................................................................................... 10 cycles/byte, minimum
Data retention ................................................................................ 10 years, minimum
1.4 Recommended operating conditions.
Supply voltage range (VCC) ............................................................. +4.5 V dc to +5.5 V dc
Ground voltage (GND) ................................................................... 0 V dc
Input high voltage (VIH) ................................................................... 2.0 V dc minimum
Input low voltage (VIL) .................................................................... 0.8 V dc maximum
Case operating temperature range (TC) ........................................ -55°C to +125°C
_______
1/ Lid shall be transparent to permit ultraviolet light erasure.
2/ Must withstand the added PD due to short circuit test (e.g., IOS).
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
5962-89815
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990 REVISION LEVEL
B SHEET 3
DSCC FORM 2234
APR 97
2. APPLICABLE DOCUMENTS
2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a
part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in
the solicitation or contract.
DEPARTMENT OF DEFENSE SPECIFICATION
MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for.
DEPARTMENT OF DEFENSE STANDARDS
MIL-STD-883 - Test Method Standard Microcircuits.
MIL-STD-1835 - Interface Standard Electronic Component Case Outlines.
DEPARTMENT OF DEFENSE HANDBOOKS
MIL-HDBK-103 - List of Standard Microcircuit Drawings.
MIL-HDBK-780 - Standard Microcircuit Drawings.
(Copies of these documents are available online at http://assist.daps.dla.mil/quicksearch/ or http://assist.daps.dla.mil or from the
Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.)
2.3 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of
this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a
specific exemption has been obtained.
3. REQUIREMENTS
3.1 Item requirements. The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for non-
JAN class level B devices and as specified herein. Product built to this drawing that is produced by a Qualified Manufacturer
Listing (QML) certified and qualified manufacturer or a manufacturer who has been granted transitional certification to MIL-
PRF-38535 may be processed as QML product in accordance with the manufacturers approved program plan and qualifying
activity approval in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Management (QM) plan
may make modifications to the requirements herein. These modifications shall not affect form, fit, or function of the device.
These modifications shall not affect the PIN as described herein. A "Q" or "QML" certification mark in accordance with MIL-
PRF-38535 is required to identify when the QML flow option is used.
3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified
in MIL-PRF-38535, appendix A and herein.
3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.2 herein.
3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1.
3.2.3 Truth table. The truth table shall be as specified on figure 2.
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
5962-89815
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990 REVISION LEVEL
B SHEET 4
DSCC FORM 2234
APR 97
3.2.3.1 Unprogrammed or erased devices. The truth table for unprogrammed devices for contracts involving no altered item
drawing shall be as specified on figure 2. When required in screening (see 4.2) group A, C, or D (see 4.3), the devices shall be
programmed by the manufacturer prior to test with a checkerboard pattern or equivalent (a minimum of 50 percent of the total
number of bits programmed) or to any altered item drawing pattern which includes at least 25 percent of the total number of bits
programmed.
3.2.3.2 Programmed devices. The truth table for programmed devices shall be as specified by an attached altered item
drawing.
3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristics are
as specified in table I and shall apply over the full case operating temperature range.
3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical
tests for each subgroup are described in table I.
3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, appendix A. The part shall be marked with the PIN listed
in 1.2 herein. In addition, the manufacturer's PIN may also be marked. For packages where marking of the entire SMD PIN
number is not feasible due to space limitations, the manufacturer has the option of not marking the "5962-" on the device.
3.5.1 Certification/compliance mark. A compliance indicator “C” shall be marked on all non-JAN devices built in compliance
to MIL-PRF-38535, appendix A. The compliance indicator “C” shall be replaced with a "Q" or "QML" certification mark in
accordance with MIL-PRF-38535 to identify when the QML flow option is used.
3.6 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in order to be listed as an
approved source of supply in MIL-HDBK-103 (see 6.6 herein). The certificate of compliance submitted to DSCC-VA prior to
listing as an approved source of supply shall affirm that the manufacturer's product meets the requirements of MIL-PRF-38535,
appendix A and the requirements herein.
3.7 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38535, appendix A shall be provided
with each lot of microcircuits delivered to this drawing.
3.8 Notification of change. Notification of change to DSCC-VA shall be required for any change that affects this drawing.
3.9 Verification and review. DSCC, DSCC's agent, and the acquiring activity retain the option to review the manufacturer's
facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the
reviewer.
3.10 Processing EPROMS. All testing requirements and quality assurance provisions herein, shall be satisfied by the
manufacturer prior to delivery.
3.10.1 Erasure of EPROMS. When specified, devices shall be erased in accordance with the procedures and characteristics
specified by the manufacturer.
3.10.2 Programmability of EPROMS. When specified, devices shall be programmed to the specified pattern using the
procedures and characteristics specified by the manufacturer.
3.10.3 Verification of programmed or erased EPROMs. When specified, devices shall be verified as either programmed to a
specified program, or erased. As a minimum, verification shall consist of performing a functional test (subgroup 7) to verify that
all bits are in the proper state. Any bit that does not verify to be in the proper state shall constitute a device failure, and shall be
removed from the lot.
3.11 Data retention. A data retention stress test shall be completed as part of the vendor's reliability monitors. This test shall
be done for initial characterization and after any design or process change which may affect data retention. The methods and
procedures may be vendor specific, but shall guarantee the number of years listed in section 1.3 herein over the full military
temperature range. The vendor's procedure shall be kept under document control and shall be made available upon request of
the acquiring or preparing activity, along with test data.
3.12 Endurance. A reprogrammability test shall be completed as part of the vendor's reliability monitors. This test shall be
done for initial characterization and after any design or process change which may affect the reprogrammability of the device.
The methods and procedures may be vendor specific, but shall guarantee the number of program/erase endurance cycles listed
in section 1.3 herein over the full military temperature range. The vendor's procedure shall be kept under document control and
shall be made available upon request of the acquiring or preparing activity, along with test data.
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
5962-89815
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990 REVISION LEVEL
B SHEET 5
DSCC FORM 2234
APR 97
TABLE I. Electrical performance characteristics.
Test
Symbol
Conditions 1/, 2/
-55°C ≤ TC ≤+125°C
4.5 V ≤ VCC ≤ 5.5 V
Group A
subgroups
Device
type
Limits Unit
unless otherwise specified Min Max
Output high voltage VOH V
CC = 4.5 V, IOH = -4.0 mA 1, 2, 3 All 2.4 V
VIN = VIH, VIL
Output low voltage VOL V
CC = 4.5 V, IOL = 16.0 mA 1, 2, 3 All 0.4 V
V
IN = VIH, VIL
Input high voltage 1/ VIH 1, 2, 3 All 2.0 V
Input low voltage 1/ VIL 1, 2, 3 All 0.8 V
Input leakage current IIX V
IN = VCC to GND 1, 2, 3 All -10 +10 µA
Output leakage current IOZ V
OUT = VCC to GND 1, 2, 3 All -40 +40 µA
3/
Output short circuit IOS V
CC = 4.5 V, and 5.5 V 1, 2, 3 All -20 -90 mA
current 4/, 5/ VOUT = 0.0 V
Power supply current I CC E/ES = VIL, INIT = VIH, 1, 2, 3 All 120 mA
Addresses cycling between
0 V and 3 V, VCC = 5.5 V,
f = PWCt2 1
Input capacitance 5/ CIN V
CC = 5.0 V, VIN = 0 V 4 All 10 pF
TA = +25°C, f = 1 MHz
(see 4.3.1c)
Output capacitance 5/ COUT V
CC = 5.0 V, VOUT = 0 V 4 All 10 pF
TA = +25°C, f = 1 MHz
(see 4.3.1c)
Functional tests See 4.3.1e 7, 8 All
Address setup to clock tSA See figures 3 and 4 6/ 9, 10, 11 01 35 ns
high 02 25
03 18
Address hold from clock tHA 9, 10, 11 All 0 ns
high
Clock high to valid tCO 9, 10, 11 01 15 ns
output 02, 03 12
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
5962-89815
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990 REVISION LEVEL
B SHEET 6
DSCC FORM 2234
APR 97
TABLE I. Electrical performance characteristics - Continued.
Test
Symbol
Conditions 1/, 2/
-55°C ≤ TC ≤+125°C
4.5 V ≤ VCC ≤ 5.5 V
Group A
subgroups
Device
type
Limits Unit
unless otherwise specified Min Max
Clock pulse width 5/ tPWC See figures 3 and 4 6/ 9, 10, 11 01 20 ns
02 15
03 12
ES setup to clock tSES 9, 10, 11 01 15 ns
high 5/ 02 12
03 10
ES hold from clock tHES 9, 10, 11 All 5 ns
high 5/
Delay from INIT to tDI 9, 10, 11 All 20 ns
valid output
INIT recovery to clock tRI 9, 10, 11 01 20 ns
high 02, 03 15
INIT pulse width tPWI 9, 10, 11 01 20 ns
02, 03 15
Valid output from clock tCOS 9, 10, 11 01 20 ns
high 5/, 7/ 02, 03 15
Inactive output from tHZC 9, 10, 11 01 20 ns
clock high 5/, 7/, 8/ 02, 03 15
Valid output from E low tDOE 9, 10, 11 01 20 ns
9/ 02, 03 15
Inactive output from tHZE 9, 10, 11 01 20 ns
E high 5/, 8/, 9/ 02, 03 15
1/ These are absolute voltages with respect to device ground pin and include all overshoots due to system or tester noise.
2/ AC tests are performed with input rise and fall times of 5 ns or less, timing reference levels of 1.5 V, input pulse levels
of 0 to 3.0 V, and the output load on figure 3.
3/ For devices using the synchronous enable, the device must be clocked after applying these voltages to perform this
measurement.
4/ For test purposes, not more than one output at a time should be shorted. Short circuit test duration should not exceed
30 seconds.
5/ This parameter tested initially and after any design or process changes which could affect this parameter, and therefore
shall be guaranteed to the limits specified in table I.
6/ See figure 3, circuit A, for all switching characteristics except tHZ.
7/ Applies only when the synchronous (ES) function is used.
8/ Transition is measured at steady-state high level -500 mV or steady-state low level +500 mV on the output from the
1.5 V level on the input with the output load on figure 3, circuit B.
9/ Applies only when the asynchronous (E) function is used.
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
5962-89815
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990 REVISION LEVEL
B SHEET 7
DSCC FORM 2234
APR 97
Device types All
Case outlines K, L 3
Terminal
number Terminal symbol
1 A7 NC
2 A6 A
7
3 A5 A
6
4 A4 A
5
5 A3 A
4
6 A2 A
3
7 A1 A
2
8 A0 A
1
9 O0 A
0
10 O1 NC
11 O2 O
0
12 GND O1
13 O3 O
2
14 O4 GND
15 O5 NC
16 O6 O
3
17 O7 O
4
18 CP O5
19 E/ES O6
20 INIT O7
21 A10 NC
22 A9 CP
23 A8 E/ES
24 VCC INIT
25 --- A10
26 --- A9
27 --- A8
28 --- VCC
FIGURE 1. Terminal connections.
Pin function
Mode A3 CP
E/ES INIT A0 Outputs
Read 1/ 2/ 3/ X X VIL V
IH X Data out
Output disable 1/ 4/ X X VIH V
IH X High Z
1/ X = Don't care.
2
/ During read operation, the output latches are loaded on a "0" to "1" transition of CP.
3
/ In the synchronous mode, pin ES must be low prior to the "0" to "1" transition on CP that loads the register.
4
/ In the synchronous mode, pin ES must be high prior to the "0" to "1" transition on CP that loads the register.
FIGURE 2. Truth table.
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
5962-89815
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990 REVISION LEVEL
B SHEET 8
DSCC FORM 2234
APR 97
3A 3B
(for tHZC and tHZE)
OUTPUT LOAD
NOTE: including scope and jig. (minimum values)
Input pulse levels GND to 3.0 V
Input rise and fall times ≤ 5 ns
Input timing reference levels 1.5 V
Output reference levels 1.5 V
FIGURE 3. Output load circuit and test conditions.
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
5962-89815
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990 REVISION LEVEL
B SHEET 9
DSCC FORM 2234
APR 97
FIGURE 4. Switching waveforms.
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
5962-89815
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990 REVISION LEVEL
B SHEET 10
DSCC FORM 2234
APR 97
4. VERIFICATION
4.1 Sampling and inspection. Sampling and inspection procedures shall be in accordance with MIL-PRF-38535,
appendix A.
4.2 Screening. Screening shall be in accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices
prior to quality conformance inspection. The following additional criteria shall apply:
a. Burn-in test, method 1015 of MIL-STD-883.
(1) Test condition D. The test circuit shall be maintained by the manufacturer under document revision level control
and shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify the
inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1015
of MIL-STD-883.
(2) TA = +125°C, minimum.
b. Interim and final electrical test parameters shall be as specified in table II herein, except interim electrical parameter
tests prior to burn-in are optional at the discretion of the manufacturer.
TABLE II. Electrical test requirements.
MIL-STD-883 test requirements Subgroups
(in accordance with
MIL-STD-883, method 5005,
table I)
Interim electrical parameters
(method 5004) 1
Final electrical test parameters
(method 5004) 1*, 2, 3, 7*, 8A, 8B, 9, 10, 11
Group A test requirements
(method 5005) 1, 2, 3, 4**,7, 8A, 8B, 9, 10, 11
Groups C and D end-point
electrical parameters
(method 5005)
2, 3, 7, 8A, 8B
1
/ * Indicates PDA applies to subgroups 1 and 7.
2
/ Any or all subgroups may be combined when using
high-speed testers.
3
/ ** See 4.3.1c.
4.3 Quality conformance inspection. Quality conformance inspection shall be in accordance with method 5005 of MIL-STD-
883 including groups A, B, C, and D inspections. The following additional criteria shall apply.
4.3.1 Group A inspection.
a. Tests shall be as specified in table II herein.
b. Subgroups 5 and 6 in table I, method 5005 of MIL-STD-883 shall be omitted.
c. Subgroup 4 (CIN and COUT measurement) shall be measured only for the initial test and after process or design
changes which may affect input or output capacitance. Sample size is 15 devices with no failures, and all input and
output terminals tested.
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
5962-89815
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990 REVISION LEVEL
B SHEET 11
DSCC FORM 2234
APR 97
d. All devices selected for testing shall be programmed with a checkerboard pattern or equivalent. After completion of all
testing, the devices shall be erased and verified (except devices submitted for groups C and D testing).
e. Subgroups 7 and 8 shall include verification of the truth table and the EPROM pattern specified in 4.3.1d.
4.3.2 Groups C and D inspections.
a. End-point electrical parameters shall be as specified in table II herein.
b. Steady-state life test conditions, method 1005 of MIL-STD-883.
(1) Test condition D. The test circuit shall be maintained by the manufacturer under document revision level control
and shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify the
inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method
1005 of MIL-STD-883.
(2) TA = +125°C, minimum.
(3) Test duration: 1,000 hours, except as permitted by method 1005 of MIL-STD-883.
c. All devices submitted for testing shall be programmed with a checkerboard pattern, or equivalent. After completion of
all testing, the devices shall be erased and verified.
5. PACKAGING
5.1 Packaging requirements. The requirements for packaging shall be in accordance with MIL-PRF-38535, appendix A.
6. NOTES
6.1 Intended use. Microcircuits conforming to this drawing are intended for use for Government microcircuit applications
(original equipment), design applications, and logistics purposes.
6.2 Replaceability. Microcircuits covered by this drawing will replace the same generic device covered by a contractor-
prepared specification or drawing.
6.3 Configuration control of SMD's. All proposed changes to existing SMD's will be coordinated with the users of record for
the individual documents. This coordination will be accomplished using DD Form 1692, Engineering Change Proposal.
6.4 Record of users. Military and industrial users shall inform Defense Supply Center Columbus (DSCC) when a system
application requires configuration control and the applicable SMD. DSCC will maintain a record of users and this list will be
used for coordination and distribution of changes to the drawings. Users of drawings covering microelectronics devices (FSC
5962) should contact DSCC-VA, telephone (614) 692-0544.
6.5 Comments. Comments on this drawing should be directed to DSCC-VA, Columbus, Ohio 43218-3990, or telephone
(614) 692-0547.
6.6 Approved sources of supply. Approved sources of supply are listed in MIL-HDBK-103. The vendors listed in MIL-
HDBK-103 have agreed to this drawing and a certificate of compliance (see 3.6 herein) has been submitted to and accepted by
DSCC-VA.
STANDARD MICROCIRCUIT DRAWING BULLETIN
DATE: 07-02-13
Approved sources of supply for SMD 5962-89815 are listed below for immediate acquisition information only and shall
be added to MIL-HDBK-103 and QML-38535 during the next revision. MIL-HDBK-103 and QML-38535 will be revised
to include the addition or deletion of sources. The vendors listed below have agreed to this drawing and a certificate
of compliance has been submitted to and accepted by DSCC-VA. This information bulletin is superseded by the next
dated revision of MIL-HDBK-103 and QML-38535. DSCC maintains an online database of all current sources of
supply at http://www.dscc.dla.mil/Programs/Smcr/.
Standard
microcircuit drawing
PIN 1/
Vendor
CAGE
number
Vendor
similar
PIN 2/
5962-8981501LA 0C7V7 WS57C45-35KMB
0C7V7 QP7C245A-35WMB
3/ CY7C245A-35WMB
5962-8981501KA 0C7V7 WS57C45-35HMB
0C7V7 QP7C245A-35TMB
3/ CY7C245A-35TMB
5962-89815013A 0C7V7 WS57C45-35ZMB
0C7V7 QP7C245A-35QMB
3/ CY7C245A-35QMB
5962-89815013C 0C7V7 WS57C45-35ZMB
5962-8981502LA 0C7V7 WS57C45-25KMB
0C7V7 QP7C245A-25WMB
3/ CY7C245A-25WMB
5962-8981502KA 0C7V7 WS57C45-25HMB
0C7V7 QP7C245A-25TMB
3/ CY7C245A-25TMB
5962-89815023A 0C7V7 WS57C45-25ZMB
0C7V7 QP7C245A-25QMB
3/ CY7C245A-25QMB
STANDARD MICROCIRCUIT DRAWING BULLETIN - continued.
Standard
microcircuit drawing
PIN 1/
Vendor
CAGE
number
Vendor
similar
PIN 2/
5962-89815023C 0C7V7 WS57C45-25ZMB
5962-8981503LA 0C7V7 CY7C245A-18WMB
0C7V7 QP7C245A-18WMB
3/ CY7C245A-18WMB
5962-8981503KA 0C7V7 7C245A/KA
0C7V7 QP7C245A-18TMB
3/ CY7C245A-18TMB
5962-89815033A 0C7V7 QP7C245A-18QMB
3/ CY7C245A-18QMB
1/ The lead finish shown for each PIN representing
a hermetic package is the most readily available
from the manufacturer listed for that part. If the
desired lead finish is not listed contact the vendor
to determine its availability.
2/ Caution. Do not use this number for item
acquisition. Items acquired to this number may not
satisfy the performance requirements of this drawing.
3/ Not available from an approved source of supply.
Vendor CAGE Vendor name
number and address
0C7V7 QP Semiconductor
2945 Oakmead Village Ct.
Santa Clara, CA 95051-0812
The information contained herein is disseminated for convenience only and the
Government assumes no liability whatsoever for any inaccuracies in the
information bulletin.
