TB62777FNG,EL - TOSHIBA - Datasheet.Live

TB62777FNG/FG

TOSHIBA Bi-CMOS Integrated Circuit Silicon Monolithic

TB62777FNG, TB62777FG

8-Channel Constant-Current LED Driver of the 3.3-V and 5-V Power Supply Voltage

Operation

TB62777FNG

TB62777FG

Weight: SSOP16-P-225-0.65B 0.07 g (typ.)

SSOP16-P-225-1.00A 0.14 g

(typ.)

The TB62777FNG/FG is comprised of constant-current drivers

designed for LEDs and LED panel displays.

The regulated current sources are designed to provide a

constant current, which is adjustable through one external

resistor.

The TB62777FNG/FG incorporates eight channels of shift

registers, latches, AND gates and constant-current outputs.

Fabricated using the Bi-CMOS process, the TB62777FNG/FG is

capable of high-speed data transfers.

The TB62777FNG/FG is RoHS.

Features

• Power supply voltages: VDD = 3.3 V/5 V

• Output drive capability and output count: 50 mA × 8 channels

• Constant-current output range: 5 to 40 mA

• Voltage applied to constant-current output terminals: 0.4 V

(min, IOUT = 5 to 40 mA)

• Designed for common-anode LEDs

• Thermal shutdown (TSD)（min: 150℃）

• Power on reset (POR)

• Logical input signal voltage level: 3.3-V and 5-V CMOS

interfaces (Schmitt trigger input)

• Maximum output voltage: 25V

• Serial data transfer rate: 25 MHz (max) @cascade connection

• Operating temperature range: Topr = −40 to 85°C

• Package: SSOP16-P-225-0.65B/ SSOP16-P-225-1.00A

• Constant-current accuracy

Output Voltage Current accuracy

Between Channels Current Accuracy

Between ICs Output Current

0.4 V to 4 V ±3% ±6% 15 mA

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TB62777FNG/FG

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Pin Assignment (top view)

Block Diagram

Truth Table

CLOCK LATCH ENABLE SERIAL-IN OUT0 … OUT5 … OUT7 SERIAL-OUT

H L Dn Dn … Dn − 5 … Dn − 7 No change

L L Dn + 1 No Change No change

H L Dn + 2 Dn + 2 … Dn − 3 … Dn − 5 No change

X H Dn + 3 OFF No change

X H Dn + 3 OFF Dn －4

Note 1: OUT0 to OUT7 = On when Dn = H; OUT0 to OUT7 = Off when Dn = L.

GND

SERIAL-IN

LATCH

CLOCK

OUT0

OUT1

OUT2

OUT3

VDD

R-EXT

SERIAL-OUT

ENABLE

OUT7

OUT6

OUT5

OUT4

SERIAL-IN

LATCH

OUT0

R-EXT

ENABLE

ST D

CLOCK

OUT1 OUT7

D Q

SERIAL-OUT

I-REG

8-bit shift register

Q0 Q1 Q7

D0 to D7

TSD VDD

GND

POR

R RR

TB62777FNG/FG

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Timing Diagram

Note 1: Latches are level-sensitive, not edge-trig gered.

Note 2: The TB62777FNG can be used at 3.3 V or 5.0 V. However , the VDD supply voltage must be equal to the input

voltage.

Note 3: Serial data is shifted out of SERIAL-OUT on the falling edge of CLOCK.

Marks: The latches hold data while the LATCH terminal is held Low. When the LATCH terminal is High, the

latches do not hold data and pass it transparently. When the ENABLE terminal is Low, OUT0 to OUT7

toggle between ON and OFF according to the data. When t he ENABLE terminal is High, OUT0 to

OUT7 are forced OFF.

SERIAL-IN

LATCH

CLOCK

OUT0

OUT1

SERIAL-OUT

ENABLE

OUT7

n = 0 1 2 34567

OFF

Data applied wh en n = 0

2OUT

TB62777FNG/FG

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Terminal Description

Pin No. Pin Name Function

1 GND GND terminal

2 SERIAL-IN Serial data input terminal

3 CLOCK Serial clock input terminal

4 LATCH Latch input terminal

5 OUT0 Constant-current output terminal (Open collector)

6 OUT1 Constant-current output terminal (Open collector)

7 2OUT Constant-current output terminal (Open collector)

8 OUT3 Constant-current output terminal (Open collector)

9 OUT4 Constant-current output terminal (Open collector)

10 OUT5 Constant-current output terminal (Open collector)

11 OUT6 Constant-current output terminal (Open collector)

12 OUT7 Constant-current output terminal (Open collector)

13 ENABLE Output enable input terminal

All outputs (OUT0 to OUT7 ) are disabled when the ENABLE terminal is driven High, and

enabled when it is driven Low.

14 SERIAL-OUT Serial data output terminal. Serial data is clocked out on the falling edge of CLOCK.

15 R-EXT

An external resistor is connected between this terminal and ground. OUT0 to OUT7 are adjusted

to the same current value.

16 VDD Power supply terminal

Equivalent Circuits for Inputs and Outputs

CLOCK, SERIAL-IN ，ENABLE ，LATCH

Terminals SERIAL-OUT Terminal

OUT0 to OUT7 Constant-current

Output Terminals

VDD

ENABLE

LATCH

GND

CLOCK

SERIAL-IN

VDD

GND

SERIAL-OUT

OUT0 ~OUT7

GND

TB62777FNG/FG

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Absolute Maximum Ratings (Ta = 25°C)

Characteristics Symbol Rating Unit

Supply voltage VDD 6.0 V

Input voltage VIN −0.3 to VDD + 0.3 (Note 1) V

Output current IOUT 55 mA/ch

Output voltage VOUT −0.3 to 25 V

Power dissipation Pd 1.19(FG TYPE) / 1.02(FNG TYPE) (Notes 2 and 3) W

Thermal resistance Rth (j-a) 105(FG TYPE) / 122(FNG TYPE) (Note 2) °C/W

Operating temperature range Topr −40 to 85 °C

Storage temperature range Tstg −55 to 150 °C

Maximum junction temperature Tj 150 °C

Note 1: However, do not exceed 6.0 V.

Note 2: When mounted on a PCB (76.2 × 114. 3 × 1.6 mm; Cu = 30%; 35-μm-thick; SEMI-compliant)

Note 3: Power dissipation is reduced by 1/Rth (j-a) for each °C above 25°C ambient.

Operating Ranges (unless otherwise specified, Ta = −40°C to 85°C)

Characteristics Symbol Test Condition Min Typ. Max Unit

Supply voltage VDD ⎯ 3 ⎯ 5.5 V

Output voltage VOUT 0OUT to 7OUT 0.4 ⎯ 4 V

IOUT 0OUT to 7OUT 5 ⎯ 40 mA/ch

IOH SERIAL-OUT ⎯ ⎯ −5

Output current

IOL SERIAL-OUT ⎯ ⎯ 5

VIH 0.7 ×

VDD ⎯ V

Input voltage VIL

SERIAL-IN/CLOCK/

LATCH /ENABLE GND ⎯ 0.3 ×

VDD

Clock frequency fCLK Cascade connection ⎯ ⎯ 25 MHz

LATCH pulse width twLAT (Note 2) 20 ⎯ ⎯

CLOCK pulse width twCLK (Note 2) 20 ⎯ ⎯ ns

IOUT ≥ 20 mA (Note 2) 2 ⎯ ⎯

ENABLE pulse width twENA 5 mA ≤ IOUT ≤ 20 mA (Note 2) 3 ⎯ ⎯ μs

tSETUP1 5 ⎯ ⎯

Setup time tSETUP2 5 ⎯ ⎯

tHOLD1 5 ⎯ ⎯

Hold time tHOLD2

(Note 2)

5 ⎯ ⎯

Maximum clock rise time tr ⎯ ⎯ 5

Maximum clock fall time tf Single operation (Notes 1 and 2)

⎯ ⎯ 5 μs

Note 1: For cascade operation, the CLOCK waveform might become ambiguous, causing the tr and tf values to be

large. Then it may not be possible to meet the timing requirement for data transfer. Please consider the

timing carefully.

Note 2: Please see the timing wavefor m on page 9.

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Electrical Characteristics (Unless otherwise specified, Ta = 25°C, VDD = 4.5 to 5.5 V)

Characteristics Symbol

Test

Circuit Test Condition Min Typ. Max Unit

Output current IOUT1 5

VOUT = 0.4 V, R-EXT = 1.2 kΩ

VDD = 5 V, ― 15 ― mA

Output current error between ICs ΔIOUT1 5 VOUT = 0.4 V, R-EXT = 1.2 kΩ

All channels ON VDD = 5 V, ― ±3 ±6 ％

Output current error between channels ΔIOUT2 5

VOUT = 0.4 V, R-EXT = 1.2 kΩ

All channels ON VDD = 5 V ⎯ ±1 ±3 %

Output leakage current IOZ 5 VOUT = 25 V ⎯ ⎯ 1 μA

VIH ⎯ SERIAL-IN/CLOCK/LATCH /

ENABLE 0.7 ×

VDD ⎯ V

Input voltage

VIL ⎯ SERIAL-IN/CLOCK/LATCH /

ENABLE GND ⎯ 0.3 ×

VDD

IIH 2

VIN = VDD CLOCK/SERIAL-IN

/LATCH /ENABLE ― ― 1

Input current

IIL 3

VIN = GND

CLOCK/SERIAL-IN/LATCH /

ENABLE ― ― −1

μA

VOL 1 IOL = 5.0 mA, VDD = 5 V ⎯ ⎯ 0.3

SERIAL-OUT output voltage VOH 1 IOH = −5.0 mA, VDD = 5 V 4.7 ⎯ ⎯ V

Changes in constant output current

dependent on VDD %/VDD 5 VDD = 3 V to 5.5 V ⎯ 1 2 %

IDD (OFF) 1 4 R-EXT = OPEN, VOUT = 25.0 V ⎯ ⎯ 1

IDD (OFF) 2 4 R-EXT = 1.2 kΩ, VOUT = 25.0 V,

All channels OFF ⎯ ⎯ 5

Supply current

IDD (ON) 4

R-EXT = 1.2 kΩ, VOUT = 0.4 V,

All channels ON ⎯ ⎯ 9

Switching Characteristics (Unless otherwise specified, Ta = 25°C, VDD = 4.5 to 5.5V)

Note 1: Topr = 25°C, VDD = VIH = 5 V, VIL = 0 V, REXT = 1.2 kΩ, IOUT = 15 mA, VL = 5.0 V,

CL = 10.5 pF (see test circuit 6.)

Characteristics Symbol

Test

Circuit Test Condition (Note 1) Min Typ. Max Unit

tpLH1 6

CLK-OUTn , LATCH = “H”,

ENABLE = “L” ⎯ 20 300

tpLH2 6

LATCH −OUTn ,

ENABLE = “L” ⎯ 20 300

tpLH3 6

ENABLE −OUTn ,

LATCH = “H” ⎯ 20 300

tpLH 6 CLK-SERIAL OUT 2 10 14

tpHL1 6

CLK-OUTn , LATCH = “H”,

ENABLE = “L” ⎯ 30 340

tpHL2 6

LATCH −OUTn ,

ENABLE = “L” ⎯ 70 340

tpHL3 6

ENABLE −OUTn ,

LATCH = “H” ⎯ 70 340

Propagation delay time

tpHL 6 CLK-SERIAL OUT 2 10 14

Output rise time tor 6

10% to 90% points of OUT0

to OUT7 voltage waveforms ― 20 150

Output fall time tof 6

90% to 10% points of OUT0

to OUT7 voltage waveforms ― 125. 300

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Electrical Characteristics (Unless otherwise specified, Ta = 25°C, VDD = 3 to 3.6 V)

Characteristics Symbol

Test

Circuit Test Condition Min Typ. Max Unit

Output current IOUT1 5 VOUT = 0.4 V, R-EXT = 1.2 kΩ

VDD = 3.3 V ― 15 ― mA

Output current error between ICs ΔIOUT1 5 VOUT = 0.4 V, R-EXT = 1.2 kΩ

All channels ON VDD = 3.3 V ― ±3 ±6 %

Output current error between channels ΔIOUT2 5 VOUT = 0.4 V, R-EXT = 1.2 kΩ

All channels ON VDD = 3.3 V ⎯ ±1 ±3 %

Output leakage current IOZ 5 VOUT = 25 V ⎯ ⎯ 1 μA

VIH ⎯ SERIAL-IN/CLOCK/LATCH /

ENABLE 0.7 ×

VDD ⎯ V

Input voltage

VIL ⎯ SERIAL-IN/CLOCK/LATCH /

ENABLE GND ⎯ 0.3 ×

VDD

IIH 2

VIN = VDD

CLOCK/SERIAL-IN/LATCH /

ENABLE ― ― 1

Input current

IIL 3

VIN = GND

CLOCK/SERIAL-IN/LATCH /

ENABLE ― ― −1

μA

VOL 1 IOL = 5.0 mA, VDD = 3.3 V ⎯ ⎯ 0.3

SERIAL-OUT output voltage VOH 1 IOH = −5.0 mA, VDD = 3.3 V 3.0 ⎯ ⎯ V

Changes in constant output current

dependent on VDD %/VDD 5 VDD = 3 V to 5.5 V ⎯ 1 2 %

IDD (OFF) 1 4 R-EXT = OPEN, VOUT = 25.0 V ⎯ ⎯ 1

IDD (OFF) 2 4 R-EXT = 1.2 kΩ, VOUT = 25.0 V,

All channels OFF ⎯ ⎯ 5

Supply current

IDD (ON) 4 R-EXT = 1.2 kΩ, VOUT = 0.4 V,

All channels ON ⎯ ⎯ 9

Switching Characteristics (Unless otherwise specified, Ta = 25°C, VDD = 3 to 3.6 V)

Note 1: Topr = 25°C, VDD = VIH = 3.3 V, VIL = 0 V, REXT = 1.2 kΩ, IOUT = 15 mA, VL = 5.0 V,

CL = 10.5 pF (see test circuit 6.)

Characteristics Symbol

Test

Circuit Test Condition (Note 1) Min Typ. Max Unit

tpLH1 6 CLK- OUTn , LATCH = “H”,

ENABLE = “L” ⎯ ⎯ 300

tpLH2 6 LATCH -OUTn ,

ENABLE = “L” ⎯ ⎯ 300

tpLH3 6 ENABLE -OUTn ,

LATCH = “H” ⎯ ⎯ 300

tpLH 6 CLK-SERIAL OUT 2 ⎯ 14

tpHL1 6 CLK- OUTn , LATCH = “H”,

ENABLE = “L” ⎯ ⎯ 340

tpHL2 6 LATCH - OUTn ,

ENABLE = “L” ⎯ ⎯ 340

tpHL3 6 ENABLE -OUTn ,

LATCH = “H” ⎯ ⎯ 340

Propagation delay time

tpHL 6 CLK-SERIAL OUT 2 ⎯ 14

Output rise time tor 6 10% to 90% points of OUT0

to OUT7 voltage waveforms ⎯ ⎯ 150

Output fall time tof 6 90% to 10% points of OUT0

to OUT7 voltage waveforms ⎯ ⎯ 300

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Test Circuits

Test Circuit 1: SERIAL-OUT output voltage (VOH/VOL)

Test Circuit 2: Input Current (IIH)

Test Circuit 3: Input Current (IIL)

REXT

VDD OUT0

OUT7

CL = 10.5 pF

= 4.5 to 5.5 V、3 to 3.6V

GND

SERIAL-IN

LATCH

CLOCK

ENABLE

R-EXT SERIAL-OUT

REXT

VDD OUT0

OUT7

CL = 10.5 pF

VIN = VDD A

VDD = 4.5 to 5.5 V、3 to 3.6V

GND

SERIAL-IN

LATCH

CLOCK

ENABLE

R-EXT SERIAL-OUT

VDD OUT0

OUT7

GND

IO = −5 mA to 5 mA

CL = 10.5 pF

VDD = 5 V、3.3V

F.G

VIH = VDD

VIL = 0 V

tr = tf = 10 ns

(10 to 90%)

REXT

SERIAL-IN

LATCH

CLOCK

ENABLE

R-EXT SERIAL-OUT

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Test Circuit 4: Supply Current

Note: The output terminal is based on the power supply current conditions on page 6 and 7.

Test Circuit 5: Output Current (IOUT1), Output Leakage Current (IOZ), Output Current Error

Margin (ΔIOUT1/ΔIOUT2), Current Variation with VDD (%/VDD)

VDD OUT0

OUT7

CL = 10.5 pF

F.G

VDD = 4.5 to 5.5 V、3 to 3.6V

GND

SERIAL-IN

LATCH

CLOCK

ENABLE

R-EXT SERIAL-OUT

VIH = VDD

VIL = 0 V

tr = tf = 10 ns

(10 to 90%)

REXT = 1.2 kΩ

VOUT = 0.4 V, 25 V

Theoretical output current = 1.13 V/REXT × 16

OUT7

CL = 10.5 pF

F.G

VIH = VDD

VIL = 0 V

tr = tf = 10 ns

(10 to 90%)

= 4.5 to 5.5 V、3 to 3.6V

GND

SERIAL-IN

LATCH

CLOCK

ENABLE

R-EXT SERIAL-OUT

OUT0

REXT = 1.2 kΩ

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Test Circuit 6: Switching Characteristics

IOUT

VDD OUT0

OUT7

CL = 10.5 pF

F.G

VDD = 4.5 to 5.5 V、3 to 3.6V

GND

SERIAL-IN

LATCH

CLOCK

ENABLE

R-EXT SERIAL-OUT

VIH = VDD

VIL = 0 V

tr = tf = 10 ns

(10 to 90%)

VL = 5 V

10.5

REXT = 1.2 kΩ

RL=300Ω

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Timing Waveforms

1. CLOCK, SERIAL-IN, SERIAL-OUT

2. CLOCK, SERIAL-IN, LATCH, ENABLE, OUTn

3. OUTn

Note: Timing chart waveforms are presented to describe functions and operations and may be simplified. Adequate

consideration should be given to timing con ditions.

tof

10%

90%

10%

90%

tor

OUTn

OFF

twENA

50%

tHOLD2

SERIAL-IN

CLOCK

50%

50% 50%

tpHL1/LH1

tpHL2/LH2 tpHL3/LH3

twLAT

ENABLE

LATCH

OUTn

50%

tSETUP2

50%

twENA

tHOLD1

tpLH/tpHL

twCLK

50%50%

50% 50%

tSETUP1

SERIAL-IN

CLOCK

SERIAL-OUT 50%

90%

10% 90%

10%

TB62777FNG/FG

Output Current vs. Derating (lighting rate) Graph

PCB Conditions: 76.2 × 114.3 × 1.6 mm, Cu = 30%, 35-μm Thick, SEMI-Compliant

TB62777FNG

1500

1.4

1.2

Pd-Ta

(°C)

Ta100

0.0

0.2

0.4

0.6

0.8

1.0

Pd(W)

IOUT − Duty ON PCB

100

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Output Current vs. External Resistor (typ.)

The above graphs are presented merely as a guide and do not constitute any guarantee as to the performance or

characteristics of the device. Each product design should be fully evaluated in a real-world environment.

IOUT (mA)

ON PCB

All outputs ON

Ta = 85°C

VDD = 5.0 V

VOUT = 1.0 V

0 20 40 60 80 100

Duty − Turn-ON rate (%)

OUT

- R

EXT

100 1000 10000

EXT

(Ω)

IOUT − REXT

IOUT (A) = 1.13 (V) ÷ REXT (Ω)) × 16

Theoretical value

OUT

(mA)

IOUT (mA)

All outputs ON

Ta = 25°C

VOUT = 0.7 V

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Application Circuit 1: General Composition for Static Lighting of LEDs

In the following diagram, it is recommended that the LED supply voltage (VLED) be equal to or greater than the sum of Vf (max) of all LEDs plus 0.7 V.

O0 O1 O2 O5 O6 O7

C.U.

SERIAL-IN

ENABLE

LATCH

CLOCK

VLED

SERIAL-OUT

SERIAL-OUTSERIAL-IN

ENABLE

LATCH

CLOCK

O0 O1 O2 O5 O6 O7

TB62777FNG/FG

R-EXT R-EXTGND GND

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Application Circuit 2: General Composition for Dynamic Lighting of LEDs

In the following diagram, it is recommended that the LED supply voltage (VLED) be equal to or greater than the sum of Vf (max) of all LEDs plus 0.7 V.

O0 O1 O6 O7

C.U.

SERIAL-IN

ENABLE

LATCH

CLOCK

VLED

SERIAL-OUT

Example) TD62M8600FG 8 bit multichip PNP transistor array.

It is not necessary when lighting statically.

SERIAL-IN

ENABLE

LATCH

CLOCK

O0 O1 O6

TB62777FNG/FG

R-EXT R-EXT

GND GND

TB62777FNG/FG

Package Dimensions

Weight: 0.07 g (typ.)

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TB62777FNG/FG

Package Dimensions

Weight: 0.14 g (typ.)

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TB62777FNG/FG

Notes on Contents

1. Block Diagrams

Some of the functional blocks, circuits, or constants in the block diagram may be omitted or simplified for

explanatory purposes.

2. Equivalent Circuits

The equivalent circuit diagrams may be simplified or some parts of them may be omitted for explanatory

purposes.

3. Timing Charts

Timing charts may be simplified for explanatory purposes.

4. Application Circuits

The application circuits shown in this document are provided for reference purposes only. Thorough

evaluation is required, especially at the mass production design stage.

Toshiba does not grant any license to any industrial property rights by providing these examples of

application circuits.

5. Test Circuits

Components in the test circuits are used only to obtain and confirm the device characteristics. These

components and circuits are not guaranteed to prevent malfunction or failure from occurring in the

application equipment.

IC Usage Considerations

Notes on handling of ICs

(1) The absolute maximum ratings of a semiconductor device are a set of ratings that must not be

exceeded, even for a moment. Do not exceed any of these ratings.

Exceeding the rating(s) may cause breakdown, damage or deterioration of the device, and may result

in injury by explosion or combustion.

(2) Use an appropriate power supply fuse to ensure that a large current does not continuously flow in the

event of over current and/or IC failure. The IC will fully break down when used under conditions that

exceed its absolute maximum ratings, when the wiring is routed improperly or when an abnormal

pulse noise occurs from the wiring or load, causing a large current to continuously flow. Such a

breakdown can lead to smoke or ignition. To minimize the effects of a large current flow in the event of

breakdown, fuse capacity, fusing time, insertion circuit location, and other such suitable settings are

required.

(3) If your design includes an inductive load such as a motor coil, incorporate a protection circuit into the

design to prevent device malfunction or breakdown caused by the current resulting from the inrush

current at power ON or the negative current resulting from the back electromotive force at power OFF.

IC breakdown may cause injury, smoke or ignition.

For ICs with built-in protection functions, use a stable power supply with. An unstable power supply

may cause the protection function to not operate, causing IC breakdown. IC breakdown may cause

injury, smoke or ignition.

(4) Do not insert devices incorrectly or in the wrong orientation. Make sure that the positive and negative

terminals of power supplies are connected properly. Otherwise, the current or power consumption may

exceed the absolute maximum rating, and exceeding the rating(s) may cause breakdown, damage or

deterioration of the device, which may result in injury by explosion or combustion. In addition, do not

use any device that has had current applied to it while inserted incorrectly or in the wrong orientation

even once.

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TB62777FNG/FG

(5) Carefully select power amp, regulator, or other external components (such as inputs and negative

feedback capacitors) and load components (such as speakers).

If there is a large amount of leakage current such as input or negative feedback capacitors, the IC

output DC voltage will increase. If this output voltage is connected to a speaker with low input

withstand voltage, overcurrent or IC failure can cause smoke or ignition. (The over current can cause

smoke or ignition from the IC itself.) In particular, please pay attention when using a Bridge Tied Load

(BTL) connection type IC that inputs output DC voltage to a speaker directly.

Points to remember on handling of ICs

(1) Heat Dissipation Design

In using an IC with large current flow such as a power amp, regulator or driver, please design the

device so that heat is appropriately dissipated, not to exceed the specified junction temperature (Tj) at

any time or under any condition. These ICs generate heat even during normal use. An inadequate IC

heat dissipation design can lead to decrease in IC life, deterioration of IC characteristics or IC

breakdown. In addition, please design the device taking into consideration the effect of IC heat

dissipation on peripheral components..

(2) Back-EMF

When a motor rotates in the reverse direction, stops, or slows down abruptly, a current flow back to the

motor’s power supply due to the effect of back-EMF. If the current sink capability of the power supply

is small, the device’s motor power supply and output pins might be exposed to conditions beyond

maximum ratings. To avoid this problem, take the effect of back-EMF into consideration in your

system design.

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TB62777FNG/FG

About solderability, following conditions were confirmed

• Solderability

(1) Use of Sn-37Pb solder Bath

· solder bath temperature = 23 0°C

· dipping time

= 5 seconds

· the number of times = once

· use of R-type flux

(2) Use of Sn-3.0Ag-0.5Cu solder Bath

· solder bath temperature = 24 5°C

· dipping time

= 5 seconds

· the number of times = once

· use of R-type flux

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TB62777FNG/FG

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relevant TOSHIBA information, including without limitation, this document, the specifications, the data sheets and application notes for

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• ABSENT A WRITTEN SIGNED AGREEMENT, EXCEPT AS PROVIDED IN THE RELEVANT TERMS AND CONDITIONS OF SALE

FOR PRODUCT, AND TO THE MAXIMUM EXTENT ALLOWABLE BY LAW, TOSHIBA (1) ASSUMES NO LIABILITY

WHATSOEVER, INCLUDING WITHOUT LIMITATION, INDIRECT, CONSEQUENTIAL, SPECIAL, OR INCIDENTAL DAMAGES OR

LOSS, INCLUDING WITHOUT LIMITATION, LOSS OF PROFITS, LOSS OF OPPORTUNITIES, BUSINESS INTERRUPTION AND

LOSS OF DATA, AND (2) DISCLAIMS ANY AND ALL EXPRESS OR IMPLIED WARRANTIES AND CONDITIONS RELATED TO

SALE, USE OF PRODUCT, OR INFORMATION, INCLUDING WARRANTIES OR CONDITIONS OF MERCHANTABILITY, FITNESS

FOR A PARTICULAR PURPOSE, ACCURACY OF INFORMATI ON, OR NONINF RINGEME NT.

• Do not use or otherwise make available Product or related software or technology for any military purposes, including without limitation,

for the design, development, use, stockpiling or manufacturing of nuclear, chemical, or biological weapons or missile technology

products (mass destruction weapons). Product and related software and technology may be controlled under the Japanese Foreign

Exchange and Foreign Trade Law and the U.S. Export Administration Regulations. Export and re-export of Product or related software

or technology are strictly prohibited except in compliance with all applicable export laws and regulations.

• Please contact your TOSHIBA sales representative for details as to environmental matters such as the RoHS compatibility of Product.

Please use Product in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances,

including without limitation, the EU RoHS Directive. TOSHIBA assumes no liability for damages or losses occurring as a result of

noncompliance with applicable laws and regulations.