SGLS008B - MARCH 2003 - REVISED MAY 2004 D Qualification in Accordance With D D D D D D D D D Input Noise Voltage . . . 11 nV/Hz D Slew Rate . . . 1.6 V/s D Micropower Shutdown Mode AEC-Q100 Qualified for Automotive Applications Customer-Specific Configuration Control Can Be Supported Along With Major-Change Approval ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Rail-to-Rail Output Swing Gain Bandwidth Product . . . 6.4 MHz 80 mA Output Drive Capability Supply Current . . . 500 A/channel Input Offset Voltage . . . 100 V D (TLV2460/3/5) . . . 0.3 A/Channel Universal Operational Amplifier EVM TLV2460 D OR PW PACKAGE (TOP VIEW) NC IN - IN + GND 1 8 2 7 3 6 4 5 SHDN VDD+ OUT NC Contact factory for details. Q100 qualification data available on request. description The TLV246x is a family of low-power rail-to-rail input/output operational amplifiers specifically designed for portable applications. The input common-mode voltage range extends beyond the supply rails for maximum dynamic range in low-voltage systems. The amplifier output has rail-to-rail performance with high-output-drive capability, solving one of the limitations of older rail-to-rail input/output operational amplifiers. This rail-to-rail dynamic range and high output drive make the TLV246x ideal for buffering analog-to-digital converters. The operational amplifier has 6.4 MHz of bandwidth and 1.6 V/s of slew rate with only 500 A of supply current, providing good ac performance with low power consumption. Devices are available with an optional shutdown terminal, which places the amplifier in an ultralow supply current mode (IDD = 0.3 A/ch). While in shutdown, the operational-amplifier output is placed in a high-impedance state. DC applications are also well served with an input noise voltage of 11 nV/Hz and input offset voltage of 100 V. ORDERING INFORMATION PACKAGE TA -40C to 125C SOP - D Tape and reel ORDERABLE PART NUMBER TOP-SIDE MARKING TLV2464AQDRQ1 V2464AQ1 -40C to 125C TSSOP - PW Tape and reel TLV2464AQPWRQ1 V2464AQ Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. All other device/package combinations are Product Preview. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2003 - 2004 Texas Instruments Incorporated !"#$%&" ' ()##*& %' "! +),-(%&" .%&*/ #".)(&' ("!"#$ &" '+*(!(%&"' +*# &0* &*#$' "! *1%' '&#)$*&' '&%.%#. 2%##%&3/ #".)(&" +#"(*''4 ."*' "& *(*''%#-3 (-).* &*'&4 "! %-- +%#%$*&*#'/ POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 SGLS008B - MARCH 2003 - REVISED MAY 2004 TLV246x PACKAGE PINOUTS TLV2461 D OR PW PACKAGE (TOP VIEW) NC IN - IN + GND 1OUT 1IN - 1IN+ GND NC 1SHDN NC 1 8 2 7 3 6 4 5 TLV2462 D OR PW PACKAGE (TOP VIEW) NC VDD+ OUT NC 1OUT 1IN - 1IN + GND 1 8 2 7 3 6 4 5 TLV2463 D OR PW PACKAGE TLV2464 D OR PW PACKAGE (TOP VIEW) (TOP VIEW) 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VDD+ 2OUT 2IN - 2IN+ NC 2SHDN NC 1OUT 1IN - 1IN+ VDD+ 2IN+ 2IN - 2OUT 1 14 2 13 3 12 4 11 5 10 6 9 7 8 NC - No internal connection 2 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 VDD+ 2OUT 2IN - 2IN+ 4OUT 4IN - 4IN+ GND 3IN+ 3IN - 3OUT SGLS008B - MARCH 2003 - REVISED MAY 2004 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, VDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V Differential input voltage, VID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.2 V to VDD + 0.2 V Input current, II (any input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 mA Output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 mA Total input current, II (into VDD +) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 mA Total output current, IO (out of GND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 mA Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40C to 125C Maximum junction temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150C Thermal resistance, Junction-to-Ambient, JA: D (8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176C/W D (14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123C/W D (16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115C/W PW (14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values, except differential voltages, are with respect to GND. recommended operating conditions Single supply Supply voltage, VDD Split supply Common-mode input voltage range, VICR MIN MAX 2.7 6 1.35 3 -0.2 VDD+0.2 -40 125 Operating free-air temperature, TA VIH VIL Shutdown on/off voltage level 2 0.7 UNIT V V C V Relative to voltage on the GND terminal of the device. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 3 SGLS008B - MARCH 2003 - REVISED MAY 2004 electrical characteristics at specified free-air temperature, VDD = 3 V (unless otherwise noted) PARAMETER TEST CONDITIONS VIO Input offset voltage VIO Temperature coefficient of input offset voltage IIO Input offset current IIB Input bias current TA 25C VDD = 3 V, VO = 1.5 V, VIC = 1.5 V, RS = 50 Full range VDD = 3 V, VO = 1.5 V, VIC = 1.5 V, RS = 50 Full range MIN 2.8 4.4 High-level output voltage IOL = 2.5 mA Low-level output voltage IOL = 10 mA Sourcing 2.5 0.1 Full range 0.2 0.5 Full range IO Output current Measured 1 V from rail AVD Large-signal differential voltage amplification RL = 10 k ri(d) Differential input resistance ci(c) Common-mode input capacitance f = 10 kHz zo Closed-loop output impedance f = 100 kHz, AV = 10 CMRR Common-mode rejection ratio VICR = 0 V to 3 V, RS = 50 VDD = 2.7 V to 6 V, No load VIC = VDD /2, 20 Supply voltage rejection ratio ((V VDD //V VIO) VDD = 3 V to 5 V, No load VIC = VDD /2, No load 20 40 25C 25C 90 Full range 89 VO = 1.5 V, IDD(SHDN) Supply current in shutdown (TLV2460, TLV2463) SHDN < 0.7 V, Per channel in shutdown Full range is -40C to 125C for the Q suffix. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 mA 105 dB 109 25C 7 pF 25C 33 25C 66 Full range 60 25C 80 Full range 75 25C 85 Full range 80 25C Supply current (per channels) mA 40 25C IDD 4 50 25C Sinking V 0.3 Full range Full range nA V 2.7 25C Short-circuit output current 14 2.9 25C VIC = 1.5 V, nA 2.8 25C VIC = 1.5 V, V V 7 75 25C Full range UNIT V/C 75 25C Full range IOH = - 10 mA kSVR 1500 2 25C IOS 150 Full range IOH = - 2.5 mA VOL MAX 1700 25C VOH TYP 80 dB 85 0.5 Full range 25C Full range dB 95 0.575 0.9 0.3 2.5 mA A A SGLS008B - MARCH 2003 - REVISED MAY 2004 operating characteristics at specified free-air temperature, VDD = 3 V (unless otherwise noted) PARAMETER SR Slew rate at unity gain Vn Equivalent input noise voltage In THD + N t(on) TEST CONDITIONS VO(PP) = 2 V, RL = 10 k CL = 160 pF, TA 25C Full range TYP 1 1.6 25C 16 f = 1 kHz 25C 11 Equivalent input noise current f = 1 kHz 25C 0.13 Total harmonic distortion plus noise VO(PP) = 2 V, RL = 10 k, f = 1 kHz Amplifier turnon time AV = 1, RL = 10 k AV = 1 AV = 10 Amplifier turnoff time AV = 1, RL = 10 k Channel 1 only, Channel 2 on ts Settling time m Phase margin at unity gain Gain margin Full range is -40C to 125C for the Q suffix. f = 10 kHz, CL = 160 pF RL = 10 k, V(STEP)PP = 2 V, AV = -1, CL = 10 pF, RL = 10 k 0.1% V(STEP)PP = 2 V, AV = -1, CL = 56 pF, RL = 10 k 0.1% RL = 10 k, POST OFFICE BOX 655303 0.02% 7.65 s 333 25C 25 C 328 ns 329 25C 5.2 MHz 1.47 1.78 25C 1.77 0.01% * DALLAS, TEXAS 75265 pA /Hz 7.6 25C 0.01% CL = 160 pF nV/Hz 0.08% Channel 2 only, Channel 1 on Gain-bandwidth product UNIT 0.006% 25C 25 C AV = 100 Both channels Channel 1 only, Channel 2 on MAX V/s 0.8 f = 100 Hz Both channels t(off) MIN ss 1.98 25C 44 25C 7 dB 5 SGLS008B - MARCH 2003 - REVISED MAY 2004 electrical characteristics at specified free-air temperature, VDD = 5 V (unless otherwise noted) PARAMETER TEST CONDITIONS VIO Input offset voltage VIO Temperature coefficient of input offset voltage IIO Input offset current IIB Input bias current VDD = 5 V, VO = 2.5 V, VDD = 5 V, VO = 2.5 V, TA 25C VIC = 2.5, RS = 50 Full range VIC = 2.5 V, RS = 50 Full range MIN 2 25C 0.3 25C 1.3 Full range Low-level output voltage IOL = 10 mA Sourcing 4.7 0.1 0.2 Full range Full range 0.3 145 60 60 80 Output current Measured at 1 V from rail 25C VIC = 2.5 V, VO = 1 V to 4 V 25C 92 AVD Large-signal differential voltage amplification Full range 90 ri(d) Differential input resistance ci(c) Common-mode input capacitance f = 10 kHz zo Closed-loop output impedance f = 100 kHz, 71 Common-mode rejection ratio VICR = 0 V to 5 V, RS = 50 25C CMRR Full range 60 80 Full range 75 kSVR VDD = 2.7 V to 6 V, No load, VIC = VDD /2 25C Supply voltage rejection ratio ((V VDD //V VIO) AV = 10 25C 7 pF 25C 29 85 Full range 80 Full range 25C VO = 2.5 V, No load, IDD(SHDN) Supply current in shutdown (TLV2460, TLV2463) SHDN < 0.7 V, Per channels in shutdown Full range is -40C to 125C for the Q suffix. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 dB 109 25C Supply current (per channel) mA 109 25C VDD = 3 V to 5 V, No load, VIC = VDD /2 IDD mA 100 IO RL = 10 k, V 0.2 25C Sinking nA V 4.8 Full range Full range 14 4.8 25C Short-circuit output current nA 4.9 25C VIC = 2.5 V, V V 7 60 25C IOL = 2.5 mA UNIT V/C V/C 60 25C VIC = 2.5 V, 6 1500 25C Full range High-level output voltage IOH = - 10 mA IOS 150 1700 25C VOL MAX Full range IOH = - 2.5 mA VOH TYP 25C Full range 85 dB 85 dB 95 dB 0.55 0.65 1 1 3 mA A A SGLS008B - MARCH 2003 - REVISED MAY 2004 operating characteristics at specified free-air temperature, VDD = 5 V (unless otherwise noted) PARAMETER SR Slew rate at unity gain Vn Equivalent input noise voltage In THD + N t(on) t(off) TEST CONDITIONS VO(PP) = 2 V, RL = 10 k CL = 160 pF, TA 25C Full range 1 1.6 14 f = 1 kHz 25C 11 Equivalent input noise current f = 100 Hz 25C 0.13 Total harmonic distortion plus noise VO(PP) = 4 V, RL = 10 k, f = 10 kHz Amplifier turnon time Amplifier turnoff time AV = 1 AV = 10 AV = 1, RL = 10 k AV = 1, RL = 10 k Settling time Gain margin pA /Hz 0.04% 7.6 25C 25 C 7.65 7.25 Both channels 333 25 C 25C 328 s ns 329 f = 10 kHz, CL = 160 pF RL = 10 k, V(STEP)PP = 2 V, AV = -1, CL = 10 pF, RL = 10 k 0.1% V(STEP)PP = 2 V, AV = -1, CL = 56 pF, RL = 10 k 0.1% 3.13 0.01% 3.33 RL = 10 k, CL = 160 pF POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 25C 6.4 MHz 1.53 0.01% 1.83 ss 25C Phase margin at unity gain nV/Hz 0.01% Channel 2 only, Channel 1 on Channel 1 only, Channel 2 on UNIT 0.004% 25C 25 C AV = 100 Both channels Channel 1 only, Channel 2 on MAX V/s 0.8 25C Gain-bandwidth product m TYP f = 100 Hz Channel 2 only, Channel 1 on ts MIN 25C 45 25C 7 dB Full range is -40C to 125C for the Q suffix. 7 SGLS008B - MARCH 2003 - REVISED MAY 2004 TYPICAL CHARACTERISTICS Table of Graphs FIGURE VIO IIB Input offset voltage vs Common-mode input voltage 1, 2 Input bias current vs Free-air temperature 3, 4 IIO VOH Input offset current vs Free-air temperature 3, 4 High-level output voltage vs High-level output current 5, 6 VOL VO(PP) Low-level output voltage vs Low-level output current 7, 8 Peak-to-peak output voltage vs Frequency 9, 10 Open-loop gain vs Frequency 11, 12 Phase vs Frequency 11, 12 Differential voltage amplification vs Load resistance 13 Capacitive load vs Load resistance 14 Zo CMRR Output impedance vs Frequency 15, 16 Common-mode rejection ratio vs Frequency 17 kSVR Supply-voltage rejection ratio vs Frequency 18, 19 AVD IDD Supply current vs Supply voltage 20 vs Free-air temperature 21 Amplifier turnon characteristics 22 Amplifier turnoff characteristics 23 Supply current turnon 24 Supply current turnoff SR 25 Shutdown supply current vs Free-air temperature Slew rate vs Supply voltage 27 vs Frequency 28, 29 vs Common-mode input voltage 30, 31 Vn Equivalent input noise voltage THD Total harmonic distortion vs Frequency 32, 33 THD+N Total harmonic distortion plus noise vs Peak-to-peak signal amplitude 34, 35 vs Frequency 11, 12 m Phase margin vs Load capacitance 36 vs Free-air temperature 37 vs Supply voltage 38 vs Free-air temperature 39 Gain bandwidth product 8 26 Large signal follower 40, 41 Small signal follower 42, 43 Inverting large signal 44, 45 Inverting small signal 46, 47 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SGLS008B - MARCH 2003 - REVISED MAY 2004 TYPICAL CHARACTERISTICS INPUT OFFSET VOLTAGE vs COMMON-MODE INPUT VOLTAGE INPUT OFFSET VOLTAGE vs COMMON-MODE INPUT VOLTAGE 1 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 0 VDD = 5 V TA = 25C 0.8 VIO - Input Offset Voltage - mV VIO - Input Offset Voltage - mV 0.8 1 VDD = 3 V TA = 25C 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 0.5 1 1.5 2 2.5 -1 3 0 VICR - Common-Mode Input Voltage - V 1 Figure 1 VDD = 3 V VI = 1.5 V 4.5 IIB 4 3.5 3 2.5 2 1.5 1 0.5 IIO -15 5 25 4 5 45 65 85 105 125 INPUT BIAS AND INPUT OFFSET CURRENT vs FREE-AIR TEMPERATURE I IB and I IO - Input Bias and Input Offset Current - nA I IB and I IO - Input Bias and Input Offset Current - nA 5 -0.5 -55 -35 3 Figure 2 INPUT BIAS AND INPUT OFFSET CURRENT vs FREE-AIR TEMPERATURE 0 2 VICR - Common-Mode Input Voltage - V 6 VDD = 5 V VI = 2.5 V 5 IIB 4 3 2 1 IIO 0 -1 -55 -35 TA - Free-Air Temperature - C -15 5 25 45 65 85 105 125 TA - Free-Air Temperature - C Figure 3 Figure 4 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 9 SGLS008B - MARCH 2003 - REVISED MAY 2004 TYPICAL CHARACTERISTICS HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT 3 5 VDD = 5 VDC 4.5 2.5 VOH - High-Level Output Voltage - V VOH - High-Level Output Voltage - V VDD = 3 VDC TA = -55C 2 1.5 TA = 125C TA = 85C TA = 25C 1 TA = -40C 0.5 TA = -55C 4 3.5 3 2.5 2 TA = 125C TA = 85C TA = 25C 1.5 TA = -40C 1 0.5 0 0 10 20 30 40 50 60 70 0 80 0 IOH - High-Level Output Current - mA 20 40 60 Figure 5 LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT 3 4.5 VDD = 3 VDC VDD = 5 VDC 4 2.5 VOL - Low-Level Output Voltage - V VOL - Low-Level Output Voltage - V 100 120 140 160 180 200 Figure 6 LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT TA = -40C 2 TA = 25C 1.5 TA = 85C TA = 125C 1 0.5 0 0 10 20 30 40 50 60 3.5 TA = -40C 3 TA = 25C 2.5 TA = 85C TA = 125C 2 1.5 1 TA = -55C 0.5 TA = -55C 70 IOL - Low-Level Output Current - mA 0 0 20 40 60 80 Figure 8 POST OFFICE BOX 655303 100 120 140 IOL - Low-Level Output Current - mA Figure 7 10 80 IOH - High-Level Output Current - mA * DALLAS, TEXAS 75265 160 SGLS008B - MARCH 2003 - REVISED MAY 2004 TYPICAL CHARACTERISTICS PEAK-TO-PEAK OUTPUT VOLTAGE vs FREQUENCY PEAK-TO-PEAK OUTPUT VOLTAGE vs FREQUENCY 5.5 2.5 VO(PP) - Peak-to-Peak Output Voltage - V VDD = 3 V AV = -10 THD = 1% RL = 10 k 2 1.5 1 0.5 100k 1M VDD = 5 V AV = -10 THD = 1% RL = 10 k 5 4.5 4 3.5 3 2.5 2 1.5 1 0.5 0 10k 10M 100k f - Frequency - Hz 1M 10M f - Frequency - Hz Figure 9 Figure 10 OPEN-LOOP GAIN AND PHASE vs FREQUENCY 100 VDD = 1.5 V RL = 10 k CL = 0 TA = 25C 90 80 70 60 40 20 0 -20 -40 AVD 50 -60 40 -80 -100 30 Phase 20 -120 10 -140 0 -160 -10 -180 -20 10 Phase 0 10k Open-Loop Gain - dB VO(PP) - Peak-to-Peak Output Voltage - V 3 100 1k 10k 100k 1M -200 10M f - Frequency - Hz Figure 11 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 11 SGLS008B - MARCH 2003 - REVISED MAY 2004 TYPICAL CHARACTERISTICS OPEN-LOOP GAIN AND PHASE vs FREQUENCY 100 VDD = 2.5 V RL = 10 k CL = 0 TA = 25C 90 80 60 20 0 -20 -40 AVD 50 -60 40 -80 Phase Open-Loop Gain - dB 70 40 -100 30 Phase 20 -120 10 -140 0 -160 -10 -180 -20 10 100 1k 100k 10k 1M -200 10M f - Frequency - Hz Figure 12 DIFFERENTIAL VOLTAGE AMPLIFICATION vs LOAD RESISTANCE CAPACITIVE LOAD vs LOAD RESISTANCE 10000 TA = 25C 160 140 CL - Capacitive Load - pF A VD - Differential Voltage Amplification - V/mV 180 120 VDD = 2.5 V 100 VDD = 1.5 V 80 60 40 Phase Margin < 30 1000 Phase Margin > 30 VDD = 5 V Phase Margin = 30 TA = 25C 20 0 100 1k 10k 100k 1M 100 10 RL - Load Resistance - Figure 14 Figure 13 12 100 POST OFFICE BOX 655303 1k RL - Load Resistance - * DALLAS, TEXAS 75265 10k SGLS008B - MARCH 2003 - REVISED MAY 2004 TYPICAL CHARACTERISTICS OUTPUT IMPEDANCE vs FREQUENCY 1000 OUTPUT IMPEDANCE vs FREQUENCY 1000 VDD = 1.5 V TA = 25C Zo - Output Impedance - 100 10 AV = 100 1 AV = 10 0.1 AV = 1 10 AV = 100 1 AV = 10 0.1 AV = 1 0.01 100 1k 10k 100k 1M 0.01 100 10M 1k f - Frequency - Hz 10k 100k 1M 10M f - Frequency - Hz Figure 15 Figure 16 COMMON-MODE REJECTION RATIO vs FREQUENCY 90 CMRR - Common-Mode Rejection Ratio - dB Zo - Output Impedance - 100 VDD = 2.5 V TA = 25C 85 80 VDD = 5 V VIC = 2.5 V 75 VDD = 3 V VIC = 1.5 V 70 65 60 10 100 1k 10k 100k 1M 10M f - Frequency - Hz Figure 17 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 13 SGLS008B - MARCH 2003 - REVISED MAY 2004 TYPICAL CHARACTERISTICS SUPPLY-VOLTAGE REJECTION RATIO vs FREQUENCY SUPPLY-VOLTAGE REJECTION RATIO vs FREQUENCY 90 +kSVR VDD = 1.5 V TA = 25C 100 k SVR - Supply Voltage Rejection Ratio - dB k SVR - Supply Voltage Rejection Ratio - dB 110 90 -kSVR 80 70 60 +kSVR 50 -kSVR 40 10 100 1k 10k 100k 1M +kSVR 80 -kSVR 70 60 +kSVR 50 -kSVR 40 10 10M VDD = 2.5 V TA = 25C 100 1k f - Frequency - Hz 10k 100k 1M 10M f - Frequency - Hz Figure 18 Figure 19 SUPPLY CURRENT vs SUPPLY VOLTAGE SUPPLY CURRENT vs FREE-AIR TEMPERATURE 0.8 0.80 IDD = 125C I DD - Supply Current - mA I DD - Supply Current - mA 0.75 IDD = 85C 0.7 0.6 0.5 0.40 IDD = 25C 0.30 IDD = -55C VDD = 5 V VI = 2.5 V 0.65 0.60 0.55 VDD = 3 V VI = 1.5 V 0.50 0.45 0.40 IDD = -40C 0.20 0.70 0.35 0.10 2.5 3 3.5 4 4.5 5 5.5 6 0.30 -55 -35 VDD - Supply Voltage - V Figure 20 14 -15 5 25 Figure 21 POST OFFICE BOX 655303 45 65 85 TA - Free-Air Temperature - C * DALLAS, TEXAS 75265 105 125 SGLS008B - MARCH 2003 - REVISED MAY 2004 TYPICAL CHARACTERISTICS AMPLIFIER WITH A SHUTDOWN PULSE TURNON CHARACTERISTICS AMPLIFIER WITH A SHUTDOWN PULSE TURNOFF CHARACTERISTICS 5 5 4 Shutdown Pin 2 1 0 Amplifier Output 3 1 0 -5 VDD = 5 V RL = 10 k AV = 1 TA = 25C -3 -1 2 1 0 Amplifier Output 3 2 1 1 3 5 9 7 0 -5 11 -3 -1 t - Time - s 1 3 5 7 t - Time - s Figure 23 Figure 22 SUPPLY CURRENT WITH A SHUTDOWN PULSE TURNON CHARACTERISTICS 1 5.5 Shutdown Pin 0.8 4.5 0.6 3.5 Supply Current 0.4 2.5 0.2 1.5 VDD = 5 V VI = 2.5 V AV = 1 TA = 25C 0 -0.2 -0.4 -0.2 0 0.2 0.4 VSD - Shutdown Voltage - V 2 VDD = 5 V RL = 10 k AV = 1 TA = 25C Shutdown Pin 3 VSD - Shutdown Voltage - V 3 I DD - Supply Current - mA VSD - Shutdown Voltage - V 4 0.5 -0.5 0.6 t - Time - s Figure 24 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 15 SGLS008B - MARCH 2003 - REVISED MAY 2004 TYPICAL CHARACTERISTICS TURNOFF SUPPLY CURRENT WITH A SHUTDOWN PULSE 1 5.5 4.5 0.6 0.4 3.5 Supply Current 2.5 0.2 1.5 0 0.5 -0.2 -0.4 -0.2 0 0.2 VSD - Shutdown Voltage - V Shutdown Pin 0.8 I DD - Supply Current - mA VDD = 5 V VI = 2.5 V AV = 1 TA = 25C -0.5 0.6 0.4 t - Time - s Figure 25 SLEW RATE vs SUPPLY VOLTAGE 3 1.8 2.5 1.75 1.7 VDD = 5 V VI = 2.5 V 2 SR - Slew Rate - V/ s I DD - Shutdown Supply Current - A SHUTDOWN SUPPLY CURRENT vs FREE-AIR TEMPERATURE 1.5 1 VDD = 3 V VI = 1.5 V 0.5 0 SR+ 1.65 1.6 1.55 1.5 1.45 1.4 -0.5 -1 -55 -35 1.35 -15 5 25 45 65 85 105 125 SR- 1.3 2.5 VO(PP) = 2 V CL = 160 pF AV = 1 RL = 10 k TA = 25C 3 TA - Free-Air Temperature - C 4 4.5 Figure 27 Figure 26 16 3.5 POST OFFICE BOX 655303 5 VDD - Supply Voltage - V * DALLAS, TEXAS 75265 5.5 6 SGLS008B - MARCH 2003 - REVISED MAY 2004 TYPICAL CHARACTERISTICS EQUIVALENT INPUT NOISE VOLTAGE vs FREQUENCY EQUIVALENT INPUT NOISE VOLTAGE vs FREQUENCY 18 VDD = 3 V AV = 10 VI = 1.5 V TA = 25C 17 Vn - Equivalent Input Noise Voltage - nV/ Hz Vn - Equivalent Input Noise Voltage - nV/ Hz 18 16 15 14 13 12 11 10 100 1k 10k VDD = 5 V AV = 10 VI = 2.5 V TA = 25C 17 16 15 14 13 12 11 10 100 100k 1k f - Frequency - Hz Figure 28 100k Figure 29 EQUIVALENT INPUT NOISE VOLTAGE vs COMMON-MODE INPUT VOLTAGE EQUIVALENT INPUT NOISE VOLTAGE vs COMMON-MODE INPUT VOLTAGE 20 20 VDD = 3 V AV = 10 f = 1 kHz TA = 25C 15 Vn - Equivalent Input Noise Voltage - nV/ Hz Vn - Equivalent Input Noise Voltage - nV/ Hz 10k f - Frequency - Hz 14 13 12 11 10 0 0.5 1 1.5 2 2.5 3 VICR - Common-Mode Input Voltage - V VDD = 5 V AV = 10 f = 1 kHz TA = 25C 15 14 13 12 11 10 0 1 2 3 4 5 VICR - Common-Mode Input Voltage - V Figure 30 Figure 31 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 17 SGLS008B - MARCH 2003 - REVISED MAY 2004 TYPICAL CHARACTERISTICS TOTAL HARMONIC DISTORTION vs FREQUENCY 1 VDD = 1.5 V VO(PP) = 2 V RL = 10 k THD - Total Harmonic Distortion - % THD - Total Harmonic Distortion - % 0.5 TOTAL HARMONIC DISTORTION vs FREQUENCY AV = 100 0.1 AV = 10 0.010 0.001 AV = 1 10 100 1k 10k 0.1 AV = 100 AV = 10 0.010 AV = 1 0.001 100k VDD = 2.5 V VO(PP) = 4 V RL = 10 k 10 100 1k f - Frequency - Hz Figure 32 THD+N - Total Harmonic Distortion + Noise - % THD+N - Total Harmonic Distortion + Noise - % TOTAL HARMONIC DISTORTION PLUS NOISE vs PEAK-TO-PEAK SIGNAL AMPLITUDE 1 RL = 250 RL = 2 k 0.1 RL = 10 k 0.010 RL = 100 k 0.001 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 1 RL = 250 RL = 2 k 0.1 RL = 10 k 0.010 RL = 100 k VDD = 5 V AV = 1 TA = 25C 0.001 4 4.1 4.2 Peak-to-Peak Signal Amplitude - V 4.3 4.4 4.5 4.6 Figure 35 POST OFFICE BOX 655303 4.7 4.8 4.9 Peak-to-Peak Signal Amplitude - V Figure 34 18 100k Figure 33 TOTAL HARMONIC DISTORTION PLUS NOISE vs PEAK-TO-PEAK SIGNAL AMPLITUDE VDD = 3 V AV = 1 TA = 25C 10k f - Frequency - Hz * DALLAS, TEXAS 75265 5 SGLS008B - MARCH 2003 - REVISED MAY 2004 TYPICAL CHARACTERISTICS PHASE MARGIN vs LOAD CAPACITANCE PHASE MARGIN vs FREE-AIR TEMPERATURE 90 80 RL = 10 k CL = 160 pF 55 70 m - Phase Margin - degrees m - Phase Margin - degrees 60 VDD = 2.5 V TA = 25C RL = 10 k Rnull = 50 60 50 40 Rnull = 20 30 20 Rnull = 0 50 VDD = 2.5 V 45 VDD = 1.5 V 40 35 10 0 100 10 1k 30 -55 -35 100k 10k CL - Load Capacitance - pF -15 Figure 36 45 65 85 105 125 GAIN BANDWIDTH PRODUCT vs FREE-AIR TEMPERATURE 5 5 CL = 160 pF RL = 10 k f = 10 kHz TA = 25C 4.75 Gain Bandwidth Product - MHz Gain Bandwidth Product - MHz 25 Figure 37 GAIN BANDWIDTH PRODUCT vs SUPPLY VOLTAGE 4.75 5 TA - Free-Air Temperature - C 4.5 4.25 4 3.75 4.5 RL = 10 k CL = 160 pF VDD = 2.5 V 4.25 4 3.75 3.5 VDD = 1.5 V 3.25 3.5 2.5 3 3.5 4 4.5 5 5.5 6 3 -55 -35 VDD - Supply Voltage - V -15 5 25 45 65 85 105 125 TA - Free-Air Temperature - C Figure 38 Figure 39 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 19 SGLS008B - MARCH 2003 - REVISED MAY 2004 TYPICAL CHARACTERISTICS LARGE SIGNAL FOLLOWER LARGE SIGNAL FOLLOWER 2.2 3.7 2 3.3 VO - Voltage - V Input VO - Voltage - V Input 1.8 Output 1.6 1.4 VDD = 3 V VI(PP) = 1 V VI = 1.5 V RL = 10 k CL = 160 pF AV = 1 TA = 25C 1.2 1 0.8 -2 0 2 4 6 Input 2.9 Output 2.5 VDD = 5 V VI(PP) = 2 V VI = 2.5 V RL = 10 k CL = 160 pF AV = 1 TA = 25C 2.1 Output 1.7 8 10 12 14 16 1.3 -2 18 0 2 4 6 t - Time - s 10 12 14 16 18 SMALL SIGNAL FOLLOWER 1.6 2.6 1.55 2.55 VO - Voltage - V VO - Voltage - V 8 Figure 41 SMALL SIGNAL FOLLOWER Input 1.5 Output 1.45 Input 2.5 Output 2.45 VDD = 3 V VI(PP) = 100 mV CL = 160 pF AV = 1 VI = 1.5 V TA = 25C RL = 10 k 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2.4 -0.2 VDD = 5 V VI(PP) = 100 mV VI = 2.5 V RL = 10 k 0 t - Time - s 0.2 0.4 0.6 CL = 160 pF AV = 1 TA = 25C 0.8 1 t - Time - s Figure 42 20 Output t - Time - s Figure 40 1.4 -0.2 Input Figure 43 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1.2 1.4 1.6 1.8 SGLS008B - MARCH 2003 - REVISED MAY 2004 TYPICAL CHARACTERISTICS INVERTING LARGE SIGNAL INVERTING LARGE SIGNAL 4 2.3 Input 2.1 Input 3.5 VDD = 3 V VI(PP) = 1 V VI = 1.5 V RL = 10 k CL = 160 pF AV = -1 TA = 25C 1.7 1.5 1.3 VO - Voltage - V VO - Voltage - V 1.9 1.1 VDD = 5 V VI(PP) = 2 V VI = 2.5 V RL = 10 k CL = 160 pF AV = -1 TA = 25C 3 2.5 2 Output 0.9 Output 1.5 0.7 0.5 -0.2 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1 -0.2 1.6 1.8 0 0.2 0.4 t - Time - s 0.6 Figure 44 INVERTING SMALL SIGNAL 1.2 1.4 1.6 1.8 INVERTING SMALL SIGNAL 2.6 Input Input 1.55 2.55 VDD = 3 V VI(PP) = 100 mV VI = 1.5 V RL = 10 k CL = 160 pF AV = -1 TA = 25C 1.5 VO - Voltage - V VO - Voltage - V 1 Figure 45 1.6 1.45 VDD = 5 V VI(PP) = 100 mV VI = 2.5 V RL = 10 k CL = 160 pF AV = -1 TA = 25C 2.5 2.45 Output 1.4 -0.2 0.8 t - Time - s 0 0.2 0.4 0.6 0.8 Output 1 1.2 1.4 1.6 1.8 2.4 -0.2 0 t - Time - s 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 t - Time - s Figure 46 Figure 47 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 21 SGLS008B - MARCH 2003 - REVISED MAY 2004 PARAMETER MEASUREMENT INFORMATION Rnull _ + RL CL Figure 48 APPLICATION INFORMATION driving a capacitive load When the amplifier is configured in this manner, capacitive loading directly on the output will decrease the device's phase margin leading to high frequency ringing or oscillations. Therefore, for capacitive loads of greater than 10 pF, it is recommended that a resistor be placed in series (RNULL) with the output of the amplifier, as shown in Figure 49. A minimum value of 20 should work well for most applications. RF RG RNULL _ Input Output + CLOAD Figure 49. Driving a Capacitive Load offset voltage The output offset voltage, (VOO) is the sum of the input offset voltage (VIO) and both input bias currents (IIB) times the corresponding gains. The following schematic and formula can be used to calculate the output offset voltage: RF IIB- RG + - VI IIB+ V OO +V IO 1) R R F G VO + RS "I IB) R S 1) R R F G "I IB- Figure 50. Output Offset Voltage Model 22 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 R F SGLS008B - MARCH 2003 - REVISED MAY 2004 APPLICATION INFORMATION general configurations When receiving low-level signals, limiting the bandwidth of the incoming signals into the system is often required. The simplest way to accomplish this is to place an RC filter at the noninverting terminal of the amplifier (see Figure 51). RG RF - VO + VI R1 C1 f V O + V I 1) R R F G -3dB + 1 2pR1C1 1 1 ) sR1C1 Figure 51. Single-Pole Low-Pass Filter If even more attenuation is needed, a multiple pole filter is required. The Sallen-Key filter can be used for this task. For best results, the amplifier should have a bandwidth that is 8 to 10 times the filter frequency bandwidth. Failure to do this can result in phase shift of the amplifier. C1 + _ VI R1 R1 = R2 = R C1 = C2 = C Q = Peaking Factor (Butterworth Q = 0.707) R2 f C2 RG RF -3dB RG = + ( 1 2pRC RF 1 2- Q ) Figure 52. 2-Pole Low-Pass Sallen-Key Filter POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 23 SGLS008B - MARCH 2003 - REVISED MAY 2004 APPLICATION INFORMATION shutdown function Three members of the TLV246x family (TLV2460/3/5) have a shutdown terminal for conserving battery life in portable applications. When the shutdown terminal is tied low, the supply current is reduced to 0.3 A/channel, the amplifier is disabled, and the outputs are placed in a high impedance mode. To enable the amplifier, the shutdown terminal can either be left floating or pulled high. When the shutdown terminal is left floating, care should be taken to ensure that parasitic leakage current at the shutdown terminal does not inadvertently place the operational amplifier into shutdown. The shutdown terminal threshold is always referenced to VDD/2. Therefore, when operating the device with split supply voltages (e.g. 2.5 V), the shutdown terminal needs to be pulled to VDD- (not GND) to disable the operational amplifier. The amplifier's output with a shutdown pulse is shown in Figures 22, 23, 24, and 25. The amplifier is powered with a single 5-V supply and configured as a noninverting configuration with a gain of 5. The amplifier turnon and turnoff times are measured from the 50% point of the shutdown pulse to the 50% point of the output waveform. The times for the single, dual, and quad are listed in the data tables. circuit layout considerations To achieve the levels of high performance of the TLV246x, follow proper printed-circuit board design techniques. A general set of guidelines is given in the following. D Ground planes - It is highly recommended that a ground plane be used on the board to provide all components with a low inductive ground connection. However, in the areas of the amplifier inputs and output, the ground plane can be removed to minimize the stray capacitance. D Proper power supply decoupling - Use a 6.8-F tantalum capacitor in parallel with a 0.1-F ceramic capacitor on each supply terminal. It may be possible to share the tantalum among several amplifiers depending on the application, but a 0.1-F ceramic capacitor should always be used on the supply terminal of every amplifier. In addition, the 0.1-F capacitor should be placed as close as possible to the supply terminal. As this distance increases, the inductance in the connecting trace makes the capacitor less effective. The designer should strive for distances of less than 0.1 inches between the device power terminals and the ceramic capacitors. D Sockets - Sockets can be used but are not recommended. The additional lead inductance in the socket pins will often lead to stability problems. Surface-mount packages soldered directly to the printed-circuit board is the best implementation. D Short trace runs/compact part placements - Optimum high performance is achieved when stray series inductance has been minimized. To realize this, the circuit layout should be made as compact as possible, thereby minimizing the length of all trace runs. Particular attention should be paid to the inverting input of the amplifier. Its length should be kept as short as possible. This will help to minimize stray capacitance at the input of the amplifier. D Surface-mount passive components - Using surface-mount passive components is recommended for high performance amplifier circuits for several reasons. First, because of the extremely low lead inductance of surface-mount components, the problem with stray series inductance is greatly reduced. Second, the small size of surface-mount components naturally leads to a more compact layout thereby minimizing both stray inductance and capacitance. If leaded components are used, it is recommended that the lead lengths be kept as short as possible. 24 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SGLS008B - MARCH 2003 - REVISED MAY 2004 APPLICATION INFORMATION general power dissipation considerations For a given JA, the maximum power dissipation is shown in Figure 53 and is calculated by the following formula: P D + Where: T -T MAX A q JA PD = Maximum power dissipation of THS246x IC (watts) TMAX = Absolute maximum junction temperature (150C) TA = Free-ambient air temperature (C) JA = JC + CA JC = Thermal coefficient from junction to case CA = Thermal coefficient from case to ambient air (C/W) MAXIMUM POWER DISSIPATION vs FREE-AIR TEMPERATURE 2 Maximum Power Dissipation - W 1.75 PDIP Package Low-K Test PCB JA = 104C/W 1.5 1.25 TJ = 150C MSOP Package Low-K Test PCB JA = 260C/W SOIC Package Low-K Test PCB JA = 176C/W 1 0.75 0.5 0.25 SOT-23 Package Low-K Test PCB JA = 324C/W 0 -55 -40 -25 -10 5 20 35 50 65 80 95 110 125 TA - Free-Air Temperature - C NOTE A: Results are with no air flow and using JEDEC Standard Low-K test PCB. Figure 53. Maximum Power Dissipation vs Free-Air Temperature POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 25 SGLS008B - MARCH 2003 - REVISED MAY 2004 APPLICATION INFORMATION macromodel information Macromodel information provided was derived using Microsim Parts Release 8, the model generation software used with Microsim PSpice . The Boyle macromodel (see Note 2) and subcircuit in Figure 54 are generated using the TLV246x typical electrical and operating characteristics at TA = 25C. Using this information, output simulations of the following key parameters can be generated to a tolerance of 20% (in most cases): D D D D D D D D D D D D Maximum positive output voltage swing Maximum negative output voltage swing Slew rate Quiescent power dissipation Input bias current Open-loop voltage amplification Unity-gain frequency Common-mode rejection ratio Phase margin DC output resistance AC output resistance Short-circuit output current limit NOTE 2: G. R. Boyle, B. M. Cohn, D. O. Pederson, and J. E. Solomon, "Macromodeling of Intergrated Circuit Operational Amplifiers", IEEE Journal of Solid-State Circuits, SC-9, 353 (1974). 99 EGND + R2 3 VDD + - + ISS RSS CSS VD - 53 RP 10 2 IN - J1 FB 6 VLIM + VB 8 GA GCM - DC J2 - RO1 OUT 1 11 12 RD1 5 DLN DE 92 54 C1 DP + RD2 VE + DLP 91 + VLP - - - + 90 HLIM - 4 .SUBCKT TLV246X 1 2 3 4 5 C1 11 12 2.46034E-12 C2 6 7 10.0000E-12 CSS 10 99 443.21E-15 DC 5 53 DY DE 54 5 DY DLP 90 91 DX DLN 92 90 DX DP 4 3 DX EGND 99 0 POLY (2) (3,0) (4,0) 0 .5 .5 FB 7 99 POLY (5) VB VC VE VLP + VLN 0 21.600E6 -1E3 1E3 22E6 -22E6 GA 6 0 11 12 345.26E-6 GCM 0 6 10 99 15.4226E-9 ISS 10 4 DC 18.850E-6 HLIM 90 0 VLIM 1K J1 11 2 10 JX1 J2 12 1 10 JX2 R2 6 9 100.00E3 PSpice and Parts are trademarks of MicroSim Corporation. POST OFFICE BOX 655303 VLN RD1 3 11 2.8964E3 RD2 3 12 2.8964E3 R01 8 5 5.6000 R02 7 99 6.2000 RP 3 4 8.9127 RSS 10 99 10.610E6 VB 9 0 DC 0 VC 3 53 DC .7836 VE 54 4 DC .7436 VLIM 7 8 DC 0 VLP 91 0 DC 117 VLN 0 92 DC 117 .MODEL DX D (IS=800.00E-18) .MODEL DY D (IS=800.00E-18 Rs = 1m Cjo=10p) .MODEL JX1 NJF (IS=1.0000E-12 BETA=6.3239E-3 + VTO= -1) .MODEL JX2 NJF (IS=1.0000E-12 BETA=6.3239E-3 + VTO= -1) .ENDS Figure 54. Boyle Macromodels and Subcircuit 26 7 + 9 IN + GND RO2 C2 * DALLAS, TEXAS 75265 SGLS008B - MARCH 2003 - REVISED MAY 2004 macromodel information (continued) .subckt TLV_246Y 1 2 3 4 5 6 c1 11 12 2.4603E-12 c2 72 7 10.000E-12 css 10 99 443.21E-15 dc 70 53 dy de 54 70 dy dlp 90 91 dx dln 92 90 dx dp 4 3 dx egnd 99 0 poly(2) (3,0) (4,0) 0 .5 .5 fb 7 99 poly(5) vb vc ve vlp vln 0 21.600E6 -1E3 1E3 22E6 -22E6 ga 72 0 11 12 345.26E-6 gcm 0 72 10 99 15.422E-9 iss 74 4 dc 18.850E-6 hlim 90 0 vlim 1K j1 11 2 10 jx1 j2 12 1 10 jx2 r2 72 9 100.00E3 rd1 3 11 2.8964E3 rd2 3 12 2.8964E3 ro1 8 70 5.6000 ro2 7 99 6.2000 rp 3 71 8.9127 rss 10 99 10.610E6 rs1 6 4 1G rs2 6 4 1G rs3 6 4 1G rs4 6 4 1G s1 71 4 6 4 s1x s2 70 5 6 4 s1x s3 10 74 6 4 s1x s4 74 4 6 4 s2x vb 9 0 dc 0 vc 3 53 dc .7836 ve 54 4 dc .7436 vlim 7 8 dc 0 vlp 91 0 dc 117 vln 0 92 dc 117 .model dx D(Is=800.00E-18) .model dy D(Is=800.00E-18 Rs=1m Cjo=10p) .model jx1 NJF(Is=1.0000E-12 Beta=6.3239E-3 Vto=-1) .model jx2 NJF(Is=1.0000E-12 Beta=6.3239E-3 Vto=-1) .model s1x VSWITCH(Roff=1E8 Ron=1.0 Voff=2.5 Von=0.0) .model s2x VSWITCH(Roff=1E8 Ron=1.0 Voff=0 Von=2.5) .ends Figure 54. Boyle Macromodels and Subcircuit (Continued) POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 27 PACKAGE OPTION ADDENDUM www.ti.com 25-Feb-2005 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty Lead/Ball Finish MSL Peak Temp (3) TLV2460AQDRQ1 ACTIVE SOIC D 8 2500 Pb-Free (RoHS) CU NIPDAU Level-2-250C-1 YEAR/ Level-1-235C-UNLIM TLV2460AQPWRQ1 ACTIVE TSSOP PW 8 TLV2460QDRQ1 ACTIVE SOIC D 8 2000 None CU NIPDAU Level-1-220C-UNLIM 2500 Pb-Free (RoHS) CU NIPDAU Level-2-250C-1 YEAR/ Level-1-235C-UNLIM TLV2460QPWRQ1 ACTIVE TSSOP PW 8 TLV2461AQDRQ1 ACTIVE SOIC D 8 2000 None CU NIPDAU Level-1-220C-UNLIM 2500 Pb-Free (RoHS) CU NIPDAU Level-2-250C-1 YEAR/ Level-1-235C-UNLIM TLV2461AQPWRQ1 ACTIVE TSSOP PW 8 TLV2461QDRQ1 ACTIVE SOIC D 8 2000 None CU NIPDAU Level-1-220C-UNLIM 2500 Pb-Free (RoHS) CU NIPDAU Level-2-250C-1 YEAR/ Level-1-235C-UNLIM TLV2461QPWRQ1 ACTIVE TSSOP PW 8 2000 None CU NIPDAU Level-1-220C-UNLIM TLV2462AQDRQ1 ACTIVE SOIC D 8 2500 Pb-Free (RoHS) CU NIPDAU Level-2-250C-1 YEAR/ Level-1-235C-UNLIM TLV2462AQPWRQ1 ACTIVE TSSOP PW 8 2000 None CU NIPDAU Level-1-220C-UNLIM TLV2462QDRQ1 ACTIVE SOIC D 8 2500 Pb-Free (RoHS) CU NIPDAU Level-2-250C-1 YEAR/ Level-1-235C-UNLIM TLV2462QPWRQ1 ACTIVE TSSOP PW 8 2000 None CU NIPDAU Level-1-220C-UNLIM TLV2463AQDRQ1 ACTIVE SOIC D 14 2500 Pb-Free (RoHS) CU NIPDAU Level-2-250C-1 YEAR/ Level-1-235C-UNLIM TLV2463AQPWRQ1 ACTIVE TSSOP PW 14 2000 None CU NIPDAU Level-1-250C-UNLIM TLV2463QDRQ1 ACTIVE SOIC D 14 2500 Pb-Free (RoHS) CU NIPDAU Level-2-250C-1 YEAR/ Level-1-235C-UNLIM TLV2463QPWRQ1 ACTIVE TSSOP PW 14 2000 None CU NIPDAU Level-1-250C-UNLIM TLV2464AQPWRQ1 ACTIVE TSSOP PW 14 2000 None CU NIPDAU Level-1-250C-UNLIM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. None: Not yet available Lead (Pb-Free). Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens, including bromine (Br) or antimony (Sb) above 0.1% of total product weight. (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 25-Feb-2005 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 MECHANICAL DATA MTSS001C - JANUARY 1995 - REVISED FEBRUARY 1999 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0- 8 A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-153 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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