SGLS008B − MARCH 2003 − REVISED MAY 2004
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DQualification in Accordance With
AEC-Q100†
DQualified for Automotive Applications
DCustomer-Specific Configuration Control
Can Be Supported Along With
Major-Change Approval
DESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
DRail-to-Rail Output Swing
DGain Bandwidth Product . . . 6.4 MHz
D±80 mA Output Drive Capability
DSupply Current . . . 500 µA/channel
DInput Offset Voltage . . . 100 µV
†Contact factory for details. Q100 qualification data available on
request.
DInput Noise Voltage ...11 nV/√Hz
DSlew Rate . . . 1.6 V/µs
DMicropower Shutdown Mode
(TLV2460/3/5) . . . 0.3 µA/Channel
DUniversal Operational Amplifier EVM
description
The TLV246x is a family of low-power rail-to-rail input/output operational amplifiers specifically designed for
portable applications. The input common-mode voltage range extends beyond the supply rails for maximum
dynamic range in low-voltage systems. The amplifier output has rail-to-rail performance with high-output-drive
capability, solving one of the limitations of older rail-to-rail input/output operational amplifiers. This rail-to-rail
dynamic range and high output drive make the TLV246x ideal for buffering analog-to-digital converters.
The operational amplifier has 6.4 MHz of bandwidth and 1.6 V/µs of slew rate with only 500 µA of supply current,
providing good ac performance with low power consumption. Devices are available with an optional shutdown
terminal, which places the amplifier in an ultralow supply current mode (IDD = 0.3 µA/ch). While in shutdown,
the operational-amplifier output is placed in a high-impedance state. DC applications are also well served with
an input noise voltage of 11 nV/√Hz and input offset voltage of 100 µV.
ORDERING INFORMATION‡
TAPACKAGE ORDERABLE
PART NUMBER§TOP-SIDE
MARKING
−40°C to 125°CSOP − D Tape and reel TLV2464AQDRQ1 V2464AQ1
−40°C to 125°CTSSOP − PW Tape and reel TLV2464AQPWRQ1 V2464AQ
‡Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
§All other device/package combinations are Product Preview.
Copyright 2003 − 2004 Texas Instruments Incorporated
!"#$%&" ' ()##*& %' "! +),-(%&" .%&*/
#".)(&' ("!"#$ &" '+*(!(%&"' +*# &0* &*#$' "! *1%' '&#)$*&'
'&%.%#. 2%##%&3/ #".)(&" +#"(*''4 ."*' "& *(*''%#-3 (-).*
&*'&4 "! %-- +%#%$*&*#'/
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1
2
3
4
8
7
6
5
NC
IN−
IN+
GND
SHDN
VDD+
OUT
NC
TLV2460
D OR PW PACKAGE
(TOP VIEW)
SGLS008B − MARCH 2003 − REVISED MAY 2004
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV246x PACKAGE PINOUTS
NC − No internal connection
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1OUT
1IN−
1IN+
GND
NC
1SHDN
NC
VDD+
2OUT
2IN−
2IN+
NC
2SHDN
NC
(TOP VIEW)
TLV2463
D OR PW PACKAGE
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1OUT
1IN−
1IN+
VDD+
2IN+
2IN−
2OUT
4OUT
4IN−
4IN+
GND
3IN+
3IN−
3OUT
(TOP VIEW)
TLV2464
D OR PW PACKAGE
1
2
3
4
8
7
6
5
1OUT
1IN−
1IN+
GND
VDD+
2OUT
2IN−
2IN+
TLV2462
D OR PW PACKAGE
(TOP VIEW)
1
2
3
4
8
7
6
5
NC
IN−
IN+
GND
NC
VDD+
OUT
NC
TLV2461
D OR PW PACKAGE
(TOP VIEW)
SGLS008B − MARCH 2003 − REVISED MAY 2004
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VDD (see Note 1) 6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Differential input voltage, VID − 0.2 V to VDD + 0.2 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input current, II (any input) ± 200 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output current, IO ± 175 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Total input current, II (into VDD+) 175 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Total output current, IO (out of GND) 175 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous total power dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, TA −40°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum junction temperature, TJ 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thermal resistance, Junction-to-Ambient, ΘJA: D (8) 176°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D (14) 123°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D (16) 115°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW (14) 174°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values, except differential voltages, are with respect to GND.
recommended operating conditions
MIN MAX UNIT
Supply voltage, VDD
Single supply 2.7 6
V
Supply voltage, VDD Split supply ±1.35 ±3V
Common-mode input voltage range, VICR −0.2 VDD+0.2 V
Operating free-air temperature, TA−40 125 °C
Shutdown on/off voltage level‡
VIH 2
V
Shutdown on/off voltage level‡
VIL 0.7
V
‡Relative to voltage on the GND terminal of the device.
SGLS008B − MARCH 2003 − REVISED MAY 2004
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics at specified free-air temperature, VDD = 3 V (unless otherwise noted)
PARAMETER TEST CONDITIONS TA†MIN TYP MAX UNIT
VIO
Input offset voltage
25°C 150 1500
V
VIO Input offset voltage V
DD
= 3 V, V
IC
= 1.5 V,
V = 1.5 V, R = 50
Full range 1700 µV
αVIO Temperature coefficient of input offset
voltage
VDD = 3 V, VIC = 1.5 V,
VO = 1.5 V, RS = 50 Ω2µV/°C
IIO
Input offset current
25°C 2.8 7
nA
IIO Input offset current
VDD = 3 V, VIC = 1.5 V,
Full range 75 nA
IIB
Input bias current
VDD = 3 V, VIC = 1.5 V,
VO = 1.5 V, RS = 50 Ω25°C 4.4 14
nA
IIB Input bias current
VO = 1.5 V, RS = 50
Full range 75 nA
IOH = −2.5 mA
25°C 2.9
VOH
High-level output voltage
IOH = −2.5 mA Full range 2.8
V
VOH High-level output voltage
IOH = −10 mA
25°C 2.7 V
IOH = −10 mA Full range 2.5
VIC = 1.5 V,
IOL = 2.5 mA
25°C 0.1
VOL
Low-level output voltage
VIC = 1.5 V, IOL = 2.5 mA Full range 0.2
V
VOL Low-level output voltage
VIC = 1.5 V,
IOL = 10 mA
25°C 0.3 V
VIC = 1.5 V, IOL = 10 mA Full range 0.5
Sourcing
25°C 50
IOS
Short-circuit output current
Sourcing Full range 20
mA
IOS Short-circuit output current
Sinking
25°C 40 mA
Sinking Full range 20
IOOutput current Measured 1 V from rail 25°C±40 mA
AVD
Large-signal differential voltage
RL = 10 kΩ
25°C 90 105
dB
AVD
Large-signal differential voltage
amplification RL = 10 kΩFull range 89 dB
ri(d) Differential input resistance 25°C 109Ω
ci(c) Common-mode input capacitance f = 10 kHz 25°C 7 pF
zoClosed-loop output impedance f = 100 kHz, AV = 10 25°C 33 Ω
CMRR
Common-mode rejection ratio
VICR = 0 V to 3 V,
RS = 50 Ω
25°C 66 80
dB
CMRR Common-mode rejection ratio VICR = 0 V to 3 V, RS = 50 ΩFull range 60 dB
VDD = 2.7 V to 6 V,
VIC = VDD/2,
25°C 80 85
kSVR
Supply voltage rejection ratio
VDD = 2.7 V to 6 V,
No load
VIC = VDD/2,
Full range 75
dB
kSVR
Supply voltage rejection ratio
(∆VDD /∆VIO)
VDD = 3 V to 5 V,
VIC = VDD/2,
25°C 85 95 dB
( VDD / VIO)
VDD = 3 V to 5 V,
No load
VIC = VDD/2,
Full range 80
IDD
Supply current (per channels)
VO = 1.5 V,
No load
25°C 0.5 0.575
mA
IDD Supply current (per channels) VO = 1.5 V, No load Full range 0.9 mA
IDD(SHDN)
Supply current in shutdown (TLV2460,
SHDN < 0.7 V,
25°C 0.3
A
IDD(SHDN
)
Supply current in shutdown (TLV2460,
TLV2463)
SHDN < 0.7 V,
Per channel in shutdown Full range 2.5 µA
†Full range is −40°C to 125°C for the Q suffix.
SGLS008B − MARCH 2003 − REVISED MAY 2004
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
operating characteristics at specified free-air temperature, VDD = 3 V (unless otherwise noted)
PARAMETER TEST CONDITIONS TA†MIN TYP MAX UNIT
VO(PP) = 2 V,
CL = 160 pF,
25°C1 1.6
SR Slew rate at unity gain VO(PP) = 2 V,
RL = 10 kΩCL = 160 pF, Full
range 0.8 V/µs
Vn
Equivalent input noise voltage
f = 100 Hz 25°C 16
nV/√Hz
VnEquivalent input noise voltage f = 1 kHz 25°C11
nV/√Hz
InEquivalent input noise current f = 1 kHz 25°C 0.13 pA/√Hz
Total harmonic distortion plus
VO(PP) = 2 V,
AV = 1 0.006%
THD + N Total harmonic distortion plus
noise
VO(PP) = 2 V,
RL = 10 kΩ, f = 1 kHz
AV = 10 25°C0.02%
THD + N
noise
RL = 10 kΩ, f = 1 kHz
AV = 100
25 C
0.08%
Both channels 7.6
t(on) Amplifier turnon time AV = 1, RL = 10 kΩChannel 1 only,
Channel 2 on 25°C7.65 µs
Both channels 333
t
(off)
Amplifier turnoff time A
V
= 1, R
L
= 10 kΩ
Channel 1 only,
Channel 2 on 25°C328 ns
t(off)
Amplifier turnoff time
AV = 1, RL = 10 kΩ
Channel 2 only,
Channel 1 on
25 C
329
ns
Gain-bandwidth product f = 10 kHz, CL = 160 pF RL = 10 kΩ,25°C 5.2 MHz
V(STEP)PP = 2 V,
AV = −1, CL = 10 pF,
0.1% 1.47
ts
Settling time
(STEP)PP
A
V
= −1, C
L
= 10 pF,
RL = 10 kΩ0.01%
25°C
1.78
s
tsSettling time V(STEP)PP = 2 V,
AV = −1, CL = 56 pF,
0.1% 25°C1.77 µs
(STEP)PP
A
V
= −1, C
L
= 56 pF,
RL = 10 kΩ0.01% 1.98
φmPhase margin at unity gain
RL = 10 kΩ,
CL = 160 pF
25°C 44°
Gain margin
R
L
= 10 k
Ω
,
C
L
= 160 pF
25°C 7 dB
†Full range is −40°C to 125°C for the Q suffix.
SGLS008B − MARCH 2003 − REVISED MAY 2004
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics at specified free-air temperature, VDD = 5 V (unless otherwise noted)
PARAMETER TEST CONDITIONS TA†MIN TYP MAX UNIT
VIO
Input offset voltage
25°C 150 1500
V
VIO Input offset voltage V
DD
= 5 V, V
IC
= 2.5, Full range 1700 µV
VIO
Temperature coefficient of input offset
VDD = 5 V, VIC = 2.5,
VO = 2.5 V, RS = 50 Ω
25°C
2
V/°C
αVIO
Temperature coefficient of input offset
voltage
VO = 2.5 V, RS = 50
25°C 2 µV/°C
IIO
Input offset current
25°C 0.3 7
nA
IIO Input offset current
VDD = 5 V, VIC = 2.5 V,
Full range 60 nA
IIB
Input bias current
VDD = 5 V, VIC = 2.5 V,
VO = 2.5 V, RS = 50 Ω25°C 1.3 14
nA
IIB Input bias current
VO = 2.5 V, RS = 50
Full range 60 nA
IOH = −2.5 mA
25°C 4.9
VOH
High-level output voltage
IOH = −2.5 mA Full range 4.8
V
VOH High-level output voltage
IOH = −10 mA
25°C 4.8 V
IOH = −10 mA Full range 4.7
VIC = 2.5 V,
IOL = 2.5 mA
25°C 0.1
VOL
Low-level output voltage
VIC = 2.5 V, IOL = 2.5 mA Full range 0.2
V
VOL Low-level output voltage
VIC = 2.5 V,
IOL = 10 mA
25°C 0.2 V
VIC = 2.5 V, IOL = 10 mA Full range 0.3
Sourcing
25°C 145
IOS
Short-circuit output current
Sourcing Full range 60
mA
IOS Short-circuit output current
Sinking
25°C 100 mA
Sinking Full range 60
IOOutput current Measured at 1 V from rail 25°C±80 mA
AVD
Large-signal differential voltage
VIC = 2.5 V,
RL = 10 k
Ω
,
25°C 92 109
dB
AVD
Large-signal differential voltage
amplification
VIC = 2.5 V,
VO = 1 V to 4 V
RL = 10 kΩ,
Full range 90 dB
ri(d) Differential input resistance 25°C 109Ω
ci(c) Common-mode input capacitance f = 10 kHz 25°C 7 pF
zoClosed-loop output impedance f = 100 kHz, AV = 10 25°C 29 Ω
CMRR
Common-mode rejection ratio
VICR = 0 V to 5 V,
25°C 71 85
dB
CMRR Common-mode rejection ratio
VICR = 0 V to 5 V,
RS = 50 ΩFull range 60 dB
VDD = 2.7 V to 6 V,
25°C 80 85
dB
kSVR
Supply voltage rejection ratio
VDD = 2.7 V to 6 V,
No load, VIC = VDD/2 Full range 75 dB
kSVR
Supply voltage rejection ratio
(∆VDD /∆VIO)
VDD = 3 V to 5 V,
25°C 85 95
dB
( VDD / VIO)
VDD = 3 V to 5 V,
No load, VIC = VDD/2 Full range 80 dB
IDD
Supply current (per channel)
VO = 2.5 V,
No load,
25°C 0.55 0.65
mA
IDD Supply current (per channel) VO = 2.5 V, No load, Full range 1mA
IDD(SHDN)
Supply current in shutdown
SHDN < 0.7 V, Per channels in
25°C 1
A
IDD(SHDN
)
Supply current in shutdown
(TLV2460, TLV2463)
SHDN < 0.7 V, Per channels in
shutdown Full range 3µA
†Full range is −40°C to 125°C for the Q suffix.
SGLS008B − MARCH 2003 − REVISED MAY 2004
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
operating characteristics at specified free-air temperature, VDD = 5 V (unless otherwise noted)
PARAMETER TEST CONDITIONS TA†MIN TYP MAX UNIT
VO(PP) = 2 V,
CL = 160 pF,
25°C1 1.6
SR Slew rate at unity gain VO(PP) = 2 V,
RL = 10 kΩCL = 160 pF, Full
range 0.8 V/µs
Vn
Equivalent input noise voltage
f = 100 Hz 25°C 14
nV/√Hz
VnEquivalent input noise voltage f = 1 kHz 25°C11
nV/√Hz
InEquivalent input noise current f = 100 Hz 25°C 0.13 pA/√Hz
VO(PP) = 4 V,
AV = 1 0.004%
THD + N Total harmonic distortion plus noise
VO(PP) = 4 V,
R
L
= 10 kΩ,
f = 10 kHz
AV = 10 25°C0.01%
THD + N
Total harmonic distortion plus noise
RL = 10 kΩ,
f = 10 kHz AV = 100
25 C
0.04%
Both channels 7.6
t
(on)
Amplifier turnon time A
V
= 1, R
L
= 10 kΩ
Channel 1 only,
Channel 2 on 25°C7.65 µs
t(on)
Amplifier turnon time
AV = 1, RL = 10 kΩ
Channel 2 only,
Channel 1 on
25 C
7.25
µs
Both channels 333
t
(off)
Amplifier turnoff time A
V
= 1, R
L
= 10 kΩ
Channel 1 only,
Channel 2 on 25°C328 ns
t(off)
Amplifier turnoff time
AV = 1, RL = 10 kΩ
Channel 2 only,
Channel 1 on
25 C
329
ns
Gain-bandwidth product f = 10 kHz,
CL = 160 pF RL = 10 kΩ,25°C 6.4 MHz
V(STEP)PP = 2 V,
AV = −1,
0.1% 1.53
ts
Settling time
AV = −1,
CL = 10 pF,
R
L
= 10 kΩ0.01%
25°C
1.83
s
tsSettling time V(STEP)PP = 2 V,
AV = −1,
0.1% 25°C3.13 µs
AV = −1,
CL = 56 pF,
R
L
= 10 kΩ0.01% 3.33
φmPhase margin at unity gain
RL = 10 kΩ,
CL = 160 pF
25°C 45°
Gain margin
R
L
= 10 k
Ω
,
C
L
= 160 pF
25°C 7 dB
†Full range is −40°C to 125°C for the Q suffix.
SGLS008B − MARCH 2003 − REVISED MAY 2004
8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
VIO Input offset voltage vs Common-mode input voltage 1, 2
IIB Input bias current vs Free-air temperature 3, 4
IIO Input offset current vs Free-air temperature 3, 4
VOH High-level output voltage vs High-level output current 5, 6
VOL Low-level output voltage vs Low-level output current 7, 8
VO(PP) Peak-to-peak output voltage vs Frequency 9, 10
Open-loop gain vs Frequency 11, 12
Phase vs Frequency 11, 12
AVD Differential voltage amplification vs Load resistance 13
Capacitive load vs Load resistance 14
ZoOutput impedance vs Frequency 15, 16
CMRR Common-mode rejection ratio vs Frequency 17
kSVR Supply-voltage rejection ratio vs Frequency 18, 19
IDD
Supply current
vs Supply voltage 20
IDD Supply current vs Free-air temperature 21
Amplifier turnon characteristics 22
Amplifier turnoff characteristics 23
Supply current turnon 24
Supply current turnoff 25
Shutdown supply current vs Free-air temperature 26
SR Slew rate vs Supply voltage 27
Vn
Equivalent input noise voltage
vs Frequency 28, 29
V
n
Equivalent input noise voltage
vs Common-mode input voltage 30, 31
THD Total harmonic distortion vs Frequency 32, 33
THD+N Total harmonic distortion plus noise vs Peak-to-peak signal amplitude 34, 35
vs Frequency 11, 12
φ
m
Phase margin vs Load capacitance 36
φm
Phase margin
vs Free-air temperature 37
Gain bandwidth product
vs Supply voltage 38
Gain bandwidth product vs Free-air temperature 39
Large signal follower 40, 41
Small signal follower 42, 43
Inverting large signal 44, 45
Inverting small signal 46, 47
SGLS008B − MARCH 2003 − REVISED MAY 2004
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 1
−0.2
−0.6
−1
0
−0.4
−0.8
1
VICR − Common-Mode Input Voltage − V
INPUT OFFSET VOLTAGE
vs
COMMON-MODE INPUT VOLTAGE
10.5 1.5 30 2 2.5
VDD = 3 V
TA = 25°C
− Input Offset Voltage − mV
VIO
0.8
0.4
0.6
0.2
Figure 2
−0.2
−0.6
−1
0
−0.4
−0.8
1
VICR − Common-Mode Input Voltage − V
INPUT OFFSET VOLTAGE
vs
COMMON-MODE INPUT VOLTAGE
213504
VDD = 5 V
TA = 25°C
− Input Offset Voltage − mV
VIO
0.8
0.4
0.6
0.2
Figure 3
TA − Free-Air Temperature − °C
INPUT BIAS AND INPUT OFFSET CURRENT
vs
FREE-AIR TEMPERATURE
2.5
1.5
0.5
−0.5 −35 5
3
2
1
0
−15 25 125
4.5
−55 45 65
3.5
4
85 105
VDD = 3 V
VI = 1.5 V
IIB and I IO − Input Bias and Input Offset Current − nA
5
IIB
IIO
Figure 4
TA − Free-Air Temperature − °C
INPUT BIAS AND INPUT OFFSET CURRENT
vs
FREE-AIR TEMPERATURE
−1 −35 5
3
2
1
0
−15 25 125−55 45 65
4
85 105
IIB and I IO − Input Bias and Input Offset Current − nA
5
IIB
IIO
VDD = 5 V
VI = 2.5 V
6
SGLS008B − MARCH 2003 − REVISED MAY 2004
10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 5
TA = 125°C
TA = 85°C
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
0102030 60
IOH − High-Level Output Current − mA
5040 70 80
2.5
1
0
2
1.5
0.5
3
VOH− High-Level Output Voltage − V
VDD = 3 VDC
TA = −55°C
TA = 25°C
TA = −40°C
Figure 6
TA = 125°C
TA = 85°C
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
0 20 40 60 120
IOH − High-Level Output Current − mA
10080 140 200
2.5
1
0
2
1.5
0.5
3
VOH− High-Level Output Voltage − V
VDD = 5 VDC
TA = −55°C
4
5
4.5
3.5
160 180
TA = 25°C
TA = −40°C
Figure 7
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
0102030 60
IOL − Low-Level Output Current − mA
5040 70
2.5
1
0
2
1.5
0.5
3VDD = 3 VDC
TA = −55°C
OL
V − Low-Level Output Voltage − V
TA = 85°C
TA = 125°C
TA = 25°C
TA = −40°C
Figure 8
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
0 204060 120
IOL − Low-Level Output Current − mA
10080 140
2.5
1
0
2
1.5
0.5
3
VDD = 5 VDC
4.5
4
3.5
160
OL
V − Low-Level Output Voltage − V
TA = −55°C
TA = 85°C
TA = 125°C
TA = 25°C
TA = −40°C
SGLS008B − MARCH 2003 − REVISED MAY 2004
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TYPICAL CHARACTERISTICS
Figure 9
PEAK-TO-PEAK OUTPUT VOLTAGE
vs
FREQUENCY
10k 100k 10M
f − Frequency − Hz
1M
3
2
1
0
2.5
1.5
0.5
VO(PP) − Peak-to-Peak Output Voltage − V
VDD = 3 V
AV = −10
THD = 1%
RL = 10 kΩ
Figure 10
PEAK-TO-PEAK OUTPUT VOLTAGE
vs
FREQUENCY
10k 100k 10M
f − Frequency − Hz
1M
3
2
1
0
2.5
1.5
0.5
VO(PP) − Peak-to-Peak Output Voltage − V
VDD = 5 V
AV = −10
THD = 1%
RL = 10 kΩ
3.5
5
4
5.5
4.5
OPEN-LOOP GAIN AND PHASE
vs
FREQUENCY
40
20
0
−20 100 10k
f − Frequency − Hz
50
30
10
−10
1k 100k 1M
60
80
10
70
90
−140°
−200°
−120°
−100°
−80°
100
−60°
−40°
−20°
0°
20°
40°
−180°
−160°
Open-Loop Gain − dB
Phase
10M
AVD
Phase
VDD = ±1.5 V
RL = 10 kΩ
CL = 0
TA = 25°C
Figure 11
SGLS008B − MARCH 2003 − REVISED MAY 2004
12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
OPEN-LOOP GAIN AND PHASE
vs
FREQUENCY
40
20
0
−20 100 10k
f − Frequency − Hz
50
30
10
−10
1k 100k 1M
60
80
10
70
90
−140°
−200°
−120°
−100°
−80°
100
−60°
−40°
−20°
0°
20°
40°
−180°
−160°
Open-Loop Gain − dB
Phase
10M
AVD
Phase
VDD = ±2.5 V
RL = 10 kΩ
CL = 0
TA = 25°C
Figure 12
Figure 13
RL − Load Resistance − Ω
DIFFERENTIAL VOLTAGE AMPLIFICATION
vs
LOAD RESISTANCE
120
80
40
0
140
100
60
20
1k 10k 1M
180
100 100k
160 TA = 25°C
− Differential Voltage Amplification − V/mVAVD
VDD = ±2.5 V
VDD = ±1.5 V
Figure 14
CL− Capacitive Load − pF
CAPACITIVE LOAD
vs
LOAD RESISTANCE
10 100 10k
RL − Load Resistance − Ω
1k
10000
100
1000
Phase Margin > 30°
VDD = 5 V
Phase Margin = 30°
TA = 25°C
Phase Margin < 30°
SGLS008B − MARCH 2003 − REVISED MAY 2004
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 15
OUTPUT IMPEDANCE
vs
FREQUENCY
f − Frequency − Hz
1
0.1
0.01
10
1000
AV = 100
100 1k 10k 10M1M100k
− Output Impedance −ZoΩ
100
VDD = ±1.5 V
TA = 25°C
AV = 10
AV = 1
Figure 16
OUTPUT IMPEDANCE
vs
FREQUENCY
f − Frequency − Hz
1
0.1
0.01
10
1000
AV = 100
100 1k 10k 10M1M100k
− Output Impedance −ZoΩ
100
VDD = ±2.5 V
TA = 25°C
AV = 10
AV = 1
CMRR − Common-Mode Rejection Ratio − dB
COMMON-MODE REJECTION RATIO
vs
FREQUENCY
f − Frequency − Hz
10 1k 10k 10M1M100k
90
80
70
60
85
75
65
VDD = 5 V
VIC = 2.5 V
100
VDD = 3 V
VIC = 1.5 V
Figure 17
SGLS008B − MARCH 2003 − REVISED MAY 2004
14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 18
SUPPLY-VOLTAGE REJECTION RATIO
vs
FREQUENCY
f − Frequency − Hz
10 1k 10k 10M1M100k
110
80
60
40
90
70
50
100
100 VDD = ±1.5 V
TA = 25°C
kSVR − Supply Voltage Rejection Ratio − dB
−kSVR
+kSVR
+kSVR
−kSVR
Figure 19
SUPPLY-VOLTAGE REJECTION RATIO
vs
FREQUENCY
f − Frequency − Hz
10 1k 10k 10M1M100k
80
60
40
90
70
50
100
VDD = ±2.5 V
TA = 25°C
kSVR − Supply Voltage Rejection Ratio − dB
−kSVR
+kSVR
+kSVR
−kSVR
Figure 20
VDD − Supply Voltage − V
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
0.7
0.5
0.30
0.10 34
0.8
0.6
0.40
0.20
3.5 4.5 62.5 5 5.5
IDD = 25°C
IDD − Supply Current − mA
IDD = 85°C
IDD = −55°C
IDD = 125°C
IDD = −40°C
Figure 21
TA − Free-Air Temperature − °C
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
0.60
0.50
0.40
0.30 −35 5
0.65
0.55
0.45
0.35
−15 25 125
0.80
−55 45 65
0.70
0.75
VDD = 5 V
VI = 2.5 V
85 105
IDD − Supply Current − mA
VDD = 3 V
VI = 1.5 V
SGLS008B − MARCH 2003 − REVISED MAY 2004
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 22
t − Time − µs
AMPLIFIER WITH A SHUTDOWN PULSE
TURNON CHARACTERISTICS
2
0
2
0−3 1
1
3
1
−1 3 9
5
−5
V
57
SD − Shutdown Voltage − V
3
11
4
VDD = 5 V
RL = 10 kΩ
AV = 1
TA = 25°C
Shutdown Pin
Amplifier Output
Figure 23
t − Time − µs
AMPLIFIER WITH A SHUTDOWN PULSE
TURNOFF CHARACTERISTICS
2
0
2
0−3 1
1
3
1
−1 3
5
−5
V
57
SD − Shutdown Voltage − V
3
4VDD = 5 V
RL = 10 kΩ
AV = 1
TA = 25°C
Shutdown Pin
Amplifier Output
VDD = 5 V
VI = 2.5 V
AV = 1
TA = 25°C
0.4
−0.2
0.2
0
−0.4 −0.2 0 0.6
t − Time − µs0.40.2
SUPPLY CURRENT WITH A SHUTDOWN PULSE
TURNON CHARACTERISTICS
0.8
1
0.6
Supply Current
Shutdown Pin
IDD − Supply Current − mA
4.5
5.5
2.5
3.5
0.5
1.5
−0.5
VSD − Shutdown Voltage − V
Figure 24
SGLS008B − MARCH 2003 − REVISED MAY 2004
16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
VDD = 5 V
VI = 2.5 V
AV = 1
TA = 25°C
0.4
−0.2
0.2
0
−0.4 −0.2 0 0.6
t − Time − µs0.40.2
TURNOFF SUPPLY CURRENT
WITH A SHUTDOWN PULSE
0.8
1
0.6
Supply Current
Shutdown Pin
IDD − Supply Current − mA
4.5
5.5
2.5
3.5
0.5
1.5
−0.5
VSD − Shutdown Voltage − V
Figure 25
Figure 26
TA − Free-Air Temperature − °C
SHUTDOWN SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
2.5
1.5
0.5
−0.5
−35 5
3
2
1
0
−15 25 125−55 45 65 85 105
VDD = 5 V
VI = 2.5 V
−1
DD
I Shutdown Supply Current − −Aµ
VDD = 3 V
VI = 1.5 V
Figure 27
VDD − Supply Voltage − V
SLEW RATE
vs
SUPPLY VOLTAGE
2.5 3 3.5 4 5.5 654.5
1.6
1.5
1.4
1.3
1.55
1.45
1.35
1.8
1.7
1.75
1.65
SR − Slew Rate − V/µs
VO(PP) = 2 V
CL = 160 pF
AV = 1
RL = 10 kΩ
TA = 25°C
SR+
SR−
SGLS008B − MARCH 2003 − REVISED MAY 2004
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 28
EQUIVALENT INPUT NOISE VOLTAGE
vs
FREQUENCY
100 1k 100k
f − Frequency − Hz
10k
10
14
12
15
13
11
17
18
16
nV/ Hz− Equivalent Input Noise Voltage −Vn
VDD = 3 V
AV = 10
VI = 1.5 V
TA = 25°C
Figure 29
EQUIVALENT INPUT NOISE VOLTAGE
vs
FREQUENCY
100 1k 100k
f − Frequency − Hz
10k
10
14
12
15
13
11
17
18
16
nV/ Hz− Equivalent Input Noise Voltage −Vn
VDD = 5 V
AV = 10
VI = 2.5 V
TA = 25°C
Figure 30
VICR − Common-Mode Input Voltage − V
EQUIVALENT INPUT NOISE VOLTAGE
vs
COMMON-MODE INPUT VOLTAGE
12
10 1
14
13
11
0.5 1.5 3
20
02 2.5
15
VDD = 3 V
AV = 10
f = 1 kHz
TA = 25°C
nV/ Hz− Equivalent Input Noise Voltage −Vn
Figure 31
VICR − Common-Mode Input Voltage − V
EQUIVALENT INPUT NOISE VOLTAGE
vs
COMMON-MODE INPUT VOLTAGE
12
10 2
14
13
11
13
20
045
15
VDD = 5 V
AV = 10
f = 1 kHz
TA = 25°C
nV/ Hz− Equivalent Input Noise Voltage −Vn
SGLS008B − MARCH 2003 − REVISED MAY 2004
18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 32
TOTAL HARMONIC DISTORTION
vs
FREQUENCY
0.010
0.001 100 10k
f − Frequency − Hz
1k 100
k
10
0.1
THD − Total Harmonic Distortion − %
VDD = ±1.5 V
VO(PP) = 2 V
RL = 10 kΩ
AV = 1
AV = 10
AV = 100
0.5
Figure 33
TOTAL HARMONIC DISTORTION
vs
FREQUENCY
0.010
0.001 100 10k
f − Frequency − Hz
1k 100k10
0.1
THD − Total Harmonic Distortion − %
VDD = ±2.5 V
VO(PP) = 4 V
RL = 10 kΩ
AV = 1
AV = 10
AV = 100
1
Figure 34
TOTAL HARMONIC DISTORTION PLUS NOISE
vs
PEAK-TO-PEAK SIGNAL AMPLITUDE
0.010
0.001
0.1
THD+N − Total Harmonic Distortion + Noise − %
VDD = 3 V
AV = 1
TA = 25°C
1
RL = 10 kΩ
RL = 2 kΩ
RL = 250 Ω
RL = 100 kΩ
Peak-to-Peak Signal Amplitude − V
1 1.2 1.4 1.6 2.2 2.421.8 2.6 2.8 3 3.2
Figure 35
TOTAL HARMONIC DISTORTION PLUS NOISE
vs
PEAK-TO-PEAK SIGNAL AMPLITUDE
0.010
0.001
0.1
THD+N − Total Harmonic Distortion + Noise − %
VDD = 5 V
AV = 1
TA = 25°C
1
RL = 10 kΩ
RL = 250 Ω
RL = 100 kΩ
Peak-to-Peak Signal Amplitude − V
4 4.1 4.2 4.3 4.6 4.74.54.4 4.8 4.9 5
RL = 2 kΩ
SGLS008B − MARCH 2003 − REVISED MAY 2004
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 36
CL − Load Capacitance − pF
PHASE MARGIN
vs
LOAD CAPACITANCE
60
40
20
0
70
50
30
10
100 1k 100
k
90
10 10k
80
m
φ− Phase Margin − degrees
VDD = ±2.5 V
TA = 25°C
RL = 10 kΩ
Rnull = 50 Ω
Rnull = 20 Ω
Rnull = 0 Ω
Figure 37
TA − Free-Air Temperature − °C
PHASE MARGIN
vs
FREE-AIR TEMPERATURE
60
50
40
30 −35 5
55
45
35
−15 25 125−55 45 65
RL = 10 kΩ
CL = 160 pF
85 105
VDD = ±2.5 V
VDD = ±1.5 V
m
φ− Phase Margin − degrees
Figure 38
VDD − Supply Voltage − V
GAIN BANDWIDTH PRODUCT
vs
SUPPLY VOLTAGE
2.5 3 3.5 4 5.5 654.5
5
4.5
4
3.5
4.75
4.25
3.75
Gain Bandwidth Product − MHz
CL = 160 pF
RL = 10 kΩ
f = 10 kHz
TA = 25°C
Figure 39
TA − Free-Air Temperature − °C
GAIN BANDWIDTH PRODUCT
vs
FREE-AIR TEMPERATURE
4.5
4
3.5
3−35 5
4.25
3.75
3.25
−15 25 125−55 45 65
RL = 10 kΩ
CL = 160 pF
85 105
VDD = ±2.5 V
VDD = ±1.5 V
5
4.75
Gain Bandwidth Product − MHz
SGLS008B − MARCH 2003 − REVISED MAY 2004
20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 40
VO− Voltage − V
1.4
0.8
1.2
1
−2 0 2 4 10
t − Time − µs
861214
LARGE SIGNAL FOLLOWER
2.2
1.8
2
1.6
Input
Output
16 18
Output
Input
VDD = 3 V
VI(PP) = 1 V
VI = 1.5 V
RL = 10 kΩ
CL = 160 pF
AV = 1
TA = 25°C
Figure 41
VO− Voltage − V
2.1
1.7
1.3
−2 0 2 4 10
t − Time − µs
861214
LARGE SIGNAL FOLLOWER
3.7
2.9
3.3
2.5
Input
Output
16 18
Output
Input
VDD = 5 V
VI(PP) = 2 V
VI = 2.5 V
RL = 10 kΩ
CL = 160 pF
AV = 1
TA = 25°C
Figure 42
VO− Voltage − V
1.5
1.4
1.45
−0.2 0 0.2 0.4 1
t − Time − µs
0.80.6 1.2 1.4
SMALL SIGNAL FOLLOWER
1.6
1.55
Input
Output
1.6 1.8
VDD = 3 V
VI(PP) = 100 mV
VI = 1.5 V
RL = 10 kΩ
CL = 160 pF
AV = 1
TA = 25°C
Figure 43
VO− Voltage − V
2.5
2.4
2.45
−0.2 0 0.2 0.4 1
t − Time − µs
0.80.6 1.2 1.4
SMALL SIGNAL FOLLOWER
2.6
2.55
Input
Output
1.6 1.8
VDD = 5 V
VI(PP) = 100 mV
VI = 2.5 V
RL = 10 kΩ
CL = 160 pF
AV = 1
TA = 25°C
SGLS008B − MARCH 2003 − REVISED MAY 2004
21
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 44
VO− Voltage − V
VDD = 3 V
VI(PP) = 1 V
VI = 1.5 V
RL = 10 kΩ
CL = 160 pF
AV = −1
TA = 25°C
1.1
0.5
0.9
0.7
−0.2 0 0.2 0.4 1
t − Time − µs
0.80.6 1.2 1.4
INVERTING LARGE SIGNAL
1.9
1.5
1.7
1.3
1.6 1.8
2.3
2.1 Input
Output
Figure 45
VDD = 5 V
VI(PP) = 2 V
VI = 2.5 V
RL = 10 kΩ
CL = 160 pF
AV = −1
TA = 25°C
2.5
1
2
1.5
−0.2 0 0.2 0.4 1
t − Time − µs
0.80.6 1.2 1.4
INVERTING LARGE SIGNAL
3.5
4
3
1.6 1.8
Input
Output
VO− Voltage − V
Figure 46
VO− Voltage − V
1.5
1.4
1.45
−0.2 0 0.2 0.4 1
t − Time − µs
0.80.6 1.2 1.4
INVERTING SMALL SIGNAL
1.6
1.55 Input
Output
1.6 1.8
VDD = 3 V
VI(PP) = 100 mV
VI = 1.5 V
RL = 10 kΩ
CL = 160 pF
AV = −1
TA = 25°C
Figure 47
VO− Voltage − V
2.5
2.4
2.45
−0.2 0 0.2 0.4 1
t − Time − µs
0.80.6 1.2 1.4
INVERTING SMALL SIGNAL
2.6
2.55 Input
Output
1.6 1.8
VDD = 5 V
VI(PP) = 100 mV
VI = 2.5 V
RL = 10 kΩ
CL = 160 pF
AV = −1
TA = 25°C
SGLS008B − MARCH 2003 − REVISED MAY 2004
22 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
_
+
Rnull
RLCL
Figure 48
APPLICATION INFORMATION
driving a capacitive load
When the amplifier is configured in this manner, capacitive loading directly on the output will decrease the
device’s phase margin leading to high frequency ringing or oscillations. Therefore, for capacitive loads of greater
than 10 pF, it is recommended that a resistor be placed in series (RNULL) with the output of the amplifier, as
shown in Figure 49. A minimum value of 20 Ω should work well for most applications.
CLOAD
RF
Input Output
RGRNULL
_
+
Figure 49. Driving a Capacitive Load
offset voltage
The output offset voltage, (VOO) is the sum of the input offset voltage (VIO) and both input bias currents (IIB) times
the corresponding gains. The following schematic and formula can be used to calculate the output offset
voltage:
VOO +VIOǒ1)ǒRF
RGǓǓ"IIB)RSǒ1)ǒRF
RGǓǓ"IIB– RF
+
−
VI+
RG
RS
RF
IIB−
VO
IIB+
Figure 50. Output Offset Voltage Model
SGLS008B − MARCH 2003 − REVISED MAY 2004
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
general configurations
When receiving low-level signals, limiting the bandwidth of the incoming signals into the system is often
required. The simplest way to accomplish this is to place an RC filter at the noninverting terminal of the amplifier
(see Figure 51).
VIVO
C1
+
−
RGRF
R1
f–3dB +1
2pR1C1
VO
VI+ǒ1)RF
RGǓǒ1
1)sR1C1Ǔ
Figure 51. Single-Pole Low-Pass Filter
If even more attenuation is needed, a multiple pole filter is required. The Sallen-Key filter can be used for this
task. For best results, the amplifier should have a bandwidth that is 8 to 10 times the filter frequency bandwidth.
Failure to do this can result in phase shift of the amplifier.
VI
C2
R2R1
C1
RF
RG
R1 = R2 = R
C1 = C2 = C
Q = Peaking Factor
(Butterworth Q = 0.707)
(
=1
Q
2 − )
RGRF
_
+f–3dB +1
2pRC
Figure 52. 2-Pole Low-Pass Sallen-Key Filter
SGLS008B − MARCH 2003 − REVISED MAY 2004
24 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
shutdown function
Three members of the TLV246x family (TLV2460/3/5) have a shutdown terminal for conserving battery life in
portable applications. When the shutdown terminal is tied low, the supply current is reduced to 0.3 µA/channel,
the amplifier is disabled, and the outputs are placed in a high impedance mode. To enable the amplifier, the
shutdown terminal can either be left floating or pulled high. When the shutdown terminal is left floating, care
should be taken to ensure that parasitic leakage current at the shutdown terminal does not inadvertently place
the operational amplifier into shutdown. The shutdown terminal threshold is always referenced to VDD/2.
Therefore, when operating the device with split supply voltages (e.g. ±2.5 V), the shutdown terminal needs to
be pulled to VDD− (not GND) to disable the operational amplifier.
The amplifier’s output with a shutdown pulse is shown in Figures 22, 23, 24, and 25. The amplifier is powered
with a single 5-V supply and configured as a noninverting configuration with a gain of 5. The amplifier turnon
and turnoff times are measured from the 50% point of the shutdown pulse to the 50% point of the output
waveform. The times for the single, dual, and quad are listed in the data tables.
circuit layout considerations
To achieve the levels of high performance o f the TLV246x, follow proper printed-circuit board design techniques.
A general set of guidelines is given in the following.
DGround planes − It is highly recommended that a ground plane be used on the board to provide all
components with a low inductive ground connection. However, in the areas of the amplifier inputs and
output, the ground plane can be removed to minimize the stray capacitance.
DProper power supply decoupling − Use a 6.8-µF tantalum capacitor in parallel with a 0.1-µF ceramic
capacitor on each supply terminal. It may be possible to share the tantalum among several amplifiers
depending on the application, but a 0.1-µF ceramic capacitor should always be used on the supply terminal
of every amplifier. In addition, the 0.1-µF capacitor should be placed as close as possible to the supply
terminal. As this distance increases, the inductance in the connecting trace makes the capacitor less
effective. The designer should strive for distances of less than 0.1 inches between the device power
terminals and the ceramic capacitors.
DSockets − Sockets can be used but are not recommended. The additional lead inductance in the socket pins
will often lead to stability problems. Surface-mount packages soldered directly to the printed-circuit board
is the best implementation.
DShort trace runs/compact part placements − Optimum high performance is achieved when stray series
inductance has been minimized. To realize this, the circuit layout should be made as compact as possible,
thereby minimizing the length of all trace runs. Particular attention should be paid to the inverting input of
the amplifier. Its length should be kept as short as possible. This will help to minimize stray capacitance at
the input of the amplifier.
DSurface-mount passive components − Using surface-mount passive components is recommended for high
performance amplifier circuits for several reasons. First, because of the extremely low lead inductance of
surface-mount components, the problem with stray series inductance is greatly reduced. Second, the small
size of surface-mount components naturally leads to a more compact layout thereby minimizing both stray
inductance and capacitance. If leaded components are used, it is recommended that the lead lengths be
kept as short as possible.
SGLS008B − MARCH 2003 − REVISED MAY 2004
25
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
general power dissipation considerations
For a given θJA, the maximum power dissipation is shown in Figure 53 and is calculated by the following formula:
PD+ǒTMAX–TA
qJA Ǔ
Where: PD= Maximum power dissipation of THS246x IC (watts)
TMAX= Absolute maximum junction temperature (150°C)
TA= Free-ambient air temperature (°C)
θJA = θJC + θCA
θJC = Thermal coefficient from junction to case
θCA = Thermal coefficient from case to ambient air (°C/W)
1
0.75
0.5
0
−55−40 −25 −10 5
Maximum Power Dissipation − W
1.25
1.5
MAXIMUM POWER DISSIPATION
vs
FREE-AIR TEMPERATURE
1.75
20 35 50
0.25
TA − Free-Air Temperature − °C
2
65 80 95 110 125
MSOP Package
Low-K Test PCB
θJA = 260°C/W
TJ = 150°C
PDIP Package
Low-K Test PCB
θJA = 104°C/W
SOIC Package
Low-K Test PCB
θJA = 176°C/W
SOT-23 Package
Low-K Test PCB
θJA = 324°C/W
NOTE A: Results are with no air flow and using JEDEC Standard Low-K test PCB.
Figure 53. Maximum Power Dissipation vs Free-Air Temperature
SGLS008B − MARCH 2003 − REVISED MAY 2004
26 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
macromodel information
Macromodel information provided was derived using Microsim Parts Release 8, the model generation
software used with Microsim PSpice. The Boyle macromodel (see Note 2) and subcircuit in Figure 54 are
generated using the TLV246x typical electrical and operating characteristics at TA = 25°C. Using this
information, output simulations of the following key parameters can be generated to a tolerance of 20% (in most
cases):
DMaximum positive output voltage swing
DMaximum negative output voltage swing
DSlew rate
DQuiescent power dissipation
DInput bias current
DOpen-loop voltage amplification
DUnity-gain frequency
DCommon-mode rejection ratio
DPhase margin
DDC output resistance
DAC output resistance
DShort-circuit output current limit
NOTE 2: G. R. Boyle, B. M. Cohn, D. O. Pederson, and J. E. Solomon, “Macromodeling of Intergrated Circuit Operational Amplifiers”, IEEE
Journal of Solid-State Circuits, SC-9, 353 (1974).
+
−
+
−
+
−
+
−+
−
.SUBCKT TLV246X 1 2 3 4 5
C1 11 12 2.46034E−12
C2 6 7 10.0000E−12
CSS 10 99 443.21E−15
DC 5 53 DY
DE 54 5 DY
DLP 90 91 DX
DLN 92 90 DX
DP 4 3 DX
EGND 99 0 POLY (2) (3,0) (4,0) 0 .5 .5
FB 7 99 POLY (5) VB VC VE VLP
+ VLN 0 21.600E6 −1E3 1E3 22E6 −22E6
GA 6 0 11 12 345.26E−6
GCM 0 6 10 99 15.4226E−9
ISS 10 4 DC 18.850E−6
HLIM 90 0 VLIM 1K
J1 11 2 10 JX1
J2 12 1 10 JX2
R2 6 9 100.00E3
RD1 3 11 2.8964E3
RD2 3 12 2.8964E3
R01 8 5 5.6000
R02 7 99 6.2000
RP 3 4 8.9127
RSS 10 99 10.610E6
VB 9 0 DC 0
VC 3 53 DC .7836
VE 54 4 DC .7436
VLIM 7 8 DC 0
VLP 91 0 DC 117
VLN 0 92 DC 117
.MODEL DX D (IS=800.00E−18)
.MODEL DY D (IS=800.00E−18 Rs = 1m Cjo=10p)
.MODEL JX1 NJF (IS=1.0000E−12 BETA=6.3239E−3
+ VTO=−1)
.MODEL JX2 NJF (IS=1.0000E−12 BETA=6.3239E−3
+ VTO=−1)
.ENDS
VDD+
RP
IN − 2
IN+ 1
GND
RD1
11
J1 J2
10
RSS
ISS
3
12
RD2
DP
VD
DC
4
C1
53
EGND FB
HLIM
90 DLP
91
DLN 92
VLNVLP
99
CSS
+
−
VE
DE
54
OUT
+
−
+
−
R2 6
9
VB
C2
GA
VLIM
8
5
RO1
RO2
7
GCM
Figure 54. Boyle Macromodels and Subcircuit
PSpice and Parts are trademarks of MicroSim Corporation.
SGLS008B − MARCH 2003 − REVISED MAY 2004
27
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
macromodel information (continued)
.subckt TLV_246Y 1 2 3 4 5 6
c1 11 12 2.4603E−12
c2 72 7 10.000E−12
css 10 99 443.21E−15
dc 70 53 dy
de 54 70 dy
dlp 90 91 dx
dln 92 90 dx
dp 43dx
egnd 99 0 poly(2) (3,0) (4,0) 0 .5 .5
fb 7 99 poly(5) vb vc ve vlp vln 0
21.600E6 −1E3 1E3 22E6 −22E6
ga 72 0 11 12 345.26E−6
gcm 0 72 10 99 15.422E−9
iss 74 4 dc 18.850E−6
hlim 90 0 vlim 1K
j1 11 2 10 jx1
j2 12 1 10 jx2
r2 72 9 100.00E3
rd1 3 11 2.8964E3
rd2 3 12 2.8964E3
ro1 8 70 5.6000
ro2 7 99 6.2000
rp 3 71 8.9127
rss 10 99 10.610E6
rs1 6 4 1G
rs2 6 4 1G
rs3 6 4 1G
rs4 6 4 1G
s1 71 4 6 4 s1x
s2 70 5 6 4 s1x
s3 10 74 6 4 s1x
s4 74 4 6 4 s2x
vb 9 0 dc 0
vc 3 53 dc .7836
ve 54 4 dc .7436
vlim 7 8 dc 0
vlp 91 0 dc 117
vln 0 92 dc 117
.model dx D(Is=800.00E−18)
.model dy D(Is=800.00E−18 Rs=1m Cjo=10p)
.model jx1 NJF(Is=1.0000E−12 Beta=6.3239E−3 Vto=−1)
.model jx2 NJF(Is=1.0000E−12 Beta=6.3239E−3 Vto=−1)
.model s1x VSWITCH(Roff=1E8 Ron=1.0 Voff=2.5 Von=0.0)
.model s2x VSWITCH(Roff=1E8 Ron=1.0 Voff=0 Von=2.5)
.ends
Figure 54. Boyle Macromodels and Subcircuit (Continued)
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
TLV2460AQDRQ1 ACTIVE SOIC D 8 2500 Pb-Free
(RoHS) CU NIPDAU Level-2-250C-1 YEAR/
Level-1-235C-UNLIM
TLV2460AQPWRQ1 ACTIVE TSSOP PW 8 2000 None CU NIPDAU Level-1-220C-UNLIM
TLV2460QDRQ1 ACTIVE SOIC D 8 2500 Pb-Free
(RoHS) CU NIPDAU Level-2-250C-1 YEAR/
Level-1-235C-UNLIM
TLV2460QPWRQ1 ACTIVE TSSOP PW 8 2000 None CU NIPDAU Level-1-220C-UNLIM
TLV2461AQDRQ1 ACTIVE SOIC D 8 2500 Pb-Free
(RoHS) CU NIPDAU Level-2-250C-1 YEAR/
Level-1-235C-UNLIM
TLV2461AQPWRQ1 ACTIVE TSSOP PW 8 2000 None CU NIPDAU Level-1-220C-UNLIM
TLV2461QDRQ1 ACTIVE SOIC D 8 2500 Pb-Free
(RoHS) CU NIPDAU Level-2-250C-1 YEAR/
Level-1-235C-UNLIM
TLV2461QPWRQ1 ACTIVE TSSOP PW 8 2000 None CU NIPDAU Level-1-220C-UNLIM
TLV2462AQDRQ1 ACTIVE SOIC D 8 2500 Pb-Free
(RoHS) CU NIPDAU Level-2-250C-1 YEAR/
Level-1-235C-UNLIM
TLV2462AQPWRQ1 ACTIVE TSSOP PW 8 2000 None CU NIPDAU Level-1-220C-UNLIM
TLV2462QDRQ1 ACTIVE SOIC D 8 2500 Pb-Free
(RoHS) CU NIPDAU Level-2-250C-1 YEAR/
Level-1-235C-UNLIM
TLV2462QPWRQ1 ACTIVE TSSOP PW 8 2000 None CU NIPDAU Level-1-220C-UNLIM
TLV2463AQDRQ1 ACTIVE SOIC D 14 2500 Pb-Free
(RoHS) CU NIPDAU Level-2-250C-1 YEAR/
Level-1-235C-UNLIM
TLV2463AQPWRQ1 ACTIVE TSSOP PW 14 2000 None CU NIPDAU Level-1-250C-UNLIM
TLV2463QDRQ1 ACTIVE SOIC D 14 2500 Pb-Free
(RoHS) CU NIPDAU Level-2-250C-1 YEAR/
Level-1-235C-UNLIM
TLV2463QPWRQ1 ACTIVE TSSOP PW 14 2000 None CU NIPDAU Level-1-250C-UNLIM
TLV2464AQPWRQ1 ACTIVE TSSOP PW 14 2000 None CU NIPDAU Level-1-250C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
PACKAGE OPTION ADDENDUM
www.ti.com 25-Feb-2005
Addendum-Page 1
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 25-Feb-2005
Addendum-Page 2
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,65 M
0,10
0,10
0,25
0,50
0,75
0,15 NOM
Gage Plane
28
9,80
9,60
24
7,90
7,70
2016
6,60
6,40
4040064/F 01/97
0,30
6,60
6,20
80,19
4,30
4,50
7
0,15
14
A
1
1,20 MAX
14
5,10
4,90
8
3,10
2,90
A MAX
A MIN
DIM PINS **
0,05
4,90
5,10
Seating Plane
0°–8°
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
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