1. General description
The 74LVC138A-Q100 is a 3-to-8 line decoder/demultiplexer. It accepts three binary
weighted address inputs (A0, A1 and A2). When the inputs are enabled, it provides eight
mutually exclusive outputs (Y0to Y7) that are LOW when selected.
There are three enable inputs: two active LOW (E1andE2) and one active HIGH (E3).
Every output is HIGH unless E1 and E2 are LOW and E3 is HIGH.
This multiple enable function allows easy parallel expansion of the device to a 1-of-32
(5 lines to 32 lines) decoder with just four 74LVC138A-Q100 devices and one inverter.
The 74LVC138A-Q100 can be used as an eight output demultiplexer by using one of the
active LOW enable inputs as the data input and the remaining enable inputs as strobes.
Unused enable inputs must be permanently tied to their appropriate active HIGH or LOW
state.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from 40 C to +85 C and from 40 C to +125 C
5 V tolerant inputs for interfacing with 5 V logic
Wide supply voltage range from 1.2 V to 3.6 V
CMOS low power consumption
Direct interface with TTL levels
Demultiplexing capability
Multiple input enab le for ea sy ex pansion
Ideal for memory chip select decoding
Mutually exclusive outputs
Output drive capability 50 transmission lines at 125 C
Complies with JEDEC standard:
JESD8-7A (1.65 V to 1.95 V)
JESD8-5A (2.3 V to 2.7 V)
JESD8-C/JESD36 (2.7 V to 3.6 V)
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )
Multiple package options
74LVC138A-Q100
3-to-8 line decoder/demultiplexer; inverting
Rev. 1 — 4 April 2013 Product data sheet
74LVC138A_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 1 — 4 April 2013 2 of 15
NXP Semiconductors 74LVC138A-Q100
3-to-8 line decoder/demultiplexer; inverting
3. Ordering information
4. Functional diagram
Table 1. Ordering information
Type number Package
Temp erature range Name Description Version
74LVC138AD-Q100 40 Cto+125C SO16 plastic small outline package; 16 leads;
body width 3.9 mm SOT109-1
74LVC138APW-Q100 40 Cto+125C TSSOP16 plastic thin shrink small outline package;
16 leads; body width 4.4 mm SOT403-1
74LVC138ABQ-Q100 40 Cto+125C DHVQFN16 plastic dual in-line compatible thermal-enhanced
very thin quad flat package; no leads;
16 terminals; body 2.5 3.5 0.85 mm
SOT763-1
Fig 1. Logic symbol Fig 2. IEC logic symbol
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7 7
9
10
11
12
13
14
15
A0
A1
A2
3
2
1
6
5
4E2
E1
E3
mna370
mna371
7
9
10
11
12
13
14
&
X/Y 15
7
EN6
5
4
3
2
1
0
6
5
4
3
2
11
4
2
7
9
10
11
12
13
14
&
DX
(a) (b)
15
7
6
5
4
3
2
1
0
6
5
4
3
2
10
2
G0
7
Fig 3. Functional diagram
mna372
ENABLE
EXITING
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7 7
9
10
11
12
13
14
15
A0
A1
A2 3-to-8
DECODER
3
2
1
6
5
4
E2
E1
E3
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Product data sheet Rev. 1 — 4 April 2013 3 of 15
NXP Semiconductors 74LVC138A-Q100
3-to-8 line decoder/demultiplexer; inverting
5. Pinning information
5.1 Pinning
5.2 Pin description
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Fig 4. Pin configuration for SO16 and TSSOP16 Fig 5. Pin configuration for DHVQFN16
/9&$4
$
9&&
$
<
$
<
(
<
(
<
(
<
<
<
*1' <
DDD







DDD
/9&$4
*1'
< <
( <
( <
( <
$ <
$ <
*1'
<
$
9&&
7UDQVSDUHQWWRSYLHZ







WHUPLQDO
LQGH[DUHD
Table 2. Pin description
Symbol Pin Description
A0 1 address input
A1 2 address input
A2 3 address input
E1 4 enable input (active LOW )
E2 5 enable input (active LOW )
E3 6 enable input (active HIGH)
GND 8 ground (0 V)
Y[0:7] 15, 14, 13, 12, 11, 10, 9, 7 output
VCC 16 supply voltage
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Product data sheet Rev. 1 — 4 April 2013 4 of 15
NXP Semiconductors 74LVC138A-Q100
3-to-8 line decoder/demultiplexer; inverting
6. Functional description
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care
7. Limiting values
[1] The minimum input voltage ratings may be exceeded if the input current ratings are observed.
[2] The output voltage ratings may be exceeded if the output current ratings are observed.
[3] For SO16 packages: above 70 C the value of PD derates linearly with 8 mW/K.
For TSSOP16 packages: above 60 C the value of PD derates linearly with 5.5 mW/K.
For DHVQFN16 packages: above 60 C the value of PD derates linearly with 4.5 mW/K.
Table 3. Function table [1]
Input Output
E1 E2 E3 A0 A1 A2 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
HXXXXXHHHHHHHH
XHXXXXHHHHHHHH
XXLXXXHHHHHHHH
LLHLLLLHHHHHHH
HLLHLHHHHHH
LHLHHLHHHHH
HHLHHHLHHHH
LLHHHHHLHHH
HLHHHHHHLHH
LHHHHHHHHLH
HHHHHHHHHHL
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
VCC supply voltage 0.5 +6.5 V
IIK input clampi n g cu rre nt VI<0 V 50 - mA
VIinput voltage [1] 0.5 +6.5 V
IOK output clamping current VO>V
CC or VO<0 V - 50 mA
VOoutput voltage output HIGH or LOW state [2] 0.5 VCC +0.5 V
IOoutput current VO=0 VtoV
CC -50 mA
ICC supply cur ren t - 100 mA
IGND ground current 100 - mA
Tstg storage temperature 65 +150 C
Ptot total power dissipation Tamb =40 C to +125 C[3] -500 mW
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Product data sheet Rev. 1 — 4 April 2013 5 of 15
NXP Semiconductors 74LVC138A-Q100
3-to-8 line decoder/demultiplexer; inverting
8. Recommended operating conditions
9. Static characteristics
Table 5. Recommended operating con ditions
Symbol Parameter Conditions Min Typ Max Unit
VCC supply voltage 1.65 - 3.6 V
functional 1.2 - - V
VIinput voltage 0 - 5.5 V
VOoutput voltage output HIGH or LOW state 0 - VCC V
Tamb ambient temperature 40 - +125 C
t/V input transition rise and fall
rate VCC = 1.65 V to 2.7 V 0 - 20 ns/V
VCC = 2.7 V to 3.6 V 0 - 10 ns/V
Table 6. Static characteristics
At recommended operating conditions. V oltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 40 C to +85 C40 C to +125 CUnit
Min Typ[1] Max Min Max
VIH HIGH-level
input voltage VCC = 1.2 V 1.08 - - 1.08 - V
VCC = 1.65 V to 1.95 V 0.65 VCC - - 0.65 VCC -V
VCC = 2.3 V to 2.7 V 1.7 - - 1.7 - V
VCC = 2.7 V to 3.6 V 2.0 - - 2.0 - V
VIL LOW-level
input voltage VCC = 1.2 V - - 0.12 - 0.12 V
VCC = 1.65 V to 1.95 V - - 0.35 VCC -0.35 VCC V
VCC = 2.3 V to 2.7 V - - 0.7 - 0.7 V
VCC = 2.7 V to 3.6 V - - 0.8 - 0.8 V
VOH HIGH-level
output
voltage
VI=V
IH or VIL
IO=100 A;
VCC =1.65Vto3.6V VCC 0.2 - - VCC 0.3 - V
IO=4mA; V
CC = 1.65 V 1.2 - - 1.05 - V
IO=8mA; V
CC = 2.3 V 1.8 - - 1.65 - V
IO=12 mA; VCC = 2.7 V 2.2 - - 2.05 - V
IO=18 mA; VCC = 3.0 V 2.4 - - 2.25 - V
IO=24 mA; VCC = 3.0 V 2.2 - - 2.0 - V
VOL LOW-level
output
voltage
VI=V
IH or VIL
IO= 100 A;
VCC = 1.65 V to 3.6 V - - 0.2 - 0.3 V
IO=4mA; V
CC = 1.65 V - - 0.45 - 0.65 V
IO=8mA; V
CC = 2.3 V - - 0.6 - 0.8 V
IO=12mA; V
CC = 2.7 V - - 0.4 - 0.6 V
IO=24mA; V
CC = 3.0 V - - 0.55 - 0.8 V
IIinput leakage
current VCC = 3.6 V; VI=5.5VorGND - 0.1 5- 20 A
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Product data sheet Rev. 1 — 4 April 2013 6 of 15
NXP Semiconductors 74LVC138A-Q100
3-to-8 line decoder/demultiplexer; inverting
[1] All typical values are measured at VCC = 3.3 V (unless stated otherwise) and Tamb =25C.
10. Dynamic characteristics
ICC supply
current VCC = 3.6 V; VI=V
CC or GND;
IO=0A -0.110-40A
ICC additional
supply
current
per input pin;
VCC = 2.7 V to 3.6 V;
VI=V
CC 0.6 V; IO=0A
- 5 500 - 5000 A
CIinput
capacitance VCC = 0 V to 3.6 V;
VI=GNDtoV
CC
-4.0---pF
Table 6. Static characteristics …continued
At recommended operating conditions. V oltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 40 C to +85 C40 C to +125 CUnit
Min Typ[1] Max Min Max
Table 7. Dynamic characteristics
Vo ltages are referenced to GND (ground = 0 V). For test circuit see Figure 8.
Symbol Parameter Conditions 40 C to +85 C40 C to +125 CUnit
Min Typ[1] Max Min Max
tpd propagation delay An to Yn; see Figure 6 [2]
VCC = 1.2 V - 14 - - - ns
VCC = 1.65 V to 1.95 V 0.5 5.2 11.5 0.5 12.7 ns
VCC = 2.3 V to 2.7 V 1.5 3.0 6.5 1.5 7.3 ns
VCC = 2.7 V 1.5 3.2 6.8 1.5 8.5 ns
VCC = 3.0 V to 3.6 V 1.0 2.7 5.8 1.0 7.5 ns
E3 to Yn; see Figure 6 [2]
VCC = 1.2 V - 14 - - - ns
VCC = 1.65 V to 1.95 V 1.0 5.5 11.4 1.0 12.5 ns
VCC = 2.3 V to 2.7 V 1.5 3.2 6.5 1.5 7.1 ns
VCC = 2.7 V 1.5 3.3 6.8 1.5 8.5 ns
VCC = 3.0 V to 3.6 V 1.0 2.9 5.8 1.0 7.5 ns
EntoYn; see Figure 7 [2]
VCC = 1.2 V - 15 - - - ns
VCC = 1.65 V to 1.95 V 1.0 5.6 11.5 1.0 12.8 ns
VCC = 2.3 V to 2.7 V 1.8 3.3 6.5 1.8 7.3 ns
VCC = 2.7 V 1.5 3.4 6.4 1.5 8.0 ns
VCC = 3.0 V to 3.6 V 1.0 2.9 5.8 1.0 7.5 ns
tsk(o) output skew time [3] - - 1.0 - 1.5 ns
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Product data sheet Rev. 1 — 4 April 2013 7 of 15
NXP Semiconductors 74LVC138A-Q100
3-to-8 line decoder/demultiplexer; inverting
[1] Typical values are measured at Tamb =25C and VCC = 1.2 V, 1.8 V, 2.5 V, 2.7 V, and 3.3 V respectively.
[2] tpd is the same as tPLH and tPHL.
[3] Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
[4] CPD is used to determine the dynamic power dissipation (PDin W).
PD=C
PD VCC2fiN+(CLVCC2fo) where:
fi= input frequency in MHz; fo= output frequency in MHz
CL= output load capacitance in pF
VCC = supply voltage in V
N = number of inputs switching
(CLVCC2fo) = sum of outputs
11. Waveforms
CPD power dissipation
capacitance VI = GND to VCC [4]
VCC = 1.65 V to 1.95 V - 9.9 - pF
VCC = 2.3 V to 2.7 V - 15.8 - pF
VCC = 3.0 V to 3.6 V - 21.1 - pF
Table 7. Dynamic characteristics …continued
Vo ltages are referenced to GND (ground = 0 V). For test circuit see Figure 8.
Symbol Parameter Conditions 40 C to +85 C40 C to +125 CUnit
Min Typ[1] Max Min Max
VM=1.5VatV
CC 2.7 V;
VM=0.5 VCC at VCC <2.7V;
VOL and VOH are typical output voltage levels that occur
with the output load.
VM=1.5VatV
CC 2.7 V;
VM=0.5 VCC at VCC <2.7V;
VOL and VOH are typical output voltage levels that occur
with the output load.
Fig 6. The inputs An, E3 to outputs Yn propagation
delays Fig 7. The inputs En to outputs Yn propagation
delays
mna373
An, E3
input
Yn
output
tPHL
tTHL
tPLH
GND
VCC
VM
VM
VOH
VOL tTLH
mna374
E1, E2
input
Yn
output
tPHL tPLH
GND
VCC
VM
VM
VOH
VOL tTHL tTLH
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Product data sheet Rev. 1 — 4 April 2013 8 of 15
NXP Semiconductors 74LVC138A-Q100
3-to-8 line decoder/demultiplexer; inverting
Test data is given in Table 8. Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
Fig 8. Test circuit for measuring switching times
V
M
V
M
t
W
t
W
10 %
90 %
0 V
V
I
V
I
negative
pulse
positive
pulse
0 V
V
M
V
M
90 %
10 %
t
f
t
r
t
r
t
f
001aaf615
V
CC
V
I
V
O
DUT
CL
RTRL
PULSE
GENERATOR
Table 8. Test data
Supply voltage Input Load
VItr, tfCLRL
1.2 V VCC 2 ns 30 pF 1 k
1.65 V to 1.95 V VCC 2 ns 30 pF 1 k
2.3 V to 2.7 V VCC 2 ns 30 pF 500
2.7V 2.7V 2.5 ns 50 pF 500
3.0Vto3.6V 2.7V 2.5 ns 50 pF 500
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Product data sheet Rev. 1 — 4 April 2013 9 of 15
NXP Semiconductors 74LVC138A-Q100
3-to-8 line decoder/demultiplexer; inverting
12. Package outline
Fig 9. Package outline SOT109-1 (SO16)
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Product data sheet Rev. 1 — 4 April 2013 10 of 15
NXP Semiconductors 74LVC138A-Q100
3-to-8 line decoder/demultiplexer; inverting
Fig 10. Package outline SOT403-1 (TSSOP16)
UNIT A1A2A3bpcD
(1) E(2) (1)
eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.15
0.05 0.95
0.80 0.30
0.19 0.2
0.1 5.1
4.9 4.5
4.3 0.65 6.6
6.2 0.4
0.3 0.40
0.06 8
0
o
o
0.13 0.10.21
DIMENSIONS (mm are the original dimensions)
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
0.75
0.50
SOT403-1 MO-153 99-12-27
03-02-18
wM
bp
D
Z
e
0.25
18
16 9
θ
A
A1
A2
Lp
Q
detail X
L
(A )
3
HE
E
c
vMA
X
A
y
0 2.5 5 mm
scale
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1
A
max.
1.1
pin 1 index
74LVC138A_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 1 — 4 April 2013 11 of 15
NXP Semiconductors 74LVC138A-Q100
3-to-8 line decoder/demultiplexer; inverting
Fig 11. Package outline SOT763-1 (DHVQFN16)
terminal 1
index area
0.51
A1Eh
b
UNIT ye
0.2
c
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 3.6
3.4
Dh
2.15
1.85
y1
2.6
2.4 1.15
0.85
e1
2.5
0.30
0.18
0.05
0.00 0.05 0.1
DIMENSIONS (mm are the original dimensions)
SOT763-1 MO-241 - - -- - -
0.5
0.3
L
0.1
v
0.05
w
0 2.5 5 mm
scale
SOT763-1
DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
16 terminals; body 2.5 x 3.5 x 0.85 mm
A(1)
max.
AA1c
detail X
y
y1C
e
L
Eh
Dh
e
e1
b
27
15 10
9
8
1
16
X
D
E
C
BA
terminal 1
index area
AC
CB
vM
wM
E(1)
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
D(1)
02-10-17
03-01-27
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Product data sheet Rev. 1 — 4 April 2013 12 of 15
NXP Semiconductors 74LVC138A-Q100
3-to-8 line decoder/demultiplexer; inverting
13. Abbreviations
14. Revision history
Table 9. Abbr eviations
Acronym Description
CDM Charged Device Mo del
DUT Device Under Test
ESD ElectroStatic Discharge
HBM Human Body Model
MIL Military
MM Machine Model
TTL Tr ansistor-Transistor Logic
Table 10. Revision history
Document ID Release date Data sheet status Change notice Supersedes
74LVC138A_Q100 v.1 20130404 Product data sheet - -
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Product data sheet Rev. 1 — 4 April 2013 13 of 15
NXP Semiconductors 74LVC138A-Q100
3-to-8 line decoder/demultiplexer; inverting
15. Legal information
15.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of de vice(s) descr ibed in th is docume nt may have cha nged since this docume nt was publis hed and ma y dif fer in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liab ility for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and tit le. A short data sh eet is intended
for quick reference only and shou ld not be rel ied u pon to cont ain det ailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall pre vail.
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data sheet shall define the specification of the product as agreed between
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customer have explicitly agreed otherwise in writing. In no event however,
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deemed to off er functions and qualities beyond tho se described in the
Product data sheet.
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testing for th e customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanent ly and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individua l agreement. In case an individual
agreement is concluded only the ter ms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly object s to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.
Product [short] dat a sheet Production This document contains the product specification.
74LVC138A_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 1 — 4 April 2013 14 of 15
NXP Semiconductors 74LVC138A-Q100
3-to-8 line decoder/demultiplexer; inverting
No offer to sell or license — Nothing in this document may be interpret ed or
construed as an of fer to sell product s that is op en for accept ance or the grant ,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
15.4 Trademarks
Notice: All referenced b rands, produc t names, service names and trademarks
are the property of their respect i ve ow ners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
NXP Semiconductors 74LVC138A-Q100
3-to-8 line decoder/demultiplexer; inverting
© NXP B.V. 2013. All rights reserved.
For more information, please visit: http://www.nxp.co m
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 4 April 2013
Document identifier: 74LVC138A_Q100
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
17. Contents
1 General description. . . . . . . . . . . . . . . . . . . . . . 1
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2
4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
6 Functional description . . . . . . . . . . . . . . . . . . . 4
7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
8 Recommended operating conditions. . . . . . . . 5
9 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
10 Dynamic characteristics . . . . . . . . . . . . . . . . . . 6
11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9
13 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 12
14 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 12
15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 13
15.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 13
15.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
15.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 13
15.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 14
16 Contact information. . . . . . . . . . . . . . . . . . . . . 14
17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
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