A8672EEGTR-T - ALLEGRO MICROSYSTEMS

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local Allegro field applications engineer or sales representative.

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for a product to accommodate changes in production capabilities, alternative product availabilities, or market demand. The

information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no respon-

sibility for its use; nor for any infringements of patents or other rights of third parties which may result from its use.

Recommended Substitutions: no direct replacement

Fixed Frequency High Current Synchronous Buck Regulator

With Fault Warnings and Power OK

A8672

For existing customer transition, and for new customers or new appli-

cations, contact Allegro Sales.

Date of status change: September 1, 2016

This device is no longer in production. The device should not be

purchased for new design applications. Samples are no longer available.

Discontinued Product

Description

The A8672 is a synchronous buck converter capable of

delivering up to 8 A. The A8672 utilizes valley current mode

control, allowing very short on-times to be achieved. This makes

it ideal for applications that require very low output voltages

relative to the input voltage, combined with high switching

frequencies. Valley current mode control inherently provides

improved transient response over traditional switcher schemes,

through the use of a voltage feedforward loop and frequency

modulation during large signal load changes.

The A8672 includes a comprehensive set of diagnostic flags,

allowing the host platform to react to a myriad of different

conditions. A fault output indicates when either the temp-

erature is becoming unusually high, or a single point failure

has occurred; for example, the switching node (LX) shorted to

ground, or the timing resistor going open-circuit. A Power OK

(POK) output is also provided after a fixed delay, to indicate

when the output voltage is within regulation. The selectable

pulse-by-pulse current limit avoids the requirement to oversize

the inductor to cope with large fault currents.

The device package (EG) is a 28-contact, 4 mm × 5 mm,

0.75 mm nominal overall height QFN with exposed thermal

pad. The package is lead (Pb) free, with 100% matte tin

leadframe plating.

A8672-DS, Rev. 3

MCO-0000466

Features and Benefits

• High efficiency integrated FETs optimized for lower duty

cycle voltage conversion: 27 mΩ high side, 12 mΩ low side

• Power input voltage range: 3 to 16 V

• Control input voltage range: 4.5 to 16V

• Adjustable output voltage, down to 0.6 V

• 5 V LDO Regulator

• Extremely short minimum controllable on-time;

example: allows 12 V conversion to 0.6 V at >1 MHz

• Reference accuracy of ±1% throughout temperature range

• ¯

and Power OK pins for operating and

protection modes

• Low power mode (LPM) or fixed continuous conduction

mode (FCCM) operation

• Programmable soft-start / hiccup shutdown period

• Ultra-fast transient response

Applications

• Servers

• Point of load supplies

Fixed Frequency High Current Synchronous Buck Regulator

With Fault Warnings and Power OK

Package: 28-contact QFN with exposed

thermal pad (suffix EG)

Typical Application Diagram

VIN = 12 V, VOUT = 1.2 V, and fSW = 500 kHz

A8672

Approximate size

12 V

BOOT

VIN

TON

VDD

VREG

BIAS

MODE

22 µF

47 nF

VOUT

1.2 V

1 µH

90.9kΩ A8672

POK

FAULT

pull-up

AGND PGND

POK

FAULT

10 kΩ

20 kΩ

56 k Ω

249 k Ω

COMP

ILIM

22 µF

100 µF

C12

22 pF

C11

680 pF

22 µF

2.2 µF C9

470 nF

C10

10 nF

PAD

• Network and telecom

• Storage

July 5, 2018

Fixed Frequency High Current Synchronous Buck Regulator

With Fault Warnings and Power OK

A8672

Allegro MicroSystems, LLC

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

Absolute Maximum Ratings

Characteristic Symbol Notes Rating Unit

VIN, VDD, TON, VREG, BIAS and EN

Pin Voltage VIWith respect to GND –0.3 to 18 V

LX Pin Voltage VLX

With respect to GND –0.6 to VIN + 0.3 V

t < 50 ns, with respect to GND –2.0 V

BOOT Pin Voltage VBOOT With respect to GND VLX – 0.3 to

VLX + 8.0 V

All Other Pins – –0.3 to 7.0 V

Operating Ambient Temperature TAE temperature range –40 to 85 ºC

Maximum Junction Temperature TJ(max) 150 ºC

Storage Temperature Tstg –55 to 150 ºC

Selection Guide

Part Number Packing*

A8672EEGTR-T 7000 pieces per 13-inch reel

*Contact Allegro™ for additional packing options

Table of Contents

Specifications 2

Thermal Characteristics 3

Functional Block Diagram 3

Pin-out Diagram and Terminal List 4

Electrical Characteristics 5

Functional Description 7

Basic Operation 7

Output Voltage Selection 7

Switch On-Time and Switching Frequency 7

Valley Current Limit 8

Inductor Selection 8

Output Capacitor Selection 9

Input Capacitor Selection 9

Soft-Start and Output Overloads 10

Fault Handling and Reporting 12

Control Loop 14

Control Loop Design Approach 15

Thermal Considerations 18

Regulator Efficiency 19

Layout 20

Package Outline Drawing 21

Fixed Frequency High Current Synchronous Buck Regulator

With Fault Warnings and Power OK

A8672

Allegro MicroSystems, LLC

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

0.6 V

Ref

Control

Logic

Timer

Regulator

Comparator

Off

Timer

Soft Start

Period

and Hiccup

Driver

Enable

Bias

Regulator

Fault

Reporting

and

Shutdown

VDD UVLO

TSD

FB OV

VDD VIN

VREG

PGND

AGND

TON

BOOT

EN 5V LDO

Regulator

gm Amplifier

BIAS

Driver

Current

Amplifier

Overvoltage

Comparator

Hiccup

OV Ref

FB UV

TOT

FB OV

PAD

COMP

POKFB UV +

BIAS

ILIM

MODE

Undervoltage

Comparator

Offset

UV Ref

Ref

FAULT

Functional Block Diagram

Thermal Characteristics may require derating at maximum conditions, see application information

Characteristic Symbol Test Conditions* Value Unit

Package Thermal Resistance (Junction to Ambient) RθJA

Estimated, on 4-layer PCB based on JEDEC

standard 33 ºC/W

Package Thermal Resistance (Junction to Pad) RθJP 2 ºC/W

*Additional thermal information available on the Allegro website

Fixed Frequency High Current Synchronous Buck Regulator

With Fault Warnings and Power OK

A8672

Allegro MicroSystems, LLC

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

Terminal List Table

Number Name Function

1 AGND Analog ground. Connect to PGND at PAD of device. This pin should be used as the FB resistor divider

ground reference for optimal accuracy (see Typical Applications section circuit diagrams).

2,3,4,5,6 PGND Power ground. Connect to PAD of device.

7,8 VIN Power input to the drain of the internal high-side MOSFET. This pin must be locally bypassed (see Typical

Applications section circuit diagrams).

9 VDD

Power input for the control circuit and drive signals for the internal switching MOSFETs. This pin can be

either connected directly to VIN, or in applications where a low VIN voltage is used, it can be driven by a

separate power source to ensure adequate overdrive of the switching MOSFETs and control supply.

10 TON On-Time pin. The resistor connected between this pin and VIN defines the on-time of the regulator. This in

turn defines the switching frequency for a given output voltage.

11 VREG 5 V LDO regulator output and supply for internal control circuitry.

12 ¯

U ¯¯L

Open drain ¯

U ¯¯L

output. This pin is logic low if the on-time exceeds a certain value, if the LX node is

shorted to ground, or if the thermal shutdown threshold (TJ > 140°C) has been reached (see Fault Handling

and Reporting table).

13 POK Open drain Power Okay (power good) output. This pin is logic low if any fault (as defined in the Fault

Handling and Reporting table) occurs, other than an overtemperature condition (TJ > 140°C).

14 EN Enable pin. This pin is a logic input that turns the converter on or off. When EN > VENHI , the part turns on.

15 BOOT High-side gate drive supply input. This pin supplies the drive for the high-side switching MOSFET switch.

16,17,18,19,

20,21,22 LX The source of the internal high-side switching MOSFET. The output inductor and BOOT capacitor should be

connected to this pin (see Typical Applications section circuit diagrams).

23 BIAS Internal regulated bias supply for the control circuit and drives for switching MOSFETs (see Typical

Applications section circuit diagrams for recommended capacitors).

24 MODE

When pulled to the VREG supply via a 10 kΩ resistor, fixed continuous conduction mode (FCCM) is

maintained across the full load range. When pulled directly to GND, the switcher enters lower power mode

(LPM) at light loads.

25 ILIM Valley current limit setting. Connect a resistor to ground to set a voltage between 2.75 and 1.5 V that

corresponds to a valley overload current of between 9 and 3 A (typ).

26 SS

Soft-start ramp pin. The capacitor connected to this pin defines the rate of rise of the output voltage and

the effective inrush current. Soft-start also defines the hiccup shutdown period with either an overload or

overvoltage condition.

27 COMP Output of the error amplifier and compensation node. Connect a series R-C network from this pin to GND for

control loop regulation.

28 FB

Feedback input pin of the error amplifier. Connect a resistor divider from the converter output voltage node,

VOUT, to this pin to set the converter output voltage. This pin is also monitored for both output overvoltage

and undervoltage conditions (see Fault Handling and Reporting table for more details).

–PAD

Exposed pad of the package provides both electrical contact to the ground and good thermal contact to the

PCB. This pad must be soldered to the PCB for proper operation and should be connected to the ground

plane by through-hole vias (see Layout section for further details).

Pin-out Diagram PAD

COMP

ILIM

MODE

BIAS

VDD

TON

VREG

FAULT

POK

BOOT

AGND

PGND

VIN

Fixed Frequency High Current Synchronous Buck Regulator

With Fault Warnings and Power OK

A8672

Allegro MicroSystems, LLC

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

Continued on the next page…

ELECTRICAL CHARACTERISTICS1 Valid at TJ = –20°C to 125°C and VIN = 12 V; unless otherwise specified

Characteristics Symbol Test Conditions Min. Typ. Max. Unit

General

Input Voltage Range (Power) VIN 3 – 16 V

Input Voltage Range (Control) VDD 4.5 – 16 V

Input VIN Leakage Current Ileak VIN = 12 V, LX = GND – – 5 μA

Input VDD Quiescent Current IDD

VEN = 5 V, VFB = 1.2 V, no switching – – 3 mA

VDD = 16 V, VEN = 0 V – 1 10 µA

Feedback Voltage VFB 7.0 V ≤ VIN ≤ 16 V, VFB = VCOMP 0.594 0.600 0.606 V

Maximum Switching Frequency fsw(max) – 1000 – kHz

Minimum Switching Frequency fsw(min) – 200 – kHz

On-Time Tolerance Δton RTON = 60 kΩ –10 – 10 %

Maximum On-Time Period ton(max) 2.5 3.5 4.5 µs

Minimum On-Time Period ton(min) – 50 90 ns

Minimum Off-Time Period toff(min) – – 350 ns

High-Side MOSFET On-Resistance RDS(on)HS IDS = 0.2 A – 27 – mΩ

Low-Side MOSFET On-Resistance RDS(on)LS IDS = 0.2 A – 12 – mΩ

Soft Start Source Current2ISS(src) VSS > VSSPWM – –30 – µA

Soft Start Sink Current2ISS(snk) – 5 – µA

Soft Start Threshold VSSPWM VSS rising – 600 – mV

Soft Start Ramp Time1tSS CSS = 10 nF – 200 – µs

5 V LDO Regulator

Output Voltage VREG IREG = 0 to 30 mA, VIN > 6 V 4.75 5.00 5.25 V

Amplifier and Power Stage Gain

Feedback Input Bias Current2IFB VFB = 0.6 V – ±50 ±250 nA

Error Amplifier Open Loop Voltage

Gain1AVEA – 60 – dB

Error Amplifier Transconductance1gmCOMP 600 800 1000 µA/V

Error Amplifier Maximum Source/Sink

Current2ICOMP(max) VFB = VFB0 ±0.4 V – ±52 – µA

COMP Voltage to Current Gain1gmPOWER – 4 – A/V

Enable

Enable High Threshold VENHI 1.8 – – V

Enable Low Threshold VENLO – – 0.8 V

Enable Hysteresis VENHYS 150 250 – mV

Enable Current2IEN VEN = 3.3 V – 50 – µA

Fixed Frequency High Current Synchronous Buck Regulator

With Fault Warnings and Power OK

A8672

Allegro MicroSystems, LLC

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

ELECTRICAL CHARACTERISTICS1 (continued) Valid at TJ = –20°C to 125°C and VIN = 12 V; unless otherwise specified

Characteristics Symbol Test Conditions Min. Typ. Max. Unit

Power OK

Power Good Threshold (Rising) VPOK(HI)

Feedback voltage relative to reference voltage,

POK = high 92 95 98 %

Power Good Threshold (Falling) VPOK(LO)

Feedback voltage relative to reference voltage,

POK = high 107 110 113 %

Power Good Hysteresis VPOKHYS POK= low – 5 – %

POK Rising Delay tdPOK – 90 – µs

POK Output Voltage VPOK IPOK = 10 mA, POK asserted – – 500 mV

POK Leakage Current IPOK VPOK = 5.5 V, POK not asserted – – 1 μA

Fault Reporting

U ¯¯L

Overtemperature TOT Temperature rising – 140 – °C

U ¯¯L

Overtemperature Hysteresis TOTHYS Fault release = TOT – TOTHYS – 20 – °C

U ¯¯L

Output Voltage VFAULT IFAULT = 10 mA, fault asserted – – 500 mV

U ¯¯L

Leakage IFAULT VFAULT = 5.5 V, fault not asserted – – 1 µA

Protection

Undervoltage Threshold (Falling) VUVFB Feedback voltage relative to reference voltage – 75 – %

Undervoltage Hysteresis VUVHYS – 5 – %

Overvoltage Threshold (Rising) VOVFB Feedback voltage relative to reference voltage 115 120 125 %

Overvoltage Hysteresis VOVHYS – 5 – %

Valley Current Limit Voltage Range ILIMVR 1.0 – 2.75 V

Valley Current Limit ILIM

ILIM resistor = 169 kΩ 3.0 4.0 5.0 A

ILIM resistor = 249 kΩ 6.0 8.0 10.0 A

Hiccup On Period1tHICOC

Either valley current limit or overvoltage

condition reached – 50 – µs

Hiccup Shutdown Period1tHICSD

CSS = 10 nF, first shutdown event – 10 – ms

CSS = 10 nF, second and subsequent shutdown

events - 1.2 - ms

Pulse-by-Pulse Negative Valley

Current Limit INLIM FCCM selected –2.4 –1.9 –1.4 A

FB Overvoltage Duration tUVFB High-side MOSFET off, low-side MOSFET on – 50 – μs

High-Side MOSFET Protection Current IHIPRO LX node short-circuited to GND – 25 – A

High-Side MOSFET Protection Voltage VHIPRO LX node short-circuited to GND 450 650 850 mV

VDD Undervoltage Lockout (Rising) VUVLO – 4.2 4.45 V

VDD Undervoltage Lockout Hysteresis VUVLOHYS – 300 – mV

Thermal Shutdown Threshold TSD Temperature rising – 165 – °C

Thermal Shutdown Hysteresis TSDHYS Recovery = TSD – TSDHYS – 15 – °C

1Specifications throughout the junction temperature, TJ , range of –20ºC to 125ºC are assured by design and characterization unless otherwise noted.

2Positive current is into the node or pin, negative current is out of the node or pin.

Fixed Frequency High Current Synchronous Buck Regulator

With Fault Warnings and Power OK

A8672

Allegro MicroSystems, LLC

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

Characteristic Performance

100

0 1 2 3 4 5 6

Eﬃciency (%)

Load Current (A)

Eﬃciency at 300 kHz, Input Voltage = 12 V

OUT

= 5 V

OUT

= 3.3 V

OUT

= 2.5 V

OUT

= 1.2 V

Fixed connuous conducon mode

Inductor series: Pulse PG0642NL

100

0 1 2 3 4 5 6

Eﬃciency (%)

Load Current (A)

Eﬃciency at 500 kHz, Input Voltage = 12 V

OUT

= 5 V

OUT

= 3.3 V

OUT

= 2.5 V

OUT

= 1.2 V

Fixed connuous conducon mode

Inductor series: Pulse PG0642NL for V

OUT

= 1.2 V to 3.3 V,

Pulse PG0871 for V

OUT

= 5 V

Fixed Frequency High Current Synchronous Buck Regulator

With Fault Warnings and Power OK

A8672

Allegro MicroSystems, LLC

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

Functional Description

Basic Operation

At the beginning of a switching cycle, the high-side switch is

turned on for a duration determined by the current flowing into

TON. The magnitude of current is determined by the value of the

input voltage and the value of the on-time resistor (RTON, R1 in

the Typical Applications section circuit diagrams).

During the on-time period, the current builds up through the

inductor at a rate determined by the voltage developed across it

and the inductance value. When the on-time period elapses, the

output of an RS latch resets, turning off the high-side switch.

After a small dead-time delay, the low-side switch is turned on.

The current through the inductor decays at a rate determined

by the output voltage and the inductance value. The current is

sensed through the low-side switch and is compared to the cur-

rent demand signal. The current demand signal is generated by

comparing the output voltage (stepped down to the FB pin) with

an accurate reference voltage.

When the current through the low-side switch drops to the current

demand level, the low-side switch is turned off. After a further

dead-time delay, the high-side switch is turned on again, and the

process is repeated.

Output Voltage Selection

The output voltage (VOUT) of the converter is set by selecting the

appropriate feedback resistors using the following formula:

VOUT VFB IFB

1+ +

=R6

R6 R7

R6 + R7

(1)

where:

VFB is the reference voltage,

R6 and R7 are as shown in the Typical Applications section

circuit diagrams, and

IFB is the reference bias current.

It is important to consider the tolerance of the feedback resistors,

because they directly affect the overall setpoint accuracy of the

output voltage.

It is also important to consider the actual resistor values selected

and consider the trade-offs. High value resistors will minimize

the shunt current flowing through the feedback network, enhanc-

ing efficiency. However, the offset error produced by the refer-

ence bias current will increase, affecting the regulation. In addi-

tion, high value resistors are more prone to noise pick-up effects

which may affect performance. As some kind of compromise, it

is recommended that R7 be in the region of 10 kΩ.

Switch On-Time and Switching Frequency

The switching frequency of the converter is selected by choosing

the appropriate on-time. The on-time can be estimated to a first

order by using the following formula:

ton

VOUT 1

VIN

=fSW

(2)

where:

VOUT is the output voltage,

fSW is the switching frequency, and

VIN is the nominal input voltage.

To factor-in the effects of resistive voltage drops in the converter

circuit, the following formula can be used to produce a more

accurate estimate of what the on-time has to be for a required

switching frequency:

ton

VOUT + (RDS(on)LS + DCRL )

VIN + (RDS(on)LS – RDS(on)HS )

IOUT 1

=IOUT fSW

(3)

where:

RDS(on)LS is the low-side MOSFET on-resistance,

RDS(on)HS is the high-side MOSFET resistance, and

DCRL is the inductive resistance.

The switching frequency will vary slightly as the resistive voltage

drops in the circuit change, either due to temperature effects or to

input voltage variations.

Note that when selecting the switching frequency, care should

be taken to ensure the converter does not operate near either the

minimum on-time (50 ns) or the minimum off-time (250 ns).

Minimum on-times will typically occur in combinations of

maximum input voltage, minimum output voltage with minimum

load, and maximum switching frequency. Minimum off-times

will typically occur in combinations of minimum input voltage,

maximum output voltage with maximum load, and maximum

switching frequency.

Fixed Frequency High Current Synchronous Buck Regulator

With Fault Warnings and Power OK

A8672

Allegro MicroSystems, LLC

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

The ton from either of the above formulae can be used to deter-

mine the TON resistor value, RTON (R1 in Typical Applications

section circuit drawings):

RTON

ton – 8

×10–9

×10–12

(VIN – 0.67) – 500

(4)

Table 1 provides preferred resistor values for a given output

voltage at target switching frequencies of 500 kHz, 700 kHz, and

1 MHz:

Valley Current Limit

The Valley Current Limit ( ILIM

) threshold can be programmed to

any level between 9 and 3 A by selecting an appropriate resistor

(RLIM ) connected between the ILIM pin and ground. The resistor

can be selected either by using the following formula, or by using

the graph in figure 1 for the typical Valley Current Limit:

RLIM = (21.8 × ILIM ) + 79 (5)

where RLIM is in kΩ.

Inductor Selection

The main factor in selecting the inductance value is the ripple

current. The ripple current affects the output voltage ripple and

current limit. A reasonable figure of merit for the ripple current

(Iripp) is 25% of the maximum load. So for a maximum load of

6 A, the peak-to-peak ripple current should be 1.5 A.

The maximum peak-to-peak ripple current occurs at the maxi-

mum input voltage. To a reasonable approximation, the minimum

duty cycle can be found:

D(min) VOUT

VIN

(max)

(6)

The required (minimum) inductance can be found:

L(min) D(min)

VIN

–

VOUT

Iripp

fSW

(7)

Note that the inductor manufacturer tolerances on the inductance

value should be taken into account. This can be as high as ±30%.

It is recommended that gapped ferrite solutions be used as

opposed to powdered iron solutions. This is because powdered

iron cores exhibit relatively high core losses, especially at higher

switching frequencies. Higher core losses do have a detrimental

impact on the long term reliability of the component.

Inductors are typically specified at two current levels:

• Saturation Current (Isat) The worst case maximum peak cur-

rent should not exceed the saturation current and indeed some

margin should be allowed. The maximum peak current in an

inductor occurs during an overload condition where the circuit

operates in current limit. The typical valley current limit (ILIM)

is 8 A, with R4 = 249 kΩ. The peak current through the inductor

is effectively the valley current limit plus the ripple current:

Isat > ILIM + Iripp (8)

ILIM Resistor Value, RLIM (kΩ)

246810

300

250

200

150

100

Valley Current Limit (Typical), ILIM (A)

Figure 1: Valley Current Limit determination: value of external

resistor on ILIM pin versus valley current limit

Table 1: Recommended RTON Resistor Values

Switching Frequency, fSW

500 kHz 700 kHz 1 MHz

VOUT

(V)

RTON

(kΩ)

VOUT

(V)

RTON

(kΩ)

VOUT

(V)

RTON

(kΩ)

5.0 374 5.0 267 5.0 182

3.3 243 3.3 174 3.3 121

2.5 187 2.5 133 2.5 90.9

1.8 137 1.8 95.9 1.8 64.9

1.5 113 1.5 80.6 1.5 54.9

1.2 90.9 1.2 63.4 1.2 43.2

1.0 76.8 1.0 52.3 1.0 35.7

0.8 60.4 0.8 42.2 0.8 28.7

0.6 44.2 0.6 30.9 0.6 23.2

Fixed Frequency High Current Synchronous Buck Regulator

With Fault Warnings and Power OK

A8672

Allegro MicroSystems, LLC

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

• Rms Current (Irms) It is important to understand how the rms

current level is specified in terms of ambient temperature. Some

manufacturers quote an ambient whilst others quote a tempera-

ture that includes a self-temperature rise. For example, if an

inductor is rated for 85°C and includes a self-temperature rise of

25°C at maximum load, then the inductor cannot be safely oper-

ated beyond an ambient temperature of 60°C at full load.

The rms current through the inductor should not exceed the rat-

ing for the inductor, taking into account the maximum ambient

temperature. The maximum rms current is effectively the valley

current limit (ILIM) plus half of the ripple current:

Irms(max) > ILIM + Iripp / 2 (9)

A final consideration in the selection of the inductor is the series

resistance (DCR). A lower DCR will reduce the power loss and

enhance power efficiency. The trade-off in using an inductor with

a relatively low DCR is the physical size is typically larger.

Recommended inductor: PIMC065T-XXMN-11 (XX is value)

series manufactured by Cyntec or the PG0871 series manufac-

tured by Pulse Electronics. Table 2 provides preferred inductor

values for a given output voltage, 2 A output at target switching

frequencies of 500 kHz, 700 kHz, and 1 MHz.

Output Capacitor Selection

The output capacitor has two main functions: influence the con-

trol loop response (see the Control Loop section), and determine

the magnitude of the output voltage ripple.

The output voltage ripple can be approximated to:

Vripp

Iripp

COUT

fSW

(10)

where:

Iripp is the peak-to-peak current in the inductor (see the Inductor

Selection section), and

COUT is the output capacitance.

It is recommended that ceramic capacitors be used, taking into

account: size, cost, reliability, and performance. It is imperative

that ceramic type X5R or X7R are used. On no account should

Y5V, Y5U, Z5U, or similar be used, because the capacitance

tolerance and the temperature stability is very poor.

There is generally no need to consider the effects of heating

caused by the ripple current flowing into the output capacitor.

This is because the equivalent series resistance (ESR) of ceramic

capacitors is extremely low.

When using ceramic capacitors, it is important to consider the

effects of capacitance reduction due to the E-field. To avoid this

voltage bias effect, it is recommended that the capacitor rated

voltage be at least twice that of the actual output voltage. So for

example, with a 5 V output, the capacitor should be rated to 10 V.

For the majority of applications, a capacitance of 200 µF is rec-

ommended to ensure good transient response.

Input Capacitor Selection

The function of the input capacitor is to provide a low impedance

shunt path for the current drawn by the A8672 when the high-

side switch is on. This minimizes the amount of ripple current

reflected back into the source supply. This reduces the potential

for higher conducted electromagnetic interference (EMI).

In a correctly designed system, with a quality capacitor posi-

tioned adjacent to the VIN pin and the PGND pin, this capacitor

should supply the high-side switch current minus the average

input current. During the high-side switch off-cycle, the capacitor

is charged by the average input current.

Table 2: Recommended Inductor Values

Switching Frequency, fSW

500 kHz 700 kHz 1 MHz

VOUT

(V)

(µH)

VOUT

(V)

(µH)

VOUT

(V)

(µH)

5.0 3.7 5.0 2.6 5.0 2.2

3.3 3.7 3.3 2.2 3.3 1.7

2.5 2.6 2.5 1.7 2.5 1.2

1.8 2.2 1.8 1.7 1.8 1

1.5 1.7 1.5 1.2 1.5 1

1.2 1.2 1.2 1 1.2 0.8

1.0 1.2 1.0 1 1.0 0.54

0.8 1 0.8 0.8 0.8 0.47

0.6 0.8 0.6 0.47 0.6 0.47

Fixed Frequency High Current Synchronous Buck Regulator

With Fault Warnings and Power OK

A8672

Allegro MicroSystems, LLC

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

The effective rms current that flows in the input filter capaci-

tor is:

Irms

VOUT

IOUT

VIN

VIN – 1

1/2

(11)

The amount of ripple voltage (Vripp ) that appears across the

input terminals (VIN with respect to GND) is determined by the

amount of charge removed from the input capacitor during the

high-side switch conduction time. If a capacitor technology such

as an electrolytic is used, then the effects of the ESR should also

be taken into account.

The amount of input capacitance (CIN) required for a given ripple

voltage can be found:

CIN

Irms ton

Vripp

= (12)

where:

ton is the on-time of the high-side switch (see the Switch On-

Time and Switching Frequency section; note that maximum ton

occurs at minimum input voltage), and

CIN is the input filter capacitance.

As mentioned in the Output Capacitor Selection section, the

effects of voltage biasing should be taken into account when

choosing the capacitor voltage rating. If ceramic capacitors are

being used, then there is generally no need to consider the effects

of ESR heating.

Soft-Start, Output Overloads and Overvoltages

The soft-start routine controls the rate of rise of the reference

voltage, which in turn controls the FB pin, and thereby the out-

put voltage (VOUT )(see figure 2). This function minimizes the

amount of inrush current drawn from the input voltage (VIN ) and

potential voltage overshoot on the output rail (VOUT ).

A soft-start routine is initiated when the enable pin (EN) is

high, no overvoltage exists on the output, the thermal protec-

tion circuitry is not activated, and VIN is above the undervoltage

threshold. Immediately after EN goes high, the soft-start capaci-

tor is charged via an internal 10 µA source and PWM switching

action occurs.

The Soft-Start Ramp Time, tss , can be found from the following

formula:

tSS

0.6

×10

–6

= (13)

where CSS is C11 in the Typical Application circuit diagrams.

During the Soft-Start Ramp Time (see A in figure 2), the refer-

ence is ramped from 0 up to 0.6 V, and the output voltage ( VOUT )

tracks the reference voltage. The POK flag is held low until the

output voltage reaches 95% (typical) of the target voltage and a

delay of 90 µs (typical) occurs.

When an output overcurrent event occurs, the regulator imme-

diately limits the valley current at a constant level on a pulse-by

pulse basis. The output voltage will tend to fold back, depending

on how low the output impedance is. When the output voltage

drops below 90% (typical) of the target voltage, the POK flag

goes low. If the overload occurs for shorter than the Hiccup On

Period (<50 µs; B in figure 2), the output will automatically

recover to the target level. If the overload occurs for longer than

the Hiccup On Period (>50 µs; C in figure 2), the regulator

will shut down, the soft-start capacitor will be discharged, and

(assuming no other fault conditions exist and the enable pin is

still high) the regulator will be delayed by the Hiccup Shutdown

Period (D in figure 2).

The Hiccup Shutdown Period ensures that prolonged overload

conditions do not cause excessive junction temperatures to occur.

After the Hiccup Shutdown Period has elapsed, the output volt-

age is again brought up, controlled by the soft-start function.

However, if the overload condition still exists and still remains

after the Soft-Start Ramp Time has elapsed, the regulator will

shut down and the process will repeat until the fault is removed.

The Hiccup Shutdown Period is determined by the discharge of

the soft-start capacitor to zero voltage. During normal operation,

the soft-start capacitor CSS is charged to 5 V. In the event of an

overload where the Hiccup On Period exceeds 50 µs, the length

of the first Hiccup Shutdown Period event can be found:

tSS(first) = (CSS × 5) / 5 × 10–6 (14)

So for example, with a CSS of 10 nF, the first Hiccup Shutdown

Period event is 10 ms.

Assuming the overload is still applied, the length of the second

and subsequent Hiccup Shutdown Periods depends on the load

resistance applied and how far the soft-start capacitor is charged

before switching action occurs. The Hiccup Shutdown Period is

approximately ten times the length of the switching period.

The overvoltage protection operates in a similar way to the over-

current protection using the same Hiccup Circuitry.

Fixed Frequency High Current Synchronous Buck Regulator

With Fault Warnings and Power OK

A8672

Allegro MicroSystems, LLC

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

Figure 2: Operation of the Soft-Start Function

Enable (EN)

Soft-Start (SS)

Output Voltage

Load Current

0 V

power OK (POK)

0 V

0 A

0 V

Soft-Start Ramp Time

<50 µs

90 µs

POK Delay

90 µs

POK Delay

90 µs

POK Delay

Valley Current Limit

Maximum load

>50 µs

Hiccup On

Period

Hiccup On

Period

Target output voltage

95% of

Target

Soft-Start Ramp Time

Maximum load

Target output voltage

Hiccup Shutdown

Period

A A

B C

95% of

Target 90% of

Target

Although the A8672 is optimized for ceramic output capacitors,

large value electrolytic capacitors can be used where either spe-

cial hold-up, or power sequencing is required. Note the guidelines

for selecting large value capacitors in the Control Loop section.

When selecting larger-value output capacitors, it is important that

the soft-start period is appropriately scaled to take into account

the charging of these capacitors. For example, if the soft-start is

optimized for a 200 µF ceramic output capacitor and a 2000 µF

capacitor is added to the output, there is every possibility that the

converter will remain in an overload condition after the soft-start

and the Hiccup On Period have elapsed. This mode of operation

could prevent the output ever reaching the target output voltage.

To demonstrate the above, consider the following example: a

regulator programmed for a 5 V output, 200 µF output capacitor,

and a soft-start time-off of 1 ms.

Assume there is no load current draw until 5 V is reached. At

start-up, the regulator has to charge the output capacitor. From

C×V = I×t , the charging current into the capacitor is:

Fixed Frequency High Current Synchronous Buck Regulator

With Fault Warnings and Power OK

A8672

Allegro MicroSystems, LLC

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

I = 200 µF × 5 / 1 ms = 1 A

Now if a 2000 µF capacitor is added to the output, the capacitor

would require a charge current of:

I = 2000 µF × 5 / 1 ms = 10 A

In this condition, the A8672 would run into the pulse-by-pulse

current limit, limiting the average charge current to 8.75 A (typ).

An average current of 8.75 A, assumes a valley current limit of

8 A and a half ripple current of 0.75 A. This means that after the

soft-start delay of 1 ms, the output voltage would only be charged

to:

V = 8.75 A × 1 ms / 2000 µF = 4.375 V

After the soft-start period is completed, the output capacitor

would be charged for a short duration, defined by the Hiccup On

Period. Then the converter would shut down and, after the Hiccup

Shutdown Period had elapsed, would enter the start-up process

again. This mode is highly undesirable and a more appropriate

soft-start capacitor should be selected.

The effects of adding an output capacitor with too-large value

would be a condition similar to starting-up into a short-circuit

across the output; where the regulator enters a hiccup mode of

operation.

If the output of the A8672 is pre-biased at start-up, the switcher

will remain in a high impedance state until the soft-start has

reached the feedback voltage ( VFB ) amplitude. This avoids the

output voltage being discharged. After the soft-start threshold

exceeds the FB pin voltage, PWM switching action occurs and

the output voltage is brought up under the control of the soft-start

circuit (see Figure 3).

Note that when the regulator is turned off, it enters a high

impedance mode (all switches off) and if the output voltage is

discharged it is done so by the load (at A in figure 3). If the load

does not discharge the output, the output voltage remains in a

pre-biased condition.

Fault Handling and Reporting

Table 3 describes the action taken for particular faults including

the status of the ¯

and POK flags.

95% of

Target

90 µs

POK Delay

Soft-start voltage

less than feedback

voltage (VFB)

No PWM switching

Enable (EN)

Soft-Start/ Hiccup (SS)

Output Voltage

0 V

Power OK (POK)

0 V

Soft-Start Ramp Time

Target output voltage

Pre-biased output voltage

Feedback voltage (VFB)

brought-up under

soft-start control

PWM switching

Load pulls

the output

voltage low

Figure 3: Operation of the Soft-Start Function with Pre-Biasing

Fixed Frequency High Current Synchronous Buck Regulator

With Fault Warnings and Power OK

A8672

Allegro MicroSystems, LLC

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

Table 3: Fault Handling and Reporting

A8672 Condition Comments POK

Flag

¯¯¯U ¯¯L

Flag Action After Fault

95% (typ) < VFB < 110% (typ) Normal operation. High High –

VFB < 95% (typ)

During start-up, the feedback voltage (VFB)

is increased under control of the soft-start

circuit.

Low High –

VFB < 90% (typ)

After start-up, if an overload occurs for less

than the Hiccup On Period (50 μs), the

regulator maintains switching operation.

Low High Auto-recovery

After start-up, if an overload occurs for greater

than the Hiccup On Period (50 μs), the

regulator turns off for Hiccup Shutdown Period

and then initiates a soft-start cycle.

Low High Auto-restart under control of soft-start

VFB > 120% (typ)

High-side MOSFET turns off and low-side

MOSFET switching is maintained. If the

feedback voltage (VFB) drops to <75% of

target VFB (undervoltage condition) within

50 μs (Hiccup On Period), a soft-start is

performed.

Low High Soft-start is performed

If the feedback voltage (VFB) does not drop to

<75% of target VFB within 50 μs (Hiccup On

Period), the low-side MOSFET is turned off

and the high-side MOSFET remains off for the

duration of the Hiccup Shutdown Period.

Low High

After the Hiccup Shutdown Period, a soft start

is performed; then if the fault is not present,

normal operation occurs, otherwise the cycle

is repeated

VDD < 4.0 V (typ) Regulator immediately turns off. Low High Auto-restart under the control of the soft-start

circuit, when VIN > 4.2 V (typ)

TJ > 140°C (typ)

Regulator keeps operating until TSD

threshold is reached (TJ > 165°C (typ)), and

then ¯

¯¯¯U ¯¯L

goes high.

High Low –

TJ > 165°C (typ) Regulator immediately turns off. Low Low Auto-restart under the control of the soft-start

circuit, when TJ < 145°C

LX pin shorted to GND

The voltage across the series switch

is monitored. If the voltage exceeds

500 mV (typ), the regulator latches off.

Low Low

Restart by cycling either the Enable pin, EN,

or the input voltage pin, VIN, low then high;

restarts under the control of the soft-start

circuit

ton > 3.5 μs (typ) Regulator immediately turns off. Low Low

Restart by cycling either the Enable pin, EN,

or the input voltage pin, VIN, low then high;

restarts under the control of the soft-start

circuit

Any of the internal bias

(BIAS), VREG regulator, or

bootstrap supply voltages

are below the respective

undervoltage threshold

Regulator immediately turns off. Low High

Auto-restart under the control of the soft-start

circuit when the low voltage rises above the

respective UVLO threshold: BIAS, VREG, or

BOOT

Fixed Frequency High Current Synchronous Buck Regulator

With Fault Warnings and Power OK

A8672

Allegro MicroSystems, LLC

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

Control Loop

To a first order, the small-signal loop can be modeled as shown

in Figure 4. The control loop can be broken into two sections:

power stage and error amplifier.

Power Stage

The power stage includes the output filter capacitor (COUT),

the equivalent load (RLOAD), and: the inner current loop, PWM

modulator, and power inductor, which together are modeled as

a transconductance amplifier with a gain of 4 A / V. The signal

Vc , supplied to the power stage, is effectively the load current

demand signal. This signal effectively controls the valley current

through the inductor; the higher the load the larger the Vc signal.

To simplify matters, we will assume this signal controls the aver-

age current through the inductor as opposed to the valley current.

The effective DC gain of the power stage, without the output

capacitor and load resistor, is 4 A / V, where the signal Vc is lim-

ited to the range 0.36 to 2.75 V. The DC current is converted into

VOUT as the current flows into the load resistor. The overall DC

gain of the power stage is given as VOUT / Vc (see figure 5). At full

load, the Vc signal would be 6 / 4 = 1.5 V.

From a small-signal point of view, the power inductor behaves

like a current source; the inductor can be ignored as far as the

bandwidth of the loop is concerned. The output capacitor inte-

grates the ripple current through the inductor, effectively forming

a single pole with the output load.

The power stage pole can be found:

fp(PS)

� × COUT × RLOAD

(15)

It can be seen that as the load changes, the position of the power

pole changes in the frequency domain. This may seem like an

issue in terms of where to optimize the loop, however, the change

in load also changes the gain in the power stage, thus compensat-

ing for this effect. Figure 5 illustrates how the loop response of the

power stage changes with a varying load. The position of fp1 and

G1 is one solution, fp2 and G2 is another solution, and so forth.

As the value of RLOAD increases (reducing load), the power

pole moves down in frequency and the DC gain increases.

Generally speaking this is not a problem, because even if the

pole approaches the low frequency pole produced by the error

amplifier, there is still plenty of gain in the system. In this case,

while the phase margin may be greatly reduced, even to a value

approaching 0°, because there is sufficient DC gain in the loop it

can be shown from Nyquist theory that the system is condition-

ally stable. The phase margin must be considered only at the 0 dB

crossover frequency.

Figure 4: 1st Order Model of the Small-Signal Control Loop

(see Typical Applications section circuit diagrams for component

references)

Figure 5: Power Stage DC Gain Characteristic

COUT

RLOAD

COMP

C11

C12 R5

FB Pin

Power Stage

VOUT

Error Amplifier

Amplifier

gm =

4 A

gm =

800 µA

Ref

VOUT

RLOAD

increasing

Gain

(dB)

1fp2 f

Frequency

Fixed Frequency High Current Synchronous Buck Regulator

With Fault Warnings and Power OK

A8672

Allegro MicroSystems, LLC

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

It is recommended that X5R/ X7R ceramic capacitors be used,

however, large-value capacitors such as electrolytic types can

be used. Care should be taken when selecting the value of an

electrolytic capacitor. As this capacitance is increased, the power

pole is pushed to such a low frequency that the gain can fall off

sufficiently to cause a loop instability.

If using an electrolytic capacitor, consideration should also be

given to the equivalent series resistance (ESR) value, because

this introduces a zero with the capacitance itself. It is important

to use a low-ESR type capacitor. It should be noted that capacitor

manufacturers usually quote an ESR which is a maximum at a

particular frequency (such as 100 kHz) and temperature (20°C).

The ESR does vary with frequency and temperature, plus there

are tolerance effects as well. If the zero produced by the ESR

of the output capacitor features in the control loop, it is strongly

recommended that a large tolerance be allowed. If necessary, the

high frequency pole in the error amplifier can be used to negate

the effects of this pole (see the Error Amplifier section).

Error Amplifier

The error amplifier is a transconductance amplifier. The DC

gain of the amplifier is 60 dB (1000) and, with a gm value of

800 µA / V, the effective output impedance of the amplifier can be

modeled as:

RO1.25 MΩ

1000

= =

800

×10–6

(16)

The transconductance amplifier has a high DC gain to ensure

good regulation. The gain is rolled off with a single pole posi-

tioned at a low frequency. A zero is positioned at higher frequen-

cies to cancel the effects of the main power stage pole. A second

pole can be introduced which should have minimal effect on the

loop response, but is useful for reducing the effects of switching

noise.

The low frequency pole occurs at:

fp1(EA)

� × R

× C

(17)

The zero occurs at:

fz(EA)

� × R

× C

(18)

The high frequency pole occurs at:

fp2(EA)

� × R

× C

(19)

The potential divider formed by R6 and R7 in figure 4 effec-

tively introduces a DC offset to the loop. This can be found from:

VFB / VOUT .

Control Loop Design Approach

There are many different approaches to designing the feedback

loop. The optimum solution is to select a target phase margin

and bandwidth for optimum transient response. This typically

requires either simulation software or detailed Bode plot analysis

to generate a solution.

The particular approach described here derives a solution through

a series of basic calculations. This approach aims for a simple

–20 dB/decade roll off, from the low frequency error amplifier

pole (fp1(EA) ) to the 0 dB crossover point (fcross

). The 0 dB cross-

over point is aimed at a thirteenth of the switching frequency

(fSW). This factor is chosen as a compromise between good band-

width and minimizing the phase lag introduced by the second

power pole, which occurs between 1/3 and 1/6 of the switching

frequency. In theory, this should introduce a phase margin of

90°, however, in practice it will be slightly less, due to the effects

of the second power pole. The introduction of this second pole

reduces the phase margin below 90°.

It is recommended that the error amplifier high frequency pole

should be positioned one octave below the switching frequency.

This provides some attenuation of the switching ripple whilst

having minimum impact on the closed loop response.

To achieve a –20 dB/decade roll off, the error amplifier zero is

positioned to coincide with the power pole at maximum load.

Figure 6 illustrates the power stage gain, the error amplifier gain,

and then the combined overall loop response (power stage and

error amplifier).

Fixed Frequency High Current Synchronous Buck Regulator

With Fault Warnings and Power OK

A8672

Allegro MicroSystems, LLC

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

Design Example

Assuming: output voltage (VOUT) = 1.2 V, maximum load (IOUT)

= 6 A, switching frequency (fSW ) = 500 kHz, and output capaci-

tance (COUT) = 200 µF. Analyze the response at full load.

1. Crossover frequency:

38.5 kHz

fcross 13 == 500

×103

(20)

2. Overall DC gain (refer to figure 6):

20 Log10 V

=VOUT

DC gain (PS)

(21)

=60 dB+20 Log10 V

OUT

VFB

DC gain (EA)

(22)

20 Log10 Vc

=VOUT 60 dB+20 Log10 VOUT

VFB

60 dB20 Log10

DC gain (All)

DC gain (PS) + DC gain (EA)

52 dB

1.2

1.5

0.6

1.2

20 Log10

(23)

Note: With a power stage gain of 4 A / V and a load of 6 A, the

corresponding Vc = 6 / 4 = 1.5 V.

3. With a 38.5 kHz crossover and a 20 dB /decade increase

in gain, at what frequency does the gain reach 52 dB? The

–20 dB / decade roll off can be described as a single pole with this

transfer function for magnitude (G):

� × f × RC (24)

Figure 6: Power Stage, Error Amplifier, and Combined Overall Control Loop Response

Gain

(dB)

Gain

(dB)

Gain

(dB)

fp(PS)

fp1(EA)fp2(EA)

fz(EA)

fcross

–20 dB / decade

Frequency

Power Stage

Error Amplifier

Overall Loop

DC gain (PS)

DC gain (EA)

DC gain (All)

Fixed Frequency High Current Synchronous Buck Regulator

With Fault Warnings and Power OK

A8672

Allegro MicroSystems, LLC

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

3a. We know that at 38.5 kHz the gain is 0 dB (1). Therefore the

constant RC can be worked out:

� × 38.5

×103

=4.13 ×10

–

(25)

3b. A magnitude of 52 dB requires a gain of 398. The error ampli-

fier pole (fp1(EA) ), the frequency at which 398 is reached, is:

fp1(EA)

96.8 Hz

� × 4.13 ×10

–

398

(26)

So the overall loop response objective is shown in figure 7.

4. Select the RC components.

4a. The error amplifier pole (fp1(EA) ) occurs at 96.8 Hz. There-

fore, C11 can be found:

� × 1.25 ×10

96.8

C11

� × RO ×

fp1(EA)

1.3 nF

(27)

The nearest preferred value is 1.5 nF.

4b. The power pole (fp(PS) ) can be found, because the output

capacitor (COUT) and maximum load (RLOAD) are known:

�

0.2

200

×10

–6

fp(PS)

� × RLOAD × COUT

3979 Hz

(28)

4c. The error amplifier zero (fz(EA)

) also occurs at 3.979 kHz to

cancel the effects of the power pole. Therefore, as C11 is known,

R5 can be found:

�

1.5 ×10

–9 × 3979

� × C11 ×

fp(PS)

26.67 kΩ

(29)

Nearest preferred value = 27 kΩ.

4d. The error amplifier high frequency pole (fp2(EA) ) is set an

octave below the switching frequency. Therefore, C12 can be

found:

�

×10

3 × (500

×10

3 / 2)

C12

� × R5 ×

(

fSW /2)

24 pF

(30)

Nearest preferred value = 22 pF.

4e. Using the above compensation component selection tech-

nique, table 4 provides preferred component values for a given

output voltage, 6 A output, at target switching frequencies of

500 kHz, 700 kHz, and 1 MHz.

Table 4: Recommended R5 and C11 Values

Switching Frequency, fSW

500 kHz 700 kHz 1 MHz

VOUT

(V)

(kΩ)

(nF)

VOUT

(V)

(kΩ)

(nF)

VOUT

(V)

(kΩ)

(nF)

5.0 110 1.5 5.0 162 1.0 5.0 240 0.68

3.3 75 1.5 3.3 110 1.0 3.3 160 0.68

2.5 56 1.5 2.5 82 1.0 2.5 120 0.68

1.8 39 1.5 1.8 62 1.0 1.8 91 0.68

1.5 33 1.5 1.5 51 1.0 1.5 75 0.68

1.2 27 1.5 1.2 39 1.0 1.2 59 0.68

1.0 22 1.5 1.0 33 1.0 1.0 51 0.68

0.8 18 1.5 0.8 27 1.0 0.8 39 0.68

0.6 13 1.5 0.6 20 1.0 0.6 20 0.68

fcross

38.5

–20 dB

decade

Overall Loop Response, Gain (dB)

0.0968

52 fp1(EA)

fp(PS), fz(EA)

Frequency (kHz)

Figure 7: Design Example Objective: overall control loop response

(power stage and error amplifier)

Fixed Frequency High Current Synchronous Buck Regulator

With Fault Warnings and Power OK

A8672

Allegro MicroSystems, LLC

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

Thermal Considerations

For a given set of conditions, the junction temperature of the

A8672 can be estimated by carrying out a few calculations. This

is important to ensure an adequate safety margin with respect to

the maximum junction temperature (150°C) to enhance reliabil-

ity. This exercise also helps to understand the overall efficiency

of the regulator.

The general approach is to work out what thermal impedance

(RθJ-A) is required to maintain the junction temperature at a given

level, for a particular power dissipation. It should be noted that

this process is usually iterative to achieve the optimum solution.

The following steps can be used as a guideline for determining a

suitable thermal solution. First, estimate the maximum ambient

temperature (TA ) of the application. Second, define the maximum

junction temperature (TJ ). Note that the absolute maximum is

150°C. Third, determine the worst case power dissipation. This

will typically occur at maximum load and minimum VIN.

Design Example

Assuming: input voltage (VIN

) = 12 V, output voltage (VOUT) =

1.2 V, maximum load (IOUT) = 6 A, switching frequency (fSW )

= 500 kHz, target junction temperature (TJ) ≤ 125ºC, maximum

ambient temperature (TA ) = 85°C, and inductive resistance

(DCRL) = 6.7 mΩ.

1. The main power loss contributors are calculated separately:

• Switch static losses

a. Estimate the RDS(on) of the high-side switch at the maximum

target junction temperature:

=125 – 25

200

20 × 10

–3

=0.03 Ω

=TJ – 25

RDS(on)HS(TJ) RDS(on)HS(25C) 1

(31)

where RDS(on)HS(25C) is the RDS(on)HS value that can be found

from the Electrical Characteristics table in this datasheet.

b. Estimate the RDS(on) of the low side switch at the given junc-

tion temperature:

=125 – 25

200

8 × 10

–3

=0.012 Ω

–

RDS(on)LS(TJ) RDS(on)LS(25C) 1

(32)

where RDS(on)LS(25C) is the RDS(on)LS value that can be found from

the Electrical Characteristics table in this datasheet.

c. Estimate the duty cycle (D) by applying equation 3 (ton ):

1.2 + (0.012 + 0.0067 )

0.11

12 + (0.012 – 0.03 ) 500 103500 103

VOUT + (RDS(on)LS + DCRL )

VIN + (RDS(on)LS – RDS(on)HS )

IOUT 1

IOUT fSW

fSW

D ton

× fSW

(33)

d. The high side static loss can be determined:

=62 × 0.11

× 0.03

=0.119

PstaticHI =I

OUT

× D

× RDS(on)HS(TJ)

(34)

e. The low side static loss can be determined:

=62 × (1 – 0.11)

× 0.012

=0.385

PstaticLO =I

OUT

× 1

– D

× RDS(on)LS(TJ)

(35)

• Switching losses The combined turn on and turn off losses for

both switches are calculated as:

× 6

×10 –9 × 500 ×103 × 2

=0.216 W

Pswitch

VIN

× I

OUT

× 6

×10 –9 × fSW × 2

(36)

Fixed Frequency High Current Synchronous Buck Regulator

With Fault Warnings and Power OK

A8672

Allegro MicroSystems, LLC

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

• Recirculation diode losses The recirculation diode losses

(low-side switch) are calculated as:

0.8 × 6

× 6

×10 –9 × 500 ×103

=0.014 W

Precirc

0.8 × I

OUT

× 6

×10 –9 × fSW

(37)

• Diode transit losses The recirculation diode losses (low-side

switch) are calculated as:

12 × 6

× 3

×10 –9 × 500 ×103

=0.108 W

Ptransit

VIN × I

OUT

× 3

×10 –9 × fSW

(38)

• BIAS losses The supply bias losses are calculated as:

0.24 W

Pbias

VIN × 20

× 10 –3

(39)

2. The total losses in the A8672 can be estimated:

Ptotal = PstaticHI + PstaticLO + Pswitch + Precirc + Ptransit + Pbias (40)

= 0.119 + 0.385 + 0.216 + 0.014 + 0.108 + 0.24

= 1.082 W

3. The thermal impedance required for the solution can be found:

RθJA

TJ – TA

Ptotal

125 – 85

1.082

= 37 °C/W

(41)

For this particular solution, a high thermal efficiency board is

required to ensure the junction temperature is kept below 125°C.

It is recommended to use a PCB with at least four layers. The

A8672 should be mounted onto a thermal pad. A number of vias

should connect the thermal pad to at least one of the internal lay-

ers and the bottom side of the PCB. Both of these layers should

be a ground plane. See the Layout section for more information.

Regulator Efficiency

The overall regulator efficiency can be determined by including

the inductor loss. In the above thermal characteristics example,

the inductor resistance, DCRL = 6.7 mΩ. Therefore the inductor

power loss can be found::

PL DCRL × I

OUT

0.0067 × 62

= 0.241 W

(42)

The overall regulator efficiency can be found:

VOUT × IOUT

(VOUT × IOUT ) + Ptotal+ PL

1.2 × 6

(1.2 × 6) + 1.082 + 0.241

= 84.5 %

(43)

Fixed Frequency High Current Synchronous Buck Regulator

With Fault Warnings and Power OK

A8672

Allegro MicroSystems, LLC

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

Layout

Although the power dissipation in the A8672 is very low, it is rec-

ommended that the thermal pad of the device should be soldered

to an appropriate pad on the printed circuit board (PCB) to help

minimize the junction temperature and enhance the efficiency.

The PCB pad should in turn be connected to multiple ground

planes by several thermal vias. As a suggestion, the following

could be used: twenty vias, arranged in 5 rows of 4, with diam-

eter 0.25 mm and spaced (pitch) 0.6 mm apart. The PCB pad not

only acts as a thermal connection, but also forms the star connec-

tion for the grounding system.

Figure 8 illustrates the key objectives in the grounding system.

The filtering capacitors (C1 through C4, and C6 through C9)

should be connected as close as possible to the respective pins.

The ground connections for each of the capacitors should be

returned directly to the star connection (PCB pad). Again, these

connections should be as short as possible. Both the PGND and

AGND connections should connect directly to the PCB pad to

form the star connection.

The ground return connection for the feedback resistor should be

Kelvin-connected directly back to the star ground. Note: To avoid

voltage offset errors in the output voltage, the feedback resistor

should not be connected to the filter capacitor or load grounds

returns.

The support components (C10, C11, and C12), which are ground

referenced, should be connected together locally and then

returned directly to the star connection. Again, this ground should

not pick-up any of the filter capacitors or load ground returns.

Due to the high impedance nature of the COMP node, it is

important to ensure the compensation components are connected

as close as possible. The feedback trace from R6 and R7 to the

FB pin is also a high impedance input and should be as short as

possible and be placed well away from noisy connections such

as LX. It is recommended to keep any ground planes well away

from the LX node to avoid any potential noise coupling effects.

Figure 8: Layout Considerations for Mounting the A8672

A8672

Ground Planes (internal planes and bottom surface of PCB)

Thermal Vias

A8672 Support

Components

Local ‘quiet’

Ground Trace

C11

PGND

Thermal Pad

PCB

Pad

VREG

VIN

BIAS

C12

C10

R5 COMP

AGND

C1 C2

C6 C7

Fixed Frequency High Current Synchronous Buck Regulator

With Fault Warnings and Power OK

A8672

Allegro MicroSystems, LLC

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

Package EG, 28-Contact QFN

ATerminal #1 mark area

BExposed thermal pad (reference only, terminal #1

identifier appearance at supplier discretion)

Concept Drawing For Reference Only; not for tooling use

(reference JEDEC MO-220WGHD-3 except for contact length)

Dimensions in millimeters

Exact case and lead configuration at supplier discretion within limits shown

CReference land pattern layout (reference

IPC7351 QFN50P400X500X080-29M);

All pads a minimum of 0.20 mm from all adjacent pads; adjust as

necessary to meet application process requirements and PCB layout

tolerances; when mounting on a multilayer PCB, thermal vias at the

exposed thermal pad land can improve thermal dissipation (reference

EIA/JEDEC Standard JESD51-5)

PCB Layout Reference View

0.50 BSC

4.00 BSC

5.00 BSC

0.75 ±0.05

0.25

0.40±0.10

0.30

0.20 MIN 0.50

0.90

5.00

4.00

3.65

2.65

3.65

C0.08

28× SEATING

PLANE

DCoplanarity includes exposed thermal pad and terminals

–0.07

+0.05

Fixed Frequency High Current Synchronous Buck Regulator

With Fault Warnings and Power OK

A8672

Allegro MicroSystems, LLC

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

For the latest version of this document, visit our website:

www.allegromicro.com

Revision Date Change

1 April 16, 2014 Revised Selection Guide

2 December 5, 2016 Updated product status to Discontinued

3 July 5, 2018 Corrected Package Drawing lead dimensions (page 22); minor editorial updates.

Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to

permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that

the information being relied upon is current.

Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of

Allegro’s product can reasonably be expected to cause bodily harm.

The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its

use; nor for any infringement of patents or other rights of third parties which may result from its use.

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