®
Alt er a Cor pora t ion 1
ACEX 1K
Programmable Logic Device Family
May 2003, ver. 3.4 Data Sheet
DS-ACEX-3.4
Development
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Tools
Features... ■Programmable logic devices (PLDs), providing low cost
system-on-a-programmable-chip (SOPC) integration in a single
device
– Enhanced embe dded array for imp l ementing megafuncti o ns
such as efficient memory and specialized logic functions
– Dual-port capability with up to 16-bit width per embedded array
block (EAB)
– Logic array for general logic functions
■High density
– 10,000 to 100,000 typical gates (see Table 1)
– Up to 49,152 RAM bits (4,096 bits per EAB, all of which can be
used with out red ucin g logi c capacity)
■Cost-efficient programmable architecture for high-volume
applications
– Cost-optimized process
– Low cost solution for high-performance communications
applications
■System-le vel features
– MultiVoltTM I/O pins can drive or be driven by 2.5-V, 3.3-V, or
5.0-V de vice s
– Low power consumption
– Bidirectional I/O performance (setup time [tSU] and clock-to-
output delay [tCO]) up to 250 MHz
– Fully compliant with the peripheral component interconnect
Special Interest Group (PCI SIG) PCI Local Bus Specification,
Revision 2.2 for 3.3- V ope ration at 3 3 M Hz or 66 MHz
■Extend e d temp er a tur e range
Table 1. ACEXTM 1K Device Features
Feature EP1K10 EP1K30 EP1K50 EP1K100
Typical gates 10,0 00 30,00 0 50,00 0 100,0 00
Maximum s yst em gat es 56,0 00 119, 000 199, 000 257,0 00
Logic elements (LEs) 576 1,728 2,880 4,992
EABs 3 6 10 12
Total RAM bit s 12,2 88 24,57 6 40,96 0 49,152
Maximum us er I /O pins 136 171 249 333
2Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
...and More
Features
– -1 speed grade dev ices are comp lian t with PCI Local Bus
Specification, Revision 2.2 for 5.0-V operation
– Built-in Joint Test Action Group (JTAG) boundary-scan test
(BST) circuitr y compliant with IEEE Std. 11 49.1-1990, available
without consuming additional device logic.
– Operate with a 2.5-V internal supply voltage
– In-circuit reconfigurability (ICR) via external configuration
devices, intelligent controller, or JTAG port
– ClockLockTM and ClockBoostTM options for red uced clock delay,
clock skew, and clock multiplication
– Built-in, low-skew clock distribution trees
–100% functiona l te st ing of a ll device s; test ve ctor s or scan cha ins
are not required
– Pull-up on I/O pins before and during configura tion
■F lexible interconnect
–FastTrack
® Interconnect continuous routing structure for fast,
predictable interconnect delays
– Dedicated carry chain that implements arithmetic functions such
as fast adders, counters, and comparators (automatically used by
softw are tools and megafunctions)
– Dedicated cascade chain that implements high-speed,
high-fan-in logic functi ons (automat ically used by software tools
and megafunctions)
– Tri-state emulation that implements internal tri-state buses
– Up to six global clock signals and four global clear signals
■Powerful I/O pins
– Individual tri-state output enable control for each pin
– Open-drain option on each I/O pin
– Programmable output slew-rate control to reduce switching
noise
–Clamp to V
CCIO user-sel ectabl e on a pin-by -pin basis
– Supports hot-socketing
Altera Corporation 3
ACEX 1K Programmable Logic Device Family Data Sheet
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■Soft ware des ign sup port and automat ic place- and-rou te provi ded by
Altera development systems for Windows-based PCs and Sun
SPARCstation, and HP 9000 Series 700/800 workstations
■Flexible package options are available in 100 to 484 pins, including
the innovative FineLine BGATM packages (see Tables 2 and 3)
■Additi ona l design entry and simula tion support pr ovide d by EDIF
2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPM),
Design War e compone nts , Verilog HDL, VHDL, a nd othe r interfa ce s
to popular EDA tools from manufacturers such as Cadence,
Exemplar Logic, Men tor Graphics, OrCAD, Synopsys, Synplici ty,
VeriBes t, an d V i ew logic
Notes:
(1) ACEX 1K device package types include thin quad flat pack (TQFP), plastic quad flat pack (PQFP), and FineLine
BGA packages.
(2) D ev ices in the same pac kage are pin-co mp at ible, al though so me devices h av e more I/ O p in s than ot h er s . When
planning device migration, use the I/O pins that are common to all devices.
(3) Thi s opt ion is su pport ed with a 256-pi n Fi neLine BGA pa ckage . By usi ng Same FrameTM p in migra tio n, al l FineLi ne
BGA pack ag es are pin-co mp ati ble. For exa mp le , a bo ard ca n be des ig ned to suppo rt 256 - pin and 484-pin Fine Line
BGA packages.
Table 2. ACEX 1K Package Options & I/O Pin Count Notes (1), (2)
Device 100-Pin TQFP 144-Pin TQFP 208-Pin PQFP 256-Pin
FineLine BGA 484-Pin
FineLin e BGA
EP1K10 66 92 120 136 136 (3)
EP1K30 102 147 171 171 (3)
EP1K50 102 147 186 249
EP1K100 147 186 333
Table 3. ACEX 1K Package Sizes
Device 100-Pin TQFP 144-Pin TQFP 208-Pin PQFP 256-Pin
FineLine BGA 484-Pin
FineLine BGA
Pitch (m m) 0.50 0.5 0 0.50 1.0 1.0
Area (mm2) 256 484 936 289 529
Length × width
(mm × mm) 16 × 16 22 × 22 30.6 × 30.6 17 × 17 23 × 23
4Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
General
Description
Altera® ACEX 1K de vices provide a di e-efficie nt, low-co st archite cture by
combining look-up table (LUT) architecture with EABs. LUT-based logic
provides optimized performance and efficiency for data-path, register
intensive , mathematic al, or d igital sig nal proce ssing (DS P) designs, w hile
EABs implement RAM, ROM, dual-port RAM, or first-in first-out (FIFO)
functions. These elements make ACEX 1K suitable for complex logic
functions and memory functions such as digital signal processing, wide
data-path manipulation, data transformation and microcontrollers, as
required in high-performance communications applications. Based on
reconfigurable CMOS SRAM elements, the ACEX 1K architecture
incorporates all features necessary to implement common gate array
megafunctions, along with a high pin count to enable an effective interface
with system components. The advanced process and the low voltage
requirement of the 2.5-V core allow ACEX 1K devices to meet the
requirements of low-cost, high-volume applications ranging from DSL
modems to low-cost switches.
The ability to reconfigure ACEX 1K devices enables complete testing prior
to shipment and allows the designer to focus on simulation and design
verification. ACEX 1K device reconfigurability eliminates inventory
management for gate array designs and test vector generation for fault
coverage.
Table 4 shows ACEX 1K device performance for some common designs.
All performance results were obtained with Synopsys DesignWare or
LPM functions. Special design techniques are not required to implement
the applica tion s; the desig ne r si mply infer s or insta ntiates a function in a
Verilog HDL, VHDL, Altera Hardware Description Language (AHDL), or
schematic design file.
Notes:
(1) This applic at io n uses co mbinat or ial inputs an d o utput s .
(2) T hi s app lication u s es re gi s t er ed in puts and ou tp u t s.
Table 4. ACEX 1K Device Pe rform ance
Application Resources
Used Performance
LEs EABs Speed Grade Units
-1 -2 -3
16-bit load able c ounter 16 0 285 232 185 MHz
16-bit accu m ulat or 16 0 285 232 185 MHz
16-to-1 mult iplexer (1) 10 0 3.5 4.5 6.6 ns
16-bit mult iplier w it h 3-s tag e pipeline(2) 592 0 156 131 93 MHz
256 × 16 RAM read cycle s peed (2) 0 1 278 196 143 MHz
256 × 16 RAM write cycle s peed (2) 0 1 185 143 111 MHz
Altera Corporation 5
ACEX 1K Programmable Logic Device Family Data Sheet
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Table 5 shows ACEX 1K device performance for more complex design s.
Thes e d esigns are avail able as Altera MegaCoreTM functions.
Each ACEX 1K device contains an embedded array and a logic array. The
embedded array is used to implement a variety of memory functions or
complex logic functions, such as digital signal processing (DSP), wide
data-path manipulation, microcontroller applications, and data-
transformation functions. The logic array performs the same function as
the sea-of-gates in the gate array and is used to implement general logic
such as counters, adders, state machines, and multiplexers. The
combination of embedded and logic arrays provides the high
performance and high density of embedded gate arrays, enabling
designers to implement an entire system on a single device.
ACEX 1K de vice s ar e config ur e d at sy st em pow er- up with da ta store d in
an Altera serial configuration device or provided by a system controller.
Altera offers EPC16 , EPC2, EPC1, and EPC 14 41 con figuration device s,
which configure ACEX 1K devices via a serial data stream. Configuration
data can also be downloaded from system RAM or via the Altera
MasterBlasterTM, ByteBlasterMVTM, or BitBlasterTM download cables. After
an A CEX 1 K d evi ce has b een c onfig ur ed, it c an be r e config ure d in-cir c uit
by resetting the device and loading new data. Because reconfiguration
requires less than 40 ms, real-time changes can be made during system
operation.
ACEX 1K devices contain an interface that permits microprocessors to
configure ACEX 1K devices serially or in parallel, and synchronously or
asynchronously. The interface also enables microprocessors to treat an
ACEX 1K device as memo ry an d c onfigure it by writing to a virtual
memory location, simplifying device reconfiguration.
Table 5. ACEX 1K Device Performance for Complex Designs
Application LEs
Used Performance
Speed Grade Units
-1 -2 -3
16-bit , 8-tap parallel finite imp uls e res ponse (FIR)
filter 597 192 156 116 MSPS
8-bit, 512-point Fast Fo urier t rans f orm (FFT )
function 1,854 23.4 28.7 38.9 µs
113 92 68 MHz
a16450 universal async hronous
receiver/transmitter (UART) 342 36 28 20.5 MHz
6Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
fFor more information on the configuration of ACEX 1K devices, see the
following documents:
■Configura tion Dev ices f o r ACEX, APEX, F LEX , & Mercu ry Dev ices Data
Sheet
■MasterBlaster Serial/USB Communications Cable Data Sheet
■ByteBlasterMV Parallel Port Download Cable Data Sheet
■BitBlaster Serial Download Cable Data Sheet
ACEX 1K devices are supported by Altera development systems, which
are inte gr a te d pack a ge s th at off e r sch ema tic, text (i nclu din g A HD L), and
waveform design entry, compilation and logic synthesis, full simulation
and worst-case timing analysis, and device configuration. The software
provides EDIF 2 0 0 and 3 0 0, LPM, VHDL, Verilog HDL, and other
interfaces for additional design entry and simulation support from other
industry-standard PC- and UNIX workstation-based EDA tools.
The Altera software works easily with common gate array EDA tools for
synthesis and simulation. For example, the Altera software can generate
Verilog HDL files for simulation with tools such as Cadence Verilog-XL.
Additionally, the Altera software contains EDA libraries that use device-
specif i c f e at ur es such as ca rry chain s, which are used fo r f a st cou nte r a nd
arithmet ic fun ction s. F or inst an ce, the Syn opsy s Des ign Co mpile r libra ry
supplied with the Altera development system includes DesignWare
functions that are optimized for the ACEX 1K device architecture.
The Altera development systems run on Windows-based PCs and Sun
SP ARCstati on, and HP 9000 Series 700/800 workstations.
fFor more information, see the MAX+PLUS II Programmable Logic
Development System & Software Data Sheet and the Quartus Programmable
Logic Development System & Software Data Sheet.
Functional
Description
Each ACEX 1K device contains an enhanced embedded array that
implements memory and specialized logic functions, and a logic array
that implements general logic.
The embedded array consists of a series of EABs. When implementing
memory functions, each EAB provides 4,096 bits, which can be used to
create RAM, ROM, dual-port RAM, or first-in first-out (FIFO) functions.
When implementing logic, each EAB can contribute 100 to 600 gates
towards complex logic functions such as multipliers, microcontrollers,
state machines, and DSP functions. EABs can be used independently, or
multiple EABs can be combined to implement larger functions.
Altera Corporation 7
ACEX 1K Programmable Logic Device Family Data Sheet
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The logic array consists of logic array blocks (LABs). Each LAB contains
eight LEs and a local interconnect. An LE consists of a 4-input LUT, a
progra mmab le flip flop, a nd ded ica te d sign al paths for c arry a nd cas cade
functions. The eight LEs can be used to create medium-sized blocks of
logic—such as 8-bit counters, address decoders, or state machines—or
combined across LABs to create larger logic blocks. Each LAB represents
ab out 96 usa ble l ogic gate s.
Signal interconnections within ACEX 1K devices (as well as to and from
device pins) are provided by the FastTrack Interconnect routin g structure,
whic h is a ser ies of fast, contin uous row and column cha nnels that run the
entire length and width of the device.
Each I/O pin is fed by an I/O element (IOE) located at the end of each row
and column of the FastTrack Interconnect routing structure. Each IOE
conta ins a bid irectio nal I/O buffe r and a flipflop that can be used as either
an output or input register to feed input, output, or bidirectional signals.
When used with a dedicat ed clock p in, these registers provide e xcep tional
performance. As inputs, they provide setup times as low as 1.1 ns and
hold times of 0 ns. As outputs, these registers provide clock-to-output
times as low as 2.5 ns. IOEs provide a variety of features, such as JTAG
BST support, slew-rate control, tri-state buffers, and open-drain outputs.
Figure 1 shows a block diagra m of the ACEX 1K devi ce architectur e. Each
group of LE s is combine d i nto an L AB; grou ps of L ABs a re arra ng ed int o
rows and column s. Each row also co ntains a single EAB . The LABs and
EABs ar e in ter c onnected b y th e Fa stT r ac k In te rconne ct rout ing structu re .
IOEs are located at the end of each row and column of the FastTrack
Interconnect routing structure.
8Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
Figure 1. ACEX 1K Device Block Diagram
ACEX 1K devi ces provide six de dicated inputs that drive the flipflops ’
control inputs and ensure the efficient distribution of high-speed, low-
skew (less than 1.0 ns) control signals. These signals use dedicated routing
channe ls tha t p r ovide shor t er d el ays a nd low er s ke ws th an the F ast Tra ck
Interconnect routing structure. Four of the dedicated inputs drive four
global signals. These four global signals can also be driven by internal
logic, providing an ideal solution for a clock divider or an internally
generated asynchronous clear signal tha t cl ea rs ma ny registers in the
device.
I/O Element
(IOE)
Logic Array
Block (LAB)
Row
Interconnect
IOEIOE
IOEIOE
IOE
IOE
IOE
Local Interconnec
t
IOEIOE
IOEIOE IOEIOE
IOEIOE
IOEIOE
Logic Element (LE
)
Column
Interconnect
IOE
EAB
EAB
Logic
Array
IOEIOE
IOEIOE IOEIOE
Embedded Array Block (EAB)
Embedded Array
IOE
IOE
Logic Array
IOE
IOE
Altera Corporation 9
ACEX 1K Programmable Logic Device Family Data Sheet
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Embedded Array Block
The E AB is a fle xible block of RAM, w ith regist ers on the input an d outp ut
ports, that is used to implement common gate array megafunctions.
Because it is large and flexible, the EAB is suitable for functions such as
multipliers, vector scalars, and error correction circuits. These functions
can be combined in applications such as digital filters and
microcontrollers.
Logic func tio ns are implement ed by programm ing the EAB with a read-
only pattern during configuration, thereby creating a large LUT. With
LUTs, combinat orial functions are implemen ted by looking up the result s
rather than by computing them. This implementation of combinatorial
functions can be faster than using algorithms implemented in general
lo gic, a perfo rmance adv antag e tha t is fu rther enha nced b y the fast ac cess
times of EABs. The large capacity of EABs enables designers to implement
complex functions in a single logic level without the routing delays
associated with linked LEs or field-programmable gate array (FPGA)
RAM bl ocks. For example , a sing le EAB can imple ment a ny function with
8 inputs and 16 outputs. Parameterized functions, such as LPM functions,
can take advantage of the EAB automatically.
The ACEX 1K enha nced EAB supports dual -port RA M. The dual-port
structure is ideal for FIFO buffers with one or two clocks. The ACEX 1K
EAB can also support up to 16-bit-wi de RAM blocks. The ACEX 1K EAB
can act in dual-port or single-port mode. When in dual-port mode,
separat e clocks may b e used for EAB read and writ e sections, allow ing the
EAB to be writte n and read at different rates. It also has separa te
synchronous clock enable signals for the EAB read and write sections,
whic h allow indep ende nt cont rol of these sections.
The EAB can also be used for bidirectional, dual-port memory
applications where two ports read or write simultaneously. To implement
this type of dual-port memory, two EABs are used to support two
simultaneous re ads o r writes.
Alte rnat ivel y, one clock an d clock en able ca n b e used to contr ol t he inp ut
registers of the EAB, while a different clock and clock enable control the
out put r e gister s (see Figure 2).
10 Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
Figure 2. ACEX 1K Device in Dual-Port RAM Mode Note (1)
Notes:
(1) All registers can be asynchronously cleared by EAB local interconnect signals, global signals, or the chip-wide reset.
(2) EP1K10, EP1K30, and EP1K50 devices have 88 EAB local interconnect channels; EP1K100 devices have 104 EAB
loca l interconnect channels .
The EAB can use Altera megafunctions to implement dual-port RAM
applica tions wher e bot h ports c an read or writ e, as shown in Figure 3. The
ACEX 1K EAB can also be used in a single-port mode (see Figure 4).
Column Interconnect
E
AB Local
I
nterconnect (2)
Dedicated Clocks
24
D
ENA Q
D
ENA
Q
D
ENA Q
D
ENA Q
D
ENA
Q
data[ ]
rdaddress[ ]
wraddress[ ]
RAM/ROM
256 × 16
512 × 8
1,024 × 4
2,048 × 2
Data In
Read Address
Write Address
Read Enable
Write Enable
Data Out
4, 8, 16, 32
4, 8, 16, 32
outclocken
inclocken
inclock
outclock
D
ENA Q
Write
Pulse
Generator
rden
wren
Multiplexers allow read
address and read
enable registers to be
clocked by inclock or
outclock signals.
Row Interconnect
4, 8
Dedicated Inputs &
Global Signals
Altera Corporation 11
ACEX 1K Programmable Logic Device Family Data Sheet
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Figure 3. ACEX 1K EAB in Dual-Port RAM Mode
Figure 4. ACEX 1K De vic e in Single-Po rt RAM Mode
Note:
(1) E P 1K 10, EP1 K 30, an d EP1K 50 devices have 88 EAB local inter con n ec t c ha nnels; EP1K1 00 d evices have 104 EAB
loc a l in t e r c o n nect ch annels.
Port A Port B
address_a[] address_b[]
data_a[] data_b[]
we_a we_b
clkena_a clkena_b
Clock A Clock B
Column Interconnect
EAB Local
Interconnect (1)
Dedicated Inputs
& Global Signals
DQ
DQ
RAM/ROM
256 × 16
512 × 8
1,024 × 4
2,048 × 2
Data In
Address
Write Enable
Data Out
4, 8, 16, 32
4, 8, 16, 32
DQ
DQ
4
8, 4, 2, 1
8, 9, 10, 11
Row Interconnect
Dedicated
Clocks
2
4, 8
Chip-Wide
Reset
12 Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
EABs ca n be use d to impl ement syn chrono us RAM, which is eas ier to use
than asynchronous RAM. A circuit using asynchronous RAM must
generate th e RAM write enable signal, while ensur ing that its da ta and
ad dre ss signals meet setup and hold tim e spe cifications relative to th e
write enable signal. In contrast, the EAB’s synchronous RAM generates its
own write enable signal and is self-timed with respect to the input or write
clock. A cir cuit u sing the E AB’s se lf-timed RAM must only me et t he set up
and hold time specifications of the global clock.
When used as RAM, each EAB can be configured in any of the following
sizes: 256 ×16; 512 ×8; 1,024 ×4; or 2,048 ×2. Figure 5 shows the ACEX 1K
EAB memo ry configurations .
Figure 5. ACEX 1K EAB Memory Configurations
Larger blocks of RAM are created by combining multiple EABs. For
example, two 256 × 16 RAM blocks can be combined to form a 256 ×32
block, and two 512 ×8 RAM blocks can be combined to form a
512 ×16 block. Figure 6 shows examples of multiple EAB combination.
Fi gure 6. Ex ampl es of C ombi n i ng A C EX 1K EABs
256 × 16 512 × 8 1,024 × 4 2,048 × 2
512 × 8
512 × 8
256 × 16
256 × 16
256 × 32 512 × 16
Altera Corporation 13
ACEX 1K Programmable Logic Device Family Data Sheet
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If necessary, all EABs in a device can be cascaded to form a single RAM
block. EABs can be cascaded to form RAM blocks of up to 2,048 words
with out impacting t imi ng . Al te ra so f twa re a utomatic all y c om bines EABs
to meet a designer’s RAM specifications.
EABs provide flexible options for driving and controlling clock signals.
Different clocks and clock enab les can be use d for rea ding and writi ng to
the EAB. Registers can be independently inserted on the data input, EAB
output, write address, write enable signals, read address, and read enable
signals. The global sig na ls and the EAB local inter connect ca n drive
write-enable, read-enable, and clock-enable signals. The global signals,
dedicated clock pins, and EAB local interconnect can drive the EAB clock
signals. Because the LEs driv e t he EAB local interconn ec t, the LEs can
control write-enable, read-enable, clear, clock, and clock-enable signals.
An EAB is fed by a row in terconnect and can drive out to row and colu mn
inte rconnect s. Ea ch EAB ou tput ca n drive u p to two row channe ls and up
to two column channels; the unused row channel can be driven by other
LEs. This feature increases the routing resources available for EAB
outpu ts (see Figures 2 and 4). T he c olumn int erc onne ct, whic h i s adjac en t
to the EAB, has twice as many channels as other columns in the device.
Logic Array Bloc k
An LAB consists of eight LEs, their associated carry and cascade chains,
LAB contr ol s i gnals, and the LA B l ocal interconnect. The LA B provides
the coarse-grained structure to the ACEX 1K architecture, facilitating
efficient routing with optimum device utilization and high performance.
Figure 7 sho ws t he ACEX 1K LAB.
14 Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
Figure 7. ACEX 1K LAB
Notes:
(1) EP1K10, EP1K30, and EP1K50 devices have 22 inputs to the LAB local interconnect channel from the row; EP1K100
devices have 26.
(2) EP1 K 10, EP1K 30, and EP1K 50 d evices have 30 LAB local intercon n ect chan n el s ; EP1K 100 devices have 34.
2
8
Carry-In &
Cascade-In
LE1
LE8
LE2
LE3
LE4
LE5
LE6
LE7
Column
Interconnect
Row Interconnect
(1)
LAB Local
Interconnect (2)
Column-to-Row
Interconnect
Carry-Out &
Cascade-Out
16
24
LAB Control
Signals
See Figure 13
for details.
6
Dedicated Inputs &
Global Signals
16
6
8
4
4
4
4
4
4
4
4
4
428
Altera Corporation 15
ACEX 1K Programmable Logic Device Family Data Sheet
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Each LAB provides four control signals with programmable inversion
that can be used in all eight LEs. Two of these signals can be used as clocks,
the oth er t wo ca n b e use d for c lea r /pre set control. T he L AB cl ock s c an b e
driven by the dedicated clock input pins, global signals, I/O signals, or
internal signals via the LAB local interconnect. The LAB preset and clear
control signals can be driven by the global signals, I/O signals, or internal
signals via the LAB local interconnect. The global control signals are
typi ca lly used for global clock, clear , or preset signa ls because they
provide asynchronous control with very low skew across the device. If
logic is required o n a control signal, it ca n be gener ated in one or more LEs
in any LAB and driven into the local inte rconnect of the target LAB. In
addition, the global control signals can be generated from LE outputs.
Logic Element
The LE, the smallest unit of logic in the ACEX 1K architecture, has a
compact size that provides efficient logic utilization. Each LE contains a
4-inp ut L UT, w hich is a func tion ge ne rator that can qui ck ly c omput e any
funct ion of four var ia bles. In addit ion, e ach LE cont ain s a prog rammable
flipflop with a synchronous clock enable, a carry chain, and a cascade
chain. Each LE drives both the local and the FastTrack Interco nnect
routing st ructure. Figure 8 shows the ACEX 1K LE.
16 Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
Figure 8. ACEX 1K Logic Element
The programmabl e flipflop in the LE can be config ured for D, T, JK, or SR
operation. The clock, clear, and preset control signals on the flipflop can
be driven by global signals, general-purpose I/O pins, or any internal
logic. For co mbin ato ri al fun cti ons, the flip flop is bypass ed a nd the LUT ’s
output driv es the LE’s output .
The LE has two outputs that drive the interconnect: one drives the local
interconnect, and the other drives either the row or column FastTrack
Interconnect routing structure. The two outputs can be controlled
independently. For example, the LUT can drive one output while the
regist er driv es th e oth er outp ut. T his fe atu re, ca lled r egister packi ng, can
improve LE utilization because the register and the LUT can be used for
unrelated functions.
The ACEX 1K architecture provides two types of dedicated high-speed
data paths that connect adjacent LEs without using local interconnect
paths: carry chains and cascade chains. The carry chain supports high-
spee d coun ters a nd adder s, and the cas cade c hain imp lements w ide-in put
functions with minimum delay. Carry and cascade chains connect all LEs
in a LAB an d all LAB s in the sam e row. Intensi ve use of ca rry and casc ade
chains can reduce routing flexibility. Therefore, the use of these chains
should be limited to speed-critical portions of a design.
To LAB Local
Interconnect
Carry-In
Clock
Select
Carry-Out
Look-Up
Table
(LUT)
Clear/
Preset
Logic
Carry
Chain Cascade
Chain
Cascade-In
Cascade-Out
To FastTrack
Interconnect
Programmable
Register
PRN
CLRN
DQ
ENA
Register Bypass
data1
data2
data3
data4
labctrl1
labctrl2
labctrl4
labctrl3
Chip-Wide
Reset
Altera Corporation 17
ACEX 1K Programmable Logic Device Family Data Sheet
Development
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Tools
Carr y Ch ain
The carry chain pr o vide s a very fast (as low as 0.2 ns) carry-forw ard
function between LEs. The carry-in signal from a lower-order bit drives
forward into the higher-order bit via the carry chain, and feeds into both
the LUT and the next portion of the carry chain. This feature allows the
ACEX 1K archi tecture to efficiently implement hi gh-sp eed c ount e r s,
adders, and comparators of arbitrary width. Carry chain logic can be
created automatically by the compiler during design processing, or
manually by the designer duri ng des i gn entry. Para met erized functions,
such as LPM and DesignW are fun ctions, a utoma tically ta ke advan tage of
carry chains.
Carry chains longer than eight LEs are automatically implemented by
linking LABs together. For enhanced fitting, a long carry chain skips
alternate LABs in a row. A carry chain longer than one LAB skips either
from even-num bere d LAB to even-numbered LAB, or from odd-
numbered LAB to odd-numbered LA B. For example, the la st LE o f the
first LAB in a row carri es to the first LE of the thir d LAB in the row. The
carr y cha i n do es not cr os s t he E AB at t he mid dle of the r ow . F or instance ,
in the EP1K5 0 device, the carry chain stops at the eighteenth LAB, and a
new carry chain b egi ns at the ninete enth L AB.
Figure 9 shows how an n- bit full adde r can be impleme nte d in n+1 LEs
with the car ry chain. One port ion of th e LUT gene rates the sum of t wo bits
using the input signals and the carry-in signal; the sum is routed to the
output of the LE. The register can be bypassed for simple adders or used
for an accumulator function. Another portion of the LUT and the carry
chain logic generates the carry-out signal, which is routed directly to the
carry-in signal of the next-higher-order bit. The final carry-out signal is
routed to an LE, where it can be used as a general-purpose signal.
18 Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
Figure 9. ACEX 1K Carry Chain Operation (n-Bit Full Adder)
LUT
a1
b1
Carry Chain
s1
LE1
Register
a2
b2
Carry Chain
s2
LE2
Register
Carry Chain
sn
LEn
Register
an
bn
Carry Chain
Carry-Out
LEn + 1
Register
Carry-In
LUT
LUT
LUT
Altera Corporation 19
ACEX 1K Programmable Logic Device Family Data Sheet
Development
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Tools
Cascade Chain
With the cascade chain, the ACEX 1K architecture can implement
functions that have a very wide fan-in. Adjacent LUTs can be used to
compute portions of the function in parallel; the cascade chain serially
conne ct s the int erme diate va lues. T he c ascade chai n can us e a l ogical AND
or logical OR (via De Morgan’s inversion) to connect the outputs of
adjacent LEs. Wi th a delay as low as 0.6 ns per LE, eac h addi tio nal LE
provides four more inputs to the effective width of a function. Cascade
chai n logic can be create d automat ica lly by the compiler during design
processing, or manually by the designer during design entry.
Cascade chains longer than eight bits are implemented automatically by
linking several LABs together. For easier routing, a long cascade chain
skips every other LAB in a row. A cascade chain longer than one LAB
skips either from even-numbered LAB to even-numbered LAB, or from
odd-numbered LA B to odd-numbered LAB (e.g ., t he last LE o f the first
LAB in a row cascades to the first LE of the third LAB). The cascade chain
does not cross the center of the row (e.g., in the EP1K50 device, the cascade
chai n s tops at the eight eenth LAB , and a ne w one begi ns at the ninete enth
LAB). This break is due to the EAB’s placement in the middle of the row.
Figure 10 shows how the cascade function can connect adjacent LEs to
form functions with a wide fan-in. These examples show functions of 4n
variables implemented with n LEs. The LE delay is 1.3 ns; the cascade
chain delay is 0.6 ns. With the cascade chain, decoding a 16-bit address
requires 3.1 ns.
Figure 10. ACEX 1K Cascade Chain Operation
LE1
LUT
LE2
LUT
d[3..0]
d[7..4]
d[(4
n –
1)..(4
n –
4)]
d[3..0]
d[7..4]
LE
n
LE1
LE2
LE
n
LUT
LUT
LUT
LUT
AND Cascade Chain OR Cascade Chain
d[(4
n –
1)..(4
n –
4)]
20 Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
LE Operating Modes
The ACEX 1K LE can operate in the following four modes:
■Normal mode
■Arithmetic mode
■Up/down counter mode
■Clea rable counter mode
Each of these modes uses LE resources differently. In each mode, seven
available inputs to the LE—the four data inputs from the LAB local
interconnect, the feedback from the programmable register, and the
carry-in and cascade-in from the previous LE—are directed to different
destinations to implement the desired logic function. Three inputs to the
LE provide clock, clear, and preset control for the register. The Altera
software, in conjunction with parameterized functions such as LPM and
DesignWare functions, automatically chooses the appropriate mode for
common functio ns suc h as cou nte rs, add ers , and multip liers. If required,
the designer can also create special-purpose functions that use a specific
LE operating mode for optimal performance.
The archi tecture provi des a sync hronous cl ock enable to the reg ister i n al l
four modes. The Altera software can set DATA1 to enable the register
synchronously, providing easy implementation of fully synchronous
designs.
Figure 11 shows the ACEX 1K LE operating mo des.
Altera Corporation 21
ACEX 1K Programmable Logic Device Family Data Sheet
Development
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Tools
Figure 11. ACEX 1K LE Operating Modes
ENA
PRN
CLRN
DQ
4-Input
LUT
Carry-In
Cascade-Out
Cascade-In
LE-Out to F astTr ac k
Interconnect
LE-Out to Local
Interconnect
ENA
Normal Mode
PRN
CLRN
DQ
Cascade-Out
LE-Out
Cascade-In
3-Input
LUT
Carry-In
3-Input
LUT
Carry-Out
Arithmetic Mode
Up/Down Counter Mode
PRN
CLRN
DQ
3-Input
LUT
Carry-In Cascade-In
LE-Out
3-Input
LUT
Carry-Out
1
0
Cascade-Out
Clearable Counter Mode
PRN
CLRN
DQ
3-Input
LUT
Carry-In
LE-Out
3-Input
LUT
Carry-Out
1
0
Cascade-Out
ENA
ENA
data1
data4
data3
data2
data1
data2
data1 (ena)
data2 (u/d)
data4 (nload)
data3 (data)
data1 (ena)
data2 (nclr)
data4 (nload)
data3 (data)
22 Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
Normal Mode
The normal mode is suitable for general logic applications and wide
deco ding f unc tions that can t ak e a d van tag e of a casca d e cha i n. In norm a l
mode, four data inputs from the LAB local interconnect and the carry-in
are inputs to a 4-input LUT. The compiler automatically selects the carry-
in or the DATA3 signal as one of the inputs to the LUT. The LUT output
can be combined with the cascade-in signal to for m a cascad e ch ain
throu gh the casca de-out signa l. Eith er th e regis ter or the L UT can be us ed
to drive both the local interconnect and the FastTrack Interconnect routing
structure at the same time.
The LUT and the register in the LE can be used independently (register
pack ing). To support regi ster p acking , the LE ha s two ou tputs; one d rives
the local interconnect, and the other drives the FastTrack Interconnect
routin g struc tur e. The DATA4 signal can drive the register directly,
allowing the LUT to compute a function that is independent of the
registered signal; a 3-input function can be computed in the LUT, and a
fourth independent signal can be registered. Alternatively, a 4-input
function can be generated, and one of the inputs to this function can be
used to drive the register. The register in a packed LE can still use the clock
enab le, clear , and pres et sign als in th e LE . In a pa cked L E, the reg ister can
drive the FastTrack Interconnect routing structure while the LUT drives
the local inter con nect, or vice versa.
Arithmetic Mode
The arithmetic mode offers two 3-input LUTs that are ideal for
implementi ng ad d ers, accumulat ors, and co mparato r s. One L UT
computes a 3-input function; the other generates a carry output. As shown
in Figure 11, the first LUT uses the carry-in signal and two data inputs
from the LAB loca l in te rconn ect to g ene rat e a c ombi nat orial or regis tere d
output. For example, in an adder, this output is the sum of three signals:
a, b, and car ry-in. The secon d LUT uses th e same th ree signal s to generat e
a carry-out signal, thereby creating a carry chain. The arithmetic mode
also supports simultaneous use of the cascade chain.
Up/Down Counter Mode
The up/down counter mode offers counter enable, clock enable,
synchronous up/down control, and data loading options. These control
signa ls a re ge ne rate d by th e d at a in puts from the LAB lo cal inter conn ect ,
the car ry-in sig nal, and outp ut feedb ack from the p rogrammable re gister .
Two 3- input L UTs ar e us ed; one gene rat es the c ount er da ta, a nd th e othe r
generates the fast carry bit. A 2-to-1 multiplexer provides synchronous
loading. Data can also be loa ded asynchro nously with t he clear and preset
register control signals without using the LUT resources.
Altera Corporation 23
ACEX 1K Programmable Logic Device Family Data Sheet
Development
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Tools
Clearable Counter Mode
The cl earabl e counte r mode is similar to the up /down coun ter mode, but
it supp orts a synchronous cl ear inst ead of the up/down control . The clear
function is substituted for the cascade-in signal in the up/down counter
mode. Two 3-input LUTs are used; one generates the counter data, and the
other generates the fast carry bit. Synchronous loading is provided by a
2-to-1 multiplexer. The output of this multiplexer is AND ed with a
synchronous clear signal.
Internal Tri-State Emulation
Internal tri-state emulation provides internal tri-states without the
limitations of a physical tri-state bus. In a physical tri-state bus, the
tri-state buffers’ output enable (OE) signals select which signal drives the
bus. H owever, if multip le OE signal s ar e act ive , conten ding sig nals ca n be
driven onto the bus. Conversely, if no OE signals are active, the bus will
fl oat. Inte rnal t ri-sta te emul atio n resolve s conte nding tr i-state buffe rs to a
low value and floating buses to a high value, thereby eliminating these
problems. The Altera software automatically implements tri-state bus
functionality with a multiplexer.
Clear & Preset Logic Control
Logic for the programmable register’s clear and preset func tions is
co ntrolled by t he DATA3, LABCTRL1, and LABCTRL2 inputs to the L E. Th e
clear and preset control structure of the LE asynchronously loads signals
into a register. Either LABCTRL1 or LABCTRL2 can control the
asynchronous clear. Alternatively, the register can be set up so that
LABCTRL1 implements an asynchronous load. The data to be loaded is
driven to DATA3; when LABCTRL1 is asserted, DATA3 is loaded into the
register.
During compilation, the compiler automatically selects the best control
signal implem entatio n. Because the clea r and p r eset func tio ns are activ e-
low, th e Compiler automatica lly assigns a logic h igh to an unused cle ar or
preset.
The clear and preset logic is implemented in one of the following six
modes chos en during design en try:
■Asynchronous clear
■Asynchronous preset
■Asynchronous clear and preset
■Asynchronous load with clear
■Asynchronous load with preset
■Asynchronous load without clear or preset
24 Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
In ad di tion to the six c l ea r a nd pr e se t mo des, ACEX 1 K d e vice s pr ovid e a
chip-wide reset pin that can reset all registers in the device. Use of this
feature is set during design entry. In any of the clear and preset modes, the
chip-wide reset overrides all other signals. Registers with asynchronous
pres ets ma y be pres et when the ch ip-w ide r eset is as sert ed. Inver si on can
be used to implement the asynchronous preset. Figure 12 shows examples
of how to setup the preset and clear inputs for the desired functionality.
Figure 12. ACEX 1K LE Clear & Preset Modes
Asynchronous Clear Asynchronous Preset Asynchronous Preset & Clear
Asynchronous Load without Clear or Preset
labctrl1
(Asynchronous
Load) PRN
CLRN
DQ
NOT
NOT
labctrl1
(Asynchronous
Load)
Asynchronous Load with Clear
labctrl2
(Clear)
PRN
CLRN
DQ
NOT
NOT
(Asynchronous
Load)
Asynchronous Load with Preset
NOT
NOT
PRN
CLRN
DQ
labctrl1 or
labctrl2
PRN
CLRN
DQ
VCC
Chip-Wide Reset
Chip-Wide Reset
Chip-Wide Reset
Chip-Wide Reset
PRN
CLRN
DQ
PRN
CLRN
DQ
VCC
Chip-Wide Reset
Chip-Wide Reset
data3
(Data)
labctrl1
labctrl2
(Preset)
data3
(Data)
data3
(Data)
labctrl1 or
labctrl2
labctrl1
labctrl2
Altera Corporation 25
ACEX 1K Programmable Logic Device Family Data Sheet
Development
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Tools
Asynchron o us C lear
The flipflop can be cleared by either LABCTRL1 or LABCTRL2. In this
mode, the preset signal is tied to VCC to deactivate it.
Asynchronou s Preset
An asynchronous preset is implemented as an asynchronous load, or with
an as ynchronous clear. I f DATA3 is tied to VCC, asserting LABCTRL1
asynchronously loads a one into the register. Alternatively, the Altera
software can provide p reset cont r ol by using th e clear and inverting the
regis ter’s inp ut and outpu t. In version c ontrol is ava ilable for t he inp uts to
bot h L Es an d IO Es. Th erefo re , if a reg ist er is pr eset by o nl y one o f t he two
LABCTRL sig na l s, t he DATA3 input is not needed and can be used for one
of the LE operating modes.
Asynchronou s Preset & Clea r
When implementin g asynchro nous clear and pr eset, LABCTRL1 controls
the preset, and LABCTRL2 contr ols the cle ar. DATA3 is tied to VCC, so that
asserting LABCTRL1 asynchronously loads a one into the register,
eff ectivel y pre settin g the regi ster. As sert ing LABCTRL2 clea rs the reg ist er.
Asynchronous Load w ith Cle ar
When implem e nt i ng an asynch ro nous load in conjun ctio n with the clear,
LABCTRL1 implements the asynchronous load of DATA3 by controlling
the register pres et and clear. LABCTRL2 implements the clear by
controlling the register clear; LABCTRL2 does not have to feed the preset
circuits.
Asynchronous Load w ith Preset
When i mplementing an asynchronous load in conjunction with preset, the
Altera software provides preset control by using the clear and inverting
the input and output of the register. Asserting LABCTRL2 presets the
register, while asserting LABCTRL1 loads the register. The Altera software
inverts the signal that drives DATA3 to account for the inversion of the
register’s output.
Asynchronous Load w ithout Preset or C l ea r
When implementing an asynchronous load without preset or clear,
LABCTRL1 implements the asynchronous load of DATA3 by controlling
the register pres et and clear.
26 Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
FastTrack Interconnect Routing Structure
In the ACEX 1K architecture, connections between LEs, EABs, and device
I/O pins are provided by the FastTrack Interconnect routing structure,
which is a series of continuous horizontal and vertical routing channels
that traverse the device. This global routing structure provides
predictable performance, even in complex designs. In contrast, the
segmented routing in FPGAs requires switch matrices to connect a
variable number of routing paths, increasing the delays between logic
resources and reducing performance.
The Fas tTr ac k Int ercon ne ct r ou ting st r uctu re consists of r ow a nd column
interconnect channels that span the entire device. Each row of LABs is
served by a dedicated row interconnect. The row interconnect can drive
I/O pins an d feed othe r LABs in the row . The column intercon nect rou tes
signals between rows and can drive I/O pins.
Row channels drive into the LAB or EAB local interconnect. The row
signal is buffered at every LAB or EAB to reduce the effect of fan-out on
delay. A row channel can be driven by an LE or by one of three column
channe ls. Th es e f our si gna ls f e ed du a l 4-to-1 multiplexe rs that co nne ct to
two specific row channels. These multiplexers, which are connected to
each LE, allow column channels to drive row channels even when all eight
LEs in a LA B dri v e the row interconnect.
Each column o f LAB s or EA Bs is served by a dedicate d col u mn
interconnect. The column interconnect that serves the EABs has twice as
many channels as other column interconnects. The column interconnect
can the n drive I/ O pins or another r ow’s i nterconn ect to ro ute the sig nals
to other LABs or EABs in the device. A signal from the column
interconnect, which can be either the output of a LE or an input from an
I/O pin, must be routed to the row interconnect before it can enter a LAB
or EAB. Each row channel that is driven by an IOE or EAB can drive one
specific column channel.
Access to row and column channels can be switched between LEs in
adjacent pa i rs of LABs. For example, a LE in one LAB can drive the row
and column channels normally driven by a particular LE in the adjacent
LAB in the same row, and vice versa. This flexibility enables routing
reso urces to be us ed m or e eff ic i en tly . Figure 13 shows the ACEX 1K LAB.
Altera Corporation 27
ACEX 1K Programmable Logic Device Family Data Sheet
Development
13
Tools
Figure 13. ACEX 1K LA B Connectio ns to R ow & Col umn Int erc onnect
From Adjacent LAB
Row Channels
Column
Channels
Each LE can drive two
row channels.
LE 2
LE 8
LE 1 To Adjacent LAB
Each LE can switch
interconnect access
with an LE in the
adjacent LAB.
At each intersection,
six row channels can
drive column channels.
To Other Rows
To LAB Local
Interconnect
To Other
Columns
28 Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
For improved routing, the row interconnect consists of a combination of
full-length and half-length channels. The full-length channels connect to
all LABs in a row; the half-length channels connect to the LABs in half of
the row . The EA B can b e dr iven by the half -lengt h cha nnels in the left hal f
of the row a nd b y t he full-le ng th cha nne ls. The EA B drive s out t o th e fu ll-
length channels. In addition to providing a predictable, row-wide
intercon ne ct, this arc hit ectu re pr ovide s in cr ease d ro uti ng resources. T w o
neighboring LABs can be connected using a half-row channel, thereb y
saving the other half of the channel for the other half of the row.
Table 6 summarizes t he Fa stTrack Interconnect r outing structure
resources available in each ACEX 1K device.
In addition to general-purpose I/O pins, ACEX 1K devices have six
dedica ted inp ut p ins tha t prov ide lo w-skew signa l dis trib ution ac ross the
device. These six inputs can be used for global clock, clear, preset, and
periph er al output -ena ble and clock-enable cont rol si gnals . These sig nals
are available as control signals for all LABs and IOEs in the device. The
dedica ted inputs can a lso be used as gene ral-pur pose data inp uts because
they can feed the local interconnect of each LAB in the device.
Figure 14 shows the interconnection of adjacent LABs and EABs, with
row, column, and local interconnects, as well as the associated cascade
and carry chains. Each LAB is labeled according to its location: a letter
repres ents t he row and a number rep r esents the column. For ex ample,
LAB B3 is in row B, column 3 .
Table 6. ACEX 1K FastTrack Interconnect Resources
Device Rows Channels per
Row Col um ns Chann el s per
Column
EP1K10 3 144 24 24
EP1K30 6 216 36 24
EP1K50 10 216 36 24
EP1K100 12 312 52 24
Altera Corporation 29
ACEX 1K Programmable Logic Device Family Data Sheet
Development
13
Tools
Figure 14 . ACEX 1K Intercon nect R esour ces
I/O Element
An IOE contains a bidirectional I/O buffer and a register that can be used
eith er as an inpu t reg ister fo r ex ternal da ta t h at requires a fa st set up tim e
or as an output register for data that requires fast clock-to-output
performan ce. In some cases , using a n LE re gister for an input regist er will
result in a faster setup time than using an IOE register. IOEs can be used
as input, output, or bidirectional pins. The compiler uses the
programmable inversion option to invert signals from the row and
column interconnect automatically where appropriate. For bidirectional
registered I/O implementation, the output register should be in the IOE
and the data input and output enable registers should be LE registers
plac ed adja cent to t he bidi rectio nal p in. Figure 15 shows the bidire ctiona l
I/O regi st ers.
I/O Element (IOE)
Row
Interconnect
IOE
IOE
IOE
IOE
Column
Interconnect
LAB
B1
See Figure 17
for details.
See Figure 16
for details.
LAB
A3
LAB
B3
LAB
A1 LAB
A2
LAB
B2
IOE
IOE
Cascade &
To LAB B4
To LAB A4
To LAB B5
To LAB A5
IOE IOEIOE IOE
IOE IOE
IOEIOE IOEIOE IOEIOE
IOE
IOE
Carry Chains
30 Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
Figure 15. ACEX 1K Bidirectional I/O Registers
VCC
OE[7..0]
CLK[1..0]
ENA[5..0]
CLRN[1..0]
Peripheral
Control Bus
CLRN
DQ
ENA
VCC
2 Dedicated
Clock Inputs
Slew-Rate
Control
Open-Drain
Output
Chip-Wide
Output Enable
CLK[3..2]
212
VCC
VCC
Chip-Wide
Reset
Programmable Delay
4 Dedicated
Inputs
Row and Column
Interconnect
4
VCC
CLRN
DQ
ENA
Chip-Wide
Reset
CLRN
DQ
ENA
Chip-Wide
Reset
VCC
Input Register
Output Register
OE Register
Altera Corporation 31
ACEX 1K Programmable Logic Device Family Data Sheet
Development
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Tools
On all AC EX 1K device s, the input path from the I/O pa d to the FastTra ck
Interconnect has a programmable delay element that can be used to
guarantee a zero hold time. Depending on the placement of the IOE
relative to what it is driving, the designer may choose to turn on the
progra mmable de lay to ensure a zero ho ld time or turn it off to minimiz e
setup time. This feature is used to reduce setup time for complex pin-to-
regist er paths ( e.g., PCI designs).
Each IOE selects the clock, clea r, clock enable , and output enab le controls
from a network of I/O control signals called the peripheral control bus.
The p e r iphe ral contro l bus u ses hi gh-s peed d r ivers to minimi ze signal
skew acros s d e vice s and p rovid es up to 12 per iphe ral contr ol signals tha t
can be allocated as follows:
■Up to eigh t out put ena b l e sig nals
■Up to six clock enable signals
■Up to two clock signals
■Up to two clear signals
If more than six clock-enable or eight output-enable signals are required,
each IOE on the device can be controlled by clock enable and output
enabl e sig nal s dr iven by spe cific LEs . In addi tion to the two cl ock signals
available on the peripheral control bus, each IOE can use one of two
dedicated clock pins. Each peripheral control signal can be driven by any
of the dedicated input pins or the first LE of each LAB in a particular row.
In addition, a LE in a different row can drive a column interconnect, which
causes a row interconnect to drive the peripheral control signal. The chip-
wide reset signal resets all IOE registers, overriding any other control
signals.
When a dedicated clock pin drives IOE registers, it can be inverted for all
IOEs in the device. All IOEs must use the same sense of the c lock. For
example , if any I OE uses the in verted clock, all IOEs mus t use th e i nverted
clock, and no IOE can use the non-inverted clock. However, LEs can still
use the true or complement of the clock on an LAB-by-LAB basis.
The incoming signal may be inverted at the dedicated clock pin and will
drive a ll I OE s. For t he true an d comp leme nt of a cloc k to be use d to d rive
IOEs, dr ive it into both global clock pins. One gl obal clock pin will supply
the true, and the other will supply the complement.
When the true and c o mplement of a dedicated in put drives IOE clocks ,
two signals on the peripheral control bus are consumed, one for each
sense of the clock.
32 Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
When dedicated inputs drive non-inverted and inverted peripheral clears,
clock enables, and output enables, two signals on the peripheral control
bus will be used.
Table 7 l ists the source s for each peri pheral c ont rol sig nal a nd sh ows how
the output enable, clock enable, clock, and clear signals share
12 peri phe ral control signal s. Table 7 also shows the rows that can drive
global signals.
Signals on the peripheral c ontrol bus can also drive the four global signals,
referred to as GLOBAL0 thro ugh GLOBAL3. An inte rnally gener ated sign al
can drive a global signal, providing the same low-skew, low-delay
characteristics as a signal driven by an input pin. An LE drives the global
signal by driving a row line that drives the peripheral bus which then
drives th e globa l signal. T his feat ure is ide al for int ernally g enerated c lear
or clock signals with high fan-out. However, internally driven global
signals offer no advantage over the general-purpose interconnect for
routin g data signals.
The chip-w ide ou tpu t en able pin is an active -hig h pin tha t c an be use d t o
tri-state all pins on the device. This option can be set in the Altera
software. The built-in I/O pin pull-up resistors (which are active during
configuration) are active when the chip-wide output enable pin is
asserted. The registers in the IOE can also be reset by the chip-wide reset
pin.
Table 7. Peripher al Bus Sources for ACEX Devices
Peripheral Control Signal EP1K10 EP1K30 EP1K50 EP1K100
OE0 Row ARow ARow ARow A
OE1 Row A Row B Row B Row C
OE2 Row B Ro w C Row D Row E
OE3 Row B Row D Row F Row L
OE4 Row C Row E Row H Row I
OE5 Row C Row F Row J Row K
CLKENA0/CLK0/GLOBAL0 Row A Row A Row A Row F
CLKENA1/OE6/GLOBAL1 Row A Row B Row C Row D
CLKENA2/CLR0 Row B Row C Row E Row B
CLKENA3/OE7/GLOBAL2 Row B Row D Row G R ow H
CLKENA4/CLR1 Row C Row E Row I Row J
CLKENA5/CLK1/GLOBAL3 Row C Row F Row J Row G
Altera Corporation 33
ACEX 1K Programmable Logic Device Family Data Sheet
Development
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Row -to -IOE Co nnectio ns
When an IOE is used as an input signal, it can drive two separate row
chan nels. T he signal is accessi ble by all LEs with in that row. Wh en an IOE
is used as an output, the signal is driven by a multiplexer that selects a
sign al f rom the row channe ls. Up to eig ht IOE s conn ect to each side of
each row channel (see Figure 16).
Figure 16 . ACEX 1 K R ow-to-IOE Connections Note (1)
Note:
(1) The values for m and n are sh own in Table 8.
Table 8 lists the ACEX 1K row-to-IOE interconnect resources.
n
n
Each IOE is driven by an
m-to-1 multiplexer.
Each IOE can drive two
row channels.
IOE8
IOE1
m
m
Row FastTrack
Interconnect
n
Table 8. A CEX 1K Row-to-IOE I nterconnect Resources
Device Channels per Row (n) Row Channels per P i n (m)
EP1K10 144 18
EP1K30 216 27
EP1K50 216 27
EP1K100 312 39
34 Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
Column-to-IOE Connections
When an IOE is used as an input, it can drive up to two separate column
channels. When an IOE is used as an output, the signal is driven by a
multiplexer that selects a signal from the column channels. Two IOEs
connect to each side of the column channels. Each IOE can be driven by
column c hannels via a multiplexer. The set of column chann els is differe nt
for each IOE (see Figure 17).
Figure 17. ACEX 1K Column-to-IOE Connections Note (1)
Note:
(1) The values for m and n are shown in Table 9.
Table 9 lists the ACEX 1K column-to-IOE interconnect resources.
Table 9. ACEX 1K Column-to-IOE Interconnect Resources
Device Channels per Column (n) Column Channels per Pin (m)
EP1K10 24 16
EP1K30 24 16
EP1K50 24 16
EP1K100 24 16
Each IOE is driven by
a m-to-1 multiplexer
Each IOE can drive two
column channels.
Column
Interconnect
n
n
m
m
n
IOE1
IOE1
Altera Corporation 35
ACEX 1K Programmable Logic Device Family Data Sheet
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SameFrame
Pin-Outs
ACEX 1K devices support the SameFrame pin-out feature for
FineLine B GA pa ckages. Th e Same Fr ame p in-ou t feat ure is the
arrangement of balls on FineLine BGA packages such that the lower-ball-
count packages form a subset of the higher-ball-count packages.
SameFrame pin-outs provide the flexibility to migrate not only from
device to device within the same package, but also from one package to
anot her. A given printed cir cuit board (PCB) layout can support multipl e
device density/package combinations. For example, a single board layout
can support a ra nge of devices from an EP1K10 dev ice in a 256-p in
FineLine BGA package to an EP1K100 device in a 484-pin FineLine BGA
package.
The Altera software provides support to design PCBs with SameFrame
pin-out devices. De vices can be defined for present a nd fut ur e use . The
Alte ra soft ware ge nerate s pin-outs descri bing how to lay out a board that
takes advantage of this migration. Figure 18 sho ws an ex ample of
SameF rame pin-o ut.
Figure 18. SameFra me Pin-Out Example
Table 10 shows the AC E X 1K de vice / pa ckag e c om binations that suppor t
SameFram e pin-o uts for ACEX 1K devices. All FineLine BGA packages
supp ort SameFrame p in-outs, provid ing the fle xibility to mig rate not only
from device to device within the same package, but also from one package
to another. The I/O count will vary from device to device.
Designed for 484-Pin FineLine BGA Package
Printed Circuit Board
256-Pin FineLine BGA Package
(Reduced I/O Count or
Logic Requirements)
484-Pin FineLine BGA Package
(Increased I/O Count or
Logic Requirements)
256-Pin
FineLine
BGA
484-Pin
FineLine
BGA
36 Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
fFor more information, search for “SameFrame” in MAX+PLUS II Help.
Note:
(1) This option is supported with a 256-pin FineLine BGA package and SameFrame
migration.
C lockLock &
ClockBoost
Features
To support high-speed desig n s, -1 a nd -2 speed grade ACEX 1K devi c es
offer Clock L ock a nd Clock B oost c ircuit ry c ontaining a pha se- locke d loop
(PLL) that is used to increase design speed and reduce resource usage. The
ClockLock circuitry uses a synchronizing PLL that reduces the clock delay
and skew within a device. This reduction minimizes clock-to-output and
setup time s w hile m ain tai ning ze ro ho ld time s. T he Clock B oost cir cu itr y,
which provide s a clock multiplier, allows the design er to enhan ce devi ce
area efficiency by sharing resources within the device. The ClockBoost
feature allows the designer to distribute a low-speed clock and multiply
that clock on-device. Combined, the ClockLock and ClockBoost features
provide significant improvements in system performance and
bandwidth.
The ClockLock and C lockB oost fe atur es in ACEX 1K d evices are enab led
through the Altera software. External devices are not required to use these
features. The output of the ClockLock and ClockBoost circuits is not
available at any of the d evice pi ns.
The ClockLock and ClockBoost circuitry lock onto the rising edge of the
incoming clock. The circuit output can drive the clock inputs of registers
only; the generated clock cannot be gated or inverted.
The dedicated clock pin (GCLK1) supplies th e cl ock to t he ClockLock and
ClockBoost circuitry. When the dedicated clock pin is driving the
ClockLock or ClockBoos t circuitr y, it c annot driv e elsewhere in the de vice.
Table 10. ACEX 1K SameFrame Pin-Out Support
Device 256-Pin
FineLine
BGA
484-Pin
FineLine
BGA
EP1K10 v(1)
EP1K30 v(1)
EP1K50 vv
EP1K100 vv
Altera Corporation 37
ACEX 1K Programmable Logic Device Family Data Sheet
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For designs that require both a multiplied and non-multiplied clock, the
clock tr ac e on the boa r d can b e conn ected to th e GCLK1 pin. I n the Alte ra
sof tware, the GCLK1 pin can feed both the ClockLock and ClockBoost
circuitry in the ACEX 1K device. However, when both circuits are used,
the other clock pin cannot be used.
ClockL ock & C lock Boost Timing Par amet er s
For the ClockLock and ClockBoost circuitry to function properly, the
incoming clock must meet certain requirements. If these specifications are
not met, the circuitry may not lock onto the incoming clock, which
generates an erroneous clock within the device. The clock generated by
the ClockLock and ClockBoost circuitry must also meet certain
specifications. If the incoming clock meets these requirements during
configuration, the ClockLock and ClockBoost circuitry will lock onto the
clock d uring config ura tion. Th e circ uit w ill be rea dy for us e immedi ately
after configuration. Figure 19 shows t he inco ming and gene rate d clock
specifications.
Figure 19. Sp ec ifications for the In co ming & Generated Clo cks Note (1)
Note:
(1) The tI parameter refers to the nominal input clock period; the tO parameter refers to the nominal output clock
period.
Input
Clock
ClockLock
Generated
Clock
tCLK1 tINDUTY tI+tCLKDEV
tRtFtOtI+tINCLKSTB
tOtOtJITTER
tO+tJITTER
tOUTDUTY
38 Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
Tables 11 and 12 summarize the ClockLock and ClockBoost parameters
for -1 and -2 speed-grade devices, respectively.
Table 11 . Cl ockLock & ClockBoost P arameters for -1 Sp eed-Grade Device s
Symbol Parameter Condition Min Typ Max Unit
tRIn put r i se time 5ns
tFIn put fa l l tim e 5ns
tINDUTY In put du ty c y c le 40 60 %
fCLK1 Input clo ck fr e que n cy (C l oc kB oost clock
multiplic at ion fa ctor equals 1) 25 180 MHz
fCLK2 Input clo ck fr e que n cy (C l oc kB oost clock
multiplic at ion fa ctor equals 2) 16 90 MHz
fCLKDEV Input deviation from user specification in the
Altera software (1) 25,000
(2) PPM
tINCLKSTB Input clock stability (measured between
adjacen t cloc ks) 100 ps
tLOCK Time required for ClockLock or ClockBoost
to acquire loc k (3) 10 µs
tJITTER Jitt er on C loc kL oc k or Cloc kB oos t -
generat ed cl oc k (4) tINCLKSTB <100 250 (4) ps
tINCLKSTB < 50 200 (4) ps
tOUTDUTY Duty cycle for Cl oc kL o ck or Cl oc kB oost-
generat ed cl oc k 40 50 60 %
Altera Corporation 39
ACEX 1K Programmable Logic Device Family Data Sheet
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Notes to table s:
(1) To imp lement the ClockLock and Clo ckBoo st circuitry with the Altera software, designers must specify the input
frequency. The Altera software tunes the PLL in the ClockLock and ClockBoost circuitry to this frequency. The
fCLKDEV paramet er spec ifies how muc h th e incom in g clock can di ffer from the s pecif ied fr eq uency du r in g de v ic e
operation. Simulation does not reflect this parameter.
(2) Twenty-five thousand parts per million (PPM) equates to 2.5% of input clock period .
(3) D u rin g devic e conf igurat i on , the Clock L ock and Clock Boost circuitry is config u red befo re the rest of the device. If
the incoming clock is s upplied dur ing co nfigur a t ion, t h e C lo c kLoc k a nd ClockB oost circu itry lo c ks dur in g
con figur at io n because the tLOCK value is less than the time required for configuration.
(4) The tJITTER specificat ion is me as ured un d er lo n g-ter m observ ation . T h e maximum v alue fo r tJITTER is 200 ps if
tINCLKSTB is lower t han 50 ps.
I/O
Configuration
This section discusses the PCI pull-up clamping diode option, slew-rate
control, open-drain output option, and MultiVolt I/O interface for
ACEX 1K devices. The PCI pull-up clamping diode, slew-rate control, and
open-drain output options are controlled pin-by-pin via Altera software
logic options. The MultiVolt I/O interface is controlled by connecting
VCCIO to a different voltage than VCCINT. Its effect can be simulated in the
Altera software via the Global Project Device Options dialog box (Assign
menu).
Table 12. ClockLock & ClockBoost Parameters for -2 Speed-Grade Devices
Symbol Parameter Condition Min Typ Max Unit
tRInput rise time 5ns
tFInput fall time 5ns
tINDUTY Input duty cycle 40 60 %
fCLK1 Input clock fr equency (Clock Boos t clock
multiplication factor equals 1) 25 80 MHz
fCLK2 Input clock fr equency (Clock Boos t clock
multiplication factor equals 2) 16 40 MHz
fCLKDEV Input dev iat ion f rom us er sp eci ficat ion in
the softw are (1) 25,000 PPM
tINCLKSTB Input clo ck stability (measured between
adjace n t cl o cks) 100 ps
tLOCK Time required for ClockLock or ClockBoost
to acquire loc k (3) 10 µs
tJITTER Jitter on ClockL o ck or Cl o ckB o os t-
generated clock (4) tINCLKSTB < 100 250 (4) ps
tINCLKSTB < 50 200 (4) ps
tOUTDUTY Dut y cycle for ClockLoc k or Cloc kB oos t -
generated clock 40 50 60 %
40 Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
PCI Pull-Up C lam ping Diode Option
ACEX 1K devices have a pull-up clamping diode on every I/O, dedicated
input , and dedica te d clo ck pin. PCI clamping diodes clamp the signal to
the VCCIO value and are required for 3.3-V PCI compliance. Clamping
diodes can also be used to limit overshoot in other systems.
Clamping diodes are controlled on a pin-by-pin basis. When VCCIO is
3.3 V, a pi n that h as the cla mping diode o ption turne d on can be d riven by
a 2.5-V or 3.3-V si gnal, but not a 5.0-V sign al. When VCCIO is 2.5 V, a pi n
that has the clamping diode option turned on can be driven by a 2.5-V
signal, but not a 3.3-V or 5.0-V signal. Additionally, a clamping diode can
be activated for a subset of pins, which allows a device to brid ge betwe en
a 3.3-V PCI bu s and a 5.0-V dev ice.
Slew-Rate Control
The outp ut buffer in each IOE has an adjustab le output sle w rate tha t can
be configured for low-noise or high-speed performance. A slower slew
rate reduces system noise and adds a maximum delay of 4.3 ns. The fast
slew rate should be used for speed-critical outputs in systems that are
adequately protected against noise. Designers can specify the slew rate
pin-by-pin or ass ign a d e faul t sle w rate t o a ll pins on a d evice -wide b as is.
The slow slew rate setting affects only the falling edge of the output.
Open-Dr ain Out put Option
ACEX 1K devices provide an optional open-drain output (electrically
equivalent to open-collector output) for each I/O pin. This open-drain
output enables the device to provide system-level control signals (e.g.,
interrupt and write enable signals) that can be asserted by any of several
devices. It can also provide an additional wired-OR plane.
MultiVolt I/O Interface
The ACEX 1K device architecture supports the MultiVolt I/O interface
feature, which allows ACEX 1K devices in all packages to interface with
systems of differing supply voltages. These devices have one set of VCC
pins for internal operation and input buffers (VCCINT), and another set for
I/O output drivers (VCCIO).
Altera Corporation 41
ACEX 1K Programmable Logic Device Family Data Sheet
Development
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Tools
The VCCINT pins must always be connected to a 2.5-V power supply.
With a 2.5-V VCCINT level, input voltages are compatible with 2.5-V, 3.3-
V, and 5.0 -V in puts. The VCCIO p i ns can b e conn ected t o e ithe r a 2.5-V or
3.3-V power supply, depending on the output requirements. When the
VCCIO pins are connected to a 2.5-V power supply, the output levels are
com pa tib le wit h 2.5-V sy ste m s. When the VCCIO pins are connected to a
3.3-V power supply, the output high is at 3.3 V and is therefore compatible
with 3.3-V or 5.0-V systems. Devices operating with VCCIO levels higher
than 3.0 V achieve a faster timing delay of tOD2 instead of tOD1.
Table 13 summarizes ACEX 1K MultiVolt I/O support.
Notes:
(1) The PCI clamping diode must be d is abled o n an input which is d r iv en with a
vo ltage highe r than VCCIO.
(2) Wh en VCCIO = 3.3 V, an ACEX 1K device can drive a 2.5-V device that has 3.3-V
tolerant inputs .
Open-drain output pins on ACEX 1K devices (with a pull-up resistor to
the 5.0-V sup ply) can drive 5.0-V CMO S input pins th at req uire a high er
VIH than LVTTL. When the open-drain pin is active, it will drive low.
When the pin is inactive, the resistor will pull up the trace to 5.0 V, thereby
me et i ng the CM O S VOH requireme nt. The ope n-dr ain pin w ill on ly d rive
low or tri-s tat e; it wi ll never dr ive hi gh . The rise time is dep en dent on the
value of the pull-up resistor and load impedance. The IOL current
specification should be considered when selecting a pull-up resistor.
Power
Sequenc i ng &
Hot-Socketing
Because ACEX 1 K devi ce s can be used in a mixed-v o ltage environment ,
they have been designed specifically to tolerate any possible power-up
sequence. The VCCIO and VCCINT power planes can be powered in any
order.
Signals can be driven into ACEX 1K devices before and during power up
without dama gi ng the device. Additionally, A CEX 1K devices do not
drive out during power up. Once operating conditions are reached,
ACEX 1K devices operate as specified by the user.
Table 13. ACEX 1K Mult iVolt I/O Suppor t
VCCIO (V) Input Si gnal (V) O utput Signal (V)
2.5 3.3 5.0 2.5 3.3 5.0
2.5 vv(1) v (1) v
3.3 vvv (1) v (2) vv
42 Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
IEEE Std.
1149.1 (J TA G )
Boundar y-Scan
Support
All ACEX 1K devices provide JTAG BST circuitry that complies with the
IEEE Std. 11 49.1-1990 speci f ication. ACEX 1K devices can also be
configur e d using the JTAG pins throug h th e B y teBl a st erM V or Bit Blast er
download cable, or via hardware that uses the JamTM Standard Test and
Programming Language (STAPL), JEDEC standard JESD-71. JTAG
boundary-scan testing can be performed before or after configuration, but
not during configuration. ACEX 1K devices support the JTAG
instructions shown in Table 14.
The instruction register length of ACEX 1K devices is 10 bits. The
USERCOD E register length i n ACEX 1K devices is 32 bi ts; 7 bits are
determined by the user, and 25 bits are pre-determined. Tables 15 and 16
show the boundary-scan register length and device IDCODE information
for ACEX 1K device s.
Table 14. ACE X 1K JTAG I nst ructions
JTAG Instruc tion Description
SAMPL E/P R ELOAD Allow s a snaps hot of sign als at the dev ic e pins to be capt ured and examined during
norm al dev ice operation and permit s an initi al dat a pat te rn to be outp ut at th e dev ice
pins.
EXTEST Allows the ex te rnal c ircu itr y and board-level interc onnections to be test ed by for cin g a
test patt ern at the outp ut pin s an d cap tu ring te st res ult s at th e input pins .
BYPASS Places the 1-bit by pas s regis te r between the TDI and TDO pins, allow ing th e BST dat a
to pass sy nch ronously throu gh a se lec ted dev ice to adja ce nt de vices during normal
operation.
USERC OD E Selec ts the use r elec tro nic sign at ure (U SER C OD E) register and plac es it betw een t he
TDI and TDO pins, allowing the USERCODE to be serially shifted out of TDO.
IDCODE Selects the IDCODE register and places it between TDI and TDO, allowing the IDCODE
to be serially sh ifted out of TDO.
ICR Instructions These instructions are used when configuring an ACEX 1K device via JTAG ports using
a Maste rBlas t er, ByteBlasterMV , or BitBlaster down load c able, or a Jam File (.jam) or
Jam Byte-Code File (.jbc) via an embedded processor.
Table 15. ACEX 1K Boundary-Scan Register Length
Device Boundary-Scan Register Length
EP1K10 438
EP1K30 690
EP1K50 798
EP1K100 1,050
Altera Corporation 43
ACEX 1K Programmable Logic Device Family Data Sheet
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Notes to table s:
(1) The most significant bit (MS B ) is o n th e left.
(2) Th e le ast sig nificant bit (LSB) for all JTA G ID CODEs is 1.
ACEX 1K devices include weak pull-up resistors on the JTAG pins.
fFor more information, see the following documents:
■Application Note 39 (IEEE Std. 1149.1 (JTAG) Boundary-Scan Testing in
Altera Devices)
■ByteBlasterMV Parallel Port Download Cable Data Sheet
■BitBlaster Serial Download Cable Data Sheet
■Jam Programming & Test Language Specification
Figure 20 shows the timing requirements for the JTAG signals.
Table 16. 32-Bit IDCODE for ACEX 1K Devices Note (1)
Device IDCODE (32 Bits )
Version
(4 Bits) Par t N umber (16 Bits) Manuf acturer’s
Identity (11 Bits) 1 (1 Bit) (2)
EP1K10 0001 0001 0000 0001 0000 00001101110 1
EP1K30 0001 0001 0000 0011 0000 00001101110 1
EP1K50 0001 0001 0000 0101 0000 00001101110 1
EP1K100 0010 0000 0001 0000 0000 00001101110 1
44 Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
Figure 20. ACEX 1K JTAG Waveforms
Table 17 shows the timi ng para m et ers and v alues fo r ACE X 1K device s.
TDO
TCK
t
JPZX
t
JPCO
t
JPH
t
JPXZ
t
JCP
t
JPSU
t
JCL
t
JCH
TDI
TMS
Signal
to Be
Captured
Signal
to Be
Driven
t
JSZX
t
JSSU
t
JSH
t
JSCO
t
JSXZ
Table 17. ACEX 1K JTAG Timing Parameters & V alues
Symbol Parameter Min Max Unit
tJCP TCK clock perio d 100 ns
tJCH TCK clock high t im e 50 ns
tJCL TCK clock low time 50 ns
tJPSU JTAG port setup time 20 ns
tJPH JTAG port hold t im e 45 ns
tJPCO J TA G port clo ck to outp ut 25 ns
tJPZX J TA G port high im pedance to vali d out put 25 ns
tJPXZ J TA G port va lid out put to hig h imp edance 25 ns
tJSSU Capture register setup time 20 ns
tJSH Capture register hold time 45 ns
tJSCO Update register clock to output 35 ns
tJSZX U pdate register high im pedance to valid output 35 ns
tJSXZ U pdate register valid outp ut to high im pedance 35 ns
Altera Corporation 45
ACEX 1K Programmable Logic Device Family Data Sheet
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Generic Testing Each ACEX 1K device is functionally tested. Complete testing of each
configurable static random access memory (SRAM) bit and all logic
functionality ensures 100% yield. AC test measurements for ACEX 1K
device s ar e mad e under co nditions eq uiva len t to those shown in
Figure 21. Multiple test patterns can be used to configure devices during
all stages of the production flow.
Figure 21. ACEX 1K AC Test C onditions
Operating
Conditions
Tables 18 through 21 provide i nform ation on absolute maximum r ating s,
recommended operating conditions, DC operating conditions, and
capacitance for 2.5-V ACEX 1K devices.
To T est
System
C1 (includes
JIG capacitance)
Device input
rise and fall
times < 3 ns
Device
Output
703 Ω
8.06 k Ω
[481 ]
Ω
[481 ]
Ω
VCCIO
Power supply transients can affect AC
measurements. Simultaneous transitions of
multi ple outputs should be avoided for
accurate measurement. Threshold tests
must not be perform ed under AC
conditions. Large-amplitude, fast-ground-
current transients normally occur as the
de vice outputs discharge the l oad
capacitanc es. When these transi ents flow
through the parasitic inductance between
the device ground pin and the test system
gr ound, signi ficant reductions in
observable noise immunity can result.
Numbers in brackets are for 2.5-V devices
or outputs. Numbers without bracke ts are
for 3.3-V devices or outputs.
Table 18. ACEX 1K Device Absolute Maximum Ratings Note (1)
Symbol Parameter Conditions Min Max Unit
VCCINT Supply volta ge With respect to ground (2) –0.5 3.6 V
VCCIO –0.5 4.6 V
VIDC input vo lta ge –2.0 5.75 V
IOUT DC output cur rent , pe r pin –25 25 mA
TSTG Stor age t em perature N o bias –65 1 50 ° C
TAMB Amb ient temperature Under bias –65 135 ° C
TJJunction temperature PQFP, TQFP, and BGA packages, under
bias 135 ° C
46 Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
Table 19. ACEX 1K Device Recommend ed Operating Conditions
Symbol Parameter Conditions Min Max Unit
VCCINT Supply voltag e fo r inter nal logic
and input buffers (3), (4) 2.375
(2.375) 2.625
(2.625) V
VCCIO Supply voltage for output buffers,
3.3-V operation (3), (4) 3.00 (3.00) 3.60 (3.6 0) V
Supply voltage for output buffers,
2.5-V operation (3), (4) 2.375
(2.375) 2.625
(2.625) V
VIInput vo lta ge (2), (5) –0.5 5.75 V
VOOutp ut volt age 0 VCCIO V
TAAmbient temperature Commercial range 0 70 ° C
Industri al range –40 85 ° C
TJJunct ion te m perat ure Commercial range 0 85 ° C
Industri al range –40 10 0 ° C
Extended range –40 125 ° C
tRInput ris e time 40 ns
tFInput fa ll time 40 ns
Table 20. ACEX 1K Dev ice DC Operating Cond itions (Part 1 o f 2) Notes (6), (7)
Symbol Parameter Conditions Min Typ Max Unit
VIH High-level input voltage 1.7,
0.5 × VCCIO (8) 5.75 V
VIL Low-level input voltage –0.5 0.8,
0.3 × VCCIO (8) V
VOH 3.3-V hig h-lev el T T L out put
voltage IOH = –8 mA DC,
VCCIO =3.00 V (9) 2.4 V
3.3-V high-level CMOS output
voltage IOH = –0.1 mA DC,
VCCIO =3.00 V (9) VCCIO –0.2 V
3.3-V hig h-lev el PC I out put
voltage IOH = –0.5 mA DC,
VCCIO = 3.00 to 3.60 V
(9)
0.9 ׆VCCIO V
2.5-V high-level output voltage IOH = –0.1 mA DC,
VCCIO = 2.375 V (9) 2.1 V
IOH = –1 mA DC,
VCCIO = 2.375 V (9) 2.0 V
IOH = –2 mA DC,
VCCIO = 2.375 V (9) 1.7 V
Altera Corporation 47
ACEX 1K Programmable Logic Device Family Data Sheet
Development
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VOL 3.3-V low-level TTL output
voltage IOL = 12 mA DC,
VCCIO = 3.00 V (10) 0.45 V
3.3- V low -lev el C MO S out put
voltage IOL = 0.1 mA DC,
VCCIO = 3.00 V (10) 0.2 V
3.3- V low -lev el PC I ou tp ut
voltage IOL = 1.5 mA DC,
VCCIO = 3.00 t o 3. 60 V
(10)
0.1 × VCCIO V
2.5- V low -lev el out put vo lta ge IOL = 0.1 mA DC,
VCCIO = 2.375 V (10) 0.2 V
IOL = 1 mA DC,
VCCIO = 2.375 V (10) 0.4 V
IOL = 2 mA DC,
VCCIO = 2.375 V (10) 0.7 V
IIInput pin leaka ge c urrent VI = 5.3 to –0.3 V (11) –10 10 µA
IOZ Tri-stat ed I/O pin leakage
current VO = 5.3 to –0.3 V (11) –10 10 µA
ICC0 VCC supply cu rrent (standby) VI = ground, no load,
no t oggling input s 5mA
VI = ground, no load,
no t oggling input s (12) 10 mA
RCONF Value of I/O pin pull-up
resist or bef ore and during
configuration
VCCIO =3.0 V (13) 20 50 kΩ
VCCIO = 2.375 V (13) 30 80 kΩ
Table 20 . ACEX 1K D evi ce DC Operatin g Cond i t ions (Part 2 of 2) Notes (6), (7)
Symbol Parameter Conditions Min Typ Max Unit
48 Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
Notes to tables:
(1) See the Operating Requirements for Altera Devices Data Sheet.
(2) Minimum DC input voltage is –0.5 V. During transitions, the inputs may undershoot to –2.0 V for input currents
less than 100 mA and per iods shor t er tha n 20 ns .
(3) Numbers in parentheses are for industrial- and extended-temperature-range devices.
(4) M aximum VCC rise time is 100 ms, and VCC must rise monotonically.
(5) All pins, including dedicated inputs, clock, I/O, and JTAG pins, may be driven before VCCINT and VCCIO are
powered.
(6 ) T ypical valu es ar e f or TA = 25° C, VCCINT = 2.5 V , and VCCIO = 2.5 V or 3.3 V .
(7) These values are specified under the ACEX 1K Recommended Operating Conditions shown in Table 19 on page 46.
(8) T he A C EX 1K in pu t bu ffers are com patible wit h 2.5-V , 3.3 -V (LVTTL an d L VCMOS), an d 5. 0-V TTL and CMOS
sign als. Ad d ition all y, the in put b uffer s ar e 3.3-V PCI compli ant wh en VCCIO and VCCINT meet the relationship
shown in Figure 22.
(9) The IOH parameter refers to high-level TTL, PCI, or CMOS output current.
(10) The IOL parameter refers to low-level TTL, PCI, or CMOS output current. This parameter appl ies to open-dra in pins
as well as outpu t pins.
(11) This v alue is sp ec ifi ed for n o r mal device opera tio n . Th e v alue may v ar y during p ower-up .
(12) This parameter applies to -1 speed grade commercial temperature devices and -2 speed grade industrial and
exten d ed t emper at ur e devic es.
(13) Pin pull-up resistance values will be lower if the pin is driven higher than VCCIO by an ext er n al sou rc e.
(14 ) Cap a c it an ce is sample-test ed o n ly.
Table 21. ACEX 1K Device Capacit ance Note (14)
Symbol Parameter Conditions Min Max Unit
CIN Input ca pac ita nc e VIN = 0 V, f = 1.0 MHz 10 pF
CINCLK I nput ca pac ita nc e on
dedicated c loc k pin VIN = 0 V, f = 1.0 MHz 12 pF
COUT Output capacit anc e VOUT = 0 V, f = 1.0 MHz 10 pF
Altera Corporation 49
ACEX 1K Programmable Logic Device Family Data Sheet
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Figure 22 shows the required relationship between VCCIO and VCCINT to
satisfy 3.3-V PCI compliance.
Figure 22. Relationship between VCCIO & VCCINT for 3.3- V PCI Compliance
Figure 23 shows the typical output drive characteristics of ACEX 1K
devices with 3.3-V and 2.5-V VCCIO. The output dr iver is comp liant to the
3.3-V PCI Local Bus Specification, Revi sion 2.2 (when VCCIO pins are
connected to 3.3 V). ACEX 1K devices with a -1 speed grade also comply
with the drive strength requirements of the PCI Local Bus Specification,
Re vis ion 2. 2 (whe n VCCINT pins are powered with a minimum supply of
2.3 75 V , and VCCIO pins are connected to 3.3 V). Therefore, these devices
can be used in open 5.0-V PCI systems.
3.0 3.1 3.3
VCCIOIO
3.6
2.3
2.5
2.7
V
CCINT
II (V)
(V)
PCI-Compliant Region
50 Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
Figure 23. Output Drive Characteristics of ACEX 1K Devices
Tim ing Model The continuous, high-performance FastTrack Interconnect routing
resources ensure accurate simulation and timing analysis as well as
predictable performance. This predictable performance contrasts with
that of FPG As, w hich u se a s eg mented c onne ction scheme a nd , there fore ,
hav e an un predictable perfo r manc e.
Device perf orm a nce c an b e e stima te d b y following the sig na l p ath fr om a
source, through the interconnect, to the destination. For example, the
registered perfo r mance between two LEs on the same r ow can b e
calculated by adding the following parameters:
■LE register clock-to-output delay (tCO)
■Interconnect delay (tSAMEROW)
■LE look-up table delay (tLUT)
■LE register setup time (tSU)
The rout ing delay depends on the placement of the source and destination
LEs. A more comp lex registered pat h may involve multiple combinatorial
LEs betwe en the sour ce and de st inat ion LEs.
Timing simulation and delay prediction are available with the simulator
and Timing Analyzer , or with industr y- st anda r d EDA tools. The
Simulator offers both pre-synthesis functional si mulation to evaluate logic
design accuracy and post-synthesis timing simulation with 0.1-ns
resolution. The Timing Analyzer provides point-to-point timing delay
information, se tup an d hold t ime analy sis, an d d evice-w ide performa nce
analysis.
VO Output Voltage (V)
IOL
IOH IOH
V
V
VCCINT = 2.5
VCCIO = 2.5
Room Temperature
V
V
VCCINT = 2.5
VCCIO = 3.3
Room Temperature
123
10
20
30
50
60
40
70
80
90
VO Output Voltage (V)
123
10
20
30
50
60
40
70
80
90 IOL
O
Typical I
Output
Current (mA)
O
Typical I
Output
Current (mA)
Altera Corporation 51
ACEX 1K Programmable Logic Device Family Data Sheet
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Figure 24 shows the overall t iming model, which maps t he pos sible paths
to and from the various elements of the ACEX 1K device.
Figure 24. ACEX 1K Device Timing Model
Figures 25 through 28 show the delays that correspond to various paths
and functions wit hin the LE, IOE, EAB, and bidirectional timin g models.
Figure 25. ACEX 1K Device LE Timi ng Model
Dedicated
Clock/Input Interconnect I/O Element
Logic
Element Embedded Array
Block
t
CGENR
t
CO
t
COMB
t
SU
t
H
t
PRE
t
CLR
Register
Delays
LUT Delay
t
LUT
t
RLUT
t
CLUT
Carry Chain
Delay
Carry-In Cascade-In
Data-Out
t
CGEN
t
CICO
Packed Register
Delay
t
PACKED
Register Control
Delay
t
C
t
EN
Data-In
Control-In
t
CASC
Cascade-Out
Carry-Out
t
LABCARRY
t
LABCASC
52 Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
Figure 26. ACEX 1K Device IOE Timing Model
Figure 27. ACEX 1K Device EAB Tim i ng Mo del
Data-In
I/O Register
Delays
t
IOCO
t
IOCOMB
t
IOSU
t
IOH
t
IOCLR
Output Data
Delay
t
IOD
I/O Element
Contol Delay
t
IOC
Input Register Delay
t
INREG
Output
Delays
t
OD1
t
OD2
t
OD3
t
XZ
t
ZX1
t
ZX2
t
ZX3
I/O Register
Feedback Delay
t
IOFD
Input Delay
t
INCOMB
Clock Enable
Clear
Data Feedback
into FastTrack
Interconnect
Clock
Output Enable
EAB Data Input
Delays
t
EABDATA1
t
EABDATA2
Data-In
Write Enable
Input Delays
t
EABWE1
t
EABWE2
EAB Clock
Delay
t
EABCLK
Input Register
Delays
t
EABCO
t
EABBYPASS
t
EABSU
t
EABH
t
EABCH
t
EABCL
t
EABRE1
t
EABRE2
RAM/ROM
Block Delays
t
AA
t
RP
t
RASU
t
RAH
t
DD
t
WP
t
WDSU
t
WDH
t
WASU
t
WAH
t
WO
Output Register
Delays
t
EABCO
t
EABBYPASS
t
EABSU
t
EABH
t
EABCH
t
EABCL
t
EABOUT
Address
WE
Input Register
Clock
Output Register
Clock
Data-Out
EAB Output
Delay
Read Enable
Input Delays
RE
Altera Corporation 53
ACEX 1K Programmable Logic Device Family Data Sheet
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Figure 28. Synchronous Bidirectional Pin External Timing Model
Tables 29 and 30 show the asynchronous and synchronous timing
wave for ms, re sp ec tive ly , for the EA B macrop ar ame te r s in Table 24.
Figure 29. EA B Asynchro nous Ti mi ng Waveforms
PRN
CLRN
DQ
PRN
CLRN
DQ
PRN
CLRN
DQ
Dedicated
Clock
Bidirectional
Pin
Output Register
tINSUBIDIR
tOUTCOBIDIR
tXZBIDIR
tZXBIDIR
tINHBIDIR
OE Register
Input Register
EAB Asynchronous Write
EAB Asynchronous Read
WE
a0
d0 d3
t
EABRCCOMB
a1 a2 a3
d2
t
EABAA
d1
Address
Data-Out
WE
a0
din1 dout2
t
EABDD
a1 a2
din1
din0
t
EABWCCOMB
t
EABWASU
t
EABWAH
t
EABWDH
t
EABWDSU
t
EABWP
din0
Data-In
Address
Data-Out
54 Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
Figure 30. EAB Synchronous Timing Waveforms
Tables 22 through 26 describe the ACEX 1K device internal timing
parameters.
WE
CLK
EAB Synchronous Read
a0
d2
tEABDATASU tEABRCREG
tEABDATACO
a1 a2 a3
d1
tEABDATAH
a0
WE
CLK
dout0 din1 din2 din3 din2
tEABWESU
tEABWCREG
tEABWEH
tEABDATACO
a1 a2 a3 a2
din3
din2
din1
tEABDATAH
tEABDATASU
EAB Synchronous Write (EAB Output Registers Used)
dout1
Address
Data-Out
Address
Data-Out
Data-In
Table 22. LE Timing Microparameters (Part 1 of 2) Note (1)
Symbol Parameter Conditions
tLUT LUT delay for data-in
tCLUT LUT delay for carry-in
tRLUT LUT delay for LE register feedback
tPACKED Data-in t o packed register delay
tEN LE register enable delay
tCICO Carry-in to carry-out delay
tCGEN Data-in to carry-out delay
tCGENR LE register feedb ac k to car ry- out delay
Altera Corporation 55
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tCASC Cascade-in to cascade-out delay
tCLE register control signal delay
tCO LE register clock-to-output delay
tCOMB Combin at orial delay
tSU LE registe r setup time for data and enable signals bef ore c loc k ; LE reg ister
recovery time after asynchronous clear, preset, or load
tHLE register hold time for data and enable signals after clock
tPRE LE register preset delay
tCLR LE register clear delay
tCH Minimu m cloc k hig h time f rom clo ck pin
tCL Minimu m cloc k low t ime from cl oc k pin
Table 23. IOE Timing Microparameters Note (1)
Symbol Parameter Conditions
tIOD IOE data de lay
tIOC IOE regis ter control s ignal delay
tIOCO IOE regis ter clock -to -out put delay
tIOCOMB IOE c om binatorial dela y
tIOSU IOE register setup time for data and enable signals before clock; IOE register
reco ve ry tim e after as y nc hronous clear
tIOH IOE regis ter hold time f or dat a and enable signa ls aft er clo ck
tIOCLR IOE register clear time
tOD1 Output buffer and pad delay, slo w slew rat e = off, VCCIO = 3.3 V C1 = 35 pF (2)
tOD2 Output buffer and pad delay, slo w slew rat e = off, VCCIO = 2.5 V C1 = 35 pF (3)
tOD3 Output buffer and pad delay, slo w slew rat e = on C1 = 35 pF (4)
tXZ IOE outpu t bu ffer dis able delay
tZX1 IOE outpu t bu ffer enable delay, slo w slew rat e = off, VCCIO = 3.3 V C1 = 35 pF (2)
tZX2 IOE outpu t bu ffer enable delay, slo w slew rat e = off, VCCIO = 2.5 V C1 = 35 pF (3)
tZX3 IOE outpu t bu ffer enable delay, slo w slew rat e = on C1 = 35 pF (4)
tINREG IOE input pad and buf f er to IOE regis ter delay
tIOFD IOE regis ter feed bac k de lay
tINCOMB IOE input pad and buff er to Fast Tra ck In te rco nnec t delay
Table 22. LE Timing Microparameters (Part 2 of 2) Note (1)
Symbol Parameter Conditions
56 Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
Table 24. EAB Timi ng Microparameters Note (1)
Symbol Parameter Conditions
tEABDATA1 Data or address delay to EAB for combinatorial input
tEABDATA2 Data or address delay to EAB for registered input
tEABWE1 W rite enable delay to EAB for combinatorial inp ut
tEABWE2 W rite enable delay to EAB for regis te red input
tEABRE1 R ead enable delay to EAB for com binat orial input
tEABRE2 R ead enable delay to EAB for regi stered input
tEABCLK EAB regist er cl o ck del a y
tEABCO EAB register clock-to-output delay
tEABBYPASS Bypa ss r egi ster delay
tEABSU EAB register setup t im e bef ore c loc k
tEABH EAB register hold time af t er cl ock
tEABCLR EAB register async hronous clear ti me to output delay
tAA Addres s acc es s de lay (inclu ding the read enabl e to output delay)
tWP Wr i te pulse wi dth
tRP Read pul se width
tWDSU D ata setup t im e bef ore f alling edge of write pulse (5)
tWDH D ata hold ti me after fa lling edge of write pulse (5)
tWASU Address setup time before rising edge of write pulse (5)
tWAH Address hold time af te r falli ng edge of write pulse (5)
tRASU Address setup time before rising edge of read pulse
tRAH Address hold time af te r falli ng edge of read pulse
tWO Write enable to data outpu t valid delay
tDD Data-in to data -out va lid delay
tEABOUT D ata -out delay
tEABCH C loc k hig h time
tEABCL Clock low time
Altera Corporation 57
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Table 25. EAB Timing Macroparameters Notes (1), (6)
Symbol Parameter Conditions
tEABAA EA B address acces s dela y
tEABRCCOMB EA B as yn ch ronous read cycle time
tEABRCREG EAB synchronous read cycle time
tEABWP EAB write pulse width
tEABWCCOMB EAB asyn ch ronous write cycle time
tEABWCREG EAB synchronous write cycle time
tEABDD EA B dat a-in to data-out valid delay
tEABDATACO EA B cl ock-t o-output delay whe n us ing out put regis t ers
tEABDATASU EA B dat a/ address setup time before clock wh en us ing input register
tEABDATAH EA B dat a/ address hold time af te r clock wh en us ing input register
tEABWESU EAB WE setup time before clock wh en us ing input register
tEABWEH EAB WE hold time af te r clock whe n us ing input register
tEABWDSU EA B dat a se tu p time bef ore falling edge of write puls e whe n not usin g input
registers
tEABWDH EAB data hold time after falling edge of write pulse when not using input
registers
tEABWASU EA B address setup time before rising edge of write pulse wh en not usin g
input registers
tEABWAH EA B address hold time after falli ng edge of write pulse when not usin g input
registers
tEABWO EA B w rite enable to data output va lid delay
58 Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
Notes to tables:
(1) Micr oparameter s ar e t iming de la y s c o n t ri buted by ind ividua l a r c hi t ec t ur al ele ments. T h es e parameters c a n not be
mea s ured expli c itly.
(2) Ope ra ting conditi o ns: VCCIO = 3.3 V ± 10% for commercia l or industrial and extended use in ACEX 1K device s
(3) Ope ra ting conditi o ns: VCCIO = 2.5 V ± 5% for com mercial or industrial and ext en ded use in ACEX 1K d evices.
(4) Ope ra ting conditi o ns: VCCIO = 2.5 V or 3.3 V.
(5) Because the RAM in the EAB is self-timed, this parameter can be ignored when the WE signal is registered.
(6) EAB macroparameters are internal parameters that can simplify predicting the behavior of an EAB at its boundary;
t hese paramet ers are calcul ated by summing s elected mi c r opar a meters.
(7) These parameters are worst-case values for typical applications. Post-compilation timing simulation and timing
analysis are required to determine actual worst-case performance.
Table 26. Interconnect Timing Microparameters Note (1)
Symbol Parameter Conditions
tDIN2IOE D elay fro m ded ic ate d input pin t o IOE con tro l input (7)
tDIN2LE D elay fro m ded ic ate d input pin t o LE or EAB c ont rol input (7)
tDIN2DATA Delay fro m ded ic ate d input or clo ck to LE or EAB data (7)
tDCLK2IOE Delay fro m ded ic ate d clo ck pin t o IOE clock (7)
tDCLK2LE D elay fro m ded ic ate d clo ck pin t o LE or EAB c loc k (7)
tSAMELAB Routing delay for an LE drivin g anot her LE in the same LAB (7)
tSAMEROW Routing delay for a row IOE, LE, or EAB driving a row IOE, LE, or EAB in the
same row (7)
tSAMECOLUMN Routing delay for an LE drivin g an IO E in the same c olum n (7)
tDIFFROW Routing delay for a column IOE, LE, or EAB driving an LE or EAB in a different
row (7)
tTWOROWS Routing delay for a row IOE or EAB driv ing an LE or EAB in a different row (7)
tLEPERIPH Routing delay for an LE drivin g a con tro l sign al of an IOE via th e peripheral
control bus (7)
tLABCARRY Routing delay for the carry-out signal of an LE driving the carry-in signal of a
different LE in a dif fer ent LAB
tLABCASC Routing delay for the cascade-out signal of an LE driv ing t he c as cad e-in
signal of a different LE in a different LAB
Altera Corporation 59
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Tables 27 through 29 describe the ACEX 1K external timing parameters
and their symbols.
Notes to table s:
(1) External reference timing parameters are factory-tested, worst-case values specified by Altera. A representative
subset of signal paths is test ed t o ap prox i mate typical devic e ap pl ications.
(2) Contact Altera Applications for test circuit specific atio ns and test conditions.
(3) These timing parameters are sample-tested only.
(4) This parameter is measured with the measurement and test conditions, including load, specified in the PCI Local
Bus Spe c ification, Revi s ion 2. 2.
Table 27. External Reference Timing Parameters Note (1)
Symbol Parameter Conditions
tDRR Register-to-register delay via four LEs, three row interconnects, and four local
interconnects (2)
Table 28. External Timing Parameters
Symbol Parameter Conditions
tINSU Setup time with global clock at IOE regist er (3)
tINH Hold time wi th glo bal c loc k at IOE regis te r (3)
tOUTCO C loc k -t o-out put delay with global clock at IOE regist er (3)
tPCISU Setup time with global clock for registers us ed in PC I de signs (3), (4)
tPCIH H old time with global c loc k for regis t ers use d in PC I designs (3), (4)
tPCICO C loc k -t o-out put delay with global clock for registers us ed in PC I de sig ns (3), (4)
Table 29. External Bidirectional Timing Parameters Note (3)
Symbol Parameter Conditions
tINSUBIDIR Setu p time f or bidirectional pins with global clock at same-row or same-
column LE register
tINHBIDIR Hold time for bidirectional pins with global clock at same-row or same-column
LE register
tOUTCOBIDIR Clock -t o-out put delay for bidire ctional pins with glob al cl ock at IOE regis te r CI = 35 pF
tXZBIDIR Sy nc hronous IOE out put buf fe r dis able delay CI = 35 pF
tZXBIDIR Sy nc hronous IOE out put buf fe r enable delay, slow sl ew rate = off CI = 35 pF
60 Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
Tables 30 through 36 show EP1K10 device in ternal and extern al timing
parameters.
Table 30. EP1K10 Devi ce LE Ti min g Micr oparameters Note (1)
Sym bol Speed Gra de Uni t
-1 -2 -3
Min Max Min Max Min Max
tLUT 0.7 0.8 1.1 ns
tCLUT 0.5 0.6 0.8 ns
tRLUT 0.6 0.7 1.0 ns
tPACKED 0.4 0.4 0.5 ns
tEN 0.9 1.0 1.3 ns
tCICO 0.1 0.1 0.2 ns
tCGEN 0.4 0.5 0.7 ns
tCGENR 0.1 0.1 0.2 ns
tCASC 0.7 0.9 1.1 ns
tC1.1 1.3 1.7 ns
tCO 0.5 0.7 0.9 ns
tCOMB 0.4 0.5 0.7 ns
tSU 0.7 0.8 1.0 ns
tH0.9 1.0 1.1 ns
tPRE 0.8 1.0 1.4 ns
tCLR 0.9 1.0 1.4 ns
tCH 2.0 2.5 2.5 ns
tCL 2.0 2.5 2.5 ns
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Table 31. EP1K10 Device IOE Timing Microparameters Note (1)
Symbol Speed Grade Unit
-1 -2 -3
Min Max Min Max Min Max
tIOD 2.6 3.1 4.0 ns
tIOC 0.3 0.4 0.5 ns
tIOCO 0.9 1.0 1.4 ns
tIOCOMB 0.0 0.0 0.0 ns
tIOSU 1.3 1.5 2.0 ns
tIOH 0.9 1.0 1.4 ns
tIOCLR 1.1 1.3 1.7 ns
tOD1 3.1 3.7 4.1 ns
tOD2 2.6 3.3 3.9 ns
tOD3 5.8 6.9 8.3 ns
tXZ 3.8 4.5 5.9 ns
tZX1 3.8 4.5 5.9 ns
tZX2 3.3 4.1 5.7 ns
tZX3 6.5 7.7 10.1 ns
tINREG 3.7 4.3 5.7 ns
tIOFD 0.9 1.0 1.4 ns
tINCOMB 1.9 2.3 3.0 ns
62 Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
Table 32. EP1K10 Device EA B I nternal Mi crop aram et ers Note (1)
Sym bol Speed Gra de Uni t
-1 -2 -3
Min Max Min Max Min Max
tEABDATA1 1.8 1.9 1.9 ns
tEABDATA2 0.6 0.7 0.7 ns
tEABWE1 1.2 1.2 1.2 ns
tEABWE2 0.4 0.4 0.4 ns
tEABRE1 0.9 0.9 0.9 ns
tEABRE2 0.4 0.4 0.4 ns
tEABCLK 0.0 0.0 0.0 ns
tEABCO 0.3 0.3 0.3 ns
tEABBYPASS 0.5 0.6 0.6 ns
tEABSU 1.0 1.0 1.0 ns
tEABH 0.5 0.4 0.4 ns
tEABCLR 0.3 0.3 0.3 ns
tAA 3.4 3.6 3.6 ns
tWP 2.7 2.8 2.8 ns
tRP 1.0 1.0 1.0 ns
tWDSU 1.0 1.0 1.0 ns
tWDH 0.1 0.1 0.1 ns
tWASU 1.8 1.9 1.9 ns
tWAH 1.9 2.0 2.0 ns
tRASU 3.1 3.5 3.5 ns
tRAH 0.2 0.2 0.2 ns
tWO 2.7 2.8 2.8 ns
tDD 2.7 2.8 2.8 ns
tEABOUT 0.5 0.6 0.6 ns
tEABCH 1.5 2.0 2.0 ns
tEABCL 2.7 2.8 2.8 ns
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Table 33. EP1K10 Device EAB Internal Timing Macroparameters Note (1)
Symbol Speed Grade Unit
-1 -2 -3
Min Max Min Max Min Max
tEABAA 6.7 7.3 7.3 ns
tEABRCCOMB 6.7 7.3 7.3 ns
tEABRCREG 4.7 4.9 4.9 ns
tEABWP 2.7 2.8 2.8 ns
tEABWCCOMB 6.4 6.7 6.7 ns
tEABWCREG 7.4 7.6 7.6 ns
tEABDD 6.0 6.5 6.5 ns
tEABDATACO 0.8 0.9 0.9 ns
tEABDATASU 1.6 1.7 1.7 ns
tEABDATAH 0.0 0.0 0.0 ns
tEABWESU 1.4 1.4 1.4 ns
tEABWEH 0.1 0.0 0.0 ns
tEABWDSU 1.6 1.7 1.7 ns
tEABWDH 0.0 0.0 0.0 ns
tEABWASU 3.1 3.4 3.4 ns
tEABWAH 0.6 0.5 0.5 ns
tEABWO 5.4 5.8 5.8 ns
64 Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
Table 34. EP1K10 Devi ce Interconnect Tim i ng Mi crop arameter s Note (1)
Sym bol Speed Gra de Uni t
-1 -2 -3
Min Max Min Max Min Max
tDIN2IOE 2.3 2.7 3.6 ns
tDIN2LE 0.8 1.1 1.4 ns
tDIN2DATA 1.1 1.4 1.8 ns
tDCLK2IOE 2.3 2.7 3.6 ns
tDCLK2LE 0.8 1.1 1.4 ns
tSAMELAB 0.1 0.1 0.2 ns
tSAMEROW 1.8 2.1 2.9 ns
tSAMECOLUMN 0.3 0.4 0.7 ns
tDIFFROW 2.1 2.5 3.6 ns
tTWOROWS 3.9 4.6 6.5 ns
tLEPERIPH 3.3 3.7 4.8 ns
tLABCARRY 0.3 0.4 0.5 ns
tLABCASC 0.9 1.0 1.4 ns
Table 35. EP1K10 External Timing Param et ers Note (1)
Sym bol Speed Gra de Uni t
-1 -2 -3
Min Max Min Max Min Max
tDRR 7.5 9.5 12.5 ns
tINSU (2), (3) 2.4 2.7 3.6 ns
tINH (2), (3) 0.0 0.0 0.0 ns
tOUTCO (2), (3) 2.0 6.6 2.0 7.8 2.0 9.6 ns
tINSU (4), (3) 1.4 1.7 – ns
tINH (4), (3) 0.5 5.1 0.5 6.4 – – ns
tOUTCO (4), (3) 0.0 0.0 – ns
tPCISU (3) 3.0 4.2 6.4 ns
tPCIH (3) 0.0 0.0 – ns
tPCICO (3) 2.0 6.0 2.0 7.5 2.0 10.2 ns
Altera Corporation 65
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Notes to table s:
(1) All timing parameters are described in Tables 22 through 29 in thi s da ta sh eet.
(2) This parameter is measured without the use of the ClockLock or ClockBoost circuits.
(3) Th ese paramete rs are specified b y char ac ter iz at ion.
(4) This parameter is measured with the use of the ClockLock or ClockBoost circuits.
Tables 37 through 43 show EP1K30 device internal and external timing
parameters.
Table 36. EP1K10 External Bidirectional Timing Parameters Notes (1), (3)
Symbol Speed Grade Unit
-1 -2 -3
Min Max Min Max Min Max
tINSUBIDIR (2) 2.2 2.3 3.2 ns
tINHBIDIR (2) 0.0 0.0 0.0 ns
tOUTCOBIDIR (2) 2.0 6.6 2.0 7.8 2.0 9.6 ns
tXZBIDIR (2) 8.8 11.2 14.0 ns
tZXBIDIR (2) 8.8 11.2 14.0 ns
tINSUBIDIR (4) 3.1 3.3 – –
tINHBIDIR (4) 0.0 0.0 –
tOUTCOBIDIR (4) 0.5 5.1 0.5 6.4 – – ns
tXZBIDIR(4) 7.3 9.2 – ns
tZXBIDIR (4) 7.3 9.2 – ns
Table 37. EP1K30 Device LE Timing Microparameters (Part 1 of 2) Note (1)
Symbol Speed Grade Unit
-1 -2 -3
Min Max Min Max Min Max
tLUT 0.7 0.8 1.1 ns
tCLUT 0.5 0.6 0.8 ns
tRLUT 0.6 0.7 1.0 ns
tPACKED 0.3 0.4 0.5 ns
tEN 0.6 0.8 1.0 ns
tCICO 0.1 0.1 0.2 ns
tCGEN 0.4 0.5 0.7 ns
tCGENR 0.1 0.1 0.2 ns
tCASC 0.6 0.8 1.0 ns
tC0.0 0.0 0.0 ns
tCO 0.3 0.4 0.5 ns
66 Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
tCOMB 0.4 0.4 0.6 ns
tSU 0.4 0.6 0.6 ns
tH0.7 1.0 1.3 ns
tPRE 0.8 0.9 1.2 ns
tCLR 0.8 0.9 1.2 ns
tCH 2.0 2.5 2.5 ns
tCL 2.0 2.5 2.5 ns
Table 38. EP1K30 Device IOE Timing Microparameters Note (1)
Sym bol Speed Gra de Uni t
-1 -2 -3
Min Max Min Max Min Max
tIOD 2.4 2.8 3.8 ns
tIOC 0.3 0.4 0.5 ns
tIOCO 1.0 1.1 1.6 ns
tIOCOMB 0.0 0.0 0.0 ns
tIOSU 1.2 1.4 1.9 ns
tIOH 0.3 0.4 0.5 ns
tIOCLR 1.0 1.1 1.6 ns
tOD1 1.9 2.3 3.0 ns
tOD2 1.4 1.8 2.5 ns
tOD3 4.4 5.2 7.0 ns
tXZ 2.7 3.1 4.3 ns
tZX1 2.7 3.1 4.3 ns
tZX2 2.2 2.6 3.8 ns
tZX3 5.2 6.0 8.3 ns
tINREG 3.4 4.1 5.5 ns
tIOFD 0.8 1.3 2.4 ns
tINCOMB 0.8 1.3 2.4 ns
Table 37. EP1K30 Devi ce LE Ti min g Microparameters (Part 2 o f 2) Note (1)
Sym bol Speed Gra de Uni t
-1 -2 -3
Min Max Min Max Min Max
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Table 39. EP1K30 Device EAB Internal Microparameters Note (1)
Symbol Speed Grade Unit
-1 -2 -3
Min Max Min Max Min Max
tEABDATA1 1.7 2.0 2.3 ns
tEABDATA1 0.6 0.7 0.8 ns
tEABWE1 1.1 1.3 1.4 ns
tEABWE2 0.4 0.4 0.5 ns
tEABRE1 0.8 0.9 1.0 ns
tEABRE2 0.4 0.4 0.5 ns
tEABCLK 0.0 0.0 0.0 ns
tEABCO 0.3 0.3 0.4 ns
tEABBYPASS 0.5 0.6 0.7 ns
tEABSU 0.9 1.0 1.2 ns
tEABH 0.4 0.4 0.5 ns
tEABCLR 0.3 0.3 0.3 ns
tAA 3.2 3.8 4.4 ns
tWP 2.5 2.9 3.3 ns
tRP 0.9 1.1 1.2 ns
tWDSU 0.9 1.0 1.1 ns
tWDH 0.1 0.1 0.1 ns
tWASU 1.7 2.0 2.3 ns
tWAH 1.8 2.1 2.4 ns
tRASU 3.1 3.7 4.2 ns
tRAH 0.2 0.2 0.2 ns
tWO 2.5 2.9 3.3 ns
tDD 2.5 2.9 3.3 ns
tEABOUT 0.5 0.6 0.7 ns
tEABCH 1.5 2.0 2.3 ns
tEABCL 2.5 2.9 3.3 ns
68 Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
Table 40. EP1K30 Devi ce EA B I nternal Timing Macroparame t ers Note (1)
Sym bol Speed Gra de Uni t
-1 -2 -3
Min Max Min Max Min Max
tEABAA 6.4 7.6 8.8 ns
tEABRCOMB 6.4 7.6 8.8 ns
tEABRCREG 4.4 5.1 6.0 ns
tEABWP 2.5 2.9 3.3 ns
tEABWCOMB 6.0 7.0 8.0 ns
tEABWCREG 6.8 7.8 9.0 ns
tEABDD 5.7 6.7 7.7 ns
tEABDATACO 0.8 0.9 1.1 ns
tEABDATASU 1.5 1.7 2.0 ns
tEABDATAH 0.0 0.0 0.0 ns
tEABWESU 1.3 1.4 1.7 ns
tEABWEH 0.0 0.0 0.0 ns
tEABWDSU 1.5 1.7 2.0 ns
tEABWDH 0.0 0.0 0.0 ns
tEABWASU 3.0 3.6 4.3 ns
tEABWAH 0.5 0.5 0.4 ns
tEABWO 5.1 6.0 6.8 ns
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Table 41. EP1K30 Device Interconnect Timing Microparameters Note (1)
Symbol Speed Grade Unit
-1 -2 -3
Min Max Min Max Min Max
tDIN2IOE 1.8 2.4 2.9 ns
tDIN2LE 1.5 1.8 2.4 ns
tDIN2DATA 1.5 1.8 2.2 ns
tDCLK2IOE 2.2 2.6 3.0 ns
tDCLK2LE 1.5 1.8 2.4 ns
tSAMELAB 0.1 0.2 0.3 ns
tSAMEROW 2.0 2.4 2.7 ns
tSAMECOLUMN 0.7 1.0 0.8 ns
tDIFFROW 2.7 3.4 3.5 ns
tTWOROWS 4.7 5.8 6.2 ns
tLEPERIPH 2.7 3.4 3.8 ns
tLABCARRY 0.3 0.4 0.5 ns
tLABCASC 0.8 0.8 1.1 ns
Table 42. EP1K30 External Timing Parameters Not es (1), (2)
Symbol Speed Grade Unit
-1 -2 -3
Min Max Min Max Min Max
tDRR 8.0 9.5 12.5 ns
tINSU (3) 2.1 2.5 3.9 ns
tINH (3) 0.0 0.0 0.0 ns
tOUTCO (3) 2. 0 4.9 2.0 5.9 2. 0 7.6 ns
tINSU (4) 1.1 1.5 – ns
tINH (4) 0.0 0.0 – ns
tOUTCO (4) 0.5 3.9 0.5 4.9 – – ns
tPCISU 3.0 4.2 – ns
tPCIH 0.0 0.0 – ns
tPCICO 2.0 6.0 2.0 7.5 – – ns
70 Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
Notes to tables:
(1) All timing parameters are described in Tables 22 through 29 in this data sheet.
(2) The se paramet er s ar e spe c ifi ed by char acterizati o n .
(3) This param eter is measured without the use of the Clock L ock or Clock B oost circuits.
(4) Thi s param eter is measured w ith the u se of t he Clock L ock or ClockBoost circuits.
Tables 44 through 50 show EP1 K50 de vice external t iming parame ters.
Table 43. EP1K30 Extern al Bidirect i onal Timing Parameter s Notes (1), (2)
Sym bol Speed Gra de Uni t
-1 -2 -3
Min Max Min Max Min Max
tINSUBIDIR (3) 2.8 3.9 5.2 ns
tINHBIDIR (3) 0.0 0.0 0.0 ns
tINSUBIDIR (4) 3.8 4.9 – ns
tINHBIDIR (4) 0.0 0.0 – ns
tOUTCOBIDIR (3) 2.0 4.9 2.0 5.9 2.0 7.6 ns
tXZBIDIR (3) 6.1 7.5 9.7 ns
tZXBIDIR (3) 6.1 7.5 9.7 ns
tOUTCOBIDIR (4) 0.5 3.9 0.5 4.9 – – ns
tXZBIDIR (4) 5.1 6.5 – ns
tZXBIDIR (4) 5.1 6.5 – ns
Table 44. EP1K50 Devi ce LE Ti min g Microparameters (Part 1 o f 2) No te (1)
Sym bol Speed Gra de Uni t
-1 -2 -3
Min Max Min Max Min Max
tLUT 0.6 0.8 1.1 ns
tCLUT 0.5 0.6 0.8 ns
tRLUT 0.6 0.7 0.9 ns
tPACKED 0.2 0.3 0.4 ns
tEN 0.6 0.7 0.9 ns
tCICO 0.1 0.1 0.1 ns
tCGEN 0.4 0.5 0.6 ns
tCGENR 0.1 0.1 0.1 ns
tCASC 0.5 0.8 1.0 ns
tC0.5 0.6 0.8 ns
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tCO 0.6 0.6 0.7 ns
tCOMB 0.3 0.4 0.5 ns
tSU 0.5 0.6 0.7 ns
tH0.5 0.6 0.8 ns
tPRE 0.4 0.5 0.7 ns
tCLR 0.8 1.0 1.2 ns
tCH 2.0 2.5 3.0 ns
tCL 2.0 2.5 3.0 ns
Table 45. EP1K50 Device IOE Timing Microparameters Note (1)
Symbol Speed Grade Unit
-1 -2 -3
Min Max Min Max Min Max
tIOD 1.3 1.3 1.9 ns
tIOC 0.3 0.4 0.4 ns
tIOCO 1.7 2.1 2.6 ns
tIOCOMB 0.5 0.6 0.8 ns
tIOSU 0.8 1.0 1.3 ns
tIOH 0.4 0.5 0.6 ns
tIOCLR 0.2 0.2 0.4 ns
tOD1 1.2 1.2 1.9 ns
tOD2 0.7 0.8 1.7 ns
tOD3 2.7 3.0 4.3 ns
tXZ 4.7 5.7 7.5 ns
tZX1 4.7 5.7 7.5 ns
tZX2 4.2 5.3 7.3 ns
tZX3 6.2 7.5 9.9 ns
tINREG 3.5 4.2 5.6 ns
tIOFD 1.1 1.3 1.8 ns
tINCOMB 1.1 1.3 1.8 ns
Table 44. EP1K50 Device LE Timing Microparameters (Part 2 of 2) Note (1)
Symbol Speed Grade Unit
-1 -2 -3
Min Max Min Max Min Max
72 Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
Table 46. EP1K50 Device EA B I nternal Mi crop aram et ers Note (1)
Sym bol Speed Gra de Uni t
-1 -2 -3
Min Max Min Max Min Max
tEABDATA1 1.7 2.4 3.2 ns
tEABDATA2 0.4 0.6 0.8 ns
tEABWE1 1.0 1.4 1.9 ns
tEABWE2 0.0 0.0 0.0 ns
tEABRE1 0.0 0.0 0.0
tEABRE2 0.4 0.6 0.8
tEABCLK 0.0 0.0 0.0 ns
tEABCO 0.8 1.1 1.5 ns
tEABBYPASS 0.0 0.0 0.0 ns
tEABSU 0.7 1.0 1.3 ns
tEABH 0.4 0.6 0.8 ns
tEABCLR 0.8 1.1 1.5
tAA 2.0 2.8 3.8 ns
tWP 2.0 2.8 3.8 ns
tRP 1.0 1.4 1.9
tWDSU 0.5 0.7 0.9 ns
tWDH 0.1 0.1 0.2 ns
tWASU 1.0 1.4 1.9 ns
tWAH 1.5 2.1 2.9 ns
tRASU 1.5 2.1 2.8
tRAH 0.1 0.1 0.2
tWO 2.1 2.9 4.0 ns
tDD 2.1 2.9 4.0 ns
tEABOUT 0.0 0.0 0.0 ns
tEABCH 1.5 2.0 2.5 ns
tEABCL 1.5 2.0 2.5 ns
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Table 47. EP1K50 Device EAB Internal Timing Macroparameters Note (1)
Symbol Speed Grade Unit
-1 -2 -3
Min Max Min Max Min Max
tEABAA 3.7 5.2 7.0 ns
tEABRCCOMB 3.7 5.2 7.0 ns
tEABRCREG 3.5 4.9 6.6 ns
tEABWP 2.0 2.8 3.8 ns
tEABWCCOMB 4.5 6.3 8.6 ns
tEABWCREG 5.6 7.8 10.6 ns
tEABDD 3.8 5.3 7.2 ns
tEABDATACO 0.8 1.1 1.5 ns
tEABDATASU 1.1 1.6 2.1 ns
tEABDATAH 0.0 0.0 0.0 ns
tEABWESU 0.7 1.0 1.3 ns
tEABWEH 0.4 0.6 0.8 ns
tEABWDSU 1.2 1.7 2.2 ns
tEABWDH 0.0 0.0 0.0 ns
tEABWASU 1.6 2.3 3.0 ns
tEABWAH 0.9 1.2 1.8 ns
tEABWO 3.1 4.3 5.9 ns
74 Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
Table 48. EP1K50 Devi ce Interconnect Tim i ng Mi crop arameter s Note (1)
Sym bol Speed Gra de Uni t
-1 -2 -3
Min Max Min Max Min Max
tDIN2IOE 3.1 3.7 4.6 ns
tDIN2LE 1.7 2.1 2.7 ns
tDIN2DATA 2.7 3.1 5.1 ns
tDCLK2IOE 1.6 1.9 2.6 ns
tDCLK2LE 1.7 2.1 2.7 ns
tSAMELAB 0.1 0.1 0.2 ns
tSAMEROW 1.5 1.7 2.4 ns
tSAMECOLUMN 1.0 1.3 2.1 ns
tDIFFROW 2.5 3.0 4.5 ns
tTWOROWS 4.0 4.7 6.9 ns
tLEPERIPH 2.6 2.9 3.4 ns
tLABCARRY 0.1 0.2 0.2 ns
tLABCASC 0.8 1.0 1.3 ns
Table 49. EP1K50 External Timing Param et ers Note (1)
Sym bol Speed Gra de Uni t
-1 -2 -3
Min Max Min Max Min Max
tDRR 8.0 9.5 12.5 ns
tINSU (2) 2.4 2.9 3.9 ns
tINH (2) 0.0 0.0 0.0 ns
tOUTCO (2) 2.0 4.3 2.0 5.2 2. 0 7.3 ns
tINSU (3) 2.4 2.9 – ns
tINH (3) 0.0 0.0 – ns
tOUTCO (3) 0.5 3.3 0.5 4.1 – – ns
tPCISU 2.4 2.9 – ns
tPCIH 0.0 0.0 – ns
tPCICO 2.0 6.0 2.0 7.7 – – ns
Altera Corporation 75
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Notes to table s:
(1) All timing parameters are described in Tables 22 through 29.
(2) This parameter is measured without use of the ClockLock or ClockBoost circuits.
(3) Th is p arameter is measu red with use of the Cl oc kLo c k or Clock Boost circuits
Table 50. EP1K50 External Bidirectional Timing Parameters No te (1)
Symbol Speed Grade Unit
-1 -2 -3
Min Max Min Max Min Max
tINSUBIDIR (2) 2.7 3.2 4.3 ns
tINHBIDIR (2) 0.0 0.0 0.0 ns
tINSUBIDIR (3) 3.7 4.2 – ns
tINHBIDIR (3) 0.0 0.0 – ns
tOUTCOBIDIR (2) 2.0 4.5 2.0 5.2 2.0 7.3 ns
tXZBIDIR (2) 6.8 7.8 10.1 ns
tZXBIDIR (2) 6.8 7.8 10.1 ns
tOUTCOBIDIR (3) 0.5 3.5 0.5 4.2 – –
tXZBIDIR (3) 6.8 8.4 – ns
tZXBIDIR (3) 6.8 8.4 – ns
76 Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
Tables 51 through 57 show E P1K 1 00 d evice inter nal and exte rn al ti mi ng
parameters.
Table 51. EP1K100 Dev i ce LE Timing Micro parameter s Note (1)
Sym bol Speed Gra de Uni t
-1 -2 -3
Min Max Min Max Min Max
tLUT 0.7 1.0 1.5 ns
tCLUT 0.5 0.7 0.9 ns
tRLUT 0.6 0.8 1.1 ns
tPACKED 0.3 0.4 0.5 ns
tEN 0.2 0.3 0.3 ns
tCICO 0.1 0.1 0.2 ns
tCGEN 0.4 0.5 0.7 ns
tCGENR 0.1 0.1 0.2 ns
tCASC 0.6 0.9 1.2 ns
tC0.8 1.0 1.4 ns
tCO 0.6 0.8 1.1 ns
tCOMB 0.4 0.5 0.7 ns
tSU 0.4 0.6 0.7 ns
tH0.5 0.7 0.9 ns
tPRE 0.8 1.0 1.4 ns
tCLR 0.8 1.0 1.4 ns
tCH 1.5 2.0 2.5 ns
tCL 1.5 2.0 2.5 ns
Altera Corporation 77
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Table 52. EP1K100 Device IOE Timing Microparameters Note (1)
Symbol Speed Grade Unit
-1 -2 -3
Min Max Min Max Min Max
tIOD 1.7 2.0 2.6 ns
tIOC 0.0 0.0 0.0 ns
tIOCO 1.4 1.6 2.1 ns
tIOCOMB 0.5 0.7 0.9 ns
tIOSU 0.8 1.0 1.3 ns
tIOH 0.7 0.9 1.2 ns
tIOCLR 0.5 0.7 0.9 ns
tOD1 3.0 4.2 5.6 ns
tOD2 3.0 4.2 5.6 ns
tOD3 4.0 5.5 7.3 ns
tXZ 3.5 4.6 6.1 ns
tZX1 3.5 4.6 6.1 ns
tZX2 3.5 4.6 6.1 ns
tZX3 4.5 5.9 7.8 ns
tINREG 2.0 2.6 3.5 ns
tIOFD 0.5 0.8 1.2 ns
tINCOMB 0.5 0.8 1.2 ns
78 Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
Table 53. EP1K100 Device EAB Internal Microparameters No te (1)
Sym bol Speed Gra de Uni t
-1 -2 -3
Min Max Min Max Min Max
tEABDATA1 1.5 2.0 2.6 ns
tEABDATA1 0.0 0.0 0.0 ns
tEABWE1 1.5 2.0 2.6 ns
tEABWE2 0.3 0.4 0.5 ns
tEABRE1 0.3 0.4 0.5 ns
tEABRE2 0.0 0.0 0.0 ns
tEABCLK 0.0 0.0 0.0 ns
tEABCO 0.3 0.4 0.5 ns
tEABBYPASS 0.1 0.1 0.2 ns
tEABSU 0.8 1.0 1.4 ns
tEABH 0.1 0.1 0.2 ns
tEABCLR 0.3 0.4 0.5 ns
tAA 4.0 5.1 6.6 ns
tWP 2.7 3.5 4.7 ns
tRP 1.0 1.3 1.7 ns
tWDSU 1.0 1.3 1.7 ns
tWDH 0.2 0.2 0.3 ns
tWASU 1.6 2.1 2.8 ns
tWAH 1.6 2.1 2.8 ns
tRASU 3.0 3.9 5.2 ns
tRAH 0.1 0.1 0.2 ns
tWO 1.5 2.0 2.6 ns
tDD 1.5 2.0 2.6 ns
tEABOUT 0.2 0.3 0.3 ns
tEABCH 1.5 2.0 2.5 ns
tEABCL 2.7 3.5 4.7 ns
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Table 54. EP1K100 Device EAB Internal Timing Macroparameters Note (1)
Symbol Speed Grade Unit
-1 -2 -3
Min Max Min Max Min Max
tEABAA 5.9 7.6 9.9 ns
tEABRCOMB 5.9 7.6 9.9 ns
tEABRCREG 5.1 6.5 8.5 ns
tEABWP 2.7 3.5 4.7 ns
tEABWCOMB 5.9 7.7 10.3 ns
tEABWCREG 5.4 7.0 9.4 ns
tEABDD 3.4 4.5 5.9 ns
tEABDATACO 0.5 0.7 0.8 ns
tEABDATASU 0.8 1.0 1.4 ns
tEABDATAH 0.1 0.1 0.2 ns
tEABWESU 1.1 1.4 1.9 ns
tEABWEH 0.0 0.0 0.0 ns
tEABWDSU 1.0 1.3 1.7 ns
tEABWDH 0.2 0.2 0.3 ns
tEABWASU 4.1 5.2 6.8 ns
tEABWAH 0.0 0.0 0.0 ns
tEABWO 3.4 4.5 5.9 ns
80 Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
Table 55. EP1K100 Device Interconnect Timing Microparameters Note (1)
Sym bol Speed Gra de Uni t
-1 -2 -3
Min Max Min Max Min Max
tDIN2IOE 3.1 3.6 4.4 ns
tDIN2LE 0.3 0.4 0.5 ns
tDIN2DATA 1.6 1.8 2.0 ns
tDCLK2IOE 0.8 1.1 1.4 ns
tDCLK2LE 0.3 0.4 0.5 ns
tSAMELAB 0.1 0.1 0.2 ns
tSAMEROW 1.5 2.5 3.4 ns
tSAMECOLUMN 0.4 1.0 1.6 ns
tDIFFROW 1.9 3.5 5.0 ns
tTWOROWS 3.4 6.0 8.4 ns
tLEPERIPH 4.3 5.4 6.5 ns
tLABCARRY 0.5 0.7 0.9 ns
tLABCASC 0.8 1.0 1.4 ns
Table 56. EP1K100 Externa l Ti min g Para mete rs Notes (1), (2)
Sym bol Speed Gra de Uni t
-1 -2 -3
Min Max Min Max Min Max
tDRR 9.0 12.0 16.0 ns
tINSU (3) 2.0 2.5 3.3 ns
tINH (3) 0.0 0.0 0.0 ns
tOUTCO (3) 2.0 5.2 2.0 6.9 2.0 9.1 ns
tINSU (4) 2.0 2.2 – ns
tINH (4) 0.0 0.0 – ns
tOUTCO (4) 0.5 3.0 0.5 4.6 – – ns
tPCISU 3.0 6.2 – ns
tPCIH 0.0 0.0 – ns
tPCICO 2.0 6.0 2.0 6.9 – – ns
Altera Corporation 81
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Notes to table s:
(1) All timing parameters are described in Tables 22 through 29 in thi s da ta sh eet.
(2) Th ese paramete rs are specified b y char ac ter iz at ion.
(3) This parameter is measured without the use of the ClockLock or ClockBoost circuits.
(4) This parameter is measured with the use of the ClockLock or ClockBoost circuits.
Power
Consumption
The supply power (P) for ACEX 1K devices can be calculated with the
followin g equation:
P = PINT + PIO = (ICCSTANDBY + ICCACTIVE) × VCC + PIO
The ICCACTIVE value depends on the switching frequency and the
appl ica tion log ic. Thi s va lue is ca lcula te d base d on the amou nt of curre nt
that each LE typically consumes. The PIO value, which depends on the
device output load characteristics and switching frequency, can be
calc ulated using the guidelin es given in Application Note 74 (Evaluating
Power for Altera Devices).
1Compa red t o the rest of the device, the embedde d arra y
consumes a negligible amount of power. Therefore, the
embedded array can be ignored when calculating supply
current.
Table 57. EP1K100 External Bidirectional Timing Parameters Not es (1) , (2)
Symbol Speed Grade Unit
-1 -2 -3
Min Max Min Max Min Max
tINSUBIDIR (3) 1.7 2.5 3.3 ns
tINHBIDIR (3) 0.0 0.0 0.0 ns
tINSUBIDIR (4) 2.0 2.8 – ns
tINHBIDIR (4) 0.0 0.0 – ns
tOUTCOBIDIR (3) 2.0 5.2 2.0 6.9 2.0 9.1 ns
tXZBIDIR (3) 5.6 7.5 10.1 ns
tZXBIDIR (3) 5.6 7.5 10.1 ns
tOUTCOBIDIR (4) 0.5 3.0 0.5 4.6 – – ns
tXZBIDIR (4) 4.6 6.5 – ns
tZXBIDIR (4) 4.6 6.5 – ns
82 Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
The ICCACTIVE value can be calculated with the following equation:
ICCACTIVE = K × fMAX × N × togLC (µA)
Where:
fMAX = Maximum operating frequency in MHz
N = Total number of LEs used in the device
togLC = Average percent of LEs toggling at each clock
(t ypical ly 12.5%)
K = Constant
Table 58 provides the constant (K) values for ACEX 1K devices.
This supply power calculation provides an ICC estimate based on typical
conditions with no output load. The actual ICC should be verified during
operation because this measurement is sensitive to the actual pattern in
the devi ce and the environmental operating conditions.
To better reflect actual designs, the power model (and the constant K in
the power calculation equations) for continuous interconnect ACEX 1K
devices assumes that LEs drive FastTrack Interconnect channels. In
contrast, the power model of segmented FPGAs assumes that all LEs drive
only one short interconnect segment. This assumption may lead to
inaccurate results when compared to measured power consumption for
actual designs in segmented FPGAs.
Figure 31 shows the relationship between the current and operating
frequency of ACEX 1K devices. For information on other ACEX 1K
devices, contact Altera Applications at (800) 800-EPLD.
Table 58. ACEX 1K Constant Values
Device K Value
EP1K10 4.5
EP1K30 4.5
EP1K50 4.5
EP1K100 4.5
Altera Corporation 83
ACEX 1K Programmable Logic Device Family Data Sheet
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Figure 31 . ACEX 1 K I CCACTIVE vs. Operating Frequency
Configuration &
Operation
The ACEX 1K architecture supports several configuration schemes. This
section summarizes the device operating modes and available device
config urat ion sche mes.
Operating Modes
The ACEX 1K architecture uses SRAM configuration elements that
require confi gura tion data to b e loaded eve ry t ime t he cir cuit powe rs up.
The p ro ces s of p hys ica lly loa ding th e SRAM da ta into the d evic e is called
configuration. Before c onfigur at ion, as VCC rises, the device initiates a
Power-On Reset (POR). This POR event clears the device and prepares it
for configuration. The ACEX 1K POR time does not exceed 50 µs.
1When configuring with a configuration device, refer to the
relevant configuration device data sheet for POR timing
information.
0Frequency (MHz)
300
200
100
50 100
EP1K100
ICC
Supply
Current (mA)
0Frequency (MHz)
ICC
Supply
Current (mA)
100
80
60
40
20
50 100
EP1K30
0Frequency (MHz)
ICC
Supply
Current (mA)
200
150
100
50
50 100
EP1K50
84 Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
During initialization, which occurs immediately after configuration, the
device resets registers, enables I/O pins, and begins to operate as a logic
device . Befo re a nd during configurat i o n, all I/O pins (except dedicated
inputs, clock, or configuration pins) are pulled high by a weak pull-up
resistor. Together, the configuration and initialization processes are called
comman d mod e ; normal device operation is called user mode.
SRAM configurat ion elements allow ACEX 1K device s to be reconfi gured
in-circuit by loading new configuration data into the device. Real-time
reconfiguration is performed by forcing the device into command mode
with a device pin, loa d ing differen t confi gura tion data , re-init ial izin g th e
device, and resuming user -mode opera tion. The entire reconf igur atio n
process requires less than 40 ms and can be used to reconfigure an entire
system dyn amically. In-fie l d upgrades can be per f or med by distributing
new configuration files.
Configuration Schemes
The configuration data for an ACEX 1K device can be loaded with one of
five conf iguration schemes (s ee Table 59), ch osen on the basis of t he target
application. An EPC1 6, EPC2, EPC1, or EPC1 44 1 c o nfiguratio n device,
intelligent controller, or the JTAG port can be used to control the
configura tion of a ACEX 1K devic e, allow ing automat ic con figu ratio n on
system power-up.
Multiple ACEX 1K devices can be configured in any of the five
configuration schemes by connecting the configuration enable (nCE) and
configuration enable output (nCEO) pins on each device. Additional
APEX 20K, APEX 20KE, FLEX 10K, FLEX 10KA, FL EX 10KE, ACEX 1K,
and FLEX 6000 devices can be configured in the same serial chain.
Device Pin-
Outs See th e Alte ra we b site (http://www.altera.com) or the Altera Documen-
tation Library for pin-out information.
Table 59. D at a Sources f or ACEX 1K Configura t i on
Configuration Scheme Da ta Source
Configurat ion device EPC16 , EP C2 , EPC1, or EPC 1441 configuration device
Passive seria l (PS) BitBlast er or By te Blas t erM V dow nload cables, or seri al dat a
source
Passive parallel asynchro nous (PPA) Parallel dat a s ourc e
Passive parallel synchronous (PPS) Parallel data source
JTAG BitBlast er or By te Blas t erM V dow nload cables, or
microproc es s or w ith a Jam ST APL F ile or J BC File
Altera Corporation 85
ACEX 1K Programmable Logic Device Family Data Sheet
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Revision
History
The information contained in the ACEX 1K Programmable Logic Device
Fami ly Data Sh eet version 3.4 supersedes information published in
previous versions.
The following changes were made to the ACEX 1K Programmable Logic
Device Family Data Sheet version 3. 4: added ex tend ed temperatur e
support.
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