SY58605U
3.2Gbps Precision, LVDS Buffer w i th
Internal Te r mination and Fail Safe Input
Precision Edge is a registered tradem ark of Micrel, Inc.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
August 2007
M9999-082907-B
hbwhelp@micrel.com or (408) 955-1690
General Description
The SY58605U is a 2.5V, high-speed, fully differential
LVDS buffer optimized to provide less than 10pspp total
jitter. The SY58605U can process clock signals as fast
as 2GHz or data patterns up to 3.2Gbps.
The differential input includes Micrel’s unique, 3-pin
input termination ar ch itec tu r e that int erfaces to LV PEC L,
LVDS or CML differential signals, (AC- or DC-coupled)
as small as 100mV (200mVpp) without any level-shifting
or termination resistor networks in the signal path. For
AC-coupled input interface applications, an integrated
voltage reference (VREF-AC) is provided to bias the VT pin.
The output is 325mV LVDS, with rise/fall times
guaranteed to be less than 100ps.
The S Y58605U opera tes f rom a 2.5V ±5% suppl y and is
guaranteed over the full industrial temperature range
(–40°C to +85°C). For applications that require CML or
LVPECL outputs, consider Micrel’s SY58603U and
SY58604U, buffers with 400mV and 800mV output
swings respectively. The SY58605U is part of Micrel’s
high-speed, Precision Edge® pr oduct line.
Datasheets and supp ort do cumentati on can be f ound on
Micrel’s web site at: www.micrel.com.
Functional Block Diagram
Precision Edge®
Features
• Precision 325mV LVDS buffer
• Guaranteed AC performance over temperature and
voltage:
– DC-to > 3.2Gbps throughput
– <300ps typical propagation delay (IN-to-Q)
– <100ps rise/fall times
• Fail Safe Input
– Prevents output from oscillating when input is
invalid
• Ultra-low jitter design
– <1psRMS cycle-to-cycle jitter
– <10psPP total jitter
– <1psRMS random jitter
– <10psPP deterministic jitter
• High-speed LVDS output
• 2.5V ±5% power supply operation
• Industrial temperature range: –40°C to +85 °C
• Available in 8-pin (2mm x 2mm) DFN package
Applications
• All SONET clock and data distribution
• Fibre Channel clock and data distribution
• Gigabit Ether net c lock and data distribution
• Backplane dis tri but ion
Markets
• Storage
• ATE
• Test and measurement
• Enterprise networking equipment
• High-end servers
• Access
• Metro area network equipment
Micrel, Inc.
SY58605U
August 2007 2 M9999-082907-B
hbwhelp@micrel.com or (408) 955-1690
Ordering Information(1)
Part Number Package
Type Operating
Range Package Marking Lead
Finish
SY58605UMG DFN-8 Industrial 605 with Pb-Free
bar-line indicator NiPdAu
Pb-Free
SY58605UMGTR(2) DFN-8 Industrial 605 with Pb-Free
bar-line indicator NiPdAu
Pb-Free
Notes:
1. Contact f act ory for die availabi lit y. Dice are guaranteed at TA = 25°C, DC Electricals only.
2. Tape and Reel.
Pin Configuration
8-Pin DFN
Pin Description
Pin Number Pin Name Pin Function
1, 4 IN, /IN Differential Input: This input pair is the differential signal input to the device. Input
accepts DC-coupled differential signals as small as 100mV (200mVPP). Each pin of
this pair internally terminates with 50Ω to the VT pin. If the input swing falls bel ow a
certain threshold (typically 30mV), them the Fail Safe Input (FSI) feature will
guarantee a stable output by latching the output to its last valid state. See “Input
Interface Applications” subsection for more details.
2 VT Input Termination Center-Tap: Each input terminates to this pin. The VT pin provides
a center-tap for each input (IN, /IN) to a termination network for maximum interface
flexibility. See “Input Interface Applications” subsection for more details.
3 VREF-AC Reference Voltage: This output biases to VCC–1.2V. It is used for AC-co upl ing inp ut
IN and /IN. Connect VREF-AC directly to the VT pin. Bypass with 0.01µF low ESR
capacitor to VCC. Maximum sink/source current is ±1.5mA. See “Input Interface
Applicat ion s” subs ect ion for m ore details.
5 GND,
Exposed pad Ground: Exposed pad must be connected to a ground plane that is the same
potential as the ground pin.
6, 7 /Q, Q LVDS Differential Output Pair: The output swing is typically 325mV. Normally
terminated with 100Ω across the pair (Q, /Q). See “LVDS Output Termination”
subsection for more details.
8 VCC Positive Power Supply: Bypass with 0.1µF//0.01µF low ESR capacit ors as clo se to
the VCC pin as possible.
Micrel, Inc.
SY58605U
August 2007 3 M9999-082907-B
hbwhelp@micrel.com or (408) 955-1690
Absolute Maximum Ratings(1)
Supply Voltage (VCC) ............................... –0.5V to +4.0V
Input Voltage (VIN) ............................ –0.5V to VCC +0.3V
LVDS Output Current (IOUT) .................................. ±10mA
Input Current
Source or Sink Current on (IN, /IN) ............... ±50mA
Current (VREF)
Source or sink current on VREF-AC(4) .............. ±1.5mA
Maximum operating Junction Temperature .......... 125°C
Lead Temperature (soldering, 20sec.) .................. 260°C
Storage Temperature (Ts) .................... –65°C to +150°C
Operating Ratings(2)
Supply Voltage (VIN) ...................... +2.375V to +2.625V
Ambient Temperature (TA) ................... –40°C to +85°C
Package Thermal Resistance(3)
DFN
Still-air (θJA) ............................................ 93°C/W
Junction-to-board (ψJB) .......................... 56°C/W
DC Electrical Characteristics(5)
TA = –40°C to +85°C, unless otherwise stated.
Symbol Parameter Condition Min Typ Max Units
VCC Power Supply Voltage Range 2.375 2.5 2.625 V
ICC Power Supply Current No load, max. VCC 35 50 mA
RDIFF_IN Differential Input Resistance
(IN-to-/IN) 90 100 110 Ω
VIH Input HIGH Voltage
(IN, /IN) IN, /IN 1.2 VCC V
VIL Input LO W Voltage
(IN, /IN) IN, /IN 0 VIH–0.1 V
VIN Input Voltage Swing
(IN, /IN) see Figure 3a, Note 6 0.1 1.7 V
VDIFF_IN Differential Input Voltage Swing
(|IN - /IN|) see Figure 3b 0.2 V
VIN_FSI Input Voltage Threshold that
Triggers FSI 30 100 mV
VREF-AC Output Reference Voltage VCC–1.3 VCC–1.2 VCC–1.1 V
VT_IN Voltage from Input to VT 1.28 V
Notes:
1. Permanent device dam age may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not
implied at conditions other than those detailed i n the operational secti ons of this data sheet. E xposure to absol ut e maximum ratings conditi ons f or
extended periods may aff ect device reliabi l i t y.
2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.
3. Package thermal resist ance assumes exposed pad is sol dered (or equivalent) t o the devic e's most negative potent i al on the PCB. ψJB and θJA
values are determined for a 4-layer board in still-air num ber, unless otherwise s tated.
4. Due to the limited drive capabi lit y, use for input of the same package only.
5. The ci rcuit is designed to meet the DC specifications shown in the above table after therm al equilibrium has been est ablis hed.
6. VIN (max) is specified when VT is floating.
Micrel, Inc.
SY58605U
August 2007 4 M9999-082907-B
hbwhelp@micrel.com or (408) 955-1690
LVDS Output DC Electrical Characteristics(7)
VCC = +2.5V ±5%, RL = 100Ω across the outputs; TA = –40°C to +85°C, unless otherwise stated.
Symbol Parameter Condition Min Typ Max Units
VOUT Output Voltage Swing See Figure 3a 250 325 mV
VDIFF_OUT Differ ential Output Voltage Swing See Figure 3b 500 650 mV
VOCM Output Common Mode Voltage 1.125 1.20 1.275 V
ΔVOCM Change in Common Mode
Voltage -50 50 mV
Note:
7. The ci rcuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been establis hed.
Micrel, Inc.
SY58605U
August 2007 5 M9999-082907-B
hbwhelp@micrel.com or (408) 955-1690
AC Electrical Characteristics
VCC = +2.5V ±5%, RL = 100Ω across the outputs, Input tr/tf: <300ps; TA = –40°C to +85°C, unless otherwise stated.
Symbol Parameter Condition Min Typ Max Units
fMAX Maximum Frequency NRZ Data 3.2 Gbps
VOUT > 200mV Clock 2.0 3 GHz
tPD Propagation Delay IN-to-Q VIN: 100mV-200mV 170 280 420 ps
200mV-800mV 130 200 300 ps
tSkew Part-to-Part Skew Note 8 135 ps
tJitter Data Random Jitter Note 9 1 psRMS
Deterministic Jitter Note 10 10 psPP
Clo ck Cycle-to-Cycle Jitter Note 11 1 psRMS
Total Jitter Note 12 10 psPP
tr, tf Output Rise/Fall Times
(20% to 80%) At full output swing. 35 60 100 ps
Duty Cycle Differential I/O 47 53 %
Notes:
8. Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and no skew at the edges at the
respective inputs.
9. Random jitter is measured with a K28.7 pattern, measured at ≤ f
MAX.
10. Determini st ic jitter is m easured at 2.5Gbps with both K28.5 and 223–1 PRBS pattern.
11. Cycle-to-cycle jitter definition: the variation period bet ween adjacent cycl es over a random sample of adjacent c ycle pairs. tJITTER_CC = Tn –Tn+1,
where T is the time between rising edges of the output signal.
12. Total jitter definition: with an ideal clock input frequency of ≤ f
MAX (device), no more than one output edge in 1012 output edges will deviate by
more than the specified peak-to-peak jitter value.
Micrel, Inc.
SY58605U
August 2007 6 M9999-082907-B
hbwhelp@micrel.com or (408) 955-1690
Functional Description
Fail-Safe Input (FSI)
The input includes a special failsafe circuit to sense
the amplitude of the input signal and to latch the
outputs when there is no input signal present, or
when the amplitude of the input signal drops
sufficiently below 100mVPK (200mVPP), typically
30mVPK. Maximum frequency of SY58605U is limited
by the FSI function.
Input Clock Failure Case
If the input c lock fails to a float ing, static, or ex tremely
low signa l swing, th e FSI f unction will then el iminate a
metastable condition and guarantee a stable output.
No ringi ng and no undetermined state will oc cur at the
output under these conditions.
Note that the FSI function will not prevent duty cycle
distortion in case of a slowly deteriorating (but still
toggling) input signal. Due to the FSI function, the
propagation delay will depend on rise and fall time of
the input sig nal and on its amplitude . Refer to “T ypical
Characteristics” for detailed information.
Timing Diagrams
Figure 1a. Propagation De lay
Figure 1b. Fail Safe Feature
Micrel, Inc.
SY58605U
August 2007 11 M9999-082907-B
hbwhelp@micrel.com or (408) 955-1690
Input Interface Applications
Figure 4a. CML Interface
(DC-Coupled)
Option: May connect VT to VCC
Figure 4b. CML Interface
(AC-Coupled)
Figure 4c. LVPECL Interface
(DC-Coupled)
Figure 4d. LVPECL Interface
(AC-Coupled)
Figure 4e. LVDS Interface
Related Product and Support Documents
Part Number Function Data Sheet Link
SY58603U 4.25Gbps Precision CML Buffer with
Internal Termination and Fail Safe Input http://www.micrel.com/page.do?page=/product-
info/products/sy58603u.shtml
SY58604U 3.2Gbps Precision LVPECL Buffer with
Internal Termination and Fail Safe Input http://www.micrel.com/page.do?page=/product-
info/products/sy58604u.shtml
HBW Solutions New Products and Termination Application
Notes http://www.micrel.com/page.do?page=/product-
info/as/HBWsolutions.shtml
Micrel, Inc.
SY58605U
August 2007 12 M9999-082907-B
hbwhelp@micrel.com or (408) 955-1690
Package Information
8-Pin (2mm x 2mm) DFN
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http://w ww .micrel.com
The inf orm ation furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is ass um ed by Micrel for
its use. Micrel reserves the right to change circuit ry and specificati ons at any time without notification to the customer.
Micrel Products are not designed or authorized for use as components in life support applianc es, devices or s ys tems where malfunction of a
product can reasonably be expected to result in personal i nj ury. Lif e support devices or systems are devices or systems that (a) are intended for
surgical implant int o the body or (b) support or sustain life, and whose failure t o perf orm can be reasonably expected to result in a significant
injury to the user. A Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser’s own risk
and Purchaser agrees to fully indem nify Micrel for any damages resulting from such use or sale.
© 2006 Micrel, Incorporated.
