7130SA100CBG - INTEGRATED DEVICE TECHNOLOGY

Low-Voltage 64/256/512/1K/2K/4K/8K x 9 Synchronous FIFOs

CY7C4421V/4201V/4211V/4221V

CY7C4231V/4241V/4251V

Cypress Semiconductor Corporation • 3901 North First Street • San Jose,CA 95134 • 408-943-2600

Document #: 38-06010 Rev. *B Revised July 14, 2005

Featuresb

•High-speed, low-power, first-in, first-out (FIFO)

memories

•64 x 9 (CY7C4421V)

•256 x 9 (CY7C4201V)

•512 x 9 (CY7C4211V)

•1K x 9 (CY7C4221V)

•2K x 9 (CY7C4231V)

•4K x 9 (CY7C4241V)

•8K x 9 (CY7C4251V)

•High-speed 66-MHz operation (15-ns read/write cycle

time)

•Low power (ICC = 20 mA)

• 3.3V operation for low power consumption and easy

integration into low-voltage systems

• 5V-tolerant inputs VIH max = 5V

• Fully asynchronous and simultaneous read and write

operation

•Empty, Full, and Programmable Almost Empty and

Almost Full status flags

• TTL compatible

• Output Enable (OE) pin

• Independent read and write enable pins

• Center power and ground pins for reduced noise

• Width expansion capability

•Space saving 32-pin 7 mm × 7 mm TQFP

•32-pin PLCC

• Available in Pb-Free Packages

Functional Description

The CY7C42X1V are high-speed, low-power, FIFO memories

with clocked read and write interfaces. All are nine bits wide.

Programmable features include Almost Full/Almost Empty

flags. These FIFOs provide solutions for a wide variety of data

buffering needs, including high-speed data acquisition, multi-

processor interfaces, and communications buffering.

These FIFOs have 9-bit input and output ports that are

controlled by separate clock and enable signals. The input port

is controlled by a Free-Running Clock (WCLK) and two Write

Enable pins (WEN1, WEN2/LD).

When WEN1 is LOW and WEN2/LD is HIGH, data is written

into the FIFO on the rising edge of the WCLK signal. While

WEN1, WEN2/LD is held active, data is continually written into

the FIFO on each WCLK cycle. The output port is controlled in

a similar manner by a Free-Running Read Clock (RCLK) and

two Read Enable Pins (REN1, REN2). In addition, the

CY7C42X1V has an Output Enable Pin (OE). The Read

(RCLK) and Write (WCLK) clocks may be tied together for

single-clock operation or the two clocks may be run indepen-

dently for asynchronous read/write applications. Clock

frequencies up to 66 MHz are achievable.

Depth expansion is possible using one enable input for system

control, while the other enable is controlled by expansion logic

to direct the flow of data.

Logic Block Diagram Pin Configuration

THREE-STATE

OUTPUTREGISTER READ

CONTROL

FLAG

LOGIC

WRITE

CONTROL

WRITE

POINTER READ

POINTER

RESET

LOGIC

INPUT

FLAG

PROGRAM

D0−8

RCLK

PAE

PAF

Q0−8

WEN1

WCLK

Dual Port

RAM Array

64 x 9

8Kx 9

WEN2/LD

REN1 REN2

PLCC

RCLK

VCC

GND

WCLK

WEN2/LD

PAF

PAE

REN1

REN2

4321 313032

14151617181920

WEN1

Top View

CY7C4421V/4201V/4211V/4221VCY7C4231V/4241V/4251VLow-Voltage 64/256/512/1K/2K/4K/8K x 9 Synchronous FIFOs

[+] Feedback

CY7C4421V/4201V/4211V/4221V

CY7C4231V/4241V/4251V

Document #: 38-06010 Rev. *B Page 2 of 18

Functional Description (continued)

The CY7C42X1V provides four status pins: Empty, Full, Almost

Empty, Almost Full. The Almost Empty/Almost Full flags are

programmable to single word granularity. The programmable flags

default to Empty-7 and Full-7.

The flags are synchronous, i.e., they change state relative to

either the Read Clock (RCLK) or the Write Clock (WCLK).

When entering or exiting the Empty and Almost Empty states,

the flags are updated exclusively by the RCLK. The flags

denoting Almost Full and Full states are updated exclusively

by WCLK. The synchronous flag architecture guarantees that

the flags maintain their status for at least one cycle

All configurations are fabricated using an advanced 0.65µ

P-Well CMOS technology. Input ESD protection is greater than

2001V, and latch-up is prevented by the use of guard rings.

Selection Guide

CY7C42X1V-15 CY7C42X1V-25 CY7C42X1V-35 Unit

Maximum Frequency 66.7 40 28.6 MHz

Maximum Access Time 11 15 20 ns

Minimum Cycle Time 15 25 35 ns

Minimum Data or Enable Set-up 4 6 7 ns

Minimum Data or Enable Hold 1 1 2 ns

Maximum Flag Delay 10 15 20 ns

Active Power Supply Current Commercial 20 20 20 mA

CY7C4421V CY7C4201V CY7C4211V CY7C4221V CY7C4231V CY7C4241V CY7C4251V

Density 64 x 9 256 x 9 512 x 9 1K x 9 2K x 9 4K x 9 8K x 9

Pin Definitions

Signal Name Description I/O Description

D0−8Data Inputs I Data Inputs for 9-bit bus.

Q0−8Data Outputs O Data Outputs for 9-bit bus.

WEN1 Write Enable 1 I The only write enable when device is configured to have programmable flags.

Data is written on a LOW-to-HIGH transition of WCLK when WEN1 is asserted and FF is

HIGH. If the FIFO is configured to have two write enables, data is written on a LOW-to-HIGH

transition of WCLK when WEN1 is LOW and WEN2/LD and FF are HIGH.

WEN2/LD

Dual Mode Pin

Write Enable 2 I If HIGH at reset, this pin operates as a second write enable. If LOW at reset, this

pin operates as a control to write or read the programmable flag offsets. WEN1 must be

LOW and WEN2 must be HIGH to write data into the FIFO. Data will not be written into the FIFO

if the FF is LOW. If the FIFO is configured to have programmable flags, WEN2/LD is held LOW

to write or read the programmable flag offsets.

Load I

REN1, REN2 Read Enable

Inputs IEnables the device for Read operation.

WCLK Write Clock I The rising edge clocks data into the FIFO when WEN1 is LOW and WEN2/LD is HIGH

and the FIFO is not Full. When LD is asserted, WCLK writes data into the programmable

flag-offset register.

RCLK Read Clock I The rising edge clocks data out of the FIFO when REN1 and REN2 are LOW and the

FIFO is not Empty. When WEN2/LD is LOW, RCLK reads data out of the programmable flag

offset register.

EF Empty Flag O When EF is LOW, the FIFO is empty. EF is synchronized to RCLK.

FF Full Flag O When FF is LOW, the FIFO is full. FF is synchronized to WCLK.

PAE Programmable

Almost Empty

OWhen PAE is LOW, the FIFO is almost empty based on the almost empty offset value

programmed into the FIFO.

PAF Programmable

Almost Full OWhen PAF is LOW, the FIFO is almost full based on the almost full offset value

programmed into the FIFO.

RS Reset I Resets device to empty condition. A reset is required before an initial read or write

operation after power-up.

OE Output Enable I When OE is LOW, the FIFO’s data outputs drive the bus to which they are connected. If

OE is HIGH, the FIFO’s outputs are in High Z (high-impedance) state.

[+] Feedback

CY7C4421V/4201V/4211V/4221V

CY7C4231V/4241V/4251V

Document #: 38-06010 Rev. *B Page 3 of 18

Architecture

The CY7C42X1V consists of an array of 64 to 8K words of nine

bits each (implemented by a dual-port array of SRAM cells),

a read pointer, a write pointer, control signals (RCLK, WCLK,

REN1, REN2, WEN1, WEN2, RS), and flags (EF, PAE, PAF,

FF.)

Resetting the FIFO

Upon power-up, the FIFO must be reset with a Reset (RS)

cycle. This causes the FIFO to enter the Empty condition

signified by EF being LOW. All data outputs (Q0-8) go LOW

tRSF after the rising edge of RS. In order for the FIFO to reset

to its default state, a falling edge must occur on RS and the

user must not read or write while RS is LOW. All flags are

guaranteed to be valid tRSF after RS is taken LOW.

FIFO Operation

When the WEN1 signal is active LOW and WEN2 is active HIGH,

data present on the D0-8 pins is written into the FIFO on each

rising edge of the WCLK signal. Similarly, when the REN1 and

REN2 signals are active LOW, data in the FIFO memory will

be presented on the Q0-8 outputs. New data will be presented

on each rising edge of RCLK while REN1 and REN2 are

active. REN1 and REN2 must set up tENS before RCLK for it

to be a valid read function. WEN1 and WEN2 must occur tENS

before WCLK for it to be a valid write function.

An Output Enable (OE) pin is provided to three-state the Q0-8

outputs when OE is asserted. When OE is enabled (LOW), data

in the output register will be available to the Q0-8 outputs after tOE.

The FIFO contains overflow circuitry to disallow additional

writes when the FIFO is full, and underflow circuitry to disallow

additional reads when the FIFO is empty. An empty FIFO

maintains the data of the last valid read on its Q0-8 outputs

even after additional reads occur.

Write Enable 1 (WEN1). If the FIFO is configured for program-

mable flags, Write Enable 1 (WEN1) is the only write enable

control pin. In this configuration, when Write Enable 1 (WEN1)

is LOW, data can be loaded into the input register and RAM

array on the LOW-to-HIGH transition of every write clock

(WCLK). Data is stored is the RAM array sequentially and

independently of any on-going read operation.

Write Enable 2/Load (WEN2/LD). This is a dual-purpose pin.

The FIFO is configured at Reset to have programmable flags

or to have two write enables, which allows for depth

expansion. If Write Enable 2/Load (WEN2/LD) is set active

HIGH at Reset (RS=LOW), this pin operates as a second write

enable pin.

If the FIFO is configured to have two write enables, when Write

Enable (WEN1) is LOW and Write Enable 2/Load (WEN2/LD)

is HIGH, data can be loaded into the input register and RAM

array on the LOW-to-HIGH transition of every write clock

(WCLK.) Data is stored in the RAM array sequentially and

independently of any on-going read operation.

Programming

When WEN2/LD is held LOW during Reset, this pin is the load

(LD) enable for flag offset programming. In this configuration,

WEN2/LD can be used to access the four 8-bit offset registers

contained in the CY7C42X1V for writing or reading data to

these registers.

When the device is configured for programmable flags and

both WEN2/LD and WEN1 are LOW, the first LOW-to-HIGH

transition of WCLK writes data from the data inputs to the

empty offset Least Significant Bit (LSB) register. The second,

third, and fourth LOW-to-HIGH transitions of WCLK store data

in the empty offset Most Significant Bit (MSB) register, full

offset LSB register, and full offset MSB register, respectively,

when WEN2/LD and WEN1 are LOW. The fifth LOW-to-HIGH

transition of WCLK while WEN2/LD and WEN1 are LOW

writes data to the empty LSB register again. Figure 1 shows

the register sizes and default values for the various device

types.

It is not necessary to write to all the offset registers at one time.

A subset of the offset registers can be written; then by bringing

the WEN2/LD input HIGH, the FIFO is returned to normal read

and write operation. The next time WEN2/LD is brought LOW,

a write operation stores data in the next offset register in

sequence.

The contents of the offset registers can be read to the data

outputs when WEN2/LD is LOW and both REN1 and REN2

are LOW. LOW-to-HIGH transitions of RCLK read register

contents to the data outputs. Writes and reads should not be

performed simultaneously on the offset registers.

[+] Feedback

CY7C4421V/4201V/4211V/4221V

CY7C4231V/4241V/4251V

Document #: 38-06010 Rev. *B Page 4 of 18

Programmable Flag (PAE, PAF) Operation

Whether the flag offset registers are programmed as

described in Table 1 or the default values are used, the

programmable Almost Empty Flag (PAE) and programmable

Almost Full Flag (PAF) states are determined by their corre-

sponding offset registers and the difference between the read

and write pointers.

The number formed by the empty offset least significant bit

to as n and determines the operation of PAE. PAE is synchro-

nized to the LOW-to-HIGH transition of RCLK by one flip-flop

and is LOW when the FIFO contains n or fewer unread words.

PAE is set HIGH by the LOW-to-HIGH transition of RCLK

when the FIFO contains (n+1) or greater unread words.

The number formed by the full offset least significant bit

as m and determines the operation of PAF. PAE is synchro-

nized to the LOW-to-HIGH transition of WCLK by one flip-flop

and is set LOW when the number of unread words in the FIFO

is greater than or equal to CY7C4421V (64 – m), CY7C4201V

(256 – m), CY7C4211V (512 – m), CY7C4221V (1K – m),

CY7C4231V (2K – m), CY7C4241V (4K – m), and

CY7C4251V (8K – m). PAF is set HIGH by the LOW-to-HIGH

transition of WCLK when the number of available memory

locations is greater than m.

Note:

1. The same selection sequence applies to reading from the registers. REN1 and REN2 are enabled and a read is performed on the LOW-to-HIGH transition of RCLK.

Figure 1. Offset Register Location and Default Values

64 x 9 256 x 9 512 x 9

1K x 9

2K x 9 4K x 9 8K x 9

(MSB)

000

(MSB)

000

Empty Offset (LSB) Reg.

Default Value = 007h

Full Offset (LSB) Reg

Default Value = 007h

(MSB)

0000

(MSB)

0000

Empty Offset (LSB) Reg.

Default Value = 007h

Full Offset (LSB) Reg

Default Value = 007h

Empty Offset (LSB) Reg.

Default Value = 007h

Full Offset (LSB) Reg

Default Value = 007h

Empty Offset (LSB) Reg.

Default Value = 007h

Full Offset (LSB) Reg

Default Value = 007h

Empty Offset (LSB) Reg.

Default Value = 007h

Full Offset (LSB) Reg

Default Value = 007h

(MSB)

00000

(MSB)

00000

Full Offset (LSB) Reg

Default Value = 007h

Empty Offset (LSB) Reg.

Default Value = 007h

Full Offset (LSB) Reg

Default Value = 007h

Empty Offset (LSB) Reg.

Default Value = 007h

Table 1. Writing the Offset Registers

LD WEN WCLK[1] Selection

0 0 Empty Offset (LSB)

Empty Offset (MSB)

Full Offset (LSB)

Full Offset (MSB)

0 1 No Operation

1 0 Write Into FIFO

1 1 No Operation

[+] Feedback

CY7C4421V/4201V/4211V/4221V

CY7C4231V/4241V/4251V

Document #: 38-06010 Rev. *B Page 5 of 18

Width Expansion Configuration

Word width may be increased simply by connecting the corre-

sponding input control signals of multiple devices. A

composite flag should be created for each of the end-point

status flags (EF and FF). The partial status flags (PAE and

PAF) can be detected from any one device. Figure 2 demon-

strates a 18-bit word width by using two CY7C42X1Vs. Any

word width can be attained by adding additional

CY7C42X1Vs.

When the CY7C42X1V is in a Width Expansion Configuration,

the Read Enable (REN2) control input can be grounded (see

Figure 2). In this configuration, the Write Enable 2/Load

(WEN2/LD) pin is set to LOW at Reset so that the pin operates

as a control to load and read the programmable flag offsets.

Flag Operation

The CY7C42X1 devices provide four flag pins to indicate the

condition of the FIFO contents. Empty, Full, PAE, and PAF are

synchronous.

Full Flag

The Full Flag (FF) will go LOW when device is full. Write opera-

tions are inhibited whenever FF is LOW regardless of the state

of WEN1 and WEN2/LD. FF is synchronized to WCLK, i.e., it

is exclusively updated by each rising edge of WCLK.

Empty Flag

The Empty Flag (EF) will go LOW when the device is empty.

Read operations are inhibited whenever EF is LOW,

regardless of the state of REN1 and REN2. EF is synchronized

to RCLK, i.e., it is exclusively updated by each rising edge of

RCLK.

Notes:

2. n = Empty Offset (n=7 default value).

3. m = Full Offset (m=7 default value).

Table 2. Status Flags

Number of Words in FIFO

FF PAF PAE EFCY7C4421V CY7C4201V CY7C4211V

000 HHLL

1 to n[2] 1 to n[2] 1 to n[2] HH L H

(n+1) to 32 (n+1) to 128 (n+1) to 256 H H H H

33 to (64−(m+1)) 129 to (256−(m+1)) 257 to (512−(m+1)) H H H H

(64−m)[3] to 63 (256−m)[3] to 255 (512−m)[3] to 511 H L H H

64 256 512 L L H H

Number of Words in FIFO

FF PAF PAE EFCY7C4221V CY7C4231V CY7C4241V CY7C4251V

0000 HHLL

1 to n[2] 1 to n[2] 1 to n[2] 1 to n[2] HH L H

(n+1) to 512 (n+1) to 1024 (n+1) to 2048 (n+1) to 4096 H H H H

513 to (1024 −(m+1)) 1025 to (2048 −(m+1)) 2049 to (4096 −(m+1)) 4097 to (8192 −(m+1)) H H H H

(1024−m)[3] to 1023 (2048−m)[3] to 2047 (4096−m)[3] to 4095 (8192−m)[3] to 8191 H L H H

1024 2048 4096 8192 L L H H

[+] Feedback

CY7C4421V/4201V/4211V/4221V

CY7C4231V/4241V/4251V

Document #: 38-06010 Rev. *B Page 6 of 18

Figure 2. Block Diagram of 64 x 9, 256 x 9, 512 x 9, 1024 x 9, 2048 x 9, 4096 x 9, 8192 x 9 Low-Voltage Synchronous FIFO

Memory Used in a Width-Expansion Configuration

EF EF

WRITE CLOCK (WCLK)

RITE ENABLE 1 (WEN1)

WRITE ENABLE 2/LOAD

(WEN2/LD)

PROGRAMMABLE (PAF)

FULL FLAG (FF)# 1

CY7C42X1V

918

DATA IN (D)

RESET(RS)

READ CLOCK (RCLK)

READ ENABLE 1 (REN1)

OUTPUT ENABLE (OE)

PROGRAMMABLE (PAE)

EMPTY FLAG (EF)#1

DATA OUT (Q)

918

Read Enable 2 (REN2)

CY7C42X1V

EMPTY FLAG (EF)#2

FULL FLAG (FF)# 2

Read Enable 2 (REN2)

[+] Feedback

CY7C4421V/4201V/4211V/4221V

CY7C4231V/4241V/4251V

Document #: 38-06010 Rev. *B Page 7 of 18

Maximum Ratings

(Above which the useful life may be impaired. For user guide-

lines, not tested.)

Storage Temperature ...................................–65°C to +150°C

Ambient Temperature with

Power Applied............................................. –-55°C to +125°C

Supply Voltage to Ground Potential ............... –0.5V to +5.0V

DC Voltage Applied to Outputs

in High-Z State ............................................... –0.5V to +5.0V

DC Input Voltage............................................ –0.5V to +5.0V

Output Current into Outputs (LOW)............................. 20 mA

Static Discharge Voltage...........................................> 2001V

(per MIL-STD-883, Method 3015)

Latch-up Current.....................................................> 200 mA

Operating Range

Range Ambient Temperature VCC

Commercial 0°C to +70°C 3.3V ± 300 mV

Industrial –40° to +85°C 3.3V ± 300 mV

Electrical Characteristics Over the Operating Range

Parameter Description Test Conditions

7C42X1V-15 7C42X1V-25 7C42X1V-35

UnitMin. Max. Min. Max. Min. Max.

VOH Output HIGH Voltage VCC = Min.,

IOH = −2.0 mA

2.4 2.4 2.4 V

VOL Output LOW Voltage VCC = Min.,

IOL = 8.0 mA 0.4 0.4 0.4 V

VIH Input HIGH Voltage 2.0 5.0 2.0 5.0 2.0 5.0 V

VIL Input LOW Voltage −0.5 0.8 −0.5 0.8 −0.5 0.8 V

IIX Input Leakage Current VCC = Max. −10 +10 −10 +10 −10 +10 µA

IOZL

IOZH

Output OFF, High Z

Current

OE > VIH,

VSS < VO < VCC

−10 +10 −10 +10 −10 +10 µA

ICC[4] Active Power Supply

Current

Com’l 20 20 20 mA

ISB[5] Average Standby

Current

Com’l 6 6 6 mA

Capacitance[6]

Parameter Description Test Conditions Max. Unit

CIN Input Capacitance TA = 25°C, f = 1 MHz,

VCC = 5.0V

5pF

COUT Output Capacitance 7 pF

AC Test Loads and Waveforms[7, 8]

Notes:

4. Outputs open. Tested at Frequency = 20 MHz.

5. All inputs = VCC – 0.2V, except WCLK and RCLK, which are switching at 20 MHz.

6. Tested initially and after any design or process changes that may affect these parameters.

7. CL = 30 pF for all AC parameters except for tOHZ.

8. CL = 5 pF for tOHZ.

3.0V

3.3V

OUTPUT

R1 = 330Ω

R2 = 510Ω

INCLUDING

JIG AND

SCOPE

GND

90%

10%

90%

10%

≤3ns ≤3ns

OUTPUT Vth = 2.0V

Equivalent to: THÉ VENIN EQUIVALENT

Rth = 200Ω

ALL INPUT PULSES

[+] Feedback

CY7C4421V/4201V/4211V/4221V

CY7C4231V/4241V/4251V

Document #: 38-06010 Rev. *B Page 8 of 18

Switching Characteristics Over the Operating Range

Parameter Description

7C42X1V-15 7C42X1V-25 7C42X1V-35

UnitMin. Max. Min. Max. Min. Max.

tSClock Cycle Frequency 66.7 40 28.6 MHz

tAData Access Time 211215220ns

tCLK Clock Cycle Time 15 25 35 ns

tCLKH Clock HIGH Time 6 10 14 ns

tCLKL Clock LOW Time 6 10 14 ns

tDS Data Set-Up Time 4 6 7 ns

tDH Data Hold Time 1 2 2 ns

tENS Enable Set-Up Time 4 6 7 ns

tENH Enable Hold Time 1 2 2 ns

tRS Reset Pulse Width[9] 15 25 35 ns

tRSS Reset Set-Up Time 10 15 20 ns

tRSR Reset Recovery Time 10 15 20 ns

tRSF Reset to Flag and Output Time 18 25 35 ns

tOLZ Output Enable to Output in Low Z[10] 000ns

tOE Output Enable to Output Valid 3 8 3 12 3 15 ns

tOHZ Output Enable to Output in High Z[10] 38312315ns

tWFF Write Clock to Full Flag 11 15 20 ns

tREF Read Clock to Empty Flag 11 15 20 ns

tPAF Clock to Programmable Almost-Full Flag 16 22 25 ns

tPAE Clock to Programmable Almost-Full Flag 16 22 25 ns

tSKEW1 Skew Time between Read Clock and Write Clock

for Empty Flag and Full Flag 61012ns

tSKEW2 Skew Time between Read Clock and Write Clock

for Almost-Empty Flag and Almost-Full Flag 15 18 20 ns

Notes:

9. Pulse widths less than minimum values are not allowed.

10. Values guaranteed by design, not currently tested.

[+] Feedback

CY7C4421V/4201V/4211V/4221V

CY7C4231V/4241V/4251V

Document #: 38-06010 Rev. *B Page 9 of 18

Switching Waveforms

Write Cycle Timing

Read Cycle Timing

Notes:

11. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH during the current clock cycle. If the time

between the rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, then FF may not change state until the next WCLK rising edge.

12. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH during the current clock cycle. It the time

between the rising edge of WCLK and the rising edge of RCLK is less than tSKEW1, then EF may not change state until the next RCLK rising edge.

tCLKH tCLKL

NO OPERATION

tDS

tSKEW1

tENS

WEN1

tCLK

tDH

tWFF tWFF

tENH

WCLK

D0–D8

REN1,REN2

RCLK

NO OPERATION

WEN2

(if applicable)

[11]

REN1,REN2

tCLKH tCLKL

NO OPERATION

tSKEW1

WEN1

tCKL

tOHZ

tREF tREF

RCLK

Q0–Q8

WCLK

tOE

tENS

tOLZ

tENH

VALID DATA

WEN2

[12]

[+] Feedback

CY7C4421V/4201V/4211V/4221V

CY7C4231V/4241V/4251V

Document #: 38-06010 Rev. *B Page 10 of 18

Reset Timing[13]

Notes:

13. The clocks (RCLK, WCLK) can be free-running during reset.

14. After reset, the outputs will be LOW if OE = 0 and three-state if OE=1.

15. Holding WEN2/LD HIGH during reset will make the pin act as a second enable pin. Holding WEN2/LD LOW during reset will make the pin act as a load enable

for the programmable flag offset registers.

Switching Waveforms (continued)

tRS

tRSR

Q0−Q8

tRSF

tRSF OE=1

OE=0

REN1,

REN2

EF,PAE

FF,PAF,

tRSS

tRSR

tRSS

tRSR

tRSS

WEN2/LD

WEN1

[15]

[14]

[+] Feedback

CY7C4421V/4201V/4211V/4221V

CY7C4231V/4241V/4251V

Document #: 38-06010 Rev. *B Page 11 of 18

First Data Word Latency after Reset with Simultaneous Read and Write

Notes:

16. When tSKEW1 > minimum specification, tFRL (maximum) = tCLK + tSKEW1. When tSKEW1 < minimum specification, tFRL (maximum) = either 2*tCLK + tSKEW1 or tCLK

+ tSKEW1. The Latency Timing applies only at the Empty Boundary (EF = LOW).

17. The first word is available the cycle after EF goes HIGH, always.

Switching Waveforms (continued)

D0(FIRSTVALID WRITE)

tSKEW1

WEN1

WCLK

Q0–Q8

REN1,

REN2

tOE

tENS

tOLZ

tDS

RCLK

tREF

tFRL

D1D2D3D4

D0D1

D0–D8

WEN2

(if applicable)

[16]

[17]

[+] Feedback

CY7C4421V/4201V/4211V/4221V

CY7C4231V/4241V/4251V

Document #: 38-06010 Rev. *B Page 12 of 18

Empty Flag Timing

Switching Waveforms (continued)

DATAWRITE2

DATAWRITE1

tENS

tSKEW1

DATA IN OUTPUT REGISTER

WEN1

WCLK

Q0–Q8

REN1,

REN2

tDS

tENH

RCLK

tREF

tFRL

D0–D8

DATA READ

tSKEW1

tFRL

tREF

tDS

tENS

tENH

tENS

WEN2

(if applicable)

tENH tENS tENH

tREF

LOW

[16] [16]

[+] Feedback

CY7C4421V/4201V/4211V/4221V

CY7C4231V/4241V/4251V

Document #: 38-06010 Rev. *B Page 13 of 18

Full Flag Timing

Programmable Almost Empty Flag Timing

Notes:

18. tSKEW2 is the minimum time between a rising WCLK and a rising RCLK edge for PAE to change state during that clock cycle. If the time between the edge of

WCLK and the rising RCLK is less than tSKEW2, then PAE may not change state until the next RCLK.

19. PAE offset = n.

20. If a read is performed on this rising edge of the read clock, there will be Empty + (n−1) words in the FIFO when PAE goes LOW.

Switching Waveforms (continued)

Q0–Q8

REN1,

REN2

WEN1

WEN2

(if applicable)

D0–D8

NEXT DATA READ

DATA WRITE

NO WRITE

DATA IN OUTPUT REGISTER

WCLK

RCLK

DATA READ

tSKEW1 tDS

tENS

tENH

tWFF

tSKEW1

tENS

tENH

tWFF

DATA WRITE

NO WRITE

tWFF

LOW

NO WRITE

[11] [11]

tENH

WCLK

PAE

RCLK

tCLKH

tENS

tCLKL

tENS

tPAE

N + 1 WORDS

INFIFO

tENH

tENS

tENH

tENS

tPAE

REN1,

REN2

WEN1

WEN2

(if applicable)

tSKEW2 [18]

Note 19

Note 20

[+] Feedback

CY7C4421V/4201V/4211V/4221V

CY7C4231V/4241V/4251V

Document #: 38-06010 Rev. *B Page 14 of 18

Programmable Almost Full Flag Timing

Write Programmable Registers

Notes:

21. If a write is performed on this rising edge of the write clock, there will be Full – (m–1) words of the FIFO when PAF goes LOW.

22. PAF offset = m.

23. 64–m words for CY7C4421V, 256-m words in FIFO for CY7C4201V, 512–m words for CY7C4211V, 1024–m words for CY7C4221V, 2048–m words for

CY7C4231V, 4096–m words for CY7C4241V, 8192–m words for CY7C4251V.

24. tSKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge for PAF to change during that clock cycle. If the time between the rising edge

of RCLK and the rising edge of WCLK is less than tSKEW2, then PAF may not change state until the next WCLK.

Switching Waveforms (continued)

tENH

WCLK

PAF

RCLK

tCLKH

tENS

FULL −M WORDS

IN FIFO

tCLKL

tENS

FULL −(M+1) WORDS

IN FIFO

tENH

tENS

tENH

tENS

tPAF

REN1,

REN2

WEN1

WEN2

(if applicable)

tSKEW2 tPAF

Note 21

[22]

[23]

[24]

tENH

WEN2/LD

WCLK

tCLKH

tENS

tCLKL

PAE OFFSET

LSB

D0–D8

WEN1

tENS

PAF OFFSET

MSB

tCLK

tDS tDH

PAE OFFSET

MSB

PAF OFFSET

LSB

[+] Feedback

CY7C4421V/4201V/4211V/4221V

CY7C4231V/4241V/4251V

Document #: 38-06010 Rev. *B Page 15 of 18

Read Programmable Registers

Ordering Information

256 x 9 Low Voltage Synchronous FIFO

Speed (ns) Ordering Code Package Name Package Type Operating Range

15 CY7C4201V-15AC A32 32-Lead Thin Quad Flatpack Commercial

CY7C4201V-15AXC A32 32-Lead Pb-Free Thin Quad Flatpack

25 CY7C4201V-25AC A32 32-Lead Thin Quad Flatpack Commercial

512 x 9 Low Voltage Synchronous FIFO

Speed (ns) Ordering Code Package Name Package Type Operating Range

15 CY7C4211V-15AC A32 32-Lead Thin Quad Flatpack Commercial

CY7C4211V-15JC J65 32-Lead Plastic Leaded Chip Carrier

CY7C4211V-15AI A32 32-Lead Thin Quad Flatpack Industrial

CY7C4211V-15AXI A32 32-Lead Pb-Free Thin Quad Flatpack

25 CY7C4211V-25AC A32 32-Lead Thin Quad Flatpack Commercial

CY7C4211V-25JC J65 32-Lead Plastic Leaded Chip Carrier

1K x 9 Low Voltage Synchronous FIFO

Speed (ns) Ordering Code Package Name Package Type Operating Range

15 CY7C4221V-15AC A32 32-Lead Thin Quad Flatpack Commercial

CY7C4221V-15JC J65 32-Lead Plastic Leaded Chip Carrier

25 CY7C4221V-25AC A32 32-Lead Thin Quad Flatpack Commercial

2K x 9 Low Voltage Synchronous FIFO

Speed (ns) Ordering Code Package Name Package Type Operating Range

15 CY7C4231V-15AC A32 32-Lead Thin Quad Flatpack Commercial

CY7C4231V-15JXC J65 32-Lead Pb-Free Plastic Leaded Chip Carrier

CY7C4231V-15JC J65 32-Lead Plastic Leaded Chip Carrier

25 CY7C4231V-25AXC A32 32-Lead Pb-Free Thin Quad Flatpack Commercial

CY7C4231V-25AC A32 32-Lead Thin Quad Flatpack

CY7C4231V-25JC J65 32-Lead Plastic Leaded Chip Carrier

Switching Waveforms (continued)

PAF OFFSET

MSB

PAF OFFSET

LSB

tENH

WEN2/LD

RCLK

tCLKH

tENS

tCLKL

PAE OFFSET LSB

Q0–Q8

REN1,

REN2

tENS

PAE OFFSET MSB

tCLK

UNKNOWN

[+] Feedback

CY7C4421V/4201V/4211V/4221V

CY7C4231V/4241V/4251V

Document #: 38-06010 Rev. *B Page 16 of 18

4K x 9 Low Voltage Synchronous FIFO

Speed (ns) Ordering Code Package Name Package Type Operating Range

15 CY7C4241V-15AC A32 32-Lead Thin Quad Flatpack Commercial

CY7C4241V-15AXC A32 32-Lead Pb-Free Thin Quad Flatpack

CY7C4241V-15JXC J65 32-Lead Pb-Free Plastic Leaded Chip Carrier

CY7C4241V-15JC J65 32-Lead Plastic Leaded Chip Carrier

25 CY7C4241V-25AC A32 32-Lead Thin Quad Flatpack Commercial

CY7C4241V-25AXC A32 32-Lead Pb-Free Thin Quad Flatpack

CY7C4241V-25JC J65 32-Lead Plastic Leaded Chip Carrier

8K x 9 Low Voltage Synchronous FIFO

Speed (ns) Ordering Code Package Name Package Type Operating Range

15 CY7C4251V-15AC A32 32-Lead Thin Quad Flatpack Commercial

CY7C4251V-15AXC A32 32-Lead Pb-Free Thin Quad Flatpack

CY7C4251V-15JC J65 32-Lead Plastic Leaded Chip Carrier

25 CY7C4251V-25AC A32 32-Lead Thin Quad Flatpack Commercial

CY7C4251V-25AXC A32 32-Lead Pb-Free Thin Quad Flatpack

Ordering Information (continued)

Package Diagrams

32-Lead Thin Plastic Quad Flatpack 7 x 7 x 1.0 mm A32

51-85063-*B

32-Lead Pb-Free Thin Plastic Quad Flatpack 7 x 7 x 1.0 mm A32

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CY7C4421V/4201V/4211V/4221V

CY7C4231V/4241V/4251V

Document #: 38-06010 Rev. *B Page 17 of 18

of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be

used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its

products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

All product and company names mentioned in this document are the trademarks of their respective holders.

Package Diagrams (continued)

51-85002-*B

32-Lead Pb-Free Plastic Leaded Chip Carrier J65

32-Lead Plastic Leaded Chip Carrier J65

[+] Feedback

CY7C4421V/4201V/4211V/4221V

CY7C4231V/4241V/4251V

Document #: 38-06010 Rev. *B Page 18 of 18

Document History Page

Document Title: CY7C4421V/4201V/4211V/4221V/CY7C4231V/4241V/4251V Low-Voltage 64/256/512/1K/2K/4K/8K x 9

Synchronous FIFOs

Document Number: 38-06010

REV. ECN NO. Issue Date

Orig. of

Change Description of Change

** 106471 09/10/01 SZV Change from Spec number: 38-00622 to 38-06010

*A 127857 08/25/03 FSG Fixed empty flag timing diagram

Fixed switching waveform diagram typo

*B 384573 See ECN ESH Added Pb-Free logo to top of front page

Inserted industrial temperature range into operating range

Added parts CY7C4251V-25AXC, CY7C4251V-15AXC,

CY7C4241V-15AXC, CY7C4241V-15JXC, CY7C4241V-25XC,

CY7C4231V-25AXC, CY7C4221V-15AI, CY7C4211V-15AXI,

CY7C4201V-15AXC to ordering information.

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