FL7740MX - ON SEMICONDUCTOR

Februar y 2018 - Rev. 3 FL7740

FL7740

Constant-Voltage Pri mary-Side-

Regulation PWM Controller for

Power Factor Correction

The FL7740 provides accurate CV regulation in the steady state with

differentiated dynamic function to minimize overshoot and undershoot of

output voltage in line and load transient condition. Standby power is less

than 0.3 W for smart lighting application and power factor is higher than

0.9 even at half load condition when enabling PF optimizer for wide

output power scalability.

Startup time is less than 0.2 sec with built-i n hi gh vo lta ge s t ar tup cir cui t

and output volta ge quickly reaches to the target CV le vel by loop gain

transition technique during s tartup.

Various protections such as over load, output diode short, sensing resistor

short, output short and output over voltage protection guarantee high

system reliability.

Features

• Wide unive rsal input range (90 VAC ~ 305 VAC)

• Precise CV regulat ion in the steady state : < ± 3 %

• CV regulation in the lo ad transient : < ±10 %

• Overshoot-less fas t H V start up time ( < 0.2 sec )

• Low standby power

• PF hi gher than 0.9 at high-line and half load by PF optimizer

• Pulse-by-pulse current li mit

• Output short protection

• Output over voltage protec tion

• Output diode short protection

• Sensing resistor short & open protection

• Over load protection

Typical Applic ations

• LED Lighti ng System

• AC-DC Adapters, TVs, Monitors

• Off Line Appliances Requiring Power Factor Correction

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SO 10L

MARKING DIAGRAM

ZXYKK

Z = Plant code

X = 1 digit year code

Y = 1 digit week code

KK = 2 digit lot traceability code

M = Package code

A = Product version

FL7740

PIN CONNECTIONS

VDD

GND

GATE

COMV

BIAS

ORDERING INFORM ATION

See detailed ordering and shipping information in the

package dimensions section on page 13 of this data sheet.

FL7740

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FL7740

GATE

GND

BIAS

VDD

COMV

Secondary

DC-DC

Converter

Dimming

Control

Module

Dimming

Signal

VAC

VOUT.MAIN

VOUT.BIAS

0-10, DALI,

Wireless, etc.

Figure 1. Application Schematic

COMV

VDD

JFET

GM amp.

EAV

REF

Dynamic

control

Gain control at startup

BIAS

5V regulator

Digital PF

optimizer

detector V

DYN-REF

control

Protection

GATE

VDD

EAV

Shutdown

OUT

open/short protection

Over current protection

Over load protection

Thermal shutdown

IN.PK

Digital Duty Control

GND

Driver

DYN-REF1,2,3

S/H

Figure 2. Simplified Block Diagram

FL7740

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PIN FUNCTION DESCRIPT ION

Pin No. Pin Name Function Description

1 VDD IC Suppl y IC operati ng current and MOSFET driving current are suppl i ed using this pin.

2 GND Ground Controller ground pin.

3 GATE PWM Driver Output This pin uses the internal totem-pole output driver to drive the power MOSFET.

4 CS Current Sense

Connected to a current sense resist or to detect the MOSFET current for pulse-by-

pulse current limit.

5 VS Voltage Sense This pin is connected to the auxiliary winding of the t ransf orm er via a resistor

divider to detect the output voltage.

6 PF Power Factor This pin is connected to a resistor to optimize power factor.

7 BIAS Int ernal Circui t BIAS Bypass pin for t he internal suppl y, which powers all cont rol circuitry on t he IC.

8 COMV Loop Compensation This pin is connected to a capacitor between COMV and GND for compensation.

9 NC No Connection

10 HV High Voltage This pin is connected to the rectified input voltage via a resistor for fast startup.

FL7740

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MAXIMUM RATINGS (Note 1)

1. Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device

functionali t y should not be assumed, damage may occur and reliability may be affected.

2. Refer to ELECTRICAL CHA RACTERISTICS, RECOMMENDE D OPERATING RANGES and/or APPLICATION INFORMATION for Safe

Operating parameters.

3. This devic e series incorporat es ESD protection and is tested by the following methods:

ESD Human Body Model tested per AEC-Q100-002 (EIA/JESD22-A114)

ESD Machine Model tested per AEC-Q100-003 (EIA/JESD22-A115)

Latchup Current Maximum Rating: ≤150 mA per JEDEC standard: JESD78

RECOMMENDED OPER ATING RANGES (Note 4)

4. Funct i onal operati on above the stress es listed i n the Recommended Operating Ranges is not impli ed. Extended exposure to stresses

beyond the Recommended Operating Ranges lim its may aff ect device reliabi l i t y.

Rating

Symbol

Value

Unit

HV Pin Voltage Range

VHV(MAX)

560 V

VDD, GATE Pin Voltage Range

VMV(MAX)

-0.3 to 30

COMV, PF, BIAS, VS, CS Pin Voltage Range

VLV(MAX)

-0.3 to 6

VS, C S Pin Negative Pulse Voltage at ILV < 0.2 A and tPULSE < 300 ns

VLV(PULSE) -1.5 V

Maximum Power Dissipati on (TA < 50°C)

PD(MAX)

663

Maximum Juncti on Temperat ure

TJ(max)

150

°C

Storage Temperature Range TSTG -55 to 150 °C

Junction-to-Ambient Thermal Impedance

RθJA

158

°C/W

Junction-to-Case Thermal Impedance

RθJC

°C/W

ESD Capability, Human Body Model (Note 3)

ESDHBM 2 kV

ESD Capability, Charged Device Model (Note 3)

ESDCDM 2 kV

Rating Symbol Min Max Unit

Ambient Temperature

-40

125

°C

FL7740

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ELECTRICAL CHARACTERISTICS

VDD = 18 V and TJ = -40 ~ 125°C u nless otherwise specified

Parameter Test Conditions Symbol Min Typ Max Unit

VDD Section

Turn-On Threshold Voltage VDD-ON 14.5 16.0 17.5 V

Turn-Off Threshold Voltage VDD-OFF 6.75 7.75 8.75 V

Operating Current CLOAD = 1 nF, VDD = 18V IDD-OP 3 5 6.5 mA

Operating Current during Aut o Restart IDD-AR 0.3 1 mA

VDD Over-Voltage-Protection VDD-OVP 24 25 26 V

VBIAS Voltage VBIAS 4.85 5.00 5.15 V

GATE Section

Output Voltage Low VOL 0.2 V

Output Voltage High VDD = 18 V VOH 17.8 V

Peak Sourcing Current

Design guaranteed

CLOAD = 1 nF, VDD = 20 V

CLOAD = 1 nF, VDD = 23 V

Isource

180

210 mA

Peak Sinking Current

Design guaranteed

CLOAD = 1 nF, VDD = 20 V

CLOAD = 1 nF, VDD = 23 V

Isink

385

435 mA

Rising Time CLOAD = 1 nF tr 110 150 190 ns

Falling Time CLOAD = 1 nF tf 40 60 80 ns

HV Section

Supply Current From HV Pin VHV = 560 V, VDD = 0 V IHV 3 9 mA

Leakage Current after Start up IHV-LC 1 10 μA

JFET Regulation Time at Startup Desi gn guarant eed tR-JFET 400 500 600 ms

VDD High Limit during JFET Regulation VDD-JFET-HL 17.5 19.0 20.5 V

VDD Low Limit during JFET Regulation VDD-JFET-LL 15.5 17.0 18.5 V

PWM Section

Min. Turn-on Time Min. Limit Design guarant eed TON-MIN-MIN 0.40 μs

Min. Turn-on Time Max. Limit Design guaranteed TON-MIN-MAX 2.0 μs

Max. Turn-on Tim e Design guarant eed TON-MAX 23.3 μs

Oscillato r Section

Max. Frequency fMAX 60 65 70 kHz

Min. Frequency fMIN 0.72 0.80 0.88 kHz

Current Sense Section

Leading-Edge Blanking T ime Design guaranteed tLEB 300 ns

Propagation Delay t o GATE Design guarant eed tPD 50 100 150 ns

Voltage Sense Section

tDIS Blanking Time at VS Sampling Design guaranteed tDIS-BNK 0.95 1.00 1.05 μs

VS Clamping Voltage

IVS=1 mA

IVS=10 µA

VVS-CLAMP

-0.1

0.35

Feedback Section

Reference voltage VREF 3.465 3.5 3.535 V

FL7740

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ELECTRICAL CHARACTERISTICS

(CONTINUED)

VDD = 18 V and TJ = -40 ~ 125°C u nless otherwise specified

Parameter Test Conditions Symbol Min Typ Max Unit

CV Regulation Toleranc e

VVS = 3.5 V, TJ = 25 °C

VVS = 3.5 V, TJ = -40~125 °C

CVREGULATION

-0.7

-1.2

+0.7

+1.2

Transconductance gM 16 20 24 μmho

COMV Sink Current VVS = 4 V ICOMV-SINK 8 10 12 μA

COMV Source Current VVS = 3 V ICOMV-SOURCE

8 10 12 μA

COMV High Voltage VCOMV-HGH 4.7 V

COMV Low Voltage VCOMV-LOW 0.1 V

Start Sequence Section

Sof t Start Time Design guaranteed tSOFT-START 25.6 ms

SS 1 Minim um Time Design guaranteed tSS1-MIN 2 ms

SS1 Maximum Time Design guaranteed tSS1-MAX 100 ms

SS21 Time Design guaranteed tSS21 45 ms

SS22 Maximum Time Design guaranteed tSS22 30 ms

Dynamic Section

DYN Reference Set Threshold VDYN-REF-SET 0.72 0.80 0.88 V

DYN Reference Set Time Design guaranteed tDYN-REF-SET 5 μs

OV Reference 5 Design guaranteed VOV-REF5 +20 %

OV Reference 4 VOV-REF4 +14 +15 +16 %

OV Reference 3 VOV-REF3 +9 +10 +11 %

OV Reference 2 VOV-REF2 +4.7 +5.7 +6.7 %

OV Reference 1 VOV-REF1 +1.86 +2.86 +3.86 %

UV Reference 1 VUV-REF1 -3.86 -2.86 -1.86 %

UV Reference 2 VUV-REF2 -6.7 -5.7 -4.7 %

UV Reference 3 Design guaranteed VUV-REF3 -10 %

Protection Section

Auto Restart Delay Time Design guaranteed tAR 3 s

VS Ouptut Short Hys. Voltage 'H' VVS-OS-H 0.85 0.90 0.95 V

VS Ouptut Short Hys. Voltage 'L' VVS-OS-L 0.65 0.70 0.75 V

OSP Delay Time Design guaranteed tOSP-DELAY 35 ms

High Current Limit Threshold VCS-HIGH-CL 1.13 1.20 1.27 V

Low Current Limit Threshold VCS-LOW-CL 0.15 0.20 0.25 V

Over Current Protecti on Voltage VCS-OCP 1.8 V

CS Threshold Voltage for SRSP VCS-SRSP 0.040 0.075 0.125 V

Max. Turn-on Time for SRSP

IVS = 100 uA

IVS = 700 uA

tTON-MAX-SRSP

7.5

1.3

10.0

1.6

12.5

1.9

μs

Threshold Temperature f or OTP Design guaranteed TOTP 150 oC

Junction Temperature Hysteresis Design guaranteed TOTP-HYS 30 oC

FL7740

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TYPICAL CHARACTERISTIC

-40 -20 020 40 60 80 100 120 140

TJ, JUNCTION TEMPERATURE (ºC)

DD-ON

(V)

Figure 3 V DD-ON vs. Temperature

4.0

4.2

4.4

4.6

4.8

5.0

5.2

5.4

5.6

5.8

6.0

-40 -20 020 40 60 80 100 120 140

TJ, JUNCTION TEMPERATURE (ºC)

BIAS

(V)

Figure 4 V BIAS vs. Temperature

6.50

6.75

7.00

7.25

7.50

7.75

8.00

8.25

8.50

8.75

9.00

-40 -20 020 40 60 80 100 120 140

TJ, JUNCTION TEMPERATURE (ºC)

DD-OFF

(V)

Figure 5 V DD-OFF vs. Temperature

1.00

1.05

1.10

1.15

1.20

1.25

1.30

1.35

1.40

-40 -20 020 40 60 80 100 120 140

TJ, JUNCTION TEMPERATURE (ºC)

CS-HIGH-CL

(V)

Figure 6 V CS-HIGH-CL vs. Temperature

3.40

3.42

3.44

3.46

3.48

3.50

3.52

3.54

3.56

3.58

3.60

-40 -20 020 40 60 80 100 120 140

TJ, JUNCTION TEMPERATURE (ºC)

VREF (V)

Figure 7 V REF vs. Temperature

1.60

1.65

1.70

1.75

1.80

1.85

1.90

1.95

2.00

-40 -20 020 40 60 80 100 120 140

TJ, JUNCTION TEMPERATURE (ºC)

CS-OCP

(V)

Figure 8 V CS-OCP vs. Temperature

FL7740

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TYPICAL CHARACTERISTIC

TJ, JUNCTION TEMPERATURE (ºC)

REGULATION

(%)

-1.0

-0.8

-0.6

-0.4

-0.2

0.0

0.2

0.4

0.6

0.8

1.0

-40 -20 020 40 60 80 100 120 140

Figure 9 CVREGULATION vs. Temperature

9.5

9.6

9.7

9.8

9.9

10.0

10.1

10.2

10.3

10.4

10.5

-40 -20 020 40 60 80 100 120 140

TJ, JUNCTION TEMPERATURE (ºC)

VOV-REF3 (%)

Figure 10 V OV-REF3 vs. Temperature

2.10

2.25

2.40

2.55

2.70

2.85

3.00

3.15

3.30

3.45

3.60

-40 -20 020 40 60 80 100 120 140

TJ, JUNCTION TEMPERATURE (ºC)

OV-REF1

(%)

Figure 11 V OV-REF1 vs. Temperature

-3.60

-3.45

-3.30

-3.15

-3.00

-2.85

-2.70

-2.55

-2.40

-2.25

-2.10

-40 -20 020 40 60 80 100 120 140

TJ, JUNCTION TEMPERATURE (ºC)

UV-REF1

(%)

Figure 12 V UV-REF1 vs. Temperature

5.2

5.3

5.4

5.5

5.6

5.7

5.8

5.9

6.0

6.1

6.2

-40 -20 020 40 60 80 100 120 140

TJ, JUNCTION TEMPERATURE (ºC)

OV-REF2

(%)

Figure 13 V OV-REF2 vs. Temperature

-6.2

-6.1

-6.0

-5.9

-5.8

-5.7

-5.6

-5.5

-5.4

-5.3

-5.2

-40 -20 020 40 60 80 100 120 140

TJ, JUNCTION TEMPERATURE (ºC)

VUV-REF2 (%)

Figure 14 V UV-REF2 vs. Temperature

FL7740

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APPLICATION INFORMATION

General

FL7740 is high power factor flyback controller with

accurate primary side constant voltage regulation for

smart LED lighting and AC-DC adapter, TV & monitors

application. Precise outp ut voltage detection and

dynamic function manage good CV regulation. Startup is

fast with int ernal HV biasing circuit with oversho ot-less

gain control. It guarantees high system reliable

protection functions such as output over voltage, output

short, over loa d, over current and thermal shut down

protections.

Constant Voltage Regulation

VS pin detects output voltage information (=VEAV)

during secondary side diode conduction time and

internal gm amplifier regulate s the de te c te d voltage at

3.5 V.

Dynamic Response at Load Transient

At load transient condition, V EAV is sho rtly out of

regulation due to the narrow PFC loop ba ndwidth. Whe n

VEAV is far from 3.5 V regulation reference, duty is

quickly changed to b ring the VEAV back to 3.5 V by

dynamic control funct i on.

HV biasing at startup

Internal HV biasing circuit quickly charge s external

VDD capacitor to begin IC ope ration at plug-in. After

500 ms initial time, HV biasing stops for low standby

power.

Overshoot-less gain control at startup

Once IC operation starts, feedback loop is dominantly

controlled in proportional gain to speed up the output

capacito r c har gin g. Once output voltage is settled down

close to the regu lation target, gain control is smoothly

chan ged to integratio n gain with no output vol tage

overshoot.

Digital PF optimizer

FL7740 compensa tes input current phase shift caused by

EMI filter cap a c itor current in a half line p e riod. With

sophisticated d igital PF optimizer, FL7740 significantly

improves power factor in the wide load range.

Pulse-by-pulse current li mit

When CS pin volta ge r e a c hes to 1. 2 V current limit

reference, GATE turn-on is terminated to limit pri mar y

peak current.

Auto Restart at Protection

Once protection is triggered, IC operation stops for 3 sec

and begin the operation for auto restart.

Output Short Protection

When VEAV is less than 0.7 V continuously for 35 ms,

output short p rotection is trigg e red.

Output Over Voltage Protection

When VEAV is higher than VVS-OVP threshold or VDD is

higher tha n VDD-OVP, output over voltage protection is

triggered.

Output Diode Short Protection

Once output d iode is short circuited, high di/dt in the

pri mary windin g is occurred by leakage inductance.

Once CS pin voltage reaches to 1.7 V, switching is shut

down.

Sensing Resistor Short Protection

At first switching, sensing resistor short conditio n is

monitored by detecting CS pin volta ge. If CS is less than

75 mV during fir st GATE turn-on time, sensing r esistor

short prote c tion is triggered.

Over Load Protection

When output is o ver loaded, pulse-by-pulse current li mit

event is occurred. If this event lasts for 60 half line

cycles, over load protection is triggered.

Thermal Shut Down

If inte rnal junction temperature is higher than 150ºC,

protection is triggered and released with 30ºC hyster esi s.

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Primary Side Constant Voltage Regulation

FL7740 utilizes auxiliary winding to detect output

voltage during secondary side diode conduction time

(=TDIS). The true output voltage le vel wi t hout secondary

diode forward voltage drop is at the end of secondary

diode c onduction time. In order to detect the right outp ut

voltage, 85% of TDIS at pre vious switching c ycle is

sampling ti me for VEAV detection at current switc hing

cycle.

S/H

VS V

REF

Error

Amp.

EAV

COMV

DIS

detection

Duty

Control

AUX

IN.PK

Figure 15. Primary Side Regulation

GATE

85% TDIS

at previous

switching

TDIS

VEAV sampling

Figure 16. VEAV Detection

The sampled VEAV is compared with 3.5 V VREF at the

input of the erro r amplifier. Several hundreds nF

capacitor is connected to the output of the error amplifier

at COMV pin to keep feedback loop slow in PFC control.

COMV voltage controls duty to regulate VEAV same as

VREF in the system.

Turn-on time is controlled by both COMV voltage and

VIN.PK information in line feedforward operation in order

to keep the constant COMV v oltage in the wide inp ut

voltage range. So, turn-on time is proportional to COMV

voltage and inversely proportional to VIN.PK.

Startup

After plug-in, e xter nal VDD capacitor is quickly

char ged by inter nal HV b iasing sup ply. Even after VDD

is higher t han 16 V VDD-ON, inte rnal HV biasing is still

enabled for 500 ms, so HV biasing can relieve VDD

capacito r discharging until auxiliary winding b ui ld s up

VDD voltage.

In order to speed up large output capacitor charging

without overshoot, FL7740 starts with proportional gain

duri ng star tup seque nce (SS1 + SS2) by using int erna l

resistive load at the output of the e r ror amplifier.

In SS1, CCM prevent operation is enabled for the initial

2 ms. When output voltage is 0 V, deep CCM could be

entered at initial startup and C S c ould touch OCP level

with startup failur e. So, pulse-by-pulse current limit is

0.2 V and switching fre quency is 2 2 kHz d uring the 2 ms

CCM prevent time. Also, duty is gradually increased for

26 ms for soft startup. Once 5 V pulled-up COMV

voltage drops less than 4.5 V as VEAV is close to V REF,

SS1 is ended. Maximum SS1 time is limited up to 100

ms.

In SS2, VCOMV drops from 5 V and goe s into p-gain

steady state in which VEAV is little bit lower than VREF

due to the error amplifier inpu t e rror in p-gain. Once p-

gain stead y state is settled down in 45 ms, SS2 is

finished at min. VCOMV range not to make oversho ot

when transitio ning to i-gain after SS2. FL7740 ends SS2

by moni toring VIN 1.5 ms after VIN.PK detection moment

where VCOMV is general ly in the min. range.

COMV

Duty

EAV

REF

Startup time by P-gain I-gain

45 ms

4.5 V

26 ms soft start

2 ms CCM prevent

5.0 V

IN.PK

1.5 ms

SS1 SS2

Figure 17. Startup Sequence

Dynamic CV Regulation

Due to the narrow loop bandwidth, PFC controller

gener ally does not guarantee good CV regulation at load

transient. Espe c ia lly in second a ry side regulation,

primary side controller does not know the output voltage

level and it only monitors the output of feedback signal

through opto-coupler. The refore, out put voltage

undershoot is severely happened at no to full load

transient in the co nventional S SR PFC control.

In order to overcome this, FL7740 utilizes the benefit of

P S R wit h ON semiconductor’s proprietary dynamic duty

control by monitoring the output voltage. For example,

when V EAV i s l ess tha n VUVD.EN (Under Volta ge Dynamic

Enable threshold), duty is quickly increa sed not to allo w

undershoot anymore. Once VEAV rises hig her than

VUVD.DIS (Under Voltage Dynamic Disable threshold),

duty quickly drops and follows COMV voltage . During

the VEAV hi ccup o peration, COMV voltage slowly

increases and dynamic operation is terminated when

COMV voltage is close to stea dy state level.

FL7740

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REF

GM amp.

EAV

COMV

OVD.EN2

Over

Voltage

Dynamic

(OVD)

Under

Voltage

Dynamic

(UVD)

OVD.EN1

UVD.EN

UVD.DIS

Duty

Generator

OVD.DIS

GATE

Figure 18. Dynamic Function Block

REF

EAV

COMV

UVD.EN

UVD.DIS

Duty

Figure 19. No to full load transient

REF

VEAV

VCOMV

OVD.EN1

OVD.DIS

Duty

OVD.EN2

Figure 20. Full to no load transient

In case of OVD (Over Voltage Dynamic) function, it

has two enable levels (VOVD.EN1 a nd VOVD.EN2) . If output

voltage overshoot at load transient is too high, VEAV

increases to VOVD.EN2 passing by VOVD.EN1. Duty quickl y

drops when reaching V OVD.EN1 and drops to min. level at

once not to allow severe output over voltage when VEAV

increases higher than VOVD.EN2.

FL7740 provides two sets of dynamic triggering

threshold. When user prefe rs narrow output voltage

variation at load transient with large output capacitor,

SET0 can be selected without capacitor at PF pin. If

wider output voltage variatio n is allowed and o utp ut

capacitor should be small due to system size, SET1 can

be selected with connection of capacitor around 0.5 nF at

PF pin. FL7740 detects capacitance at PF pin at the

beginning of swit chi ng star tup a nd mai nt ains the SET#

until UVLO is tr iggered. During the 1st switching, PF

pin is pulled down to 0 V. In the 2nd switching, PF pull

down is disabled and PF voltage is monitored 5 us after

2nd switching period b egins. If the PF voltage is higher

than 0.8 V VDYN-REF-SET, SET0 is decided. If not, SET1 is

determined.

Dynamic Threshold at SET0 and SET1

VVS.OVP VOVD.EN2 VOVD.EN1 VOVD.DIS VUVD.DIS VUVD.EN

VOV-REF5

+20%VREF SET1

VOV-REF4

+15%VREF SET0 SET1

VOV-REF3

+10%VREF SET0 SET1

VOV-REF2

+5.7%VREF SET0 SET1

OV-REF1

+2.9%VREF SET0

VUV-REF1

-2.9%VREF SET0

VUV-REF2

-5.7%VREF SET1 SET0

VUV-REF3

-10%VREF SET1

Digital PF Optimizer

As line voltage increases and output load decreases, PF

is degraded due to the effect of EMI filter capacitor

char ging/disc hargi ng current. Input current is the sum of

EMI Filter capacitor current and flyback input current.

Whet her the flyb ack input current is exactly in-phase

sinusoidal current with line voltage, 90º phase shifted

EMI filter cap current worsens displacement factor of the

overall system i nput c urrent.

The ON semiconductor’s proprietary PF optimizer

accurately compensates the EMI filter capacitor current

and improves PF more than 0.1 at high line and half load

condition.

The calculation coefficient in the PF optimizer is

externally programmable by supplying a certain level of

voltage at PF pin with external resistive divider from 5 V

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BIAS p in. Before 1st switching, FL7740 converts the PF

voltage int o digit al value without switching noise and

keeps the digital value for the coefficient until UVLO is

triggered.

Recommended VPF is in Equat ion 1, where LM is

magne tizing inductance and CEMI is total EM I filter

capacitance.

1.5

+×××=

EMIM

(eq. 1)

As VPF increases, the coefficient in the PF optimizer

calculatio n is larger with better PF, but THD is worse

due to the input current distor tion at input voltage zer o

cross. Therefore, VPF adjustment by changing PF

resistors is recommended to bring the best PF and THD

performance to meet user’s target. When VPF is lower

than 1.5 V, PF optimizer is disabled.

EMI.CAP

FLYBACK

GATE

Ideal I

Figure 21. With PF Optimizer

GATE

EMI.CAP

FLYBACK

(=Ideal I

)

Leading

phase

Figure 22. Without PF Optimizer

Protection

• Auto-restart

Once protec tion is triggered, FL7740 terminates

switching and internal 3 se c counter makes delay time.

In 3 sec, VDD voltage is regulated between 17 V and 19

V by internal HV b ia sing not to fall in UVLO. After 3

sec, VDD falls down to 7.75 V VDD-OFF and IC is reset

with released protection. When VDD voltage is up again

to 16 V VDD-ON, FL7740 begins startup sequence.

VDD

GATE

19 V

17 V

7.75 V

16 V

Protection

triggered

VDD regulation

for 3 sec

reset IC

restart

Figure 23. Auto Restart

• Output Over Volta ge Protection

Output ove r voltage is hardly triggered due to the

powering limit by dynamic function. But , in the

abnormal condition, output OVP is triggered when VEAV

is higher than 4.0 V @ SET0 / 4.2 V @ SET1 for 4

switching cycles or V DD voltage is higher tha n 25 V for

10 us delay.

• Output Short Protection

At output short c ondition, VEAV is less than 0.7 V. I f this

condition lasts for continuous 3 5 ms switching time,

OSP is trigger e d.

• Over Current Protection

When CS volt age is higher than 1.8 V over the 1.2 V

pulse-by-pulse current l imit, protection is immediately

triggered. OCP protects output diode short, sensing

resistor open and transformer saturatio n co nd ition.

• Sensing Resistor Sho rt Protection

1st switching is 0.2 V current mode. If CS doesn’t reach

over 75 mV threshold during 1st turn-on time, SRSP is

triggered. Max. turn-on time at 1st switching is i nversely

proportio nal to input voltage to limit the primary peak

current.

• Over Load Protection

At over load condition, CS reaches to 1.2 V pulse-by-

pulse current limit. FL7740 generates internal ZC (Zero

Cross) signal a nd OLP is trigge r e d if the event (1.2V

current limit event b etween the two close ZC signals) is

occurred for consecutive 60 ZC si gna ls.

OLP

1.2 V

current limit

event

0 0 2358

57 59 60

OLP Count

Figure 24. Over Load Protection

• Thermal Shut Down

When i nternal junctio n temp era ture is higher than

150ºC, TS D i s triggered and protection is released when

the junction temperature drops under 120ºC.

FL7740

www.onsemi.com

AC Input

Secondary

DC-DC

Converter

MCU

module

Dimming

Signal

(Power GND)

(Signal GND)

FL7740

GATE

BIAS

VDD

COMV

GND

PG line goes

under R

HV1

GATE

CS line goes

under R

GATE

HV2

VDD line goes

under R

HV2

HV3

SG line goes

under R

HV3

G-GATE and S-GND distance should be short.

SG and PG are connected close at GND pin.

COMV,BIAS,PF,VS circuit ground and aux. winding

VDD circuit ground are connected close at GND pin.

SMD filter cap is connected close at VDD and GND pin.

Powering lines (Drain and PG) are closely placed and

away from FL7740 control circuits.

Bridge

diode

Single layer PCB layout guidance

ORDERING INFORMATION

Device Package Shipping

FL7740MX 10 Lead SOIC, JDEC MS-012, 150” Narrow Body Tape and Reel

FL7740

PACKAGE DIMENSIONS

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