IS61SP25616
IS61SP25618 ISSI®
Integrated Silicon Solution, Inc. — 1-800-379-4774
1
Rev. A
04/17/01
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any
errors which may appear in this publication. © Copyright 2001, Integrated Silicon Solution, Inc.
FEATURES
• Internal self-timed write cycle
• Individual Byte Write Control and Global Write
• Clock controlled, registered address, data and
control
• Pentium™ or linear burst sequence control using
MODE input
• Three chip enables for simple depth expansion
and address pipelining
• Common data inputs and data outputs
• JEDEC 100-Pin TQFP and
119-pin PBGA package
• Single +3.3V, +10%, -5% power supply
• Power-down snooze mode
DESCRIPTION
The ISSI IS61SP25616 and IS61SP25618 is a high-speed
synchronous static RAM designed to provide a burstable,
high-performance memory for high speed networking and
communication applications. It is organized as 262,144
words by 16 bits and 18 bits, fabricated with ISSI's
advanced CMOS technology. The device integrates a 2-bit
burst counter, high-speed SRAM core, and high-drive
capability outputs into a single monolithic circuit. All
synchronous inputs pass through registers controlled by
a positive-edge-triggered single clock input.
Write cycles are internally self-timed and are initiated by
the rising edge of the clock input. Write cycles can be from
one to four bytes wide as controlled by the write control
inputs.
Separate byte enables allow individual bytes to be written.
BW1 controls DQ1-8, BW2 controls DQ9-16, conditioned
by BWE being LOW. A LOW on GW input would cause all
bytes to be written.
Bursts can be initiated with either ADSP (Address Status
Processor) or ADSC (Address Status Cache Controller)
input pins. Subsequent burst addresses can be generated
internally and controlled by the ADV (burst address
advance) input pin.
The mode pin is used to select the burst sequence order,
Linear burst is achieved when this pin is tied LOW.
Interleave burst is achieved when this pin is tied HIGH or
left floating.
APRIL 2001
FAST ACCESS TIME
Symbol Parameter -166 -150 -133 -5 Units
tKQ Clock Access Time 3.5 3.8 4 5 ns
tKC Cycle Time 6 6.7 7.5 10 ns
Frequency 166 150 133 100 MHz
256K x 16, 256K x 18 SYNCHRONOUS
PIPELINED STATIC RAM
IS61SP25616
IS61SP25618 ISSI
®
2
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
04/17/01
BLOCK DIAGRAM
BURST
COUNTER
A2-A17
A1
A0
GW
MODE
ADSC
ADSP
ADDRESS
REGISTER
BW1
BYTE WRITE
REGISTER
BW2
BYTE WRITE
REGISTER
ENABLE
REGISTER
ENABLE
REGISTER
BWE
BW1
BW2
256K x 16/256K x 18
MEMORY ARRAY
16 or 18
DATA
INPUT
REGISTER
CLK
16 or 18
2
ADV
CLK
218
18 16
2
CLK2
DATA
OUTPUT
REGISTER
CLK2 CLK
OE
CE1
CE2
CE2
CLR
DQ1 - DQ16
or
DQ1 - DQ18
IS61SP25616
IS61SP25618 ISSI
®
Integrated Silicon Solution, Inc. — 1-800-379-4774
3
Rev. A
04/17/01
PIN CONFIGURATION
PIN DESCRIPTIONS
A0, A1 Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
A2-A17 Synchronous Address Inputs
CLK Synchronous Clock
ADSP Synchronous Processor Address
Status
ADSC Synchronous Controller Address
Status
ADV Synchronous Burst Address Advance
BW1-BW2 Synchronous Byte Write Enable
BWE Synchronous Byte Write Enable
GW Synchronous Global Write Enable
CE, CE2, CE2 Synchronous Chip Enable
OE Output Enable
DQ1-DQ16 Synchronous Data Input/Output
MODE Burst Sequence Mode Selection
VCC +3.3V Power Supply
GND Ground
VCCQ
Isolated Output Buffer Supply: +3.3V
ZZ Snooze Enable
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
VCCQ
NC
NC
DQ9
NC
VCCQ
NC
DQ12
VCCQ
NC
DQ14
VCCQ
DQ16
NC
NC
NC
VCCQ
A6
CE2
A7
NC
DQ10
NC
DQ11
NC
VCC
DQ13
NC
DQ15
NC
NC
A5
A11
NC
A4
A3
A2
GND
GND
GND
BW2
GND
NC
GND
GND
GND
GND
GND
MODE
A10
NC
ADSP
ADSC
VCC
NC
CE
OE
ADV
GW
VCC
CLK
NC
BWE
A1
A0
VCC
NC
NC
A8
A9
A12
GND
GND
GND
GND
GND
NC
GND
BW1
GND
GND
GND
NC
A14
NC
A16
CE2
A15
NC
NC
DQ7
NC
DQ5
VCC
NC
DQ3
NC
DQ2
NC
A13
A17
NC
VCCQ
NC
NC
NC
DQ8
VCCQ
DQ6
NC
VCCQ
DQ4
NC
VCCQ
NC
DQ1
NC
ZZ
VCCQ
1 2 3 4 5 6 7
A17
NC
NC
VCCQ
GND
NC
NC
DQ8
DQ7
GND
VCCQ
DQ6
DQ5
GND
NC
VCC
ZZ
DQ4
DQ3
VCCQ
GND
DQ2
DQ1
NC
NC
GND
VCCQ
NC
NC
NC
A6
A7
CE
CE2
NC
NC
BW2
BW1
CE2
VCC
GND
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A8
A9
NC
NC
NC
VCCQ
GND
NC
NC
DQ9
DQ10
GND
VCCQ
DQ11
DQ12
NC
VCC
NC
GND
DQ13
DQ14
VCCQ
GND
DQ15
DQ16
NC
NC
GND
VCCQ
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
MODE
A5
A4
A3
A2
A1
A0
NC
NC
GND
VCC
NC
NC
A10
A11
A12
A13
A14
A15
A16
46 47 48 49 50
256K x 16
119-pin PBGA (Top View) 100-Pin TQFP
IS61SP25616
IS61SP25618 ISSI
®
4
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
04/17/01
PIN CONFIGURATION
PIN DESCRIPTIONS
A0, A1 Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
A2-A17 Synchronous Address Inputs
CLK Synchronous Clock
ADSP Synchronous Processor Address
Status
ADSC Synchronous Controller Address
Status
ADV Synchronous Burst Address Advance
BW1-BW2 Synchronous Byte Write Enable
BWE Synchronous Byte Write Enable
GW Synchronous Global Write Enable
CE, CE2, CE2 Synchronous Chip Enable
OE Output Enable
DQ1-DQ16 Synchronous Data Input/Output
MODE Burst Sequence Mode Selection
VCC +3.3V Power Supply
GND Ground
VCCQ Isolated Output Buffer Supply: +3.3V
ZZ Snooze Enable
DQP1-DQP2
Parity Data I/O DQP1 is parity for DQ1-8;
DQP2 is parity for DQ9-16
A17
NC
NC
VCCQ
GND
NC
DQP1
DQ8
DQ7
GND
VCCQ
DQ6
DQ5
GND
NC
VCC
ZZ
DQ4
DQ3
VCCQ
GND
DQ2
DQ1
NC
NC
GND
VCCQ
NC
NC
NC
A6
A7
CE
CE2
NC
NC
BW2
BW1
CE2
VCC
GND
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A8
A9
NC
NC
NC
VCCQ
GND
NC
NC
DQ9
DQ10
GND
VCCQ
DQ11
DQ12
NC
VCC
NC
GND
DQ13
DQ14
VCCQ
GND
DQ15
DQ16
DQP2
NC
GND
VCCQ
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
MODE
A5
A4
A3
A2
A1
A0
NC
NC
GND
VCC
NC
NC
A10
A11
A12
A13
A14
A15
A16
46 47 48 49 50
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
VCCQ
NC
NC
DQ9
NC
VCCQ
NC
DQ12
VCCQ
NC
DQ14
VCCQ
DQ16
NC
NC
NC
VCCQ
A6
CE2
A7
NC
DQ10
NC
DQ11
NC
VCC
DQ13
NC
DQ15
NC
DQP2
A5
A11
NC
A4
A3
A2
GND
GND
GND
BW2
GND
NC
GND
GND
GND
GND
GND
MODE
A10
NC
ADSP
ADSC
VCC
NC
CE
OE
ADV
GW
VCC
CLK
NC
BWE
A1
A0
VCC
NC
NC
A8
A9
A12
GND
GND
GND
GND
GND
NC
GND
BW1
GND
GND
GND
GND
A14
NC
A16
CE2
A15
DQP1
NC
DQ7
NC
DQ5
VCC
NC
DQ3
NC
DQ2
NC
A13
A17
NC
VCCQ
NC
NC
NC
DQ8
VCCQ
DQ6
NC
VCCQ
DQ4
NC
VCCQ
NC
DQ1
NC
ZZ
VCCQ
1 2 3 4 5 6 7
256K x 18
119-pin PBGA (Top View) 100-Pin TQFP
IS61SP25616
IS61SP25618 ISSI
®
Integrated Silicon Solution, Inc. — 1-800-379-4774
5
Rev. A
04/17/01
TRUTH TABLE
Address
Operation Used CE CE2 CE2 ADSP ADSC ADV WRITE OE DQ
Deselected, Power-down None H X X X L X X X High-Z
Deselected, Power-down None L X H L XXXXHigh-Z
Deselected, Power-down None L L X L XXXXHigh-Z
Deselected, Power-down None X X H H L X X X High-Z
Deselected, Power-down None X L X H L X X X High-Z
Read Cycle, Begin Burst External L H L L XXXXQ
Read Cycle, Begin Burst External L H L H L X Read X Q
Write Cycle, Begin Burst External L H L H L X Write X D
Read Cycle, Continue Burst Next X X X H H L Read L Q
Read Cycle, Continue Burst Next X X X H H L Read H High-Z
Read Cycle, Continue Burst Next H X X X H L Read L Q
Read Cycle, Continue Burst Next H X X X H L Read H High-Z
Write Cycle, Continue Burst Next X X X H H L Write X D
Write Cycle, Continue Burst Next H X X X H L Write X D
Read Cycle, Suspend Burst Current X X X H H H Read L Q
Read Cycle, Suspend Burst Current X X X H H H Read H High-Z
Read Cycle, Suspend Burst Current H X X X H H Read L Q
Read Cycle, Suspend Burst Current H X X X H H Read H High-Z
Write Cycle, Suspend Burst Current X X X H H H Write X D
Write Cycle, Suspend Burst Current H X X X H H Write X D
PARTIAL TRUTH TABLE
Function GW BWE BW1 BW2
Read H H X X
Read H L H H
Write Byte 1 H L L H
Write All Bytes H L L L
Write All Bytes L X X X
IS61SP25616
IS61SP25618 ISSI
®
6
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
04/17/01
INTERLEAVED BURST ADDRESS TABLE (MODE = VCC or No Connect)
External Address 1st Burst Address 2nd Burst Address 3rd Burst Address
A1 A0 A1 A0 A1 A0 A1 A0
00 01 10 11
01 00 11 10
10 11 00 01
11 10 01 00
LINEAR BURST ADDRESS TABLE (MODE = GND)
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Parameter Value Unit
TBIAS Temperature Under Bias –40 to +85 °C
TSTG Storage Temperature –55 to +150 °C
PDPower Dissipation 1.6 W
IOUT Output Current (per I/O) 100 mA
VIN, VOUT Voltage Relative to GND for I/O Pins –0.5 to VCCQ + 0.3 V
VIN Voltage Relative to GND for –0.5 to VCC + 0.5 V
for Address and Control Inputs
VCC Voltage on Vcc Supply Relatiive to GND –0.5 to 4.6 V
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause perma-
nent damage to the device. This is a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
2. This device contains circuitry to protect the inputs against damage due to high static voltages
or electric fields; however, precautions may be taken to avoid application of any voltage higher
than maximum rated voltages to this high-impedance circuit.
3. This device contains circuitry that will ensure the output devices are in High-Z at power up.
0,0
1,0
0,1A1', A0' = 1,1
IS61SP25616
IS61SP25618 ISSI
®
Integrated Silicon Solution, Inc. — 1-800-379-4774
7
Rev. A
04/17/01
OPERATING RANGE
Range Ambient Temperature VCC
Commercial 0°C to +70°C 3.3V, +10%, –5%
Industrial –40°C to +85°C 3.3V, +10%, –5%
DC ELECTRICAL CHARACTERISTICS(1) (Over Operating Range)
Symbol Parameter Test Conditions Min. Max. Unit
VOH Output HIGH Voltage IOH = –4.0 mA 2.4 —V
VOL Output LOW Voltage IOL = 8.0 mA —0.4 V
VIH Input HIGH Voltage 2.0 VCCQ + 0.3 V
VIL Input LOW Voltage –0.3 0.8 V
ILI Input Leakage Current GND ≤ VIN ≤ VCCQ(2) Com. –22µA
Ind. –55
ILO Output Leakage Current GND ≤ VOUT ≤ VCCQ, OE = VIH Com. –22µA
Ind. –55
POWER SUPPLY CHARACTERISTICS (Over Operating Range)
-166 -
150
-
133
-5
Symbol Parameter Test Conditions
Max. Max. Max Max. Uni
t
ICC AC Operating Device Selected, Com. 210 190 170 160 mA
Supply Current All Inputs = VIL or VIH Ind. —200 180 170 mA
OE = VIH, Vcc = Max.
Cycle Time ≥ tKC min.
ISB Standby Current Device Deselected, Com. 60 60 60 60 mA
VCC = Max., Ind. —70 70 70 mA
All Inputs = VIH or VIL
CLK Cycle Time ≥ tKC min.
IZZ Power-down Mode ZZ = VCC Com. 15 15 15 15 mA
Current Clock Running Ind. —20 20 20 mA
All Inputs ≤ GND + 0.2V
or ≥ Vcc – 0.2V
Notes:
1. The MODE pin has an internal pullup. This pin may be a No Connect, tied to GND, or tied to VCC.
2. The MODE pin could be tied to Vcc or GND. It exhibits ±10 µA maximum leakage current when tied to ≤ GND + 0.2V
or ≥ Vcc – 0.2V.
IS61SP25616
IS61SP25618 ISSI
®
8
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
04/17/01
CAPACITANCE(1,2)
Symbol Parameter Conditions Max. Unit
CIN Input Capacitance VIN = 0V 6 pF
COUT Input/Output Capacitance VOUT = 0V 8 pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25°C, f = 1 MHz, Vcc = 3.3V.
AC TEST CONDITIONS
Parameter Unit
Input Pulse Level 0V to 3.0V
Input Rise and Fall Times 1.5 ns
Input and Output Timing 1.5V
and Reference Level
Output Load See Figures 1 and 2
AC TEST LOADS
Output
Buffer
ZO
= 50Ω
1.5V
50Ω
30 pF
317 Ω
5 pF
Including
jig and
scope
351 Ω
OUTPUT
3.3V
Figure 1 Figure 2
IS61SP25616
IS61SP25618 ISSI
®
Integrated Silicon Solution, Inc. — 1-800-379-4774
9
Rev. A
04/17/01
READ/WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
-166 -150 -133 -5
Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Unit
fMAX
(3)
Clock Frequency —166 —150 —133 —100 MHz
tKC
(3)
Cycle Time 6 —6.7 —7.5 —10 —ns
tKH Clock High Time 2.4 —2.6 —2.8 —3—ns
tKL
(3)
Clock Low Time 2.4 —2.6 —2.8 —3—ns
tKQ
(3)
Clock Access Time —3.5 —3.8 —4—5ns
tKQX
(1)
Clock High to Output Invalid 3 —3—3—3—ns
tKQLZ
(1,2)
Clock High to Output Low-Z 0 —0—0—0—ns
tKQHZ
(1,2)
Clock High to Output High-Z 1.5 3.5 1.5 3.5 1.5 3.5 1.5 3.5 ns
tOEQ
(3)
Output Enable to Output Valid —3.5 —3.5 —3.8 —5ns
tOEQX
(1)
Output Disable to Output Invalid 0 —0—0—0—ns
tOELZ
(1,2)
Output Enable to Output Low-Z 0 —0—0—0—ns
tOEHZ
(1,2)
Output Disable to Output High-Z 2 3.5 2 3.5 2 3.8 2 5 ns
tAS
(3)
Address Setup Time 2 —2—2—2—ns
tSS
(3)
Address Status Setup Time 2 —2—2—2—ns
tWS
(3)
Write Setup Time 2 —2—2—2—ns
tCES
(3)
Chip Enable Setup Time 2 —2—2—2—ns
tAVS
(3)
Address Advance Setup Time 2 —2—2—2—ns
tAH
(3)
Address Hold Time 0.5 —0.5 —0.5 —0.5 —ns
tSH
(3)
Address Status Hold Time 0.5 —0.5 —0.5 —0.5 —ns
tWH
(3)
Write Hold Time 0.5 —0.5 —0.5 —0.5 —ns
tCEH
(3)
Chip Enable Hold Time 0.5 —0.5 —0.5 —0.5 —ns
tAVH
(3)
Address Advance Hold Time 0.5 —0.5 —0.5 —0.5 —ns
Note:
1. Guaranteed but not 100% tested. This parameter is periodically sampled.
2. Tested with load in Figure 2.
3. Tested with load in Figure 1.
IS61SP25616
IS61SP25618 ISSI
®
10
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
04/17/01
READ/WRITE CYCLE TIMING
Single Read
High-Z
High-Z
DATA
OUT
DATA
IN
OE
CE2
CE2
CE
BW2-BW1
BWE
GW
A17-A0
ADV
ADSC
ADSP
CLK
RD1 RD2
1a 2c 2d 3a
Unselected
Burst Read
tKQX
tKC
tKLtKH
tSS tSH
tSS tSH
tAS tAH
tWS tWH
tWS tWH
RD3
tCES tCEH
tCES tCEH
tCES tCEH
CE2 and CE2 only sampled with ADSP or ADSC
CE Masks ADSP
Unselected with CE2
tOEQ
tOEQX
tOELZ
tKQLZ
tKQ
tOEHZ
tKQHZ
ADSC initiate read
ADSP is blocked by CE inactive
tAVH
tAVS
Suspend Burst
Pipelined Read
2a 2b
IS61SP25616
IS61SP25618 ISSI
®
Integrated Silicon Solution, Inc. — 1-800-379-4774
11
Rev. A
04/17/01
WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
-166 -150 -133 -5
Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Unit
tKC
(1)
Cycle Time 6 —6.7 —7.5 —10 —ns
tKH
(1)
Clock High Time 2.4 —2.6 —2.8 —4—ns
tKL
(1)
Clock Low Time 2.4 —2.6 —2.8 —4—ns
tAS
(1)
Address Setup Time 2 —2—2—2—ns
tSS
(1)
Address Status Setup Time 2 —2—2—2—ns
tWS
(1)
Write Setup Time 2 —2—2—2—ns
tDS
(1)
Data In Setup Time 2 —2—2—2—ns
tCES
(1)
Chip Enable Setup Time 2 —2—2—2—ns
tAVS
(1)
Address Advance Setup Time 2 —2—2—2—ns
tAH
(1)
Address Hold Time 0.5 —0.5 —0.5 —0.5 —ns
tSH
(1)
Address Status Hold Time 0.5 —0.5 —0.5 —0.5 —ns
tDH
(1)
Data In Hold Time 0.5 —0.5 —0.5 —0.5 —ns
tWH
(1)
Write Hold Time 0.5 —0.5 —0.5 —0.5 —ns
tCEH
(1)
Chip Enable Hold Time 0.5 —0.5 —0.5 —0.5 —ns
tAVH
(1)
Address Advance Hold Time 0.5 —0.5 —0.5 —0.5 —ns
Note:
1. Tested with load in Figure 1.
IS61SP25616
IS61SP25618 ISSI
®
12
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
04/17/01
WRITE CYCLE TIMING
Single Write
DATA
OUT
DATA
IN
OE
CE2
CE2
CE
BW2-BW1
BWE
GW
A17-A0
ADV
ADSC
ADSP
CLK
WR1 WR2
Unselected
Burst Write
t
KC
t
KL
t
KH
t
SS
t
SH
t
AS
t
AH
t
WS
t
WH
t
WS
t
WH
WR3
t
CES
t
CEH
t
CES
t
CEH
t
CES
t
CEH
CE2 and CE2 only sampled with ADSP or ADSC
CE Masks ADSP
Unselected with CE2
ADSC initiate Write
ADSP is blocked by CE inactive
t
AVH
t
AVS
ADV must be inactive for ADSP Write
WR1 WR2
t
WS
t
WH
WR3
t
WS
t
WH
High-Z
High-Z 1a 3a
t
DS
t
DH
BW4-BW1 only are applied to first cycle of WR2
Write
2c 2d2b2a
IS61SP25616
IS61SP25618 ISSI
®
Integrated Silicon Solution, Inc. — 1-800-379-4774
13
Rev. A
04/17/01
SNOOZE AND RECOVERY CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
-166 -150 -133 -5
Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Unit
tKC
(3)
Cycle Time 6 —6.7 —7.5 —10 —ns
tKH
(3)
Clock High Time 2.4 —2.6 —2.8 —4—ns
tKL
(3)
Clock Low Time 2.4 —2.6 —2.8 —4—ns
tKQ
(3)
Clock Access Time —3.5 —3.8 —4—5ns
tKQX
(1)
Clock High to Output Invalid 1.5 —1.5 —1.5 —2.5 —ns
tKQLZ
(1,2)
Clock High to Output Low-Z 0 —0—0—0—ns
tKQHZ
(1,2)
Clock High to Output High-Z 1.5 3.5 1.5 3.5 1.5 3.5 1.5 3.5 ns
tOEQ
(3)
Output Enable to Output Valid —3.5 —3.5 —3.9 —5ns
tOEQX
(1)
Output Disable to Output Invalid 0 —0—0—0—ns
tOELZ
(1,2)
Output Enable to Output Low-Z 0 —0—0—0—ns
tOEHZ
(1,2)
Output Disable to Output High-Z 2 3.5 2 3.5 2 3.8 2 5 ns
tAS
(3)
Address Setup Time 2 —2—2—2—ns
tSS
(3)
Address Status Setup Time 2 —2—2—2—ns
tCES
(3)
Chip Enable Setup Time 2 —2—2—2—ns
tAH
(3)
Address Hold Time 0.5 —0.5 —0.5 —0.5 —ns
tSH
(3)
Address Status Hold Time 0.5 —0.5 —0.5 —0.5 —ns
tCEH
(3)
Chip Enable Hold Time 0.5 —0.5 —0.5 —0.5 —ns
tZZS ZZ Standby 2 —2—2—2—cyc
tZZREC ZZ Recovery 2 —2—2—2—cyc
Notes:
1. Guaranteed but not 100% tested. This parameter is periodically sampled.
2. Tested with load in Figure 2.
3. Tested with load in Figure 1.
IS61SP25616
IS61SP25618 ISSI
®
14
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
04/17/01
SNOOZE AND RECOVERY CYCLE TIMING
Single Read
High-Z
High-Z
DATAOUT
DATAIN
ZZ
OE
CE2
CE2
CE
BW2-BW1
BWE
GW
A17-A0
ADV
ADSC
ADSP
CLK
RD1
1a
Read
Snooze with Data Retention
tKC
tKLtKH
tSS tSH
tAS tAH
RD2
tCES tCEH
tCES tCEH
tCES tCEH
tOEQ
tOEQX
tOELZ
tKQLZ
tKQ
tOEHZ
tKQX
tKQHZ
tZZS tZZREC
IS61SP25616
IS61SP25618 ISSI
®
Integrated Silicon Solution, Inc. — 1-800-379-4774
15
Rev. A
04/17/01
ORDERING INFORMATION
Commercial Range: 0°C to +70°C
Speed Order Part Number Package
166 MHz IS61SP25618-166TQ TQFP
IS61SP25618-166B PBGA
150 MHz IS61SP25618-150TQ TQFP
IS61SP25618-150B PBGA
133 MHz IS61SP25618-133TQ TQFP
IS61SP25618-133B PBGA
5 ns IS61SP25618-5TQ TQFP
IS61SP25618-5B PBGA
Industrial Range: –40°C to +85°C
Speed Order Part Number Package
150 MHz IS61SP25618-150TQI TQFP
133 MHz IS61SP25618-133TQI TQFP
5 ns IS61SP25618-5TQI TQFP
ISSI
®
Integrated Silicon Solution, Inc.
2231 Lawson Lane
Santa Clara, CA 95054
Tel: 1-800-379-4774
Fax: (408) 588-0806
E-mail: sales@issi.com
www.issi.com
ORDERING INFORMATION
Commercial Range: 0°C to +70°C
Speed Order Part Number Package
166 MHz IS61SP25616-166TQ TQFP
IS61SP25616-166B PBGA
150 MHz IS61SP25616-150TQ TQFP
IS61SP25616-150B PBGA
133 MHz IS61SP25616-133TQ TQFP
IS61SP25616-133B PBGA
5 ns IS61SP25616-5TQ TQFP
IS61SP25616-5B PBGA
Industrial Range: –40°C to +85°C
Speed Order Part Number Package
150 MHz IS61SP25616-150TQI TQFP
133 MHz IS61SP25616-133TQI TQFP
5 ns IS61SP25616-5TQI TQFP
