1
Features
•32-Mbit Flash and 4-Mbit/8-Mbit SRAM
•Single 66-ball 8 mm x 11 mm CBGA Package
•2.7V to 3.3V Operating Voltage
Flash
•2.7V to 3.3V Read/Write
•Access Time – 85, 90, 110 ns
•Sector Erase Architecture
– Sixty-three 32K Word (64K Byte) Sectors with Individual Write Lockout
– Eight 4K Word (8K Byte) Sectors with Individual Write Lockout
•Fast Word Program Time – 20 µs
•Fast Sector Erase Time – 200 ms
•Dual-plane Organization, Permitting Concurrent Read while Program/Erase
Memory Plane A: Eight 4K Word and Fifteen 32K Word Sectors
Memory Plane B: Forty-eight 32K Word Sectors
•Erase Suspend Capability
– Supports Reading/Programming Data from Any Sector by Suspending Erase of
Any Different Sector
•Low-power Operation
–25mAActive
– 10 µA Standby
•Data Polling, Toggle Bit, Ready/Busy for End of Program Detection
•VPP Pin for Accelerated Program/Erase Operations
•RESET Input for Device Initialization
•Sector Lockdown Support
•Top or Bottom Boot Block Configuration Available
•128-bit Protection Register
SRAM
•4-megabit (256K x 16)/8-megabit (512K x 16)
•2.7V to 3.3V VCC
•70 ns Access Time
•Fully Static Operation and Tri-state Output
•1.2V (Min) Data Retention
•Industrial Temperature Range
Device Number Flash Boot Location
Flash Plane
Architecture SRAM Configuration
AT52BR3244 Bottom 24M + 8M 256K x 16
AT52BR3244T Top 24M + 8M 256K x 16
AT52BR3248 Bottom 24M + 8M 512K x 16
AT52BR3248T Top 24M + 8M 512K x 16
32-megabit
(2M x 16) Flash
+4-megabit
(256K x 16)/
8-megabit
(512K x 16)
SRAM
Stack Memory
AT52BR3244
AT52BR3244T
AT52BR3248
AT52BR3248T
Not Recommended for
New Designs. New
Designs Should Use
AT52BR3224(T)/3228(T)
Rev. 2471E–STKD–10/02
2AT52BR3244(T)/3248(T)
2471E–STKD–10/02
AT52BR3244(T)/
AT52BR3248(T)
(Top View)
Pin Configurations l
A
B
C
D
E
F
G
H
123456789101112
NC
NC
NC
NC
A20
A16
WE
SGND
NC
SLB
A18
NC
A11
A8
RDY/BSY
RESET
VPP
SUB
A17
A5
A15
A10
A19
SOE
A7
A4
A14
A9
D11
A6
A0
A13
D15
D13
D12
D9
A3
CE
A12
SWE
D6
SCS2
D10
D8
A2
GND
GND
D14
D4
SVCC
D2
D0
A1
OE
NC
D7
D5
VCC
D3
D1
SCS1
NC
NC
NC
NC
NC
Pin Name Function
A0 - A20 Addresses
CE Flash Chip Enable
OE Flash Output Enable
WE Flash Write Enable
RESET Flash Reset
RDY/BUSY Flash READY/BUSY Output
VPP Flash Power Supply for Accelerated Program/Erase Operations
VCC Flash Power
GND Flash Ground
I/O0 - I/O15 Data Inputs/Outputs
NC No Connect
SLB SRAM Lower Byte
SUB SRAM Upper Byte
SVCC SRAM Power
SGND SRAM Ground
SCS1 SRAM Chip Select 1
SCS2 SRAM Chip Select 2
SWE SRAM Write Enable
SOE SRAM Output Enable
3
AT52BR3244(T)/3248(T)
2471E–STKD–10/02
Description
The AT52BR3244(T) combines a 32-megabit Flash (2M x 16) and a 4-megabit SRAM in a stacked 66-ball CBGA package.
The AT52BR3248(T) combines a 32-megabit Flash (2M x 16) and a 8-megabit SRAM in a stacked 66-ball CBGA package.
The devices operate at 2.7V to 3.3V in the industrial temperature range. They use a 32-megabit Flash with dual plane
architecture for concurrent read/write operations. It is organized as 24M + 8M for planes A and B, respectively. The
4-megabit SRAM is organized as 256K x 16, while the 8-megabit SRAM is organized as 512K x 16.
Block Diagram
Absolute Maximum Ratings
Temperature under Bias .................................. -40°Cto+85°C*NOTICE: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability.
Storage Temperature ..................................... -55°Cto+150°C
All Input Voltages
except VPP and RESET
(including NC Pins)
with Respect to Ground .....................................-0.2V to +3.3V
Voltage on VPP
with Respect to Ground ..................................-0.2V to + 6.25V
Voltage on RESET
with Respect to Ground ...................................-0.2V to +13.5V
All Output Voltages
with Respect to Ground .....................................-0.2V to +0.2V
DC and AC Operating Range
AT52BR3244(T)-85, -90 AT52BR3248(T)-85, -90
Operating Temperature (Case) Industrial -40°C-85°C-40°C-85°C
VCC Power Supply 2.7V to 3.3V 2.7V to 3.3V
32-Mbit
FLASH
4/8-Mbit
SRAM
ADDRESS
DATA
RESET
CE
RDY/BUSY
SCS1
SCS2
WEOE SWESOE
4AT52BR3244(T)/3248(T)
2471E–STKD–10/02
32-megabit Flash
Description
The 32-megabit Flash memory is organized as 2,097,152 words of 16 bits each or
4,194,304 bytes of 8 bits each. The x16 data appears on I/O0 - I/O15; the x8 data
appears on I/O0 - I/O7. The memory is divided into 71 sectors for erase operations. The
device has CE and OE control signals to avoid any bus contention. This device can be
read or reprogrammed using a single 2.7V power supply, making it ideally suited for in-
system programming.
The device powers on in the read mode. Command sequences are used to place the
device in other operation modes such as program and erase. The device has the capa-
bility to protect the data in any sector (see Sector Lockdown section).
The device is segmented into two memory planes. Reads from memory plane B may be
performed even while program or erase functions are being executed in memory plane
A and vice versa. This operation allows improved system performance by not requiring
the system to wait for a program or erase operation to complete before a read is per-
formed. To further increase the flexibility of the device, it contains an Erase Suspend
feature. This feature will put the erase on hold for any amount of time and let the user
read data from or program data to any of the remaining sectors within the same memory
plane. There is no reason to suspend the erase operation if the data to be read is in the
other memory plane. The end of a program or an erase cycle is detected by the
Ready/Busy pin, Data Polling or by the toggle bit.
The VPP pin provides faster program/erase times. With VPP at 5.0V or 12.0V, the pro-
gram and erase operations are accelerated.
A six-byte command (Enter Single Pulse Program Mode) sequence to remove the
requirement of entering the three-byte program sequence is offered to further improve
programming time. After entering the six-byte code, only single pulses on the write con-
trol lines are required for writing into the device. This mode (Single Pulse Word
Program) is exited by powering down the device, or by pulsing the RESET pin low for a
minimum of 50 ns and then bringing it back to VCC. Erase and Erase Suspend/Resume
commands will not work while in this mode; if entered they will result in data being pro-
grammed into the device. It is not recommended that the six-byte code reside in the
software of the final product but only exist in external programming code.
5
AT52BR3244(T)/3248(T)
2471E–STKD–10/02
32-megabit Flash Memory Block Diagram
IDENTIFIER
REGISTER
STATUS
REGISTER
DATA
COMPARATOR
OUTPUT
MULTIPLEXER
OUTPUT
BUFFER
INPUT
BUFFER
COMMAND
REGISTER
DATA
REGISTER
Y-GATING
WRITE STATE
MACHINE PROGRAM/ERASE
VOLTAGE SWITCH
CE
WE
OE
RESET
RDY/BUSY
VPP
VCC
GND
Y-DECODER
X-DECODER
INPUT
BUFFER
ADDRESS
LATCH
I/O0 - I/O15/A-1
A0 - A20
PLANE B
SECTORS
PLANE A SECTORS
6AT52BR3244(T)/3248(T)
2471E–STKD–10/02
Device Operation READ: The 32-megabit Flash is accessed like an EPROM. When CE and OE are low
and WE is high, the data stored at the memory location determined by the address pins
are asserted on the outputs. The outputs are put in the high-impedance state whenever
CE or OE is high. This dual-line control gives designers flexibility in preventing bus
contention.
COMMAND SEQUENCES: Whenthedeviceisfirstpoweredonitwillberesettothe
read or standby mode, depending upon the state of the control line inputs. In order to
perform other device functions, a series of command sequences are entered into the
device. The command sequences are shown in the Command Definitions table (I/O8 -
I/O15 are don’t care inputs for the command codes). The command sequences are writ-
ten by applying a low pulse on the WE or CE input with CE or WE low (respectively) and
OE high. The address is latched on the falling edge of CE or WE, whichever occurs last.
The data is latched by the first rising edge of CE or WE. Standard microprocessor write
timings are used. The address locations used in the command sequences are not
affected by entering the command sequences.
RESET: A RESET input pin is provided to ease some system applications. When
RESET is at a logic high level, the device is in its standard operating mode. A low level
on the RESET input halts the present device operation and puts the outputs of the
device in a high-impedance state. When a high level is reasserted on the RESET pin,
the device returns to the read or standby mode, depending upon the state of the control
inputs.
ERASURE: Before a word can be reprogrammed, it must be erased. The erased state
of memory bits is a logical “1”. The entire device can be erased by using the Chip Erase
command or individual sectors can be erased by using the Sector Erase command.
CHIP ERASE: Theentiredevicecanbeerasedatonetimebyusingthesix-bytechip
erase software code. After the chip erase has been initiated, the device will internally
time the erase operation so that no external clocks are required. The maximum time to
erase the chip is tEC.
If the sector lockdown has been enabled, the chip erase will not erase the data in the
sector that has been locked out; it will erase only the unprotected sectors. After the chip
erase, the device will return to the read or standby mode.
SECTOR ERASE: As an alternative to a full chip erase, the device is organized into 71
sectors (SA0 - SA70) that can be individually erased. The Sector Erase command is a
six-bus cycle operation. The sector address is latched on the falling WE edge of the
sixth cycle while the 30H data input command is latched on the rising edge of WE.The
sector erase starts after the rising edge of WE of the sixth cycle. The erase operation is
internally controlled; it will automatically time to completion. The maximum time to erase
a section is tSEC. When the sector programming lockdown feature is not enabled, the
sector will erase (from the same Sector Erase command). An attempt to erase a sector
that has been protected will result in the operation terminating in 2 µs.
WORD PROGRAMMING: Once a memory block is erased, it is programmed (to a logi-
cal “0”) on a word-by-word basis. Programming is accomplished via the internal device
command register and is a four-bus cycle operation. The device will automatically gen-
erate the required internal program pulses.
Any commands written to the chip during the embedded programming cycle will be
ignored. If a hardware reset happens during programming, the data at the location being
programmed will be corrupted. Please note that a data “0” cannot be programmed back
to a “1”; only erase operations can convert “0”s to “1”s. Programming is completed after
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AT52BR3244(T)/3248(T)
2471E–STKD–10/02
the specified tBP cycle time. The Data Polling feature or the Toggle Bit feature may be
used to indicate the end of a program cycle.
VPP PIN: The circuitry of the 32-megabit Flash is designed so that the device can be
programmed or erased from the VCC power supply or from the VPP input pin. When VPP
is less than or equal to the VCC pin, the device selects the VCC supply for programming
and erase operations. When the VPP pin is greater than the VCC supply, the device will
select the VPP input as the power supply for programming and erase operations. The
device will allow for some variations between the VPP input and the VCC power supply in
its selection of VCC or VPP for program or erase operations. If the VPP pin is within 0.3V
of VCC for 2.7V < VCC < 3.3V, then the program or erase operations will use VCC and dis-
regard the VPP input signal. When the VPP signal is used to accelerate program and
erase operations, the VPP must be in the 5V ± 0.5V or 12V ± 0.5V range to ensure
proper operation. The Vpp pin can be left unconnected.
SECTOR LOCKDOWN: Each sector has a programming lockdown feature. This feature
prevents programming of data in the designated sectors once the feature has been
enabled. These sectors can contain secure code that is used to bring up the system.
Enabling the lockdown feature will allow the boot code to stay in the device while data in
the rest of the device is updated. This feature does not have to be activated; any sec-
tor’s usage as a write protected region is optional to the user.
At power-up or reset all sectors are unlocked. To activate the lockdown for a specific
sector, the six-bus cycle Sector Lockdown command must be issued. Once a sector has
been locked down, the contents of the sector is read-only and cannot be erased or
programmed.
SECTOR LOCKDOWN DETECTION: A software method is available to determine if
programming of a sector is locked down. When the device is in the software product
identification mode (see Software Product Identification Entry and Exit sections) a read
from address location 00002H within a sector will show if programming the sector is
lockeddown.IfthedataonI/O0islow,thesectorcanbeprogrammed;ifthedataon
I/O0 is high, the program lockdown feature has been enabled and the sector cannot be
programmed. The software product identification exit code should be used to return to
standard operation.
SECTOR LOCKDOWN OVERRIDE: The only way to unlock a sector that is locked
down is through reset or power-up cycles. After power-up or reset, the content of a sec-
tor that is locked down can be erased and reprogrammed.
ERASE SUSPEND/ERASE RESUME: The Erase Suspend command allows the sys-
tem to interrupt a sector erase operation and then program or read data from a different
sector within the same plane. Since this device has a dual-plane architecture, there is
no need to use the Erase Suspend feature while erasing a sector when you want to read
data from a sector in the other plane. After the Erase Suspend command is given, the
device requires a maximum time of 15 µs to suspend the erase operation. After the
erase operation has been suspended, the plane that contains the suspended sector
enters the erase-suspend-read mode. The system can then read data or program data
to any other sector within the device. An address is not required during the Erase Sus-
pend command. During a sector erase suspend, another sector cannot be erased. To
resume the sector erase operation, the system must write the Erase Resume command.
The Erase Resume command is a one-bus cycle command, which does require the
plane address (determined by A20 - A19). The device also supports an erase suspend
during a complete chip erase. While the chip erase is suspended, the user can read
from any sector within the memory that is protected. The command sequence for a chip
erase suspend and a sector erase suspend are the same.
8AT52BR3244(T)/3248(T)
2471E–STKD–10/02
PRODUCT IDENTIFICATION: The product identification mode identifies the device and
manufacturer as Atmel. It may be accessed by hardware or software operation. The
hardware operation mode can be used by an external programmer to identify the correct
programming algorithm for the Atmel product.
For details, see “Operating Modes” on page 16 (for hardware operation) or “Software
Product Identification Entry/Exit” on page 24. The manufacturer and device codes are
the same for both modes.
128-BIT PROTECTION REGISTER: The 32-megabit Flash contains a 128-bit register
that can be used for security purposes in system design. The protection register is
divided into two 64-bit blocks. The two blocks are designated as block A and block B.
The data in block A is non-changeable and is programmed at the factory with a unique
number. The data in block B is programmed by the user and can be locked out such that
data in the block cannot be reprogrammed. To program block B in the protection regis-
ter, the four-bus cycle Program Protection Register command must be used as shown in
the Command Definition table on page 10. To lock out block B, the four-bus cycle Lock
Protection Register command must be used as shown in the Command Definition table.
Data bit D0 must be one during the fourth bus cycle. All other data bits during the fourth
bus cycle are don’t cares. Please see the “Protection Register Addressing Table” on
page 11 for the address locations in the protection register. To read the protection regis-
ter, the Product ID Entry command is given followed by a normal read operation from an
address within the protection register. After reading the protection register, the Product
ID Exit command must be given prior to performing any other operation.
DATA POLLING: The Flash features Data Polling to indicate the end of a program
cycle. During a program cycle an attempted read of the last word loaded will result in the
complement of the loaded data on I/O7. Once the program cycle has been completed,
true data is valid on all outputs and the next cycle may begin. During a chip or sector
erase operation, an attempt to read the device will give a “0” on I/O7. Once the program
or erase cycle has completed, true data will be read from the device. Data Polling may
begin at any time during the program cycle. Please see “Status Bit Table” on page 25 for
more details.
TOGGLE BIT: In addition to Data Polling, the 32-megabit Flash provides another
method for determining the end of a program or erase cycle. During a program or erase
operation, successive attempts to read data from the same memory plane will result in
I/O6 toggling between one and zero. Once the program cycle has completed, I/O6 will
stop toggling and valid data will be read. Examining the toggle bit may begin at any time
during a program cycle.
An additional toggle bit is available on I/O2, which can be used in conjunction with the
toggle bit that is available on I/O6. While a sector is erase suspended, a read or a pro-
gram operation from the suspended sector will result in the I/O2 bit toggling. Please see
“Status Bit Table” on page 25 for more details.
RDY/BUSY:An open-drain Ready/Busy output pin provides another method of detect-
ing the end of a program or erase operation. RDY/BUSY is actively pulled low during the
internal program and erase cycles and is released at the completion of the cycle. The
open-drain connection allows for OR-tying of several devices to the same RDY/BUSY
line.
HARDWARE DATA PROTECTION: The Hardware Data Protection feature protects
against inadvertent programs to the Flash in the following ways: (a) VCC sense: if VCC is
below 1.8V (typical), the program function is inhibited. (b) VCC power-on delay: once VCC
has reached the VCC sense level, the device will automatically time out 10 ms (typical)
before programming. (c) Program inhibit: holding any one of OE low, CE high or WE
9
AT52BR3244(T)/3248(T)
2471E–STKD–10/02
high inhibits program cycles. (d) Noise filter: pulses of less than 15 ns (typical) on the
WE or CE inputs will not initiate a program cycle.
INPUT LEVELS: While operating with a 2.7V to 3.3V power supply, the address inputs
and control inputs (OE,CEand WE) may be driven from 0 to 5.5V without adversely
affecting the operation of the device. The I/O lines can only be driven from 0 to VCC +
0.6V.
10 AT52BR3244(T)/3248(T)
2471E–STKD–10/02
Notes: 1. The DATA FORMAT shown for each bus cycle is as follows; I/O7 - I/O0 (Hex). In word operation I/O15 - I/O8 are Don’t Care.
The ADDRESS FORMAT shown for each bus cycle is as follows: A11 - A0 (Hex). Address A20 through A11 are Don’t Care
in the word mode. Address A20 through A11 and A-1 are Don’t Care in the byte mode.
2. Since A11 is a Don’t Care, AAA can be replaced with 2AA.
3. SA = sector address. Any word address within a sector can be used to designate the sector address (see pages 12-14 for
details).
4. Once a sector is in the lockdown mode, data in the protected sector cannot be changed unless the chip is reset or power
cycled.
5. PA is the plane address (A20 - A19).
6. Either one of the Product ID Exit commands can be used.
7. If data bit D1 is “0”, block B is locked. If data bit D1 is “1”, block B can be reprogrammed.
CommandDefinitioninHex
(1)
Command
Sequence
Bus
Cycles
1st Bus
Cycle
2nd Bus
Cycle
3rd Bus
Cycle
4th Bus
Cycle
5th Bus
Cycle
6th Bus
Cycle
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Read 1 Addr DOUT
Chip Erase 6 555 AA AAA(2) 55 555 80 555 AA AAA 55 555 10
Sector Erase 6 555 AA AAA 55 555 80 555 AA AAA 55 SA(3)(4) 30
Word Program 4 555 AA AAA 55 555 A0 Addr DIN
Enter Single Pulse
Program Mode 6 555 AA AAA 55 555 80 555 AA AAA 55 555 A0
Single Pulse Word
Program 1AddrD
IN
Sector Lockdown 6 555 AA AAA 55 555 80 555 AA AAA 55 SA(3)(4) 60
Erase Suspend 1 XXX B0
Erase Resume 1 PA(5) 30
Product ID Entry 3 555 AA AAA 55 555 90
Product ID Exit(6) 3 555 AA AAA 55 555 F0
Product ID Exit(6) 1 XXX F0
Program Protection
Register 4 555 AA AAA 55 555 C0 Addr DIN
Lock Protection
Register - Block B 4 555 AA AAA 55 555 C0 080 X0
Status of Block B
Protection 4 555 AA AAA 55 555 90 80 DOUT(7)
Absolute Maximum Ratings*
Temperature under Bias ................................ -55°C to +125°C *NOTICE: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability.
Storage Temperature ..................................... -65°C to +150°C
All Input Voltages
(including NC Pins)
with Respect to Ground ...................................-0.6V to +6.25V
All Output Voltages
with Respect to Ground .............................-0.6V to VCC +0.6V
Voltage on OE and VPP
with Respect to Ground ...................................-0.6V to +13.0V
11
AT52BR3244(T)/3248(T)
2471E–STKD–10/02
Note: 1. All address lines not specified in the above table must be 0 when accessing the protection register, i.e., A20 - A8 = 0.
Protection Register Addressing Table
Word Use Block A7 A6 A5 A4 A3 A2 A1 A0
0 Factory A 10000001
1 Factory A 10000010
2 Factory A 10000011
3 Factory A 10000100
4 User B 10000101
5 User B 10000110
6 User B 10000111
7 User B 10001000
12 AT52BR3244(T)/3248(T)
2471E–STKD–10/02
Bottom Boot 32-megabit Flash (24M + 8M ) Sector Address Table
Plane Sector Size (Words)
x16
Address Range (A20 - A0)
A SA0 4K 00000 - 00FFF
A SA1 4K 01000 - 01FFF
A SA2 4K 02000 - 02FFF
A SA3 4K 03000 - 03FFF
A SA4 4K 04000 - 04FFF
A SA5 4K 05000 - 05FFF
A SA6 4K 06000 - 06FFF
A SA7 4K 07000 - 07FFF
A SA8 32K 08000 - 0FFFF
A SA9 32K 10000 - 17FFF
A SA10 32K 18000 - 1FFFF
A SA11 32K 20000 - 27FFF
A SA12 32K 28000 - 2FFFF
A SA13 32K 30000 - 37FFF
A SA14 32K 38000 - 3FFFF
A SA15 32K 40000 - 47FFF
A SA16 32K 48000 - 4FFFF
A SA17 32K 50000 - 57FFF
A SA18 32K 58000 - 5FFFF
A SA19 32K 60000 - 67FFF
A SA20 32K 68000 - 6FFFF
A SA21 32K 70000 - 77FFF
A SA22 32K 78000 - 7FFFF
B SA23 32K 80000 - 87FFF
B SA24 32K 88000 - 8FFFF
B SA25 32K 90000 - 97FFF
B SA26 32K 98000 - 9FFFF
B SA27 32K A0000 - A7FFF
B SA28 32K A8000 - AFFFF
B SA29 32K B0000 - B7FFF
B SA30 32K B8000 - BFFFF
B SA31 32K C0000 - C7FFF
B SA32 32K C8000 - CFFFF
B SA33 32K D0000 - D7FFF
B SA34 32K D8000 - DFFFF
B SA35 32K E0000 - E7FFF
B SA36 32K E8000 - EFFFF
13
AT52BR3244(T)/3248(T)
2471E–STKD–10/02
B SA37 32K F0000 - F7FFF
B SA38 32K F8000 - FFFFF
B SA39 32K 100000 - 107FFF
B SA40 32K 108000 - 10FFFF
B SA41 32K 110000 - 117FFF
B SA42 32K 118000 - 11FFFF
B SA43 32K 120000 - 127FFF
B SA44 32K 128000 - 12FFFF
B SA45 32K 130000 - 137FFF
B SA46 32K 138000 - 13FFFF
B SA47 32K 140000 - 147FFF
B SA48 32K 148000 - 14FFFF
B SA49 32K 150000 - 157FFF
B SA50 32K 158000 - 15FFFF
B SA51 32K 160000 - 167FFF
B SA52 32K 168000 - 16FFFF
B SA53 32K 170000 - 177FFF
B SA54 32K 178000 - 17FFFF
B SA55 32K 180000 - 187FFF
B SA56 32K 188000 - 18FFFF
B SA57 32K 190000 - 197FFF
B SA58 32K 198000 - 19FFFF
B SA59 32K 1A0000 - 1A7FFF
B SA60 32K 1A8000 - 1AFFFF
B SA61 32K 1B0000 - 1B7FFF
B SA62 32K 1B8000 - 1BFFFF
B SA63 32K 1C0000 - 1C7FFF
B SA64 32K 1C8000 - 1CFFFF
B SA65 32K 1D0000 - 1D7FFF
B SA66 32K 1D8000 - 1DFFFF
B SA67 32K 1E0000 - 1E7FFF
B SA68 32K 1E8000 - 1EFFFF
B SA69 32K 1F0000 -1F7FFF
B SA70 32K 1F8000 - 1FFFF
Bottom Boot 32-megabit Flash (24M + 8M ) Sector Address Table (Continued)
Plane Sector Size (Words)
x16
Address Range (A20 - A0)
14 AT52BR3244(T)/3248(T)
2471E–STKD–10/02
Top Boot 32-megabit Flash (24M + 8M) Sector Address Table
Plane Sector Size (Words)
x16
Address Range (A20 - A0)
B SA0 32K 00000 - 07FFF
B SA1 32K 08000 - 0FFFF
B SA2 32K 10000 - 17FFF
B SA3 32K 18000 - 1FFFF
B SA4 32K 20000 - 27FFF
B SA5 32K 28000 - 2FFFF
B SA6 32K 30000 - 37FFF
B SA7 32K 38000 - 3FFFF
B SA8 32K 40000 - 47FFF
B SA9 32K 48000 - 4FFFF
B SA10 32K 50000 - 57FFF
B SA11 32K 58000 - 5FFFF
B SA12 32K 60000 - 67FFF
B SA13 32K 68000 - 6FFFF
B SA14 32K 70000 - 77FFF
B SA15 32K 78000 - 7FFFF
B SA16 32K 80000 - 87FFF
B SA17 32K 88000 - 8FFFF
B SA18 32K 90000 - 97FFF
B SA19 32K 98000 - 9FFFF
B SA20 32K A0000 - A7FFF
B SA21 32K A8000 - AFFFF
B SA22 32K B0000 - B7FFF
B SA23 32K B8000 - BFFFF
B SA24 32K C0000 - C7FFF
B SA25 32K C8000 - CFFFF
B SA26 32K D0000 - D7FFF
B SA27 32K D8000 - DFFFF
B SA28 32K E0000 - E7FFF
B SA29 32K E8000 - EFFFF
B SA30 32K F0000 - F7FFF
B SA31 32K F8000 - FFFFF
B SA32 32K 100000 - 107FFF
B SA33 32K 108000 - 10FFFF
B SA34 32K 110000 - 117FFF
B SA35 32K 118000 - 11FFFF
B SA36 32K 120000 - 127FFF
15
AT52BR3244(T)/3248(T)
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B SA37 32K 128000 - 12FFFF
B SA38 32K 130000 - 137FFF
B SA39 32K 138000 - 13FFFF
B SA40 32K 140000 - 147FFF
B SA41 32K 148000 - 14FFFF
B SA42 32K 150000 - 157FFF
B SA43 32K 158000 - 15FFFF
B SA44 32K 160000 - 167FFF
B SA45 32K 168000 - 16FFFF
B SA46 32K 170000 - 177FFF
B SA47 32K 178000 - 17FFFF
A SA48 32K 180000 - 187FFF
A SA49 32K 188000 - 18FFFF
A SA50 32K 190000 - 197FFF
A SA51 32K 198000 - 19FFFF
A SA52 32K 1A0000 - 1A7FFF
A SA53 32K 1A8000 - 1AFFFF
A SA54 32K 1B0000 - 1B7FFF
A SA55 32K 1B8000 - 1BFFFF
A SA56 32K 1C0000 - 1C7FFF
A SA57 32K 1C8000 - 1CFFFF
A SA58 32K 1D0000 - 1D7FFF
A SA59 32K 1D8000 - 1DFFFF
A SA60 32K 1E0000 - 1E7FFF
A SA61 32K 1E8000 - 1EFFFF
A SA62 32K 1F0000 - 1F7FFF
A SA63 4K 1F8000 - 1F8FFF
A SA64 4K 1F9000 - 1F9FFF
A SA65 4K 1FA000 - 1FAFFF
A SA66 4K 1FB000 - 1FBFFF
A SA67 4K 1FC000 - 1FCFFF
A SA68 4K 1FD000 - 1FDFFF
A SA69 4K 1FE000 - 1FEFFF
A SA70 4K 1FF000 - 1FFFFF
Top Boot 32-megabit Flash (24M + 8M) Sector Address Table (Continued)
Plane Sector Size (Words)
x16
Address Range (A20 - A0)
16 AT52BR3244(T)/3248(T)
2471E–STKD–10/02
Notes: 1. X can be VIL or VIH.
2. Refer to AC programming waveforms on page 23.
3. VH= 12.0V ± 0.5V.
4. Manufacturer Code: 001FH, Device Code: 00D8H - AT4952BR3244/3248;
00D9H - AT52BR3244T/3248T.
5. See details under “Software Product Identification Entry/Exit” on page 24.
6. VPP can be left unconnected or 0V ≤VPP ≤3.3V. For faster erase/program operations, VPP can be set to 5.0V ± 0.5V or
12V ± 0.5V.
DC and AC Operating Range
AT52BR3244(T)-85, 90 AT52BR3248(T)-85, 90
Operating Temperature (Case) Ind. -40°C - 85°C -40°C - 85°C
VCC Power Supply 2.7V to 3.3V 2.7V to 3.3V
Operating Modes
Mode CE OE WE RESET VPP Ai I/O
Read VIL VIL VIH VIH XAiD
OUT
Program/Erase(2) VIL VIH VIL VIH VPP(6) Ai DIN
Standby/Program Inhibit VIH X(1) XV
IH XXHigh-Z
Program Inhibit
XXV
IH VIH X
XV
IL XV
IH X
Output Disable X VIH XV
IH XHigh-Z
Reset X X X VIL XXHigh-Z
Product Identification
Hardware VIL VIL VIH VIH
A1 - A20 = VIL,A9=V
H(3),A0=V
IL Manufacturer Code(4)
A1 - A20 = VIL,A9=V
H(3),A0=V
IH Device Code(4)
Software(5) VIH
A0 = VIL,A1-A20=V
IL Manufacturer Code(4)
A0 = VIH,A1-A20=V
IL Device Code(4)
17
AT52BR3244(T)/3248(T)
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Note: 1. In the erase mode, ICC is 50 mA.
DC Characteristics
Symbol Parameter Condition Min Max Units
ILI Input Load Current VIN =0VtoV
CC 10 µA
ILO Output Leakage Current VI/O =0VtoV
CC 10 µA
ISB1 VCC Standby Current CMOS CE =V
CC -0.3VtoV
CC 10 µA
ISB2 VCC Standby Current TTL CE =2.0VtoV
CC 1mA
ISB3 VCC Standby Current TTL CE =2.0VtoV
CC,V
CC = 2.85V 10 µA
ICC (1) VCC Active Read Current f = 5 MHz; IOUT =0mA 30 mA
ICC1 VCC Programming Current (VPP =V
CC)30 mA
IPP1 VPP Input Load Current
VPP =0V,V
CC =3.0V -10 µA
VPP =V
CC =3.0V 50 µA
ICC2 VCC Programming Current (VPP = 5.0V ± 0.5V) 30 mA
IPP2 VPP Programming Current (VPP = 5.0V ± 0.5V) 25 mA
ICC3 VCC Programming Current (VPP = 12.0V ± 0.5V) 30 mA
IPP3 VPP Programming Current (VPP = 12.0V ± 0.5V) 40 mA
VIL Input Low Voltage 0.6 V
VIH Input High Voltage 2.0 V
VOL1 Output Low Voltage IOL =2.1mA 0.45 V
VOL2 Output Low Voltage IOL =1.0mA 0.20 V
VOH1 Output High Voltage IOH =-400µA 2.4 V
VOH2 Output High Voltage IOH =-100µA 2.5 V
18 AT52BR3244(T)/3248(T)
2471E–STKD–10/02
AC Read Waveforms(1)(2)(3)(4)
Notes: 1. CE may be delayed up to tACC -t
CE after the address transition without impact on tACC.
2. OE may be delayed up to tCE -t
OE after the falling edge of CE withoutimpacton
tCE or by tACC -t
OE after an address change without impact on tACC.
3. tDF is specified from OE or CE, whichever occurs first (CL = 5 pF).
4. This parameter is characterized and is not 100% tested.
AC Read Characteristics
Symbol Parameter
AT52BR3244(T)/3248(T)-85 AT52BR3244(T)/3248(T)-90 AT52BR3244(T)/3248(T)-110
UnitsMin Max Min Max Min Max
tACC Address to Output Delay 85 90 110 ns
tCE(1) CE to Output Delay 85 90 110 ns
tOE(2) OE to Output Delay 0 40 0 40 0 40 ns
tDF(3)(4) CE or OE to Output Float 0 25 0 25 0 25 ns
tOH
Output Hold from OE,CEor
Address, whichever
occurred first
000ns
tRO RESET to Output Delay 600 600 600 ns
OUTPUT
VALID
OUTPUT HIGH Z
RESET
OE tOE
tCE
ADDRESS VALID
tDF
tOH
tACC
tRO
CE
ADDRESS
19
AT52BR3244(T)/3248(T)
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Input Test Waveforms and Measurement Level
tR,t
F<5ns
Output Test Load
Note: 1. This parameter is characterized and is not 100% tested.
Pin Capacitance
f=1MHz,T=25°C
(1)
Symbol Typ Max Units Conditions
CIN 46pFV
IN =0V
COUT 812pFV
OUT =0V
20 AT52BR3244(T)/3248(T)
2471E–STKD–10/02
AC Word Load Characteristics
AC Word Load Waveforms
WE Controlled
CE Controlled
Symbol Parameter Min Max Units
tAS,t
OES Address, OE Setup Time 0 ns
tAH Address Hold Time 50 ns
tCS Chip Select Setup Time 0 ns
tCH Chip Select Hold Time 0 ns
tWP Write Pulse Width (WE or CE)50ns
tDS Data Setup Time 40 ns
tDH,t
OEH Data, OE Hold Time 10 ns
tWPH Write Pulse Width High 40 ns
21
AT52BR3244(T)/3248(T)
2471E–STKD–10/02
Program Cycle Waveforms
Program Cycle Characteristics
Symbol Parameter Min Typ Max Units
tBP Word Programming Time (0V < VPP < 4.5V) 20 50 µs
tBPVPP Word Programming Time (VPP >4.5V) 10 25 µs
tAS Address Setup Time 0 ns
tAH Address Hold Time 50 ns
tDS Data Setup Time 40 ns
tDH Data Hold Time 10 ns
tWP Write Pulse Width 50 ns
tWPH Write Pulse Width High 40 ns
tWC WriteCycleTime 90 ns
tSR/W Latency between Read and Write Operations 0 ns
tRP Reset Pulse Width 500 ns
tRH Reset High Time before Read 200 ns
tEC ChipEraseCycleTime(V
PP < 4.5V) 10 seconds
tECVPP ChipEraseCycleTime(V
PP >4.5V) 5 seconds
tSEC SectorEraseCycleTime(V
PP < 4.5V) 200 400 ms
tSECVPP SectorEraseCycleTime(V
PP >4.5V) 100 150 ms
tEPS Erase or Program Suspend Time 15 µs
OE
PROGRAM CYCLE
ADDRESS
A0
55
555
AA
AAA
tBP
tWPH
tWP
CE
WE
A0- A20
DATA
tAS tAH
tWC
tDH
tDS
OUTPUT
DATA
555
SR/W
t
VALID
READ ADDRESS
ACC
t
INPUT DATA
22 AT52BR3244(T)/3248(T)
2471E–STKD–10/02
Sector or Chip Erase Cycle Waveforms
Notes: 1. OE must be high only when WE and CE are both low.
2. For chip erase, the address should be 555. For sector erase, the address depends on what sector is to be erased.
(See note 3 under Command Definitions.)
3. For chip erase, the data should be 10H, and for sector erase, the data should be 30H.
OE (1)
AA
80 Note 3
55 55
555 555 Note 2
AA
WORD 0 WORD 1 WORD 2 WORD 3 WORD 4 WORD 5
AAA AAA
t
WPH
t
WP
CE
WE
A0 - A20
DATA
t
AS
t
AH
EC
t
t
DH
t
DS
555
t
WC
ADDRESS
VALID
OUTPUT
VALID
ACC
t
t
SR/W
t
23
AT52BR3244(T)/3248(T)
2471E–STKD–10/02
Notes: 1. These parameters are characterized and not 100% tested.
2. See tOE spec in “AC Read Characteristics” on page 18.
Data Polling Waveforms
Notes: 1. These parameters are characterized and not 100% tested.
2. See tOE spec in “AC Read Characteristics” on page 18.
Toggle Bit Waveforms(1)(2)(3)
Notes: 1. Toggling either OE or CE or both OE and CE will operate toggle bit.
The tOEHP specification must be met by the toggling input(s).
2. Beginning and ending state of I/O6 will vary.
3. Any address location may be used but the address should not vary.
Data Polling Characteristics(1)
Symbol Parameter Min Typ Max Units
tDH Data Hold Time 10 ns
tOEH OE Hold Time 10 ns
tOE OE to Output Delay(2) ns
tWR Write Recovery Time 0 ns
A0-A20
FWE
FCE
FOE
I/O7
tDH
t
tHIGH Z
An An An An An
t
OEH
OE WR
Toggle Bit Characteristics(1)
Symbol Parameter Min Typ Max Units
tDH Data Hold Time 10 ns
tOEH OE Hold Time 10 ns
tOE OE to Output Delay(2) ns
tOEHP OE High Pulse 150 ns
tWR Write Recovery Time 0 ns
FWE
FCE
FOE
I/O6
tOEH
tDH tOE
tOEHP
HIGH Z tWR
24 AT52BR3244(T)/3248(T)
2471E–STKD–10/02
Software Product Identification
Entry(1)
Software Product Identification
Exit(1)(6)
Notes: 1. Data Format: I/O15 - I/O8 (Don’t Care); I/O7 - I/O0 (Hex)
Address Format: A11 - A0 (Hex) and A11 - A20 (Don’t
Care).
2. A1 - A20 = VIL. Manufacturer Code is read for A0 = VIL;
Device Code is read for A0 = VIH. Additional Device Code
is read for address 0003H
3. The device does not remain in identification mode if pow-
ered down.
4. The device returns to standard operation mode.
5. Manufacturer Code: 001FH(x16) Device Code: 00D8H-
AT52BR3244/3248; 00D9H-AT52BR3244T/3248T.
6. Either one of the Product ID Exit commands can be used.
LOAD DATA AA
TO
ADDRESS 555
LOAD DATA 55
TO
ADDRESS AAA
LOAD DATA 90
TO
ADDRESS 555
ENTER PRODUCT
IDENTIFICATION
MODE(2)(3)(5)
LOAD DATA AA
TO
ADDRESS 555
LOAD DATA 55
TO
ADDRESS AAA
LOAD DATA F0
TO
ADDRESS 555
EXIT PRODUCT
IDENTIFICATION
MODE(4)
OR LOAD DATA F0
TO
ANY ADDRESS
EXIT PRODUCT
IDENTIFICATION
MODE(4)
Sector Lockdown Enable Algorithm(1)
Notes: 1. Data Format: I/O15 - I/O8 (Don’t Care); I/O7 - I/O0 (Hex)
Address Format: A11 - A0 (Hex) and A11 - A20 (Don’t
Care).
2. Sector Lockdown feature enabled.
LOAD DATA AA
TO
ADDRESS 555
LOAD DATA 55
TO
ADDRESS AAA
LOAD DATA 80
TO
ADDRESS 555
LOAD DATA AA
TO
ADDRESS 555
LOAD DATA 55
TO
ADDRESS AAA
LOAD DATA 60
TO
SECTOR ADDRESS
PAUSE 200 µs(2)
25
AT52BR3244(T)/3248(T)
2471E–STKD–10/02
Status Bit Table
Status Bit
I/O7 I/O6 I/O2
Read Address In Plane A Plane B Plane A Plane B Plane A Plane B
While
Programming in Plane A I/O7 DATA TOGGLE DATA 1 DATA
Programming in Plane B DATA I/O7 DATA TOGGLE DATA 1
Erasing in Plane A 0 DATA TOGGLE DATA TOGGLE DATA
Erasing in Plane B DATA 0 DATA TOGGLE DATA TOGGLE
Erase Suspended & Read
Erasing Sector 1 1 1 1 TOGGLE TOGGLE
Erase Suspended & Read
Non-erasing Sector DATA DATA DATA DATA DATA DATA
Erase Suspended &
Program Non-erasing Sector
in Plane A
I/O7 DATA TOGGLE DATA TOGGLE DATA
Erase Suspended &
Program Non-erasing Sector
in Plane B
DATA I/O7 DATA TOGGLE DATA TOGGLE
26 AT52BR3244(T)/3248(T)
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4-megabit SRAM
Description
The 4-megabit SRAM is a high-speed, super low-power CMOS SRAM organized as
256K words by 16 bits. The SRAM uses high-performance full CMOS process technol-
ogy and is designed for high-speed and low-power circuit technology. It is particularly
well-suited for the high-density low-power system application. This device has a data
retention mode that guarantees data to remain valid at a minimum power supply voltage
of 1.2V.
Features
•Fully Static Operation and Tri-state Output
•TTL Compatible Inputs and Outputs
•Battery Backup
– 1.2V (Min) Data Retention
Block Diagram
Voltage (V) Speed (ns)
Operation
Current/ICC (mA)
(Max)
Standby
Current (µA)
(Max)
Temperature
(°C)
2.7 - 3.3 70 5 15 -40 - 85
MEMORY ARRAY
256K X 16
I/O0
SUB
SLB
SOE
SCS2
SCS1
SWE
DATA I/O BUFFER
SENSE AMP WRITE DRIVER
I/O7
I/O8
I/O15
ROW DECODER
COLUMN
DECODER
BLOCK
DECODER
PRE DECODER
ADD INPUT BUFFER
A0
A17
27
AT52BR3244(T)/3248(T)
2471E–STKD–10/02
Note: 1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is
stress rating only and the functional operation of the device under these or any other conditions above those indicated in the
operation of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may
affect reliability.
Notes: 1. H = VIH,L=V
IL,X=Don'tCare(V
IL or VIH)
2. SUB,SLB(Upper, Lower Byte Enable). These active LOW inputs allow individual bytes to be written or read. When SLB is
LOW, data is written or read to the lower byte, I/O0 - I/O7. When SUB is LOW, data is written or read to the upper byte, I/O8
- I/O15.
Note: 1. Undershoot: VIL = -1.5V for pulse width less than 30 ns. Undershoot is sampled, not 100% tested.
Absolute Maximum Ratings(1)
Symbol Parameter Rating Unit
VIN,V
OUT Input/Output Voltage -0.3 to 3.6 V
VCC Power Supply -0.3 to 4.6 V
TAOperating Temperature -40 to 85 °C
TSTG Storage Temperature -55 to 150 °C
PDPower Dissipation 1.0 W
Truth Table
SCS1 SCS2 SWE SOE SLB(2) SUB(2) Mode
I/O Pin
PowerI/O0 - I/O7 I/O8 - I/O15
H(1) X
XXXXDeselected High-Z High-Z StandbyX(1) L
XX HH
L(1) HHH
LH
Output Disabled High-Z High-Z ActiveHL
LL
LHLX
LH
Write
DIN High-Z
Active
HL High-Z D
IN
LL
DIN DIN
DIN High-Z
LHHL
LH
Read
DOUT High-Z
Active
HL High-Z D
OUT
LL DOUT DOUT
DOUT High-Z
Recommended DC Operating Condition
Symbol Parameter Min Typ Max Unit
VCC Supply Voltage 2.7 3.0 3.3 V
VSS Ground 0 0 0 V
VIH Input High Voltage 2.2 VCC +0.3 V
VIL(1) Input Low Voltage -0.31(1) 0.6 V
28 AT52BR3244(T)/3248(T)
2471E–STKD–10/02
Note: 1. Typical values are at VCC =1.8VT
A=25°C. Typical values are not 100% tested.
Note: 1. These parameters are sampled and not 100% tested.
DC Electrical Characteristics
TA=-40°Cto85°C
Symbol Parameter Test Condition Min Typ(1) Max Unit
ILI Input Leakage Current VSS <V
IN <V
CC -1 1 µA
ILO Output Leakage Current VSS <V
OUT <V
CC,
SCS1 =V
IH or SCS2=VIL or
SOE =V
IH or SWE =VILor
SUB =V
IH,SLB=V
IH
-1 1 µA
ICC Operating Power Supply Current SCS1 =V
IL,SCS2=V
IH,
VIN =V
IH or VIL,I
I/O =0mA
5mA
ICC1 Average Operating Current SCS1 =V
IL,SCS2=V
IH,
VIN =V
IH or VIL,CycleTime=Min
100% Duty, II/O =0mA
35 mA
SCS1 < 0.2V, SCS2 > VCC -0.2V
VIN <0.2VorV
IN >V
CC -0.2V,
CycleTime=1µs
100% Duty, II/O =0mA
5mA
ISB Standby Current (TTL Input) SCS1 =V
IH or SCS2 = VIL or
SUB,SLB=V
IH
VIN =V
IH or VIL
0.5 mA
ISB1 Standby Current (CMOS Input) SCS1 >V
CC -0.2Vor
SCS2 < VSS +0.2Vor
SUB,SLB>V
CC -0.2V
VIN >V
CC -0.2Vor
VIN <V
SS +0.2V
SL 0.2 4 µA
LL 0.2 15 µA
VOL Output Low IOL =0.1mA 0.4 V
VOH Output High IOH =-0.1mA 2.4 V
Capacitance(1)
(Temp = 25°C, f = 1.0 MHz)
Symbol Parameter Condition Max Unit
CIN Input Capacitance (Add, SCS1,
SCS2, SLB,SUB,SWE,SOE)
VIN =0V 8 pF
COUT Output Capacitance (I/O) VI/O =0V 10 pF
29
AT52BR3244(T)/3248(T)
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AC Characteristics
TA=-40°Cto85°C, Unless Otherwise Specified
# Symbol Parameter
70 ns
UnitMin Max
1t
RC Read Cycle Time 70 ns
2t
AA Address Access Time 70 ns
3t
ACS Chip Select Access Time 70 ns
4t
OE Output Enable to Output Valid 35 ns
5t
BA SLB,SUBAccess Time 70 ns
6t
CLZ Chip Select to Output in Low Z 10 ns
7t
OLZ Output Enable to Output in Low Z 5 ns
8t
BLZ SLB,SUBEnable to Output in Low Z 10 ns
9t
CHZ Chip Deselection to Output in High Z 0 30 ns
10 tOHZ Out Disable to Output in High Z 0 30 ns
11 tBHZ SLB,SUBDisable to Output in High Z 0 30 ns
12 tOH Output Hold from Address Change 10 ns
13 tWC WriteCycleTime 70 ns
14 tCW Chip Selection to End of Write 60 ns
15 tAW Address Valid to End of Write 60 ns
16 tBW SLB,SUBValidtoEndofWrite 60 ns
17 tAS Address Setup Time 0 ns
18 tWP Write Pulse Width 50 ns
19 tWR Write Recovery Time 0 ns
20 tWHZ Write to Output in High Z 0 20 ns
21 tDW Data to Write Time Overlap 30 ns
22 tDH Data Hold from Write Time 0 ns
23 tOW Output Active from End of Write 5 ns
AC Test Conditions
TA = - 4 0 °Cto85°C, Unless Otherwise Specified
Parameter Value
Input Pulse Level 0.4V to 2.2V
Input Rise and Fall Time 5 ns
Input and Output Timing Reference Level 1.5V
Output Load CL = 5 pF + 1 TTL Load CL = 5 pF + 1 TTL Load
CL = 30 pF + 1 TTL Load CL = 30 pF + 1 TTL Load
30 AT52BR3244(T)/3248(T)
2471E–STKD–10/02
AC Test Loads
Note: Including jig and scope capacitance.
DOUT
3273 Ohm
CL
4091 Ohm
VTM = 1.8V
(1)
31
AT52BR3244(T)/3248(T)
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Timing Diagrams
Read Cycle 1(1),(4)
Read Cycle 2(1),(2),(4)
Read Cycle 3(1),(2),(4)
Notes: 1. Read Cycle occurs whenever a high on the SWE and SOE is low, while SUB and/or SLB and SCS1 and SCS2 are in active
status.
2. SOE =V
IL.
3. Transition is measured + 200 mV from steady state voltage. This parameter is sampled and not 100% tested.
4. SCS1 in high for the standby, low for active. SCS2 in low for the standby, high for active. SUB and SLB in high for the
standby, low for active.
ADDRESS
SOE
SUB, SLB
SCS1
SCS2
DATA OUT HIGH-Z DATA VALID
tAA
tRC
tBA
tACS
tOE
tOLZ
tBLZ
tCLZ
tBHZ
tCHZ
tOH
tOHZ
(3)
(3)
(3)
(3)
(3)
(3)
DATA OUT
ADDRESS
t
AA
PREVIOUS DATA
t
OH
DATA VALID
t
OH
t
RC
SUB, SLB
SCS1
SCS2
DATA OUT
tACS
tCLZ (3)
DATA VALID
tCHZ(3)
32 AT52BR3244(T)/3248(T)
2471E–STKD–10/02
WriteCycle1(SWEControlled)(1),(4),(8)
WriteCycle2(SCS1, SCS2 Controlled)(1),(4),(8)
Notes: 1. A write occurs during the overlap of a low SWE,alowSCS1, a high SCS2 and a low SUB and/or SLB.
2. tWR is measured from the earlier of SCS1,SLB,SUB,orSWEgoing high or SCS2 going low to the end of write cycle.
3. During this period, I/O pins are in the output state so that the input signals of opposite phase to the output must not be
applied.
4. If the SCS1,SLBand SUB low transition and SCS2 high transition occur simultaneously with the SWE low transition or after
the SWE transition, outputs remain in a high impedance state.
5. Q (data out) is the same phase with the write data of this write cycle.
6. Q (data out) is the read data of the next address.
7. Transition is measured + 200 mV from steady state. This parameter is sampled and not 100% tested.
8. SCS1 in high for the standby, low for active SCS2 in low for the standby, high for active. SUB and SLB in high for the
standby, low for active.
ADDRESS
SWE
SUB, SLB
DATA IN
SCS1
SCS2
DATA OUT
t
WC
t
CW
t
AW
t
BW
t
WP
t
AS
t
WHZ
t
WR
t
DW
t
DH
t
OW
DATA VALID
HIGH-Z
t
AS
(2)
(5) (5)
(3)(7)
ADDRESS
SWE
SUB, SLB
DATA IN
SCS1
SCS2
DATA OUT
t
WC
t
CW
t
AW
t
BW
t
WP
t
AS
t
WR
t
DW
t
DH
DATA VALID
HIGH-Z
(2)
HIGH-Z
33
AT52BR3244(T)/3248(T)
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Note: 1. Typical values are under the condition of TA=25°C. Typical values are sampled and not 100% tested.
Data Retention Timing Diagram 1
Data Retention Timing Diagram 2
Data Retention Electric Characteristic
TA=-40°Cto85°C
Symbol Parameter Test Condition Min Typ Max Unit
VDR VCC for Data Retention SCS1 >V
CC -0.2Vor
SCS2 < VSS +0.2Vor
SUB,SLB>V
CC -0.2V
VIN >V
CC -0.2Vor
VIN <V
SS +0.2V
1.2 3.3 V
ICCDR Data Retention Current Vcc=1.5V,
SCS1 >V
CC -0.2Vor
SCS2 < VSS +0.2Vor
SUB,SLB>V
CC -0.2V
VIN >V
CC -0.2Vor
VIN <V
SS +0.2V
SL 0.1 2 µA
LL 0.1 10 µA
tCDR See Data Retention
Timing Diagram
Chip Deselect to Data Retention Time 0 ns
tR Operating Recovery Time tRC
DATA RETENTION MODE
tR
tCDR
VCC
SCS1 > VCC - 0.2V
2.7V
IH
VDR
SCS1
VSS
VCC
2.7V
VDR
SCS2
VSS
0.4V
DATA RETENTION MODE
tR
tCDR
SCS2 < 0.2V
34 AT52BR3244(T)/3248(T)
2471E–STKD–10/02
8-megabit SRAM
Description
The 8-megabit SRAM is a high-speed, super low-power CMOS SRAM organized as
512K words by 16 bits. The SRAM uses high-performance full CMOS process technol-
ogy and is designed for high-speed and low-power circuit technology. It is particularly
well-suited for the high-density low-power system application. This device has a data
retention mode that guarantees data to remain valid at a minimum power supply voltage
of 1.2V.
Features
•Fully Static Operation and Tri-state Output
•TTL Compatible Inputs and Outputs
•Battery Backup
– 1.2V (Min) Data Retention
Block Diagram
Voltage (V) Speed (ns)
Operation
Current/ICC (mA)
(Max)
Standby
Current (µA)
(Max)
Temperature
(°C)
2.7 - 3.3 70 5 15 -40 - 85
MEMORY ARRAY
512K X 16
I/O0
SUB
SLB
SOE
SCS2
SCS1
SWE
DATA I/O BUFFER
SENSE AMP WRITE DRIVER
I/O7
I/O8
I/O15
ROW DECODER
COLUMN
DECODER
BLOCK
DECODER
PRE DECODER
ADD INPUT BUFFER
A0
A18
35
AT52BR3244(T)/3248(T)
2471E–STKD–10/02
Note: 1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is
stress rating only and the functional operation of the device under these or any other conditions above those indicated in the
operation of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may
affect reliability.
Notes: 1. H = VIH,L=V
IL,X=Don'tCare(V
IL or VIH)
2. SUB,SLB(Upper, Lower Byte Enable). These active LOW inputs allow individual bytes to be written or read. When SLB is
LOW, data is written or read to the lower byte, I/O0 - I/O7. When SUB is LOW, data is written or read to the upper byte, I/O8
- I/O15.
Note: 1. Undershoot: VIL = -1.5V for pulse width less than 30 ns. Undershoot is sampled, not 100% tested.
Absolute Maximum Ratings(1)
Symbol Parameter Rating Unit
VIN,V
OUT Input/Output Voltage -0.3 to 3.6 V
VCC Power Supply -0.3 to 4.6 V
TAOperating Temperature -40 to 85 °C
TSTG Storage Temperature -55 to 150 °C
PDPower Dissipation 1.0 W
Truth Table
SCS1 SCS2 SWE SOE SLB(2) SUB(2) Mode
I/O Pin
PowerI/O0 - I/O7 I/O8 - I/O15
H(1) X
XXXXDeselected High-Z High-Z StandbyX(1) L
XX HH
L(1) HHH
LH
Output Disabled High-Z High-Z ActiveHL
LL
LHLX
LH
Write
DIN High-Z
Active
HL High-Z D
IN
LL DIN DIN
DIN High-Z
LHHL
LH
Read
DOUT High-Z
Active
HL High-Z D
OUT
LL
DOUT DOUT
DOUT High-Z
Recommended DC Operating Condition
Symbol Parameter Min Typ Max Unit
VCC Supply Voltage 2.7 3.0 3.3 V
VSS Ground 0 0 0 V
VIH Input High Voltage 2.2 VCC +0.3 V
VIL(1) Input Low Voltage -0.31(1) 0.6 V
36 AT52BR3244(T)/3248(T)
2471E–STKD–10/02
Note: 1. Typical values are at VCC =1.8VT
A=25°C. Typical values are not 100% tested.
Note: 1. These parameters are sampled and not 100% tested.
DC Electrical Characteristics
TA=-40°Cto85°C
Symbol Parameter Test Condition Min Typ(1) Max Unit
ILI Input Leakage Current VSS <V
IN <V
CC -1 1 µA
ILO Output Leakage Current VSS <V
OUT <V
CC,
SCS1 =V
IH or SCS2=VIL or
SOE =V
IH or SWE =VILor
SUB =V
IH,SLB=V
IH
-1 1 µA
ICC Operating Power Supply Current SCS1 =V
IL,SCS2=V
IH,
VIN =V
IH or VIL,I
I/O =0mA
5mA
ICC1 Average Operating Current SCS1 =V
IL,SCS2=V
IH,
VIN =V
IH or VIL,CycleTime=Min
100% Duty, II/O =0mA
40 mA
SCS1 < 0.2V, SCS2 > VCC -0.2V
VIN <0.2VorV
IN >V
CC -0.2V,
CycleTime=1µs
100% Duty, II/O =0mA
5mA
ISB Standby Current (TTL Input) SCS1 =V
IH or SCS2 = VIL or
SUB,SLB=V
IH
VIN =V
IH or VIL
0.5 mA
ISB1 Standby Current (CMOS Input) SCS1 >V
CC -0.2Vor
SCS2 < VSS +0.2Vor
SUB,SLB>V
CC -0.2V
VIN >V
CC -0.2Vor
VIN <V
SS +0.2V
LL 25 µA
VOL Output Low IOL =0.1mA 0.4 V
VOH Output High IOH =-0.1mA 2.4 V
Capacitance(1)
(Temp = 25°C, f = 1.0 MHz)
Symbol Parameter Condition Max Unit
CIN Input Capacitance (Add, SCS1,
SCS2, SLB,SUB,SWE,SOE)
VIN =0V 8 pF
COUT Output Capacitance (I/O) VI/O =0V 10 pF
AC Characteristics
TA=-40°Cto85°C, Unless Otherwise Specified
# Symbol Parameter
70 ns
UnitMin Max
1t
RC Read Cycle Time 70 ns
2t
AA Address Access Time 70 ns
3t
ACS Chip Select Access Time 70 ns
37
AT52BR3244(T)/3248(T)
2471E–STKD–10/02
4t
OE Output Enable to Output Valid 35 ns
5t
BA SLB,SUBAccess Time 70 ns
6t
CLZ Chip Select to Output in Low Z 10 ns
7t
OLZ Output Enable to Output in Low Z 5 ns
8t
BLZ SLB,SUBEnable to Output in Low Z 10 ns
9t
CHZ Chip Deselection to Output in High Z 0 30 ns
10 tOHZ Out Disable to Output in High Z 0 30 ns
11 tBHZ SLB,SUBDisable to Output in High Z 0 30 ns
12 tOH Output Hold from Address Change 10 ns
13 tWC WriteCycleTime 70 ns
14 tCW Chip Selection to End of Write 60 ns
15 tAW Address Valid to End of Write 60 ns
16 tBW SLB,SUBValidtoEndofWrite 60 ns
17 tAS Address Setup Time 0 ns
18 tWP Write Pulse Width 50 ns
19 tWR Write Recovery Time 0 ns
20 tWHZ Write to Output in High Z 0 20 ns
21 tDW Data to Write Time Overlap 30 ns
22 tDH Data Hold from Write Time 0 ns
23 tOW Output Active from End of Write 5 ns
AC Characteristics
TA=-40°Cto85°C, Unless Otherwise Specified
# Symbol Parameter
70 ns
UnitMin Max
AC Test Conditions
TA = - 4 0 °Cto85°C, Unless Otherwise Specified
Parameter Value
Input Pulse Level 0.4V to 2.2V
Input Rise and Fall Time 5 ns
Input and Output Timing Reference Level 1.5V
Output Load CL = 5 pF + 1 TTL Load CL = 5 pF + 1 TTL Load
CL = 30 pF + 1 TTL Load CL = 30 pF + 1 TTL Load
38 AT52BR3244(T)/3248(T)
2471E–STKD–10/02
AC Test Loads
Note: Including jig and scope capacitance.
DOUT
2048 Ohm
CL
1045 Ohm
VTM = 2.8V
(1)
39
AT52BR3244(T)/3248(T)
2471E–STKD–10/02
Timing Diagrams
Read Cycle 1(1),(4)
Read Cycle 2(1),(2),(4)
Read Cycle 3(1),(2),(4)
Notes: 1. Read Cycle occurs whenever a high on the SWE and SOE is low, while SUB and/or SLB and SCS1 and SCS2 are in active
status.
2. SOE =V
IL.
3. Transition is measured + 200 mV from steady state voltage. This parameter is sampled and not 100% tested.
4. SCS1 in high for the standby, low for active. SCS2 in low for the standby, high for active. SUB and SLB in high for the
standby, low for active.
ADDRESS
SOE
SUB, SLB
SCS1
SCS2
DATA OUT HIGH-Z DATA VALID
tAA
tRC
tBA
tACS
tOE
tOLZ
tBLZ
tCLZ
tBHZ
tCHZ
tOH
tOHZ
(3)
(3)
(3)
(3)
(3)
(3)
DATA OUT
ADDRESS
t
AA
PREVIOUS DATA
t
OH
DATA VALID
t
OH
t
RC
SUB, SLB
SCS1
SCS2
DATA OUT
tACS
tCLZ (3)
DATA VALID
tCHZ(3)
40 AT52BR3244(T)/3248(T)
2471E–STKD–10/02
WriteCycle1(SWEControlled)(1),(4),(8)
WriteCycle2(SCS1, SCS2 Controlled)(1),(4),(8)
Notes: 1. A write occurs during the overlap of a low SWE,alowSCS1, a high SCS2 and a low SUB and/or SLB.
2. tWR is measured from the earlier of SCS1,SLB,SUB,orSWEgoing high or SCS2 going low to the end of write cycle.
3. During this period, I/O pins are in the output state so that the input signals of opposite phase to the output must not be
applied.
4. If the SCS1,SLBand SUB low transition and SCS2 high transition occur simultaneously with the SWE low transition or after
the SWE transition, outputs remain in a high impedance state.
5. Q (data out) is the same phase with the write data of this write cycle.
6. Q (data out) is the read data of the next address.
7. Transition is measured + 200 mV from steady state. This parameter is sampled and not 100% tested.
8. SCS1 in high for the standby, low for active SCS2 in low for the standby, high for active. SUB and SLB in high for the
standby, low for active.
ADDRESS
SWE
SUB, SLB
DATA IN
SCS1
SCS2
DATA OUT
t
WC
t
CW
t
AW
t
BW
t
WP
t
AS
t
WHZ
t
WR
t
DW
t
DH
t
OW
DATA VALID
HIGH-Z
t
AS
(2)
(5) (5)
(3)(7)
ADDRESS
SWE
SUB, SLB
DATA IN
SCS1
SCS2
DATA OUT
t
WC
t
CW
t
AW
t
BW
t
WP
t
AS
t
WR
t
DW
t
DH
DATA VALID
HIGH-Z
(2)
HIGH-Z
41
AT52BR3244(T)/3248(T)
2471E–STKD–10/02
Note: 1. Typical values are under the condition of TA=25°C. Typical values are sampled and not 100% tested.
Data Retention Timing Diagram 1
Data Retention Timing Diagram 2
Data Retention Electric Characteristic
TA=-40°Cto85°C
Symbol Parameter Test Condition Min Typ Max Unit
VDR VCC for Data Retention SCS1 >V
CC -0.2Vor
SCS2 < VSS +0.2Vor
SUB,SLB>V
CC -0.2V
VIN >V
CC -0.2Vor
VIN <V
SS +0.2V
1.2 3.3 V
ICCDR Data Retention Current Vcc=1.5V,
SCS1 >V
CC -0.2Vor
SCS2 < VSS +0.2Vor
SUB,SLB>V
CC -0.2V
VIN >V
CC -0.2Vor
VIN <V
SS +0.2V
SL 0.1 2 µA
LL 0.1 10 µA
tCDR See Data Retention
Timing Diagram
Chip Deselect to Data Retention Time 0 ns
tR Operating Recovery Time tRC
DATA RETENTION MODE
tR
tCDR
VCC
SCS1 > VCC - 0.2V
2.7V
IH
VDR
SCS1
VSS
VCC
2.7V
VDR
SCS2
VSS
0.4V
DATA RETENTION MODE
tR
tCDR
SCS2 < 0.2V
42 AT52BR3244(T)/3248(T)
2471E–STKD–10/02
Ordering Information
tACC
(ns) Ordering Code
Flash Boot
Block
Flash Plane
Architecture SRAM Package Operation Range
85 AT52BR3244-85CI Bottom 24M + 8M 256K x 16 66C4 Industrial
(-40°to 85°C)
90 AT52BR3244-90CI Bottom 24M + 8M 256K x 16 66C4 Industrial
(-40°to 85°C)
110 AT52BR3244-11CI Bottom 24M + 8M 256K x 16 66C4 Industrial
(-40°to 85°C)
85 AT52BR3244T-85CI Top 24M + 8M 256K x 16 66C4 Industrial
(-40°to 85°C)
90 AT52BR3244T-90CI Top 24M + 8M 256K x 16 66C4 Industrial
(-40°to 85°C)
110 AT52BR3244T-11CI Top 24M + 8M 256K x 16 66C4 Industrial
(-40°to 85°C)
85 AT52BR3248-85CI Bottom 24M + 8M 512K x 16 66C4 Industrial
(-40°to 85°C)
90 AT52BR3248-90CI Bottom 24M + 8M 512K x 16 66C4 Industrial
(-40°to 85°C)
85 AT52BR3248T-85CI Top 24M + 8M 512K x 16 66C4 Industrial
(-40°to 85°C)
90 AT52BR3248T-90CI Top 24M + 8M 512K x 16 66C4 Industrial
(-40°to 85°C)
Package Type
66C4 66-ball, Plastic Chip-size Ball Grid Array Package (CBGA)
43
AT52BR3244(T)/3248(T)
2471E–STKD–10/02
Packaging Information
66C4 – CBGA
2325 Orchard Parkway
San Jose, CA 95131
TITLE DRAWING NO.
R
REV.
66C4, 66-ball (12 x 8 Array), 11 x 8 x 1.2 mm Body, 0.8 mm Ball
Pitch Chip-scale Ball Grid Array Package (CBGA) A
66C4
08/29/01
Side View
Top View
Bottom View
A
B
C
D
E
F
G
H
1
2
3
4
5
6
7
89
1.20 REF
1.10 REF
101112
Marked A1 Identifier
D
E
D1
E1
e
e
Øb
A
A1
0.12
Seating Plane
C
C
A1 Ball Corner
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
A – – 1.20
A1 0.25 – –
D 10.90 11.00 11.10
D1 8.80 TYP
E 7.90 8.00 8.10
E1 5.60 TYP
e 0.80 TYP
Ø
b 0.40 TYP
Printed on recycled paper.
© Atmel Corporation 2002.
Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty
which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors
which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does
not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted
by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical
components in life support devices or systems.
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