L6393 Half-bridge gate driver Preliminary Data Features High voltage rail up to 600 V dV/dt immunity 50 V/nsec in full temperature range Driver current capability: - 270 mA source, - 430 mA sink Switching times 75/35 nsec rise/fall with 1 nF load 3.3 V, 5 V CMOS/TTL inputs comparators with hysteresys Integrated bootstrap diode Uncommitted comparator Adjustable dead-time Compact and simplified layout Bill of material reduction Flexible, easy and fast design Application Motor driver for home appliances, factory automation, industrial drives and fans. HID ballasts, power supply units. Table 1. March 2008 SO-14 DIP-14 Description The L6393 is a high-voltage device manufactured with the BCD "OFF-LINE" technology. It has a monolithic half-bridge gate driver for N-channel Power MOSFET or IGBT. The high side (floating) section is designed to stand a voltage rail up to 600 V. The logic inputs are CMOS/TTL compatible down to 3.3 V for easy of interfacing C/DSP. The IC embeds an uncommited comparator available for protections against over-current, over-temperature, etc. Device summary Order codes Package Packaging L6393 DIP-14 Tube L6393D SO-14 Tube L6393D013TR SO-14 Tape and reel Rev 2 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. 1/20 www.st.com 20 Contents L6393 Contents 1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 Truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 5 4.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4.3 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5.1 AC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5.2 DC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 6 Waveforms definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 7 Typical application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 8 Bootstrap driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 8.1 CBOOT selection and charging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 9 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2/20 L6393 1 Block diagram Block diagram Figure 1. VCC Block diagram BOOTSTRAPDRIVER 4 UV DETECTION PHASE FLOATINGSTRUCTURE from LVG 14 UV DETECTION 1 LEVEL SHIFTER HVG DRIVER S 13 R LOGIC BRAKE 3 12 SHOOT THROUGH PREVENTION VCC SD CPOUT OUT LVG 10 6 5V 10 + - GND HVG LVG DRIVER 2 COMPARATOR DT BOOT 5 9 8 CP+ CP- DEAD TIME 7 3/20 Pin connection 2 L6393 Pin connection Figure 2. 2.1 Pin connection (top view) PHASE 1 14 BOOT SD 2 13 HVG BRAKE 3 12 OUT VCC 4 11 NC DT 5 10 LVG CPOUT 6 9 CP+ GND 7 8 CP- Pin description Table 2. Pin description Pin N# Pin name Type 1 PHASE I Driver logic input (active high) I Shut down input (active low) 2 SD (1) Function 3 BRAKE I Driver logic input (active low) 4 VCC P Lower section supply voltage 5 DT I Dead time setting 6 CPOUT O Comparator output (open drain) 7 GND P Ground 8 CP- I Comparator negative input 9 CP+ I Comparator positive input O Low side driver output 10 LVG (1) 11 NC 12 OUT (1) 13 HVG 14 BOOT Not connected P High side (floating) common voltage O High side driver output P Bootstrapped supply voltage 1. The circuit guarantees less than 1 V on the LVG and HVG pins (@ Isink = 10 mA), with VCC > 3 V. This allows omitting the "bleeder" resistor connected between the gate and the source of the external MOSFET normally used to hold the pin low; the gate driver assures low impedance also in SD condition. 4/20 L6393 3 Truth table Truth table Table 3. Truth table INPUTS Note: OUTPUTS SD PHASE BRAKE LVG HVG L X X L L H L L H L H L H H L H H L H L H H H L H X: don't care In the L6393 IC the two input signals PHASE and BRAKE are fed into an AND logic port and the resulting signal is in phase with the high side output HVG and in opposition of phase with the low side output LVG. This means that if BRAKE is kept to high level, the PHASE signal drives the half-bridge in phase with the HVG output and in opposition of phase with the LVG output. If BRAKE is set to low level the low side output LVG is always ON and the high side output HVG is always OFF, whatever the PHASE signal. This kind of logic interface provides the possibility to control the power stages using the PHASE signal to select the current direction in the bridge and the BRAKE signal to perform current slow decay on the low sides. From the point of view of the logic operations the two signals PHASE and BRAKE are completely equivalent, that means the two signals can be exchanged without any change in the behavior on the resulting output signals (see the Block Diagram in Fig.1). Note: the dead time between the turn OFF of one power switch and the turn ON of the other power switch is defined by the resistor connected between DT pin and the ground. 5/20 Electrical data L6393 4 Electrical data 4.1 Absolute maximum ratings Table 4. Absolute maximum rating Symbol Parameter Value Unit Vout Output voltage Vboot - 21 to Vboot + 0.3 V Vcc Supply voltage - 0.3 to + 21 V Vcp- Comparator negative input voltage -0.3 to VCC + 0.3 V Vcp+ Comparator positive input voltage -0.3 to VCC + 0.3 V Vboot Floating supply voltage VCC - 0.3 to 620 V Vhvg High side gate output voltage output voltage Vout - 0.3 to Vboot + 0.3 V VIvg High side gate output voltage output voltage -0.3 to Vcc +0.3 V Vi Logic input voltage -0.3 to 15 V Vcpout Open drain voltage -0.3 to 15 V 50 V/ns TBD mW dVout/dt Allowed output slew rate Ptot Total power dissipation (TA = 85 C) TJ Junction temperature 150 C Tstg Storage temperature -50 to 150 C Note: ESD immunity for pins 12, 13 and 14 is guaranteed up to V (Human Body Model) 4.2 Thermal data Table 5. Symbol Rth(JA) 6/20 Thermal data Parameter Thermal resistance junction to ambient max. SO-14 DIP-14 Unit 165 100 C/W L6393 4.3 Electrical data Recommended operating conditions Table 6. Recommended operating conditions Symbol Pin Vout Parameter 12 Output voltage VBS (2) 14 Floating supply voltage (1) fsw Switching frequency Vcc Tj 4 Test condition Min Max Unit 580 V TBD V 800 kHz TBD TBD V 40 125 C (1) Supply Voltage Junction Temperature TBD HVG, LVG load CL = 1 nF 1. If the condition TBD V < Vboot - Vout < TBD V and Vboot < TBD V are guaranteed, Vout can range from TBD V to 580 V 2. VBS = Vboot -Vout 7/20 Electrical characteristics L6393 5 Electrical characteristics 5.1 AC operation Table 7. AC operation electrical characteristics (VCC = 15 V, TJ = +25 C) Symbol Pin Parameter Test condition Min Typ Max Unit AC operation ton toff tsd 1,3 vs 10, 13 tf 8/20 Vout = 0 V Vboot = Vcc CL = 1 nF Vi = 0 to 3.3 V see Figure 3 on page 9 125 ns 125 ns 125 ns Delay matching, HS & LS turn-ON/OFF 5 MDT tr High/low side driver turnoff propagation delay 2 vs Shut down to high/low 10, side propagation delay 13 MT dt High/low side driver turnon propagation delay 10, 13 40 ns s s s s Dead time setting range Rdt = 0, CL = 1 nF, CDT = 100 nF Rdt = 37 k, CL = 1 nF, CDT = 100 nF Rdt = 136 k, CL = 1 nF, CDT = 100 nF Rdt = 260 k, CL = 1 nF, CDT = 100 nF Matching dead time Rdt = 0 ; CL = 1 nF; CDT = 100 nF Rdt = 37 k;CL = 1 nF;CDT = 100 nF Rd = 136 k;CL = 1 nF;CDT = 100 nF Rdt = 260 k;CL = 1 nF;CDT = 100 nF Rise time CL = 1000 pF 75 ns Fall time CL = 1000 pF 35 ns 0.15 0.5 1.5 2.8 60 TBD TBD TBD ns ns ns ns L6393 Electrical characteristics Figure 3. Timing Logic Input 50% 50% (PHASE or BRAKE) tr tf 90% 90% HVG 10% 10% ton Logic Input toff 50% 50% (PHASE or BRAKE) tf tr 90% 90% LVG 10% SD 10% ton toff 50% 50% tr tf 90% LVG/HVG 90% 10% ton 10% toff 9/20 Electrical characteristics L6393 5.2 DC operation Table 8. DC opereation electrical characteristics (VCC = 15 V; TJ = +25 C) Symbol Pin Parameter Test condition Min Typ Max Unit 600 1500 mV Low supply voltage section Vcc_hys Vcc UV hysteresis Vcc_thON Vcc UV Turn ON threshold 9.5 V Vcc_thOFF Vcc UV Turn OFF threshold 8.0 V Iqccu 4 Iqcc Undervoltage quiescent supply current VCC = 8 V SD = 5 V; PHASE and BRAKE = GND; RDT = 0 ; CP + = GND; CP - = 0.5 V 110 150 A Quiescent current VCC = 15 V SD = 5 V; PHASE and BRAKE = GND; RDT = 0 ; CP + = GND; CP - = 0.5 V 600 1000 A Bootstrapped supply voltage section VBS UV hysteresis VBS_hys 600 1000 mV VBS_thON VBS UV turn ON Threshold 9.1 V VBS_thOFF VBS UV turn OFF Threshold 8.1 V IQBSU IQBS ILK Rdson 10/20 14 Undervoltage Vboot quiescent current VBS = 7 V SD = 5 V; PHASE and BRAKE = 5 V; RDT = 0 ; CP + = GND; CP - = 0.5 V 60 110 A Vboot quiescent current VBS = 15 V SD = 5 V; PHASE and BRAKE = 5 V; RDT = 0 ; CP + = GND; CP - = 0.5 V 140 210 A High voltage leakage current Vhvg = Vout = Vboot = 600 V 10 A Bootstrap driver on resistance (1) LVG ON 120 L6393 Electrical characteristics Table 8. DC opereation electrical characteristics (VCC = 15 V; TJ = +25 C) (continued) Symbol Pin Parameter Test condition Min Typ Max Unit Driving buffers section Iso High/low side source short VIN = Vih (tp < 10 s) circuit current 270 mA High/low side sink short circuit current 430 mA 10, 13 Isi VIN = Vil (tp < 10 s) Logic inputs Low level logic threshold voltage Vil 0.83 V 1, 2, 3 High level logic threshold voltage Vih 2.21 PHASE logic "1" input bias PHASE = 15 V current IPHASEh V 260 A 1 A 260 A 1 A 100 A 1 A Typ Max Unit 10 TBD mV 1 A 0.5 V 210 ns 175 1 IPHASEl PHASE logic "0" input bias PHASE = 0 V current IBRAKEh BRAKE logic "1" input bias BRAKE = 15 V current 175 3 BRAKE logic "0" input bias BRAKE = 0 V current IBRAKEl ISDh SD logic "1" input bias current SD = 15 V SD logic "0" input bias current SD = 0 V 30 2 ISDl 1. RDSon is tested in the following way: RDSon = [(VCC - VCBOOT1) - (VCC - VCBOOT2)] / [I1(VCC,VCBOOT1) - I2(VCC,VCBOOT2)] where I1 is pin 14 current when VCBOOT = VCBOOT1, I2 when VCBOOT = VCBOOT2. Table 9. Symbol Vio Sense comparator Pin Input offset voltage Min Input bias current 6 td_comp SR Test conditions 8, 9 Iib Vol Parameter 6 Open drain low level Output voltage Iod = - 3 mA Comparator delay CPOUT pulled to 5 V through 100k resistor 110 Slew rate CL = 180 nF, Rpu = 5 k TBD V/s 11/20 Waveforms definition L6393 6 Waveforms definition Figure 4. Dead time waveform definition PHASE BRAKE LVG DT HVG 12/20 DT DT DT L6393 Typical application diagram 7 Typical application diagram Figure 5. Application diagram VCC BOOTSTRAP DRIVER 4 UV DETECTION PHASE FLOATING STRUCTURE from LVG 14 BOOT UV DETECTION 1 S LEVEL SHIFTER H.V. HVG DRIVER 13 HVG 12 OUT Cboot R LOGIC BRAKE 3 SHOOT THROUGH PREVENTION VCC SD TO LOAD LVG DRIVER LVG 2 10 CPOUT 6 5V COMPARATOR 10 + - DT 5 9 CP+ 8 CP- DEAD TIME GND 7 13/20 Bootstrap driver 8 L6393 Bootstrap driver A bootstrap circuitry is needed to supply the high voltage section. This function is normally accomplished by a high voltage fast recovery diode (Figure 6.a). In the L6393 a patented integrated structure replaces the external diode. It is realized by a high voltage DMOS, driven synchronously with the low side driver (LVG), with diode in series, as shown in Figure 6.b. An internal charge pump (Figure 6.b) provides the DMOS driving voltage. The diode connected in series to the DMOS has been added to avoid undesirable turn on of it. 8.1 CBOOT selection and charging To choose the proper CBOOT value the external MOS can be seen as an equivalent capacitor. This capacitor CEXT is related to the MOS total gate charge: Q gate C EXT = ------------V gate The ratio between the capacitors CEXT and CBOOT is proportional to the cyclical voltage loss. It has to be: CBOOT >>> CEXT e.g.: if Qgate is 30nC and Vgate is 10 V, CEXT is 3 nF. With CBOOT = 100 nF the drop would be 300 mV. If HVG has to be supplied for a long time, the CBOOT selection has to take into account also the leakage and quiescent losses. e.g.: HVG steady state consumption is lower than 200 A, so if HVG TON is 5 ms, CBOOT has to supply 1 C to CEXT. This charge on a 1 F capacitor means a voltage drop of 1 V. The internal bootstrap driver gives a great advantage: the external fast recovery diode can be avoided (it usually has great leakage current). This structure can work only if VOUT is close to GND (or lower) and in the meanwhile the LVG is on. The charging time (Tcharge ) of the CBOOT is the time in which both conditions are fulfilled and it has to be long enough to charge the capacitor. The bootstrap driver introduces a voltage drop due to the DMOS RDSon (typical value: 120 ). At low frequency this drop can be neglected. Anyway increasing the frequency it must be taken in to account. The following equation is useful to compute the drop on the bootstrap DMOS: Q gate V drop = I ch arg e R dson V drop = ------------------ R dson T ch arg e 14/20 L6393 Bootstrap driver where Qgate is the gate charge of the external power MOS, RDSon is the on resistance of the bootstrap DMOS, and Tcharge is the charging time of the bootstrap capacitor. For example: using a power MOS with a total gate charge of 30 nC the drop on the bootstrap DMOS is about 1 V, if the Tcharge is 5 s. In fact: 30nC V drop = --------------- 120 0.7V 5s Vdrop has to be taken into account when the voltage drop on CBOOT is calculated: if this drop is too high, or the circuit topology doesn't allow a sufficient charging time, an external diode can be used. Figure 6. Bootstrap driver DBOOT VS BOOT BOOT VS H.V. HVG H.V. HVG CBOOT VOUT VOUT TO LOAD TO LOAD LVG LVG a CBOOT b D99IN1067 15/20 Package mechanical data 9 L6393 Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a Lead-free second level interconnect . The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com 16/20 L6393 Package mechanical data Figure 7. DIP-14 mechanical data and package dimensions mm DIM. MIN. a1 0.51 B 1.39 TYP. inch MAX. MIN. TYP. MAX. 0.020 1.65 0.055 0.065 b 0.5 0.020 b1 0.25 0.010 D 20 0.787 E 8.5 0.335 e 2.54 0.100 e3 15.24 0.600 F 7.1 0.280 I 5.1 0.201 L OUTLINE AND MECHANICAL DATA 3.3 0.130 DIP-14 Z 1.27 2.54 0.050 0.100 17/20 Package mechanical data Figure 8. L6393 SO-14 mechanical data and package dimensions mm inch DIM. MIN. TYP. MAX. MIN. TYP. MAX. A 1.35 1.75 0.053 0.069 A1 0.10 0.30 0.004 0.012 A2 1.10 1.65 0.043 0.065 B 0.33 0.51 0.013 0.020 C 0.19 0.25 0.007 0.01 8.55 8.75 0.337 0.344 3.80 4.0 0.150 0.157 D (1) E e 1.27 0.050 H 5.8 6.20 0.228 0.244 h 0.25 0.50 0.01 0.02 L 0.40 1.27 0.016 0.050 k ddd OUTLINE AND MECHANICAL DATA 0 (min.), 8 (max.) 0.10 0.004 (1) "D" dimension does not include mold flash, protusions or gate burrs. Mold flash, protusions or gate burrs shall not exceed 0.15mm per side. SO-14 0016019 D 18/20 L6393 10 Revision history Revision history Table 10. Document revision history Date Revision Changes 03-Mar-2008 1 Initial release 18-Mar-2008 2 Cover page updated 19/20 L6393 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST's terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. 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