Never stop thinking.
EiceDRIVERTM
1ED020I12-F
Single IGBT Driver IC
Datasheet, Version 2.3, May 2011
Asic & Power ICs
5
Asic & Power ICs
Revision History: May 2011 Version 2.3
Previous Version: 2.2
Page Subjects (major changes since last revision)
5Figure2 changed to more details
14 4.4.6 Dynamic Characteristics changed delays
Edition 2011-05-03
Published by Infineon Technologies AG,
Campeon 1-12,
85579 Neubiberg, Germany
© Infineon Technologies AG 2011.
All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as a guarantee of
characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding
circuits, descriptions and charts stated herein.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
Type Gate drive current Package
1ED020I12-F +/- 2A PG-DSO-16-15
Datasheet 3 Version 2.3, 2011-05-03
EiceDRIVERTM
1ED020I12-F
Single IGBT Driver IC
Product Highlights
• Coreless transformer isolated driver
• Galvanic Insulation
• Integrated protection features
• Suitable for operation at high ambient temperature
• Cost effective technology
• Approvals: DIN EN 60747-5-2, UL1577
Features
• Single channel isolated IGBT Driver
• For 600V/1200V IGBTs
• 2A rail-to-rail output
• Vcesat-detection
• Active Miller Clamp
Typical
Application
• AC-Drives
• UPS-Systems
• Welding
DESAT
CLAMP
DESAT
CLAMP
OUT
OUT
CPU
EiceDRIVERTM 1ED020I12-F
EiceDRIVERTM 1ED020I12-F
IN+, IN-, /RST
IN+, IN-, /RST
/FLT, RDY
/FLT, RDY
GND1
VCC1 VCC2,H
VCC2,L
VEE2,L
VEE2,H
GND2,L
GND2,H
Figure 1: Typical Application
Datasheet 4 Version 2.3, 2011-05-03
EiceDRIVERTM
1ED020I12-F
Table of Contents Page
1 Blockdiagram and Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.2 Internal Protection Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.2.1 Undervoltage Lockout (UVLO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.2.2 READY status output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.2.3 Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.2.4 Active Shut-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.3 Non-Inverting and Inverting Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.4 Driver Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.5 External Protection Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.5.1 Desaturation Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.5.2 Active Miller Clamping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.5.3 Short Circuit Clamping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.6 RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3 Pin Configuration and Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.1 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.2 Pin Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4 Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.2 Operating Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.3 Recommended Operating Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.4 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.4.1 Voltage Supply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.4.2 Logic Input and Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.4.3 Gate Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.4.4 Active Miller Clamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.4.5 Short Circuit Clamping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.4.6 Dynamic Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.4.7 Desaturation protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.4.8 Active Shut Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5 Insulation Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.1 DIN EN 60747-5-2 (VDE 0884 Teil 2): 2003-01. Basic Insulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.2 UL 1577 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.3 Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
8 Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
8.1 Reference Layout for Thermal Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
8.2 Printed Circuit Board Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
EiceDRIVERTM
1ED020I12-F
Datasheet 5 Version 2.3, 2011-05-03
1 Blockdiagram and Application
GND1
IN+
IN-
RDY
/RST
/FLT
VCC1
10
11
12
13
14
15
9
7
6
5
4
3
2
VCC2
OUT
GND2
CLA MP
DESAT
NC
delay
TX
RXDECODER
UVLO
TX
VEE2
2V
ENCODER
I3
9V
K3
&
delay
1
FLT
VCC1
VCC1
VCC1
VCC1
&
&
&
delay 1
Q
S
R
/RDY
1
1
1
FLTNL
RST
UVLO
RX
&
VEE2
≥1
&
≥1
&
VCC2
RDY2
FLT2
2
16 1 8
VEE2
GND1
K4
VCC2
1ED020I12-F
2kΩ1kΩ
Figure 2: Blockdiagram 1ED020I12-F
Figure 3: Application example
EiceDRIVERTM
1ED020I12-F
Datasheet 6 Version 2.3, 2011-05-03
2 Functional Description
2.1 Introduction
The 1ED020I12-F is an advanced IGBT gate driver that
can be also used for driving power MOS devices.
Control and protection functions are included to make
possible the design of high reliability systems.
The device consists of two galvanic separated parts.
The input chip can be directly connected to a standard
5V DSP or microcontroller with CMOS in/output and the
output chip is connected to the high voltage side.
An effective active Miller clamp function avoids the
need of negative gate driving in most applications and
allows the use of a simple bootstrap supply for the high
side driver.
A rail-to-rail driver output enables the user to provide
easy clamping of the IGBTs gate voltage during short
circuit of the IGBT. So an increase of short circuit
current due to the feedback via the Miller capacitance
can be avoided. Further, a rail-to-rail output reduces
power dissipation.
The device also includes an IGBT desaturation
protection with a FAULT status output.
A READY status output reports if the device is supplied
and operates correctly.
2.2 Internal Protection Features
2.2.1 Undervoltage Lockout (UVLO)
To ensure correct switching of IGBTs the device is
equipped with an undervoltage lockout for both chips.
If the power supply voltage VVCC1 of the input chip drops
below VUVLOL1 a turn-off signal is sent to the output chip
before power-down. The IGBT is switched off and the
signals at IN+ and IN- are ignored as long as VVCC1
reaches the power-up voltage VUVLOH1 .
If the power supply voltage VVCC2 of the output chip
goes down below VUVLOL2 the IGBT is switched off and
signals from the input chip are ignored as long as VVCC2
reaches the power-up voltage VUVLOH2 .
2.2.2 READY status output
The READY output shows the status of three internal
protection features.
• UVLO of the input chip
• UVLO of the output chip after a short delay
• Internal signal transmission
It is not necessary to reset the READY signal since its
state only depends on the status of the former
protection signals.
2.2.3 Watchdog Timer
The 1ED020I12-F incorporates two level of signal
transmission security implemented through two
independent watchdog timers. First level ensures the
short term signal integrity by resending the (turn on/off)
signals with a watchdog period of typical 500ns. The
second level monitors during normal operation the
internal signal transmission. If the transmission fails for
a given time, the IGBT is switched off and the READY
output reports an internal error.
2.2.4 Active Shut-Down
The Active Shut-Down feature ensures a safe IGBT off-
state if the output chip is not connected to the power
supply.
2.3 Non-Inverting and Inverting
Inputs
There are two possible input modes to control the
IGBT. At non-inverting mode IN+ controls the driver
output while IN- is set to low. At inverting mode IN-
controls the driver output while IN+ is set to high. A
minimum input pulse width is defined to filter occasional
glitches.
2.4 Driver Output
The output driver section uses only MOSFETs to
provide a rail-to-rail output. This feature permits that
tight control of gate voltage during on-state and short
circuit can be maintained as long as the drivers supply
is stable. Due to the low internal voltage drop, switching
behaviour of the IGBT is predominantly governed by
the gate resistor. Furthermore, it reduces the power to
be dissipated by the driver.
Datasheet 7 Version 2.3, 2011-05-03
EiceDRIVERTM
1ED020I12-F
2.5 External Protection Features
2.5.1 Desaturation Protection
A desaturation protection ensures the protection of the
IGBT at short circuit. When the DESAT voltage goes up
and reaches 9V, the output is driven low. Further, the
/FAULT output is activated. A programmable blanking
time is used to allow enough time for IGBT saturation.
Blanking time is provided by a highly precise internal
current source and an external capacitor.
2.5.2 Active Miller Clamping
A Miller clamp allows sinking the Miller current during a
high dV/dt situation. Therefore, the use of a negative
supply voltage can be avoided in many applications.
During turn-off, the gate voltage is monitored and the
clamp output is activated when the gate voltage goes
below 2V (related to VEE2).
2.5.3 Short Circuit Clamping
During short circuit the IGBTs gate voltage tends to rise
because of the feedback via the Miller capacitance. An
additional protection circuit connected to OUT and
CLAMP limits this voltage to a value slightly higher than
the supply voltage. A current of maximum 500 mA for
10us may be fed back to the supply through one of this
paths. If higher currents are expected or a tighter
clamping is desired external Schottky diodes may be
added.
2.6 RESET
The reset input has two functions.
Firstly, /RST is in charge of setting back the FAULT
output. If /RST is low longer than a given time , /FLT will
be reseted at the rising edge of /RST; otherwise, it will
remain unchanged. Moreover, it works as
enable/shutdown of the input logic.
EiceDRIVERTM
1ED020I12-F
Datasheet 8 Version 2.3, 2011-05-03
3 Pin Configuration and Functionality
3.1 Pin Configuration
Pin Symbol Function
1VEE2 Negative power supply output side
2DESAT Desaturation protection
3 GND2 Signal ground output side
4NC Not connected
5VCC2 Positive power supply output side
6 OUT Driver output
7CLAMP Miller clamping
8VEE2 Negative power supply output side
9 GND1 Signal ground input side
10 IN+ Non inverted driver input
11 IN- Inverted driver input
12 RDY Ready output
13 FLT Fault output
14 RST Reset input
15 VCC1 Positive power supply input side
16 GND1 Signal ground input side
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VEE2
VCC2
OUT
GND2
CLAMP
DESAT
NC
VEE2
GND1
IN+
IN-
RDY
/RST
/FLT
VCC1
GND1
Figure 4: PG-DSO-16-15
3.2 Pin Functionality
GND1
Ground connection of the input side.
IN+ Non-inverting driver input
IN+ control signal for the driver output if IN- is set to low.
(The IGBT is on if IN+ = high and IN- = low)
A minimum pulse width is defined to make the IC robust
against glitches at IN+. An internal Pull-Down-Resistor
ensures IGBT Off-State.
IN- Inverting driver input
IN- control signal for driver output if IN+ is set to high.
(IGBT is on if IN- = low and IN+ = high)
A minimum pulse width is defined to make the IC robust
against glitches at IN-. An internal Pull-Up-Resistor
ensures IGBT Off-State.
/RST (Reset) input
Function 1: Enable/shutdown of the input chip. (The
IGBT is off if /RST = low). A minimum pulse width is
defined to make the IC robust against glitches at IN-.
Function 2: Resets the DESAT-FAULT-state of the chip
if /RST is low for a time TRST. An internal Pull-Up-
Resistor is used to ensure FLT status output.
/FLT (Fault output)
Open-drain with internal pull up resistor output to report
a desaturation error of the IGBT (/FLT is low if
desaturation occurs)
RDY (Ready status)
Open-drain with internal pull up resistor output to report
the correct operation of the device. (RDY = high if both
chips are above the UVLO level and the internal chip
transmission is faultless)
VCC1
5V power supply of the input chip
VEE2
Negative power supply pins of the output chip. If no
negative supply voltage is available, both pins have to
be connected to GND2.
DESAT (Desaturation)
Monitoring of the IGBT saturation voltage (VCE) to
detect desaturation caused by short circuits. If OUT is
high, VCE is above a defined value and a certain
blanking time has expired, the desaturation protection
is activated and the IGBT is switched off. The blanking
Datasheet 9 Version 2.3, 2011-05-03
EiceDRIVERTM
1ED020I12-F
time is adjustable by an external capacitor.
CLAMP (Clamping)
Ties the gate voltage to ground after the IGBT has been
switched off at a defined voltage to avoid a parasitic
switch-on of the IGBT.During turn-off, the gate voltage
is monitored and the clamp output is activated when the
gate voltage goes below 2V (related to VEE2).
GND2
Reference ground of the output chip.
OUT (Driver output)
Output pin to drive an IGBT. The voltage is switched
between VEE2 and VCC2. In normal operating mode
Vout is controlled by IN+, IN- and /RST. During error
mode (UVLO, internal error or DESAT) Vout is set to
VEE2 independent of the input control signals.
VCC2
Positive power supply pin of the output side.
Datasheet 10 Version 2.3, 2011-05-03
EiceDRIVERTM
1ED020I12-F
Electrical Parameters
4 Electrical Parameters
4.1 Absolute Maximum Ratings
Note: Absolute maximum ratings are defined as ratings, which when being exceeded may lead to destruction of
the integrated circuit. Unless otherwise noted all parameters refer to GND1.
Parameter Symbol Limit Values Unit Remarks
min. max.
Positive power supply output side VVCC2 -0.3 20 V1)
1) With respect to GND2.
Negative power supply output side VVEE2 -12 0.3 V1)
Maximum power supply voltage output side
(VVCC2-VVEE2)
Vmax2 ⎯28 V
Gate driver output VOUT VVEE2-0.3 Vmax2+0.3 V
Gate driver high output maximum current IOUT —2.4 At = 2µs
Gate driver low output maximum current IOUT —2.4 At = 2µs
Maximum short circuit clamping time tCLP ⎯10 us ICLAMP/OUT =
500mA
Positive power supply input side VVCC1 -0.3 6.5 V
Logic input voltages
(IN+,IN-,RST)
VLogicIN -0.3 6.5 V
Opendrain Logic output voltage
(FLT)
VFLT -0.3 6.5 V
Opendrain Logic output voltage
(RDY)
VRDY -0.3 6.5 V
Opendrain Logic output current
(FAULT)
IFLT ⎯10 mA
Opendrain Logic output current
(RDY)
IRDY ⎯10 mA
Pin DESAT voltage VDESAT -0.3 VVCC2 +0.3 V1) VVEE2 = -8V
Pin CLAMP voltage VCLAMP VVEE2-0.3 VVCC2+0.3
2)
2) may be exceeded during short circuit clamping
V
Junction temperature TJ-40 150 °C
Storage temperature TS-55 150 °C
Power dissipation, Input chip PD, IN ⎯100 mW 3)
3) Output IC power dissipation is derated linearly at 10 mW/°C above 62°C. Input IC power dissipation does not require
derating. See section 8.1 for reference layouts for these thermal data. Thermal performance may change significantly with
layout and heat dissipation of components in close proximity.
@TA = 25°
Power dissipation, Output chip PD, OUT ⎯700 mW 3)@TA = 25°
Thermal resistance (Input chip active) RTHJA,IN ⎯160 K/W @TA = 25°C
Thermal resistance (Output chip active) RTHJA,OUT ⎯125 K/W @TA = 25°C
ESD Capability VESD ⎯1 kV Human Body
Model4)
4) According to EIA/JESD22-A114-B (discharging a 100pF capacitor through a 1.5kΩ series resistor).
EiceDRIVERTM
1ED020I12-F
Electrical Parameters
Datasheet 11 Version 2.3, 2011-05-03
4.2 Operating Parameters
Note: Within the operating range the IC operates as described in the functional description. Unless otherwise
noted all parameters refer to GND1.
Parameter Symbol Limit Values Unit Remarks
min. max.
Positive power supply output side VVCC2 13 20 V1)
1) With respect to GND2.
Negative power supply output side VVEE2 -12 0 V 1)
Maximum power supply voltage output side
(VVCC2-VVEE2)
Vmax2 ⎯28 V
Positive power supply input side VVCC1 4.5 5.5 V
Logic input voltages
(IN+,IN-,RST)
VLogicIN -0.3 5.5 V
Pin CLAMP voltage VCLAMP VVEE2-0.3 VVCC2
2)
2) may be exceeded during short circuit clamping
V
Pin DESAT voltage VDESAT -0.3 VVCC2 V1)
Ambient temperature TA-40 105 °C
Common mode transient immunity3)
3) The parameter is not subject to production test - verified by design/characterization
|ΔVISO/dt| —50 kV/µs @ 500V
4.3 Recommended Operating Parameters
Note: Unless otherwise noted all parameters refer to GND1.
Parameter Symbol Values Unit Remarks
Positive power supply output side VVCC2 15 V1)
1) With respect to GND2.
Negative power supply output side VVEE2 -8 V1)
Positive power supply input side VVCC1 5 V
Datasheet 12 Version 2.3, 2011-05-03
EiceDRIVERTM
1ED020I12-F
Electrical Parameters
4.4 Electrical Characteristics
Note: The electrical characteristics involve the spread of values for the supply voltages, load and junction
temperatures given below. Typical values represent the median values, which are related to production
processes at T = 25°C. Unless otherwise noted all voltages are given with respect to GND.
4.4.1 Voltage Supply.
Parameter Symbol Limit Values Unit Test Conditions
min. typ. max.
UVLO Threshold Input Chip VUVLOH1 —4.1 4.3 V
VUVLOL1 3.5 3.8 — V
UVLO Hysteresis Input Chip
(VUVLOH1 - VUVLOL1)
VHYS1 0.15 — — V
UVLO Threshold Output Chip VUVLOH2 —12.0 12.6 V
VUVLOL2 10.4 11.0 — V
UVLO Hysteresis Output Chip
(VUVLOH1 - VUVLOL1)
VHYS2 0.7 0.9 — V
Quiescent Current Input Chip IQ1 — 7 9 mA VVCC1 =5V
IN+ = High, IN- = Low
=>OUT = High, RDY =
High, /FLT = High
Quiescent Current Output Chip IQ2 — 4 6 mA VVCC2 =15V
VVEE2 =-8V
IN+ = High, IN- = Low
=>OUT = High, RDY =
High, /FLT = High
4.4.2 Logic Input and Output
Parameter Symbol Limit Values Unit Test Conditions
min. typ. max.
IN+,IN-, RST Low Input Voltage VIN+L,VIN-
L,VRSTL
— — 1.5 V
IN+,IN-, RST High Input Voltage VIN+H,VIN-
HVRSTH
3.5 — — V
IN-, RST Input Current IIN-,IRST —100 400 uA VIN-=GND1
VRST =GND1
IN+ Input Current IIN+, —100 400 uA VIN+=VCC1
RDY,FLT Pull Up Current IPRDY,
IPFLT
—100 400 uA VRDY=GND1
VFLT=GND1
Input Pulse Suppression IN+, IN- TMININ+,
TMININ-
30 40 —ns
Input Pulse Suppression RST
for ENABLE/SHUTDOWN
TMINRST 30 40 —ns
Pulse Width RST
for Reseting FLT
TRST 800 — — ns
FLT Low Voltage VFLTL — — 300 mV ISINK(FLT) = 5mA
RDY Low Voltage VRDYL — — 300 mV ISINK(RDY) = 5mA
EiceDRIVERTM
1ED020I12-F
Electrical Parameters
Datasheet 13 Version 2.3, 2011-05-03
4.4.3 Gate Driver
Parameter Symbol Limit Values Unit Test Conditions
min. typ. max.
High Level Output Voltage VOUTH1 VVCC2-1.2 VVCC2-0.8 ⎯V IOUTH = -20mA
VOUTH2 VVCC2-2.5 VVCC2-2 ⎯V IOUTH = -200mA
VOUTH3 VVCC2-9 VVCC2-5 ⎯V IOUTH = -1A
VOUTH4 VVCC2-10 ⎯V IOUTH = -2A
High Level Output Peak Current IOUTH -1.5 -2 ⎯AIN+ = High, IN- =
Low; OUT = High
Low Level Output Voltage VOUTL1 ⎯VVEE2+0.04 VVEE2 +0.09 V IOUTL = 20mA
VOUTL2 ⎯VVEE2+0.5 VVEE2 +0.85 V IOUTL = 200mA
VOUTL3 ⎯VVEE2+2.5 VVEE2 +5.0 V IOUTL = 1A
VOUTL4 ⎯VVEE2+7 — V IOUTL = 2A
Low Level Output Peak Current IOUTL 1.5 2 — A IN+ = Low, IN- = Low;
OUT = Low
4.4.4 Active Miller Clamp
Parameter Symbol Limit Values Unit Test Conditions
min. typ. max.
Low Level Clamp Voltage VCLAMPL1 — VVEE2+0.03 VVEE2 +0.08 V IOUTL = 20mA
VCLAMPL2 — VVEE2+0.3 VVEE2 +0.8 V IOUTL = 200mA
VCLAMPL3 — VVEE2+1.9 VVEE2 +4.8 V IOUTL = 1A
Low Level Clamp Current ICLAMPL 2⎯ ⎯ A1)
1) The parameter is not subject to production test - verified by design/characterization
Clamp Threshold Voltage VCLAMP 1.6 2.1 2.4 VRelated to VEE2
Datasheet 14 Version 2.3, 2011-05-03
EiceDRIVERTM
1ED020I12-F
Electrical Parameters
4.4.5 Short Circuit Clamping
Parameter Symbol Limit Values Unit Test Conditions
min. typ. max.
Clamping voltage (OUT)
(VOUT-VVCC2)
VCLPout ⎯0.8 1.3 VIN+=High, IN-=Low,
OUT=High
IOUT = 500mA (pulse
test,tCLPmax=10us)
Clamping voltage (CLAMP)
(VVCLAMP-VVCC2)
VCLPclamp ⎯1.3 ⎯VIN+=High, IN-=Low,
OUT=High
ICLAMP = 500mA (pulse
test,tCLPmax=10us)
Clamping voltage (CLAMP) VCLPclamp ⎯0.7 1.1 VIN+=High, IN-=Low,
OUT=High
ICLAMP = 20mA
4.4.6 Dynamic Characteristics
Parameter Symbol Limit Values Unit Test Conditions
min. typ. max.
Input to output propagation delay ON TPDON 180 205 225 ns VVCC1 = 5V,
VVCC2 =15V,VVEE2 =-8V
CLOAD= 100pF
VIN+=50%, VOUT=50%
@ 25°C
Input to output propagation delay
OFF
TPDOFF 155 175 195 ns
Input to output propagation delay
distortion TPDOFF-TPDON
TPDISTO -60 -30 0ns
Input to output propagation delay ON
variation due to temp 1)
1) The parameter is not subject to production test - verified by design/characterization
TPDONt — — 20 ns
VVCC2 =15V,VVEE2 =-8V
CLOAD= 100pF
VIN+=50%, VOUT=50%
Input to output propagation delay
OFF variation due to temp 1)
TPDOFFt — — 35 ns
Input to output propagation delay
distortion variation due to temp 1)
TPDISTOt — — 20 ns
Rise Time TRISE —60 —ns VVCC2 =15V,VVEE2 =-8V
CLOAD= 1nF
VL 10% ,VH 90%
—400 —ns VVCC2 =15V,VVEE2 =-8V
CLOAD= 34nF
VL 10% ,VH 90%
Fall Time TFALL —60 —ns VVCC2 =15V,VVEE2 =-8V
CLOAD= 1nF
VL 10% ,VH 90%
—600 —ns VVCC2 =15V,VVEE2 =-8V
CLOAD= 34nF
VL 10% ,VH 90%
EiceDRIVERTM
1ED020I12-F
Electrical Parameters
Datasheet 15 Version 2.3, 2011-05-03
4.4.7 Desaturation protection
Parameter Symbol Limit Values Unit Test Conditions
min. typ. max.
Blanking Capacitor Charge Current IDESATC 215 250 295 uA VVCC2 =15V,VVEE2 =-8V
VDESAT=2V
Blanking Capacitor Discharge
Current
IDESATD 1 2 — mA VVCC2 =15V,VVEE2 =-8V
VDESAT=6V
Desaturation Reference Level VDESAT 8.3 99.5 V VVCC2 =15V,VVEE2 =-8V
Desaturation Reference Level VDESAT 7.6 8.6 9.5 V VVCC2 =15V,VVEE2 =0V
Desaturation Sense to OUT Low
Delay
TDESATOUT —100 150 ns VOUT =90%
CLOAD= 1nF
Desaturation Sense to FLT Low
Delay
TDESATFLT — — 2.25 us VFLT =10%; IFLT =5mA
Desaturation Low Voltage VDESATL 0.4 0.6 0.95 VIN+=Low, IN-=Low,
OUT=Low
4.4.8 Active Shut Down
Parameter Symbol Limit Values Unit Test Conditions
min. typ. max.
Active Shut Down Voltage VACTSD
1)
1) With reference to VEE2
⎯ ⎯ 4 V IOUT=-200mA,
VCC2 open
Datasheet 16 Version 2.3, 2011-05-03
EiceDRIVERTM
1ED020I12-F
Insulation Characteristics
5 Insulation Characteristics
5.1
I-IV
I-III
I-II
55/105/21
2
8.12
8.24
175
1420
2663
2272
6000
6000
>109
DIN EN 60747-5-2 (VDE 0884 Teil 2): 2003-01. Basic Insulation
5.2 UL 1577
3750
4500
5.3 Reliability
For Qualification Report please contact your local Infineon Technologies office.
Description Symbol Characteristic Unit
Installation classification per EN 60664-1, Table 1
for rated mains voltage ≤ 150 VRMS
for rated mains voltage ≤ 300 VRMS
for rated mains voltage ≤ 600 VRMS
Climatic Classification
Pollution Degree (EN 60664-1)
Minimum External Clearance CLR mm
Minimum External Creepage CPG mm
Minimum Comparative Tracking Index CTI
Maximum Repetitive Insulation Voltage VIORM VPEAK
Input to Output Test Voltage, Method b1)
VIORM * 1.875 = VPR, 100% Production Test with tm = 1 sec,
Partial Discharge < 5pC
1) Refer to VDE 0884 for a detailed description of Method a and Method b partial discharge test profiles.
*Note 1:Insulation characteristics are guaranteed only within the safety maximum ratings which must be ensured by protective
circuits in application. Surface mount classification is class A in accordance with CECCOO802.
*Note 2: This coupler is suitable for “basic insulation” only within the safety ratings. Compliance with the safety ratings shall
be ensured by means of suitable protective circuits.
VPR VPEAK
Input to Output Test Voltage, Method a1)
VIORM * 1.6 = VPR, Type and sample Test, tm = 60 sec,
Partial Discharge < 5pC
VPR VPEAK
Highest Allowable Overvoltage1) VIOTM VPEAK
Maximum Surge Insulation Voltage VIOSM V
Insulation Resistance at Ts, VIO = 500 V RIO Ω
Description Symbol Characteristic Unit
Insulation Withstand Voltage / 1min VISO Vrms
Insulation Test Voltage / 1sec VISO Vrms
EiceDRIVERTM
1ED020I12-F
Timing Diagrams
Datasheet 17 Version 2.3, 2011-05-03
6Timing Diagrams
IN
OUT
TPDELAY TPDELAY
Figure 5: Propagation Delay
IN+
IN-
RST
OUT
Figure 6: Turn-on and Turn-off
IN+
IN-
DESAT
OUT
9V
FLT
RST
Tdesatflt
1.0...1.8us
RDY
Figure 7: Desaturation Fault
Datasheet 18 Version 2.3, 2011-05-03
EiceDRIVERTM
1ED020I12-F
Timing Diagrams
Figure 8: UVLO
EiceDRIVERTM
1ED020I12-F
Package Outlines
Datasheet 19 Version 2.3, 2011-05-03
7 Package Outlines
PG-DSO-16-15
(Plastic Dual Small
1)
Does not include plastic or metal protusions of 0.15 max per side
Figure 9: PG-DSO-16-15
Datasheet 20 Version 2.3, 2011-05-03
EiceDRIVERTM
1ED020I12-F
Application Notes
8 Application Notes
8.1 Reference Layout for Thermal Data
The PCB layout shown in figure 12 represents the reference layout used for the thermal characterisation. Pins 9
and 16 (GND1) and pins 1 and 8 (VEE2) require ground plane connections for achiving maximum power
dissipation. The 1ED020I12-F is conceived to dissipate most of the heat generated through this pins.
PCB + Top-Layer
PCB + Bottom-Layer
Total Area = 374.4 mm2
Out
p
ut Side
In
p
ut Side
Figure 10: Reference layout for thermal data (Copper thickness 105μm)
8.2 Printed Circuit Board Guidelines
Following factors should be taken into account for an optimum PCB layout.
- Sufficient spacing should be kept between high voltage isolated side and low voltage side circuits.
- The same minimum distance between two adjacent high-side isolated parts of the PCB should be maintained to
increase the effective isolation and reduce parasitic coupling.
- In order to ensure low supply ripple and clean switching signals, bypass capacitor trace lengths should be kept
as short as possible.
Published by Infineon Technologies AG
www.infineon.com/gatedriver
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