LT3757/LT3757A
1
3757afe
For more information www.linear.com/LT3757
n Wide Input Voltage Range: 2.9V to 40V
n Positive or Negative Output Voltage Programming
with a Single Feedback Pin
n Current Mode Control Provides Excellent Transient
Response
n Programmable Operating Frequency (100kHz to
1MHz) with One External Resistor
n Synchronizable to an External Clock
n Low Shutdown Current < 1µA
n Internal 7.2V Low Dropout Voltage Regulator
n Programmable Input Undervoltage Lockout with
Hysteresis
n Programmable Soft-Start
n Small 10-Lead DFN (3mm × 3mm) and Thermally
Enhanced 10-Pin MSOP Packages
Typical applicaTion
DescripTion
Boost, Flyback, SEPIC and
Inverting Controller
The LT
®
3757/LT3757A are wide input range, current
mode, DC/DC controllers which are capable of generating
either positive or negative output voltages. They can be
configured as either a boost, flyback, SEPIC or inverting
converter. The LT3757/LT3757A drive a low side external
N-channel power MOSFET from an internal regulated 7.2V
supply. The fixed frequency, current-mode architecture
results in stable operation over a wide range of supply
and output voltages.
The operating frequency of LT3757/LT3757A can be set
with an external resistor over a 100kHz to 1MHz range,
and can be synchronized to an external clock using the
SYNC pin. A low minimum operating supply voltage of
2.9V, and a low shutdown quiescent current of less than
1µA, make the LT3757/LT3757A ideally suited for battery-
operated systems.
The LT3757/LT3757A feature soft-start and frequency
foldback functions to limit inductor current during start-
up and output short-circuit. The LT3757A has improved
load transient performance compared to the LT3757.
High Efficiency Boost Converter
FeaTures
applicaTions
n Automotive and Industrial Boost, Flyback, SEPIC and
Inverting Converters
n Telecom Power Supplies
n Portable Electronic Equipment
Efficiency
SENSE
LT3757
VIN
VIN
8V TO 16V 10µF
25V
X5R
VOUT
24V
2A
0.01Ω
41.2k
300kHz
GATE
FBX
GND INTVCC
SHDN/UVLO
SYNC
RT
SS
VC
200k
43.2k
0.1µF
22k
6.8nF
10µH
3757 TA01a
226k
16.2k
4.7µF
10V
X5R
10µF
25V
X5R
47µF
35V
×2
+
OUTPUT CURRENT (A)
0.001
EFFICIENCY (%)
30
50
40
60
70
80
90
100
0.01 0.1 1
3757 TA01b
10
VIN = 8V
VIN = 16V
L, LT, LTC, LTM, Linear Technology, the Linear logo and Burst Mode are registered trademarks
and No RSENSE and ThinSOT are trademarks of Analog Devices, Inc. All other trademarks are the
property of their respective owners.
LT3757/LT3757A
2
3757afe
For more information www.linear.com/LT3757
pin conFiguraTion
absoluTe MaxiMuM raTings
VIN, SHDN/UVLO (Note 6) .........................................40V
INTVCC ....................................................VIN + 0.3V, 20V
GATE ........................................................ INTVCC + 0.3V
SYNC ..........................................................................8V
VC, SS .........................................................................3V
RT ............................................................................1.5V
SENSE .................................................................... ±0.3V
FBX ................................................................. –6V to 6V
(Note 1)
TOP VIEW
DD PACKAGE
10-LEAD (3mm
×
3mm) PLASTIC DFN
10
9
6
7
8
4
5
11
3
2
1VIN
SHDN
/UVLO
INTVCC
GATE
SENSE
VC
FBX
SS
RT
SYNC
TJMAX = 125°C, θJA = 43°C/W
EXPOSED PAD (PIN 11) IS GND, MUST BE SOLDERED TO PCB
1
2
3
4
5
VC
FBX
SS
RT
SYNC
10
9
8
7
6
VIN
SHDN
/UVLO
INTVCC
GATE
SENSE
TOP VIEW
MSE PACKAGE
10-LEAD PLASTIC MSOP
11
TJMAX = 150°C, θJA = 40°C/W
EXPOSED PAD (PIN 11) IS GND, MUST BE SOLDERED TO PCB
orDer inForMaTion
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LT3757EDD#PBF LT3757EDD#TRPBF LDYW 10-Lead (3mm × 3mm) Plastic DFN –40°C to 125°C
LT3757IDD#PBF LT3757IDD#TRPBF LDYW 10-Lead (3mm × 3mm) Plastic DFN –40°C to 125°C
LT3757EMSE#PBF LT3757EMSE#TRPBF LTDYX 10-Lead (3mm × 3mm) Plastic MSOP –40°C to 125°C
LT3757IMSE#PBF LT3757IMSE#TRPBF LTDYX 10-Lead (3mm × 3mm) Plastic MSOP –40°C to 125°C
LT3757HMSE#PBF LT3757HMSE#TRPBF LTDYX 10-Lead (3mm × 3mm) Plastic MSOP –40°C to 150°C
LT3757MPMSE#PBF LT3757MPMSE#TRPBF LTDYX 10-Lead (3mm × 3mm) Plastic MSOP –55°C to 150°C
LT3757AEDD#PBF LT3757AEDD#TRPBF LGGR 10-Lead (3mm × 3mm) Plastic DFN –40°C to 125°C
LT3757AIDD#PBF LT3757AIDD#TRPBF LGGR 10-Lead (3mm × 3mm) Plastic DFN –40°C to 125°C
LT3757AEMSE#PBF LT3757AEMSE#TRPBF LTGGM 10-Lead (3mm × 3mm) Plastic MSOP –40°C to 125°C
LT3757AIMSE#PBF LT3757AIMSE#TRPBF LTGGM 10-Lead (3mm × 3mm) Plastic MSOP –40°C to 125°C
LT3757AHMSE#PBF LT3757AHMSE#TRPBF LTGGM 10-Lead (3mm × 3mm) Plastic MSOP –40°C to 150°C
LT3757AMPMSE#PBF LT3757AMPMSE#TRPBF LTGGM 10-Lead (3mm × 3mm) Plastic MSOP –55°C to 150°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through
designated sales channels with #TRMPBF suffix.
Operating Temperature Range (Notes 2, 8)
LT3757E/LT3757AE............................ –40°C to 125°C
LT3757I/LT3757AI ............................. –40°C to 125°C
LT3757H/LT3757AH ........................... –40°C to 150°C
LT3757MP/LT3757AMP ..................... –55°C to 150°C
Storage Temperature Range
DFN .................................................... –65°C to 125°C
MSOP ................................................ –65°C to 150°C
Lead Temperature (Soldering, 10 sec)
MSOP ............................................................... 300°C
http://www.linear.com/product/LT3757#orderinfo
LT3757/LT3757A
3
3757afe
For more information www.linear.com/LT3757
elecTrical characTerisTics
The l denotes the specifications which apply over the full operating temp-
erature range, otherwise specifications are at TA = 25°C. VIN = 24V, SHDN/UVLO = 24V, SENSE = 0V, unless otherwise noted.
PARAMETER CONDITIONS MIN TYP MAX UNITS
VIN Operating Range 2.9 40 V
VIN Shutdown IQSHDN/UVLO = 0V
SHDN/UVLO = 1.15V
0.1 1
6
µA
µA
VIN Operating IQVC = 0.3V, RT = 41.2k 1.6 2.2 mA
VIN Operating IQ with Internal LDO Disabled VC = 0.3V, RT = 41.2k, INTVCC = 7.5V 280 400 µA
SENSE Current Limit Threshold l100 110 120 mV
SENSE Input Bias Current Current Out of Pin –65 µA
Error Amplifier
FBX Regulation Voltage (VFBX(REG)) VFBX > 0V (Note 3)
VFBX < 0V (Note 3)
l
l
1.569
–0.816
1.6
–0.80
1.631
–0.784
V
V
FBX Overvoltage Lockout VFBX > 0V (Note 4)
VFBX < 0V (Note 4)
6
7
8
11
10
14
%
%
FBX Pin Input Current VFBX = 1.6V (Note 3)
VFBX = –0.8V (Note 3)
–10
70 100
10
nA
nA
Transconductance gm (∆IVC /∆VFBX) (Note 3) 230 µS
VC Output Impedance (Note 3) 5 MΩ
VFBX Line Regulation [∆VFBX /(∆VIN • VFBX(REG))] VFBX > 0V, 2.9V < VIN < 40V (Notes 3, 7)
VFBX < 0V, 2.9V < VIN < 40V (Notes 3, 7)
0.002
0.0025
0.056
0.05
%/V
%/V
VC Current Mode Gain (∆VVC /∆VSENSE) 5.5 V/V
VC Source Current VFBX = 0V, VC = 1.5V –15 µA
VC Sink Current VFBX = 1.7V
VFBX = –0.85V
12
11
µA
µA
Oscillator
Switching Frequency RT = 41.2k to GND, VFBX = 1.6V
RT = 140k to GND, VFBX = 1.6V
RT = 10.5k to GND, VFBX = 1.6V
270 300
100
1000
330 kHz
kHz
kHz
RT Voltage VFBX = 1.6V 1.2 V
Minimum Off-Time 220 ns
Minimum On-Time 220 ns
SYNC Input Low 0.4 V
SYNC Input High 1.5 V
SS Pull-Up Current SS = 0V, Current Out of Pin –10 µA
Low Dropout Regulator
INTVCC Regulation Voltage l7 7.2 7.4 V
INTVCC Undervoltage Lockout Threshold Falling INTVCC
UVLO Hysteresis
2.6 2.7
0.1
2.8 V
V
INTVCC Overvoltage Lockout Threshold 16 17.5 V
INTVCC Current Limit VIN = 40V
VIN = 15V
30 40
95
55 mA
mA
INTVCC Load Regulation (∆VINTVCC /V
INTVCC) 0 < IINTVCC < 20mA, VIN = 8V –0.9 –0.5 %
INTVCC Line Regulation ∆VINTVCC /(VINTVCC • ∆VIN) 8V < VIN < 40V 0.008 0.03 %/V
Dropout Voltage (VIN – VINTVCC) VIN = 6V, IINTVCC = 20mA 400 mV
INTVCC Current in Shutdown SHDN/UVLO = 0V, INTVCC = 8V 16 µA
LT3757/LT3757A
4
3757afe
For more information www.linear.com/LT3757
TEMPERATURE (°C)
–75 –50
1580
1585
REGULATED FEEDBACK VOLTAGE (mV)
1590
1605
1600
0 50 75
1595
–25 25 100
150
125
3757 G01
VIN = 40V
VIN = 24V
VIN = 8V
VIN = INTVCC = 2.9V
SHDN/UVLO = 1.33V
TEMPERATURE (°C)
REGULATED FEEDBACK VOLTAGE (mV)
–802
–800
–798
–788
–790
–792
–794
–804
–796
3757 G02
–75 –50 0 50 75–25 25 100
150
125
VIN = 40V
VIN = 24V
VIN = 8V
VIN = INTVCC = 2.9V
SHDN/UVLO = 1.33V
Typical perForMance characTerisTics
Positive Feedback Voltage
vs Temperature, VIN
Negative Feedback Voltage
vs Temperature, VIN
Quiescent Current
vs Temperature, VIN
TA = 25°C, unless otherwise noted.
elecTrical characTerisTics
The l denotes the specifications which apply over the full operating temp-
erature range, otherwise specifications are at TA = 25°C. VIN = 24V, SHDN/UVLO = 24V, SENSE = 0V, unless otherwise noted.
PARAMETER CONDITIONS MIN TYP MAX UNITS
INTVCC Voltage to Bypass Internal LDO 7.5 V
Logic Inputs
SHDN/UVLO Threshold Voltage Falling VIN = INTVCC = 8V l1.17 1.22 1.27 V
SHDN/UVLO Input Low Voltage I(VIN) Drops Below 1µA 0.4 V
SHDN/UVLO Pin Bias Current Low SHDN/UVLO = 1.15V 1.7 2 2.5 µA
SHDN/UVLO Pin Bias Current High SHDN/UVLO = 1.30V 10 100 nA
Gate Driver
tr Gate Driver Output Rise Time CL = 3300pF (Note 5), INTVCC = 7.5V 22 ns
tf Gate Driver Output Fall Time CL = 3300pF (Note 5), INTVCC = 7.5V 20 ns
Gate VOL 0.05 V
Gate VOH INTVCC –0.05 V
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LT3757E/LT3757AE are guaranteed to meet performance
specifications from the 0°C to 125°C junction temperature. Specifications
over the –40°C to 125°C operating junction temperature range are
assured by design, characterization and correlation with statistical process
controls. The LT3757I/LT3757AI are guaranteed over the full –40°C to
125°C operating junction temperature range. The LT3757H/LT3757AH are
guaranteed over the full –40°C to 150°C operating junction temperature
range. High junction temperatures degrade operating lifetimes. Operating
lifetime is derated at junction temperatures greater than 125°C. The
LT3757MP/LT3757AMP are 100% tested and guaranteed over the full
–55°C to 150°C operating junction temperature range.
Note 3: The LT3757/LT3757A are tested in a feedback loop which servos
VFBX to the reference voltages (1.6V and –0.8V) with the VC pin forced
to 1.3V.
Note 4: FBX overvoltage lockout is measured at VFBX(OVERVOLTAGE) relative
to regulated VFBX(REG).
Note 5: Rise and fall times are measured at 10% and 90% levels.
Note 6: For VIN below 6V, the SHDN/UVLO pin must not exceed VIN.
Note 7: SHDN/UVLO = 1.33V when VIN = 2.9V.
Note 8: The LT3757/LT3757A include overtemperature protection that
is intended to protect the device during momentary overload conditions.
Junction temperature will exceed the maximum operating junction
temperature when overtemperature protection is active. Continuous
operation above the specified maximum operating junction temperature
may impair device reliability.
–75 –50 0 50 75–25 25 100
150
125
TEMPERATURE (°C)
1.4
QUIESCENT CURRENT (mA)
1.6
1.8
1.5
1.7
3757 G03
VIN = 40V VIN = 24V
VIN = INTVCC = 2.9V
LT3757/LT3757A
5
3757afe
For more information www.linear.com/LT3757
Typical perForMance characTerisTics
Switching Frequency
vs Temperature
SENSE Current Limit Threshold
vs Temperature
SENSE Current Limit Threshold
vs Duty Cycle
SHDN/UVLO Threshold
vs Temperature SHDN/UVLO Current vs Voltage
SHDN/UVLO Hysteresis Current
vs Temperature
Dynamic Quiescent Current
vs Switching Frequency RT vs Switching Frequency
Normalized Switching Frequency
vs FBX
TA = 25°C, unless otherwise noted.
FBX VOLTAGE (V)
–0.8
0
NORMALIZED FREQUENCY (%)
20
40
60
80
120
–0.4 0 0.4 0.8
3757 G06
1.2 1.6
100
–75 –50 0 50 75–25 25 100
150
125
TEMPERATURE (°C)
100
SENSE THRESHOLD (mV)
105
110
115
120
3757 G08
DUTY CYCLE (%)
0
95
SENSE THRESHOLD (mV)
105
20 40 8060
115
100
110
100
3757 G09
SHDN/UVLO VOLTAGE (V)
0
0
SHDN/UVLO CURRENT (µA)
20
10 20 30
40
10
30
40
3757 G11
–75 –50 0 50 75–25 25 100
150
125
TEMPERATURE (°C)
1.6
I
SHDN/ UVLO
(µA)
1.8
2.0
2.2
2.4
3757 G12
SWITCHING FREQUENCY (KHz)
0
0
I
Q
(mA)
15
20
35
300 500 600 700
10
5
25
30
100 200 400 900800 1000
3757 G04
CL = 3300pF
SWITCHING FREQUENCY (KHz)
0
10
RT (kΩ)
100
1000
300 500 600 700
100 200 400 900800 1000
3757 G05
–75 –50 0 50 75–25 25 100
150
125
TEMPERATURE (°C)
270
SWITCHING FREQUENCY (kHz)
280
290
300
310
330
3757 G07
320
RT = 41.2K
–75 –50 0 50 75–25 25 100
150
125
TEMPERATURE (°C)
1.18
SHDN/UVLO VOLTAGE (V)
1.22
1.24
1.26
1.28
1.20
3757 G10
SHDN/UVLO FALLING
SHDN/UVLO RISING
LT3757/LT3757A
6
3757afe
For more information www.linear.com/LT3757
Typical perForMance characTerisTics
INTVCC Line Regulation
INTVCC Dropout Voltage
vs Current, Temperature
Gate Drive Rise
and Fall Time vs INTVCC Typical Start-Up Waveforms
INTVCC vs Temperature
INTVCC Minimum Output Current
vs VIN INTVCC Load Regulation
TA = 25°C, unless otherwise noted.
Gate Drive Rise
and Fall Time vs CL
FBX Frequency Foldback
Waveforms During Overcurrent
–75 –50 0 50 75–25 25 100
150
125
TEMPERATURE (°C)
7.0
INTV
CC
(V)
7.1
7.2
7.3
7.4
3757 G13
VIN (V)
0
INTV
CC
VOLTAGE (V)
35
7.25
7.20
10 20
515 25 30 40
7.15
7.10
7.30
3757 G16
CL (nF)
0
TIME (ns)
60
70
80
50
40
5 1510 20 25 30
10
0
30
90
20
3757 G18
RISE TIME
INTVCC = 7.2V
FALL TIME
INTVCC (V)
3
TIME (ns)
20
25
15
10
9
612 15
5
0
30
3757 G19
CL = 3300pF
RISE TIME
FALL TIME
2ms/DIV
VOUT
5V/DIV
IL1A + IL1B
5A/DIV
3757 G20
VIN = 12V
PAGE 31 CIRCUIT
50µs/DIV
PAGE 31 CIRCUIT
VOUT
10V/DIV
VSW
20V/DIV
IL1A + IL1B
5A/DIV
3757 G21
VIN = 12V
INTVCC LOAD (mA)
0
6.8
7
7.1
7.2
7.3
20 40 50 60
6.9
10 30 70
3757 G15
INTV
CC
VOLTAGE (V)
VIN = 8V
INTVCC LOAD (mA)
0
DROPOUT VOLTAGE (mV)
500
600
300
400
200
10
515
20
100
0
700
3757 G17
150°C
125°C
25°C
0°C
–55°C
75°C
VIN = 6V
VIN (V)
0
INTV
CC
CURRENT (mA)
50
60
70
40
3757 G14
40
30
0
10
10 20 305 15 25 35
20
90
80
TJ = 150°C
INTVCC = 6V
INTVCC = 4.5V
LT3757/LT3757A
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3757afe
For more information www.linear.com/LT3757
pin FuncTions
V
C
(Pin 1): Error Amplifier Compensation Pin. Used to
stabilize the voltage loop with an external RC network.
FBX (Pin 2): Positive and Negative Feedback Pin. Receives
the feedback voltage from the external resistor divider
across the output. Also modulates the frequency during
start-up and fault conditions when FBX is close to GND.
SS (Pin 3): Soft-Start Pin. This pin modulates compensa-
tion pin voltage (VC) clamp. The soft-start interval is set
with an external capacitor. The pin has a 10µA (typical)
pull-up current source to an internal 2.5V rail. The soft-
start pin is reset to GND by an undervoltage condition
at SHDN/UVLO, an INTVCC undervoltage or overvoltage
condition or an internal thermal lockout.
RT (Pin 4): Switching Frequency Adjustment Pin. Set the
frequency using a resistor to GND. Do not leave this pin
open.
SYNC (Pin 5): Frequency Synchronization Pin. Used to
synchronize the switching frequency to an outside clock.
If this feature is used, an RT resistor should be chosen
to program a switching frequency 20% slower than the
SYNC pulse frequency. Tie the SYNC pin to GND if this
feature is not used. SYNC is ignored when FBX is close
to GND.
SENSE (Pin 6): The Current Sense Input for the Control
Loop. Kelvin connect this pin to the positive terminal of
the switch current sense resistor in the source of the
N-channel MOSFET. The negative terminal of the current
sense resistor should be connected to GND plane close
to the IC.
GATE (Pin 7): N-Channel MOSFET Gate Driver Output.
Switches between INTVCC and GND. Driven to GND when
IC is shut down, during thermal lockout or when INTVCC
is above or below the OV or UV thresholds, respectively.
INTVCC (Pin 8): Regulated Supply for Internal Loads and
Gate Driver. Supplied from V
IN
and regulated to 7.2V (typi
-
cal). INTVCC must be bypassed with a minimum of 4.7µF
capacitor placed close to pin. INTVCC can be connected
directly to VIN, if VIN is less than 17.5V. INTVCC can also
be connected to a power supply whose voltage is higher
than 7.5V, and lower than VIN, provided that supply does
not exceed 17.5V.
SHDN/UVLO (Pin 9): Shutdown and Undervoltage Detect
Pin. An accurate 1.22V (nominal) falling threshold with
externally programmable hysteresis detects when power
is okay to enable switching. Rising hysteresis is generated
by the external resistor divider and an accurate internal
2µA pull-down current. An undervoltage condition resets
sort-start. Tie to 0.4V, or less, to disable the device and
reduce VIN quiescent current below 1µA.
VIN (Pin 10): Input Supply Pin. Must be locally bypassed
with a 0.22µF, or larger, capacitor placed close to the pin.
Exposed Pad (Pin 11): Ground. This pin also serves as
the negative terminal of the current sense resistor. The
Exposed Pad must be soldered directly to the local ground
plane.
LT3757/LT3757A
8
3757afe
For more information www.linear.com/LT3757
block DiagraM
Figure1. LT3757 Block Diagram Working as a SEPIC Converter
L1
R1
R3R4
M1
R2
L2
FBX
1.22V
2.5V
D1
CDC
CIN
VOUT
COUT2
COUT1
CVCC
INTVCC
VIN
RSENSE
VISENSE
•+
+
VIN
IS1
2µA
10
8
7
1
9
SHDN/UVLO
INTERNAL
REGULATOR
AND UVLO
TSD
165˚C
A10
Q3
VC
VC
17.5V
2.7V UP
2.6V DOWN
A8
UVLO
IS2
10µA
IS3
CC1
CC2 RC
DRIVER
SLOPE
SENSE
GND
GATE
108mV
SR1
+
–
+
–
CURRENT
LIMIT
RAMP
GENERATOR
7.2V LDO
•
+
–
+
–
R O
S
2.5V
G1
RT
RT
SS
CSS
SYNC
1.25V
1.25V
FBX
FBX
1.6V
–0.8V
+
–
+
–
+
–
2
3 5 4
+
–
+
–
6
11
RAMP
PWM
COMPARATOR
FREQUENCY
FOLDBACK
100kHz-1MHz
OSCILLATOR
FREQ
FOLDBACK
FREQ
PROG
3757 F01
–
+
+Q1
A1
A2
1.72V
–0.88V
+
–
+
–
A11
A12
A3
A4
A5
A6
G2
G5
G6
A7
A9
Q2
D2
R5
8k D3
G4 G3
LT3757/LT3757A
9
3757afe
For more information www.linear.com/LT3757
applicaTions inForMaTion
Main Control Loop
The LT3757 uses a fixed frequency, current mode con-
trol scheme to provide excellent line and load regulation.
Operation can be best understood by referring to the
Block Diagram in Figure1.
The start of each oscillator cycle sets the SR latch (SR1)
and turns on the external power MOSFET switch M1
through driver G2. The switch current flows through the
external current sensing resistor RSENSE and generates a
voltage proportional to the switch current. This current
sense voltage VISENSE (amplified by A5) is added to a
stabilizing slope compensation ramp and the resulting
sum (SLOPE) is fed into the positive terminal of the PWM
comparator A7. When SLOPE exceeds the level at the
negative input of A7 (VC pin), SR1 is reset, turning off the
power switch. The level at the negative input of A7 is set
by the error amplifier A1 (or A2) and is an amplified ver-
sion of the difference between the feedback voltage (FBX
pin) and the reference voltage (1.6V or –0.8V, depending
on the configuration). In this manner, the error ampli-
fier sets the correct peak switch current level to keep the
output in regulation.
The LT3757 has a switch current limit function. The cur-
rent sense voltage is input to the current limit compara-
tor A6. If the SENSE pin voltage is higher than the sense
current limit threshold VSENSE(MAX) (110mV, typical), A6
will reset SR1 and turn off M1 immediately.
The LT3757 is capable of generating either positive or
negative output voltage with a single FBX pin. It can be
configured as a boost, flyback or SEPIC converter to gen-
erate positive output voltage, or as an inverting converter
to generate negative output voltage. When configured as
a SEPIC converter, as shown in Figure1, the FBX pin is
pulled up to the internal bias voltage of 1.6V by a volt-
age divider (R1 and R2) connected from VOUT to GND.
Comparator A2 becomes inactive and comparator A1 per
-
forms the inverting amplification from FBX to VC. When
the LT3757 is in an inverting configuration, the FBX pin
is pulled down to –0.8V by a voltage divider connected
from VOUT to GND. Comparator A1 becomes inactive and
comparator A2 performs the noninverting amplification
from FBX to VC.
The LT3757 has overvoltage protection functions to pro-
tect the converter from excessive output voltage over-
shoot during start-up or recovery from a short-circuit
condition. An overvoltage comparator A11 (with 20mV
hysteresis) senses when the FBX pin voltage exceeds the
positive regulated voltage (1.6V) by 8% and provides a
reset pulse. Similarly, an overvoltage comparator A12
(with 10mV hysteresis) senses when the FBX pin voltage
exceeds the negative regulated voltage (–0.8V) by 11%
and provides a reset pulse. Both reset pulses are sent to
the main RS latch (SR1) through G6 and G5. The power
MOSFET switch M1 is actively held off for the duration of
an output overvoltage condition.
Programming Turn-On and Turn-Off Thresholds with
the SHDN/UVLO Pin
The SHDN/UVLO pin controls whether the LT3757 is
enabled or is in shutdown state. A micropower 1.22V
reference, a comparator A10 and a controllable current
source IS1 allow the user to accurately program the supply
voltage at which the IC turns on and off. The falling value
can be accurately set by the resistor dividers R3 and R4.
When SHDN/UVLO is above 0.7V, and below the 1.22V
threshold, the small pull-down current source I
S1
(typical
2µA) is active.
The purpose of this current is to allow the user to program
the rising hysteresis. The Block Diagram of the compara-
tor and the external resistors is shown in Figure1. The
typical falling threshold voltage and rising threshold volt-
age can be calculated by the following equations:
VVIN,FALLING =1.22 •
(R3
+
R4)
R4
VVIN,RISING =2µA •R3+VIN,FALLIN
G
For applications where the SHDN/UVLO pin is only used
as a logic input, the SHDN/UVLO pin can be connected
directly to the input voltage VIN for always-on operation.
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INTVCC Regulator Bypassing and Operation
An internal, low dropout (LDO) voltage regulator produces
the 7.2V INTVCC supply which powers the gate driver,
as shown in Figure1. If a low input voltage operation is
expected (e.g., supplying power from a lithium-ion battery
or a 3.3V logic supply), low threshold MOSFETs should
be used. The LT3757 contains an undervoltage lockout
comparator A8 and an overvoltage lockout compara-
tor A9 for the INTVCC supply. The INTVCC undervoltage
(UV) threshold is 2.7V (typical), with 100mV hysteresis,
to ensure that the MOSFETs have sufficient gate drive
voltage before turning on. The logic circuitry within the
LT3757 is also powered from the internal INTVCC supply.
The INTVCC overvoltage (OV) threshold is set to be 17.5V
(typical) to protect the gate of the power MOSFET. When
INTVCC is below the UV threshold, or above the OV thresh-
old, the GATE pin will be forced to GND and the soft-start
operation will be triggered.
The INTVCC regulator must be bypassed to ground imme-
diately adjacent to the IC pins with a minimum of 4.7µF
ceramic capacitor. Good bypassing is necessary to supply the
high transient currents required by the MOSFET gate driver.
In an actual application, most of the IC supply current is
used to drive the gate capacitance of the power MOSFET.
The on-chip power dissipation can be a significant concern
when a large power MOSFET is being driven at a high fre-
quency and the VIN voltage is high. It is important to limit
the power dissipation through selection of MOSFET and/
or operating frequency so the LT3757 does not exceed its
maximum junction temperature rating. The junction tem-
perature TJ can be estimated using the following equations:
TJ = TA + PIC • θJA
TA = ambient temperature
θJA = junction-to-ambient thermal resistance
PIC = IC power consumption
= VIN • (IQ + IDRIVE)
IQ = VIN operation IQ = 1.6mA
IDRIVE = average gate drive current = f • QG
f = switching frequency
QG = power MOSFET total gate charge
The LT3757 uses packages with an Exposed Pad for
enhanced thermal conduction. With proper soldering to
the Exposed Pad on the underside of the package and a
full copper plane underneath the device, thermal resis-
tance (θJA) will be about 43°C/W for the DD package and
40°C/W for the MSE package. For an ambient board tem-
perature of T
A
= 70°C and maximum junction temperature
of 125°C, the maximum I
DRIVE
(I
DRIVE(MAX)
) of the DD
package can be calculated as:
IDRIVE(MAX) =
(T
J−
T
A
)
(θJA •VIN )−IQ=
1.28W
VIN
−1.6mA
The LT3757 has an internal INTVCC IDRIVE current limit
function to protect the IC from excessive on-chip power
dissipation. The IDRIVE current limit decreases as the VIN
increases (see the INTVCC Minimum Output Current vs VIN
graph in the Typical Performance Characteristics section).
If IDRIVE reaches the current limit, INTVCC voltage will fall
and may trigger the soft-start.
Based on the preceding equation and the INTVCC Minimum
Output Current vs VIN graph, the user can calculate the
maximum MOSFET gate charge the LT3757 can drive at
a given VIN and switch frequency. A plot of the maximum
QG vs VIN at different frequencies to guarantee a minimum
4.5V INTVCC is shown in Figure2.
As illustrated in Figure2, a trade-off between the operat-
ing frequency and the size of the power MOSFET may
be needed in order to maintain a reliable IC junction
Figure2. Recommended Maximum QG vs VIN at Different
Frequencies to Ensure INTVCC Higher Than 4.5V
VIN (V)
0
Q
G
(nC)
200
250
150
100
10 20
515 30 4025 35
50
0
300
3757 F02
300kHz
1MHz
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temperature. Prior to lowering the operating frequency,
however, be sure to check with power MOSFET manufac-
turers for their most recent low QG, low RDS(ON) devices.
Power MOSFET manufacturing technologies are con-
tinually improving, with newer and better performance
devices being introduced almost yearly.
An effective approach to reduce the power consumption
of the internal LDO for gate drive is to tie the INTVCC pin
to an external voltage source high enough to turn off the
internal LDO regulator.
If the input voltage VIN does not exceed the absolute maxi-
mum rating of both the power MOSFET gate-source volt-
age (VGS) and the INTVCC overvoltage lockout threshold
voltage (17.5V), the INTVCC pin can be shorted directly
to the VIN pin. In this condition, the internal LDO will be
turned off and the gate driver will be powered directly
from the input voltage, V
IN
. With the INTV
CC
pin shorted to
VIN, however, a small current (around 16µA) will load the
INTVCC in shutdown mode. For applications that require
the lowest shutdown mode input supply current, do not
connect the INTVCC pin to VIN.
In SEPIC or flyback applications, the INTVCC pin can be
connected to the output voltage VOUT through a blocking
diode, as shown in Figure3, if VOUT meets the following
conditions:
1. VOUT < VIN (pin voltage)
2. VOUT < 17.5V
3. VOUT < maximum VGS rating of power MOSFET
A resistor R
VCC
can be connected, as shown in Figure 3, to
limit the inrush current from VOUT. Regardless of whether
or not the INTV
CC
pin is connected to an external volt-
age source, it is always necessary to have the driver cir-
cuitry bypassed with a 4.7µF low ESR ceramic capacitor to
ground immediately adjacent to the INTV
CC
and GND pins.
Figure3. Connecting INTVCC to VOUT
CVCC
4.7µF
VOUT
3757 F03
INTVCC
GND
LT3757 RVCC
DVCC
Operating Frequency and Synchronization
The choice of operating frequency may be determined
by on-chip power dissipation, otherwise it is a trade-off
between efficiency and component size. Low frequency
operation improves efficiency by reducing gate drive cur-
rent and MOSFET and diode switching losses. However,
lower frequency operation requires a physically larger
inductor. Switching frequency also has implications
for loop compensation. The LT3757 uses a constant-
frequency architecture that can be programmed over a
100kHz to 1000kHz range with a single external resistor
from the RT pin to ground, as shown in Figure1. The
RT pin must have an external resistor to GND for proper
operation of the LT3757. A table for selecting the value
of RT for a given operating frequency is shown in Table 1.
Table 1. Timing Resistor (RT) Value
OSCILLATOR FREQUENCY (kHz) RT (kΩ)
100 140
200 63.4
300 41.2
400 30.9
500 24.3
600 19.6
700 16.5
800 14
900 12.1
1000 10.5
The operating frequency of the LT3757 can be synchro-
nized to an external clock source. By providing a digital
clock signal into the SYNC pin, the LT3757 will oper-
ate at the SYNC clock frequency. If this feature is used,
an RT resistor should be chosen to program a switch-
ing frequency 20% slower than SYNC pulse frequency.
The SYNC pulse should have a minimum pulse width of
200ns. Tie the SYNC pin to GND if this feature is not used.
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Duty Cycle Consideration
Switching duty cycle is a key variable defining con-
verter operation. As such, its limits must be considered.
Minimum on-time is the smallest time duration that the
LT3757 is capable of turning on the power MOSFET. This
time is generally about 220ns (typical) (see Minimum
On-Time in the Electrical Characteristics table). In each
switching cycle, the LT3757 keeps the power switch off
for at least 220ns (typical) (see Minimum Off-Time in the
Electrical Characteristics table).
The minimum on-time and minimum off-time and the
switching frequency define the minimum and maximum
switching duty cycles a converter is able to generate:
Minimum duty cycle = minimum on-time • frequency
Maximum duty cycle = 1 – (minimum off-time • frequency)
Programming the Output Voltage
The output voltage (VOUT) is set by a resistor divider, as
shown in Figure1. The positive and negative VOUT are set
by the following equations:
VOUT,POSITIVE =1.6V •1+
R2
R1
⎛
⎝
⎜⎞
⎠
⎟
VOUT,NEGATIVE =–0.8V •1+R2
R1
⎛
⎝
⎜⎞
⎠
⎟
The resistors R1 and R2 are typically chosen so that
the error caused by the current flowing into the FBX pin
during normal operation is less than 1% (this translates
to a maximum value of R1 at about 158k).
In the applications where VOUT is pulled up by an exter-
nal positive power supply, the FBX pin is also pulled up
through the R2 and R1 network. Make sure the FBX does
not exceed its absolute maximum rating (6V). The R5, D2,
and D3 in Figure1 provide a resistive clamp in the positive
direction. To ensure FBX is lower than 6V, choose suf-
ficiently large R1 and R2 to meet the following condition:
6V •1+
R2
R1
⎛
⎝
⎜⎞
⎠
⎟+3.5V •
R2
8kΩ>VOUT(MAX)
where VOUT(MAX) is the maximum VOUT that is pulled up
by an external power supply.
Soft-Start
The LT3757 contains several features to limit peak switch
currents and output voltage (VOUT) overshoot during
start-up or recovery from a fault condition. The primary
purpose of these features is to prevent damage to external
components or the load.
High peak switch currents during start-up may occur
in switching regulators. Since V
OUT
is far from its final
value, the feedback loop is saturated and the regulator
tries to charge the output capacitor as quickly as possible,
resulting in large peak currents. A large surge current may
cause inductor saturation or power switch failure.
The LT3757 addresses this mechanism with the SS pin. As
shown in Figure1, the SS pin reduces the power MOSFET
current by pulling down the VC pin through Q2. In this
way the SS allows the output capacitor to charge gradu-
ally toward its final value while limiting the start-up peak
currents. The typical start-up waveforms are shown in the
Typical Performance Characteristics section. The inductor
current IL slewing rate is limited by the soft-start function.
Besides start-up, soft-start can also be triggered by the
following faults:
1. INTVCC > 17.5V
2. INTVCC < 2.6V
3. Thermal lockout
Any of these three faults will cause the LT3757 to stop
switching immediately. The SS pin will be discharged by
Q3. When all faults are cleared and the SS pin has been
discharged below 0.2V, a 10µA current source IS2 starts
charging the SS pin, initiating a soft-start operation.
The soft-start interval is set by the soft-start capacitor
selection according to the equation:
TSS =CSS •
1.25V
10µA
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FBX Frequency Foldback
When VOUT is very low during start-up or a short-circuit
fault on the output, the switching regulator must operate
at low duty cycles to maintain the power switch current
within the current limit range, since the inductor cur-
rent decay rate is very low during switch off time. The
minimum on-time limitation may prevent the switcher
from attaining a sufficiently low duty cycle at the pro-
grammed switching frequency. So, the switch current
will keep increasing through each switch cycle, exceed-
ing the programmed current limit. To prevent the switch
peak currents from exceeding the programmed value, the
LT3757 contains a frequency foldback function to reduce
the switching frequency when the FBX voltage is low (see
the Normalized Switching Frequency vs FBX graph in the
Typical Performance Characteristics section).
The typical frequency foldback waveforms are shown
in the Typical Performance Characteristics section. The
frequency foldback function prevents IL from exceeding
the programmed limits because of the minimum on-time.
During frequency foldback, external clock synchroniza
-
tion is disabled to prevent interference with frequency
reducing operation.
Thermal Lockout
If LT3757 die temperature reaches 165°C (typical), the
part will go into thermal lockout. The power switch will
be turned off. A soft-start operation will be triggered. The
part will be enabled again when the die temperature has
dropped by 5°C (nominal).
Loop Compensation
Loop compensation determines the stability and transient
performance. The LT3757/LT3757A use current mode
control to regulate the output which simplifies loop com-
pensation. The LT3757A improves the no-load to heavy
load transient response, when compared to the LT3757.
New internal circuits ensure that the transient from not
switching to switching at high current can be made in a
few cycles.
The optimum values depend on the converter topology, the
component values and the operating conditions (including
the input voltage, load current, etc.). To compensate the
feedback loop of the LT3757/LT3757A, a series resistor-
capacitor network is usually connected from the VC pin
to GND. Figure1 shows the typical VC compensation net-
work. For most applications, the capacitor should be in
the range of 470pF to 22nF, and the resistor should be
in the range of 5k to 50k. A small capacitor is often con-
nected in parallel with the RC compensation network to
attenuate the VC voltage ripple induced from the output
voltage ripple through the internal error amplifier. The par-
allel capacitor usually ranges in value from 10pF to 100pF.
A practical approach to design the compensation network
is to start with one of the circuits in this data sheet that
is similar to your application, and tune the compensation
network to optimize the performance. Stability should
then be checked across all operating conditions, includ-
ing load current, input voltage and temperature.
SENSE Pin Programming
For control and protection, the LT3757 measures the
power MOSFET current by using a sense resistor (RSENSE)
between GND and the MOSFET source. Figure4 shows a
typical waveform of the sense voltage (VSENSE) across the
sense resistor. It is important to use Kelvin traces between
the SENSE pin and RSENSE, and to place the IC GND as
close as possible to the GND terminal of the RSENSE for
proper operation.
Figure4. The Sense Voltage During a Switching Cycle
3757 F04
VSENSE(PEAK)
∆VSENSE = χ • VSENSE(MAX)
VSENSE
t
DTS
VSENSE(MAX)
TS
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Due to the current limit function of the SENSE pin,
RSENSE should be selected to guarantee that the peak
current sense voltage VSENSE(PEAK) during steady state
normal operation is lower than the SENSE current limit
threshold (see the Electrical Characteristics table). Given
a 20% margin, VSENSE(PEAK) is set to be 80mV. Then,
the maximum switch ripple current percentage can be
calculated using the following equation:
c = Δ
V
SENSE
80mV −0.5 •ΔV
SENSE
c is used in subsequent design examples to calculate
inductor value. ∆VSENSE is the ripple voltage across
RSENSE.
The LT3757 switching controller incorporates 100ns tim-
ing interval to blank the ringing on the current sense signal
immediately after M1 is turned on. This ringing is caused
by the parasitic inductance and capacitance of the PCB
trace, the sense resistor, the diode, and the MOSFET. The
100ns timing interval is adequate for most of the LT3757
applications. In the applications that have very large and
long ringing on the current sense signal, a small RC filter
can be added to filter out the excess ringing. Figure5
shows the RC filter on SENSE pin. It is usually suffi-
cient to choose 22Ω for RF LT and 2.2nF to 10nF for CFLT.
Keep RF LT ’s resistance low. Remember that there is 65µA
(typical) flowing out of the SENSE pin. Adding RF LT will
affect the SENSE current limit threshold:
VSENSE_ILIM = 108mV – 65µA • RF LT
APPLICATION CIRCUITS
The LT3757 can be configured as different topologies. The
first topology to be analyzed will be the boost converter,
followed by the flyback, SEPIC and inverting converters.
Boost Converter: Switch Duty Cycle and Frequency
The LT3757 can be configured as a boost converter for
the applications where the converter output voltage is
higher than the input voltage. Remember that boost con-
verters are not short-circuit protected. Under a shorted
output condition, the inductor current is limited only by
the input supply capability. For applications requiring a
step-up converter that is short-circuit protected, please
refer to the Applications Information section covering
SEPIC converters.
The conversion ratio as a function of duty cycle is
V
OUT
VIN
=
1
1−D
in continuous conduction mode (CCM).
For a boost converter operating in CCM, the duty cycle
of the main switch can be calculated based on the output
voltage (VOUT) and the input voltage (VIN). The maximum
duty cycle (DMAX) occurs when the converter has the
minimum input voltage:
DMAX =
V
OUT −
V
IN(MIN)
V
OUT
Discontinuous conduction mode (DCM) provides higher
conversion ratios at a given frequency at the cost of
reduced efficiencies and higher switching currents.
Figure5. The RC Filter on SENSE Pin
CFLT
3757 F05
LT3757
RFLT
RSENSE
M1
SENSE
GATE
GND
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Boost Converter: Inductor and Sense Resistor Selection
For the boost topology, the maximum average inductor
current is:
IL(MAX) =IO(MAX) •
1
1−DMAX
Then, the ripple current can be calculated by:
ΔIL= c •IL(MAX) = c •IO(MAX) •
1
1−D
MAX
The constant c in the preceding equation represents the
percentage peak-to-peak ripple current in the inductor,
relative to IL(MAX).
The inductor ripple current has a direct effect on the
choice of the inductor value. Choosing smaller values of
∆IL requires large inductances and reduces the current
loop gain (the converter will approach voltage mode).
Accepting larger values of ∆IL provides fast transient
response and allows the use of low inductances, but
results in higher input current ripple, greater core losses,
and in some cases, sub-harmonic oscillation. A good
starting point of c is 0.2 and careful evaluation of system
stability should be made to ensure adequate design
margin.
Given an operating input voltage range, and having cho-
sen the operating frequency and ripple current in the
inductor, the inductor value of the boost converter can
be determined using the following equation:
L=
V
IN(MIN)
ΔI
L
•f•DMAX
The peak and RMS inductor current are:
IL(PEAK) =IL(MAX) •1+c
2
⎛
⎝
⎜⎞
⎠
⎟
IL(RMS) =IL(MAX) •1+c2
12
Based on these equations, the user should choose the
inductors having sufficient saturation and RMS current
ratings.
Set the sense voltage at I
L(PEAK)
to be the minimum of the
SENSE current limit threshold with a 20% margin. The
sense resistor value can then be calculated to be:
RSENSE =
80mV
IL(PEAK)
Boost Converter: Power MOSFET Selection
Important parameters for the power MOSFET include the
drain-source voltage rating (VDS), the threshold voltage
(VGS(TH)), the on-resistance (RDS(ON)), the gate to source
and gate to drain charges (QGS and QGD), the maximum
drain current (ID(MAX)) and the MOSFET’s thermal
resistances (RθJC and RθJA).
The power MOSFET will see full output voltage, plus a
diode forward voltage, and any additional ringing across
its drain-to-source during its off-time. It is recommended
to choose a MOSFET whose BVDSS is higher than VOUT by
a safety margin (a 10V safety margin is usually sufficient).
The power dissipated by the MOSFET in a boost converter
is:
P
FET
= I
2L(MAX)
• R
DS(ON)
• D
MAX
+ 2 • V
2OUT
• I
L(MAX)
• CRSS • f /1A
The first term in the preceding equation represents the
conduction losses in the device, and the second term, the
switching loss. CRSS is the reverse transfer capacitance,
which is usually specified in the MOSFET characteristics.
For maximum efficiency, RDS(ON) and CRSS should be
minimized. From a known power dissipated in the power
MOSFET, its junction temperature can be obtained using
the following equation:
TJ = TA + PFET • θJA = TA + PFET • (θJC + θCA)
TJ must not exceed the MOSFET maximum junction
temperature rating. It is recommended to measure the
MOSFET temperature in steady state to ensure that abso-
lute maximum ratings are not exceeded.
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Figure6. The Output Ripple Waveform of a Boost Converter
VOUT
(AC)
t
ON
ΔVESR
RINGING DUE TO
TOTAL INDUCTANCE
(BOARD + CAP)
ΔVCOUT
3757 F06
t
OFF
Boost Converter: Output Diode Selection
To maximize efficiency, a fast switching diode with low
forward drop and low reverse leakage is desirable. The
peak reverse voltage that the diode must withstand is
equal to the regulator output voltage plus any additional
ringing across its anode-to-cathode during the on-time.
The average forward current in normal operation is equal
to the output current, and the peak current is equal to:
ID(PEAK) =IL(PEAK) =1+c
2
⎛
⎝
⎜⎞
⎠
⎟•IL(MAX)
It is recommended that the peak repetitive reverse voltage
rating VRRM is higher than VOUT by a safety margin (a 10V
safety margin is usually sufficient).
The power dissipated by the diode is:
PD = IO(MAX) • VD
and the diode junction temperature is:
TJ = TA + PD • RθJA
The RθJA to be used in this equation normally includes
the RθJC for the device plus the thermal resistance from
the board to the ambient temperature in the enclosure.
TJ must not exceed the diode maximum junction tem-
perature rating.
Boost Converter: Output Capacitor Selection
Contributions of ESR (equivalent series resistance), ESL
(equivalent series inductance) and the bulk capacitance
must be considered when choosing the correct output
The choice of component(s) begins with the maximum
acceptable ripple voltage (expressed as a percentage of
the output voltage), and how this ripple should be divided
between the ESR step ∆VESR and the charging/discharg-
ing ∆VCOUT. For the purpose of simplicity, we will choose
2% for the maximum output ripple, to be divided equally
between ∆VESR and ∆VCOUT. This percentage ripple will
change, depending on the requirements of the application,
and the following equations can easily be modified. For a
1% contribution to the total ripple voltage, the ESR of the
output capacitor can be determined using the following
equation:
ESRCOUT ≤
0.01•V
OUT
ID(PEAK)
capacitors for a given output ripple voltage. The effect of
these three parameters (ESR, ESL and bulk C) on the out-
put voltage ripple waveform for a typical boost converter
is illustrated in Figure6.
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For the bulk C component, which also contributes 1% to
the total ripple:
COUT ≥
I
O(MAX)
0.01•VOUT •f
The output capacitor in a boost regulator experiences
high RMS ripple currents, as shown in Figure6. The RMS
ripple current rating of the output capacitor can be deter-
mined using the following equation:
IRMS(COUT) ≥IO(MAX) •DMAX
1−DMAX
Multiple capacitors are often paralleled to meet ESR
requirements. Typically, once the ESR requirement is sat-
isfied, the capacitance is adequate for filtering and has the
required RMS current rating. Additional ceramic capaci-
tors in parallel are commonly used to reduce the effect of
parasitic inductance in the output capacitor, which reduces
high frequency switching noise on the converter output.
Boost Converter: Input Capacitor Selection
The input capacitor of a boost converter is less critical
than the output capacitor, due to the fact that the inductor
is in series with the input, and the input current wave-
form is continuous. The input voltage source impedance
determines the size of the input capacitor, which is typi-
cally in the range of 10µF to 100µF. A low ESR capacitor
is recommended, although it is not as critical as for the
output capacitor
.
The RMS input capacitor ripple current for a boost con-
verter is:
IRMS(CIN) = 0.3 • ∆IL
FLYBACK CONVERTER APPLICATIONS
The LT3757 can be configured as a flyback converter for
the applications where the converters have multiple out-
puts, high output voltages or isolated outputs. Figure7
shows a simplified flyback converter.
The flyback converter has a very low parts count for mul-
tiple outputs, and with prudent selection of turns ratio,
can have high output/input voltage conversion ratios with
a desirable duty cycle. However, it has low efficiency due
to the high peak currents, high peak voltages and con-
sequent power loss. The flyback converter is commonly
used for an output power of less than 50W.
The flyback converter can be designed to operate either
in continuous or discontinuous mode. Compared to con-
tinuous mode, discontinuous mode has the advantage of
smaller transformer inductances and easy loop compen-
sation, and the disadvantage of higher peak-to-average
current and lower efficiency. In the high output voltage
applications, the flyback converters can be designed
to operate in discontinuous mode to avoid using large
transformers.
Figure7. A Simplified Flyback Converter
RSENSE
NP:NS
VIN
CIN CSN
VSN
LP
D
SUGGESTED
RCD SNUBBER
ID
ISW
VDS
3757 F07
GATE
GND
LT3757
SENSE
LS
M
+
–
+
–
RSN
DSN
–
+
+
COUT
+
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Flyback Converter: Switch Duty Cycle and Turns Ratio
The flyback converter conversion ratio in the continuous
mode operation is:
V
OUT
VIN
=
N
S
NP
•
D
1−D
where NS/NP is the second to primary turns ratio.
Figure8 shows the waveforms of the flyback converter
in discontinuous mode operation. During each switching
period TS, three subintervals occur: DTS, D2TS, D3TS.
During DTS, M is on, and D is reverse-biased. During
D2TS, M is off, and LS is conducting current. Both LP and
LS currents are zero during D3TS.
The flyback converter conversion ratio in the discontinu-
ous mode operation is:
V
OUT
V
IN
=
N
S
N
P
•
D
D2
According to the preceding equations, the user has rela-
tive freedom in selecting the switch duty cycle or turns
ratio to suit a given application. The selections of the
duty cycle and the turns ratio are somewhat iterative pro-
cesses, due to the number of variables involved. The user
can choose either a duty cycle or a turns ratio as the start
point. The following trade-offs should be considered when
selecting the switch duty cycle or turns ratio, to optimize
the converter performance. A higher duty cycle affects the
flyback converter in the following aspects:
• Lower MOSFET RMS current ISW(RMS), but higher
MOSFET VDS peak voltage
• Lower diode peak reverse voltage, but higher diode
RMS current ID(RMS)
• Higher transformer turns ratio (NP/NS)
The choice,
D
D+D2
=
1
3
(for discontinuous mode operation with a given D3) gives
the power MOSFET the lowest power stress (the prod-
uct of RMS current and peak voltage). However, in the
high output voltage applications, a higher duty cycle may
be adopted to limit the large peak reverse voltage of the
diode. The choice,
D
D+D2
=
2
3
(for discontinuous mode operation with a given D3)
gives the diode the lowest power stress (the product of
RMS current and peak voltage). An extreme high or low
duty cycle results in high power stress on the MOSFET
or diode, and reduces efficiency. It is recommended to
choose a duty cycle, D, between 20% and 80%.
Figure8. Waveforms of the Flyback Converter
in Discontinuous Mode Operation
3757 F08
ISW
VDS
ID
t
DTSD2TSD3TS
ISW(MAX)
ID(MAX)
TS
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Flyback Converter: Transformer Design for
Discontinuous Mode Operation
The transformer design for discontinuous mode of opera-
tion is chosen as presented here. According to Figure8,
the minimum D3 (D3MIN) occurs when the converter
has the minimum VIN and the maximum output power
(POUT). Choose D3MIN to be equal to or higher than 10%
to guarantee the converter is always in discontinuous
mode operation (choosing higher D3 allows the use of low
inductances, but results in a higher switch peak current).
The user can choose a DMAX as the start point. Then, the
maximum average primary currents can be calculated by
the following equation:
ILP(MAX) =ISW(MAX) =
P
OUT(MAX)
DMAX •VIN(MIN) •h
where h is the converter efficiency.
If the flyback converter has multiple outputs, POUT(MAX)
is the sum of all the output power.
The maximum average secondary current is:
ILS(MAX) =ID(MAX) =
I
OUT(MAX)
D2
where:
D2 = 1 – DMAX – D3
the primary and secondary RMS currents are:
ILP(RMS) =2•ILP(MAX) •DMAX
3
ILS(RMS) =2•ILS(MAX) •D2
3
According to Figure8, the primary and secondary peak
currents are:
ILP(PEAK) = ISW(PEAK) = 2 • ILP(MAX)
ILS(PEAK) = ID(PEAK) = 2 • ILS(MAX)
The primary and second inductor values of the flyback
converter transformer can be determined using the fol-
lowing equations:
LP=D
2
MAX •V
2
IN(MIN) •h
2•P
OUT(MAX) •f
LS=D22•(VOUT +VD)
2•IOUT(MAX) •f
The primary to second turns ratio is:
NP
NS
=LP
LS
Flyback Converter: Snubber Design
Transformer leakage inductance (on either the primary
or secondary) causes a voltage spike to occur after the
MOSFET turn-off. This is increasingly prominent at higher
load currents, where more stored energy must be dis-
sipated. In some cases a snubber circuit will be required
to avoid overvoltage breakdown at the MOSFET’s drain
node. There are different snubber circuits, and Application
Note 19 is a good reference on snubber design. An RCD
snubber is shown in Figure7.
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The snubber resistor value (RSN) can be calculated by the
following equation:
RSN =2•
V2
SN −VSN •VOUT •
N
P
NS
I2
SW(PEAK) •LLK •f
where VSN is the snubber capacitor voltage. A smaller
VSN results in a larger snubber loss. A reasonable VSN is
2 to 2.5 times of:
V
OUT
•N
P
N
S
LLK is the leakage inductance of the primary winding,
which is usually specified in the transformer character-
istics. LLK can be obtained by measuring the primary
inductance with the secondary windings shorted. The
snubber capacitor value (CCN) can be determined using
the following equation:
CCN =
V
SN
ΔV
SN
•R
CN
•f
where ∆VSN is the voltage ripple across CCN. A reasonable
∆VSN is 5% to 10% of VSN. The reverse voltage rating of
DSN should be higher than the sum of VSN and VIN(MAX).
Flyback Converter: Sense Resistor Selection
In a flyback converter, when the power switch is turned
on, the current flowing through the sense resistor
(ISENSE) is:
ISENSE = ILP
Set the sense voltage at ILP(PEAK) to be the minimum of
the SENSE current limit threshold with a 20% margin. The
sense resistor value can then be calculated to be:
RSENSE =
80mV
ILP(PEAK)
Flyback Converter: Power MOSFET Selection
For the flyback configuration, the MOSFET is selected
with a V
DC
rating high enough to handle the maximum
VIN, the reflected secondary voltage and the voltage spike
due to the leakage inductance. Approximate the required
MOSFET VDC rating using:
BVDSS > VDS(PEAK)
where:
V
DS(PEAK) =
V
IN(MAX) +
V
SN
The power dissipated by the MOSFET in a flyback con-
verter is:
PFET = I2M(RMS) • RDS(ON) + 2 • V2DS(PEAK) • IL(MAX) •
CRSS • f /1A
The first term in this equation represents the conduction
losses in the device, and the second term, the switching
loss. CRSS is the reverse transfer capacitance, which is
usually specified in the MOSFET characteristics.
From a known power dissipated in the power MOSFET, its
junction temperature can be obtained using the following
equation:
TJ = TA + PFET • θJA = TA + PFET • (θJC + θCA)
TJ must not exceed the MOSFET maximum junction
temperature rating. It is recommended to measure the
MOSFET temperature in steady state to ensure that abso-
lute maximum ratings are not exceeded.
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Flyback Converter: Output Diode Selection
The output diode in a flyback converter is subject to large
RMS current and peak reverse voltage stresses. A fast
switching diode with a low forward drop and a low reverse
leakage is desired. Schottky diodes are recommended if
the output voltage is below 100V.
Approximate the required peak repetitive reverse voltage
rating VRRM using:
VRRM >
N
S
NP
•VIN(MAX) +VOUT
The power dissipated by the diode is:
PD = IO(MAX) • VD
and the diode junction temperature is:
TJ = TA + PD • RθJA
The RθJA to be used in this equation normally includes
the RθJC for the device, plus the thermal resistance from
the board to the ambient temperature in the enclosure.
TJ must not exceed the diode maximum junction tem-
perature rating.
Flyback Converter: Output Capacitor Selection
The output capacitor of the flyback converter has a similar
operation condition as that of the boost converter. Refer to
the Boost Converter: Output Capacitor Selection section
for the calculation of COUT and ESRCOUT.
The RMS ripple current rating of the output capacitors
in discontinuous operation can be determined using the
following equation:
IRMS(COUT),DISCONTINUOUS ≥IO(MAX) •4−(3 •D2)
3•D2
Flyback Converter: Input Capacitor Selection
The input capacitor in a flyback converter is subject to
a large RMS current due to the discontinuous primary
current. To prevent large voltage transients, use a low
ESR input capacitor sized for the maximum RMS current.
The RMS ripple current rating of the input capacitors in
discontinuous operation can be determined using the fol-
lowing equation:
IRMS(CIN),DISCONTINUOUS ≥
P
OUT(MAX)
VIN(MIN) •h
•4−(3 •DMAX )
3•DMAX
SEPIC CONVERTER APPLICATIONS
The LT3757 can be configured as a SEPIC (single-ended
primary inductance converter), as shown in Figure 1. This
topology allows for the input to be higher, equal, or lower
than the desired output voltage. The conversion ratio as
a function of duty cycle is:
V
OUT +
V
D
VIN
=
D
1−D
in continuous conduction mode (CCM).
In a SEPIC converter, no DC path exists between the input
and output. This is an advantage over the boost converter
for applications requiring the output to be disconnected
from the input source when the circuit is in shutdown.
Compared to the flyback converter, the SEPIC converter
has the advantage that both the power MOSFET and the
output diode voltages are clamped by the capacitors (CIN,
CDC and COUT), therefore, there is less voltage ringing
across the power MOSFET and the output diodes. The
SEPIC converter requires much smaller input capacitors
than those of the flyback converter. This is due to the fact
that, in the SEPIC converter, the inductor L1 is in series
with the input, and the ripple current flowing through the
input capacitor is continuous.
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Figure9. The Switch Current Waveform of the SEPIC Converter
3757 F08
∆ISW = χ • ISW(MAX)
ISW
t
DTS
ISW(MAX)
TS
SEPIC Converter: Switch Duty Cycle and Frequency
For a SEPIC converter operating in CCM, the duty cycle
of the main switch can be calculated based on the output
voltage (VOUT), the input voltage (VIN) and the diode for-
ward voltage (VD).
The maximum duty cycle (DMAX) occurs when the con-
verter has the minimum input voltage:
DMAX =
V
OUT +
V
D
VIN(MIN) +VOUT +VD
SEPIC Converter: Inductor and Sense Resistor Selection
As shown in Figure1, the SEPIC converter contains two
inductors: L1 and L2. L1 and L2 can be independent, but
can also be wound on the same core, since identical volt-
ages are applied to L1 and L2 throughout the switching
cycle.
For the SEPIC topology, the current through L1 is the
converter input current. Based on the fact that, ideally, the
output power is equal to the input power, the maximum
average inductor currents of L1 and L2 are:
IL1(MAX) =IIN(MAX) =IO(MAX) •
D
MAX
1−DMAX
IL2(MAX) =IO(MAX)
In a SEPIC converter, the switch current is equal to IL1 +
IL2 when the power switch is on, therefore, the maximum
average switch current is defined as:
ISW(MAX) =IL1(MAX) +IL2(MAX) =IO(MAX) •
1
1−DMAX
and the peak switch current is:
ISW(PEAK) =1+c
2
⎛
⎝
⎜⎞
⎠
⎟•IO(MAX) •
1
1−D
MAX
The constant c in the preceding equations represents the
percentage peak-to-peak ripple current in the switch, rela-
tive to ISW(MAX), as shown in Figure9. Then, the switch
ripple current ∆ISW can be calculated by:
∆ISW = c • ISW(MAX)
The inductor ripple currents ∆IL1 and ∆IL2 are identical:
∆IL1 = ∆IL2 = 0.5 • ∆ISW
The inductor ripple current has a direct effect on the
choice of the inductor value. Choosing smaller values of
∆I
L
requires large inductances and reduces the current
loop gain (the converter will approach voltage mode).
Accepting larger values of ∆IL allows the use of low induc-
tances, but results in higher input current ripple, greater
core losses, and in some cases, subharmonic oscillation.
A good starting point for c is 0.2 and careful evaluation
of system stability should be made to ensure adequate
design margin.
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Given an operating input voltage range, and having cho-
sen the operating frequency and ripple current in the
inductor, the inductor value (L1 and L2 are independent)
of the SEPIC converter can be determined using the fol-
lowing equation:
L1=L2 =
V
IN(MIN)
0.5 •ΔI
SW
•f•DMAX
For most SEPIC applications, the equal inductor values
will fall in the range of 1µH to 100µH.
By making L1 = L2, and winding them on the same core,
the value of inductance in the preceding equation is
replaced by 2L, due to mutual inductance:
L=
V
IN(MIN)
ΔI
SW
•f•DMAX
This maintains the same ripple current and energy storage
in the inductors. The peak inductor currents are:
IL1(PEAK) = IL1(MAX) + 0.5 • ∆IL1
IL2(PEAK) = IL2(MAX) + 0.5 • ∆IL2
The RMS inductor currents are:
IL1(RMS) =IL1(MAX) •1+c2L1
12
where:
cL1 =Δ
I
L1
IL1(MAX)
IL2(RMS) =IL2(MAX) •1+c2L2
12
where:
cL2 =Δ
I
L2
IL2 (MAX)
Based on the preceding equations, the user should choose
the inductors having sufficient saturation and RMS cur-
rent ratings.
In a SEPIC converter, when the power switch is turned on,
the current flowing through the sense resistor (ISENSE) is
the switch current.
Set the sense voltage at ISENSE(PEAK) to be the minimum
of the SENSE current limit threshold with a 20% margin.
The sense resistor value can then be calculated to be:
RSENSE =
80 mV
ISW(PEAK)
SEPIC Converter: Power MOSFET Selection
For the SEPIC configuration, choose a MOSFET with a
VDC rating higher than the sum of the output voltage and
input voltage by a safety margin (a 10V safety margin is
usually sufficient).
The power dissipated by the MOSFET in a SEPIC converter
is:
PFET = I2SW(MAX) • RDS(ON) • DMAX
+ 2 • (VIN(MIN) + VOUT)2 • IL(MAX) • CRSS • f /1A
The first term in this equation represents the conduction
losses in the device, and the second term, the switching
loss. CRSS is the reverse transfer capacitance, which is
usually specified in the MOSFET characteristics.
For maximum efficiency, RDS(ON) and CRSS should be
minimized. From a known power dissipated in the power
MOSFET, its junction temperature can be obtained using
the following equation:
TJ = TA + PFET • θJA = TA + PFET • (θJC + θCA)
TJ must not exceed the MOSFET maximum junction
temperature rating. It is recommended to measure the
MOSFET temperature in steady state to ensure that abso-
lute maximum ratings are not exceeded.
applicaTions inForMaTion
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Figure10. A Simplified Inverting Converter
RSENSE
CDC
VIN
CIN
L1
D1 COUT
VOUT
3757 F10
+
GATE
GND
LT3757
SENSE
L2
M1
+
–
+–
+
SEPIC Converter: Output Diode Selection
To maximize efficiency, a fast switching diode with a low
forward drop and low reverse leakage is desirable. The
average forward current in normal operation is equal to
the output current, and the peak current is equal to:
ID(PEAK) =1+c
2
⎛
⎝
⎜⎞
⎠
⎟•IO(MAX) •
1
1−DMAX
It is recommended that the peak repetitive reverse voltage
rating VRRM is higher than VOUT + VIN(MAX) by a safety
margin (a 10V safety margin is usually sufficient).
The power dissipated by the diode is:
PD = IO(MAX) • VD
and the diode junction temperature is:
TJ = TA + PD • RθJA
The R
θJA
used in this equation normally includes the R
θJC
for the device, plus the thermal resistance from the board,
to the ambient temperature in the enclosure. TJ must not
exceed the diode maximum junction temperature rating.
SEPIC Converter: Output and Input Capacitor Selection
The selections of the output and input capacitors of
the SEPIC converter are similar to those of the boost
converter. Please refer to the Boost Converter, Output
Capacitor Selection and Boost Converter, Input Capacitor
Selection sections.
SEPIC Converter: Selecting the DC Coupling Capacitor
The DC voltage rating of the DC coupling capacitor (CDC,
as shown in Figure1) should be larger than the maximum
input voltage:
VCDC > VIN(MAX)
CDC has nearly a rectangular current waveform. During
the switch off-time, the current through CDC is IIN, while
approximately –I
O
flows during the on-time. The RMS
rating of the coupling capacitor is determined by the fol-
lowing equation:
IRMS(CDC) >IO(MAX) •VOUT +VD
VIN(MIN)
A low ESR and ESL, X5R or X7R ceramic capacitor works
well for CDC.
INVERTING CONVERTER APPLICATIONS
The LT3757 can be configured as a dual-inductor invert-
ing topology, as shown in Figure10. The VOUT to VIN
ratio is:
V
OUT −
V
D
V
IN
= −
D
1−D
in continuous conduction mode (CCM).
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Inverting Converter: Switch Duty Cycle and Frequency
For an inverting converter operating in CCM, the duty
cycle of the main switch can be calculated based on the
negative output voltage (V
OUT
) and the input voltage (V
IN
).
The maximum duty cycle (DMAX) occurs when the con-
verter has the minimum input voltage:
DMAX =
V
OUT −
V
D
VOUT −VD−VIN(MIN)
Inverting Converter: Inductor, Sense Resistor, Power
MOSFET, Output Diode and Input Capacitor Selections
The selections of the inductor, sense resistor, power
MOSFET, output diode and input capacitor of an invert-
ing converter are similar to those of the SEPIC converter.
Please refer to the corresponding SEPIC converter
sections.
Inverting Converter: Output Capacitor Selection
The inverting converter requires much smaller output
capacitors than those of the boost, flyback and SEPIC
converters for similar output ripples. This is due to the
fact that, in the inverting converter, the inductor L2 is
in series with the output, and the ripple current flowing
through the output capacitors are continuous. The output
ripple voltage is produced by the ripple current of L2 flow-
ing through the ESR and bulk capacitance of the output
capacitor:
ΔVOUT(P–P) = ΔIL2 •ESRCOUT +1
8•f•COUT
⎛
⎝
⎜⎞
⎠
⎟
After specifying the maximum output ripple, the user can
select the output capacitors according to the preceding
equation.
The ESR can be minimized by using high quality X5R or
X7R dielectric ceramic capacitors. In many applications,
ceramic capacitors are sufficient to limit the output volt-
age ripple.
The RMS ripple current rating of the output capacitor
needs to be greater than:
IRMS(COUT) > 0.3 • ∆IL2
Inverting Converter: Selecting the DC Coupling Capacitor
The DC voltage rating of the DC coupling capacitor (CDC,
as shown in Figure 10) should be larger than the maxi-
mum input voltage minus the output voltage (negative
voltage):
VCDC > VIN(MAX) – VOUT
CDC has nearly a rectangular current waveform. During
the switch off-time, the current through CDC is IIN, while
approximately –IO flows during the on-time. The RMS
rating of the coupling capacitor is determined by the fol-
lowing equation:
IRMS(CDC) >IO(MAX) •DMAX
1−DMAX
A low ESR and ESL, X5R or X7R ceramic capacitor works
well for CDC.
applicaTions inForMaTion
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Figure11. 8V to 16V Input, 24V/2A Output Boost Converter Suggested Layout
VIN
3757 F10
VOUT
L1
VIAS TO GROUND
PLANE
D1
COUT1
COUT2
1
2
8
7
3
4
6
5
M1
CIN
R4
RC
R1
R2
RSS
RT
R3
CVCC
CC1
CC2
LT3757
1
2
3
4
5
9
10
6
7
8
RS
Board Layout
The high speed operation of the LT3757 demands careful
attention to board layout and component placement. The
Exposed Pad of the package is the only GND terminal of
the IC, and is important for thermal management of the
IC. Therefore, it is crucial to achieve a good electrical and
thermal contact between the Exposed Pad and the ground
plane of the board. For the LT3757 to deliver its full output
power, it is imperative that a good thermal path be pro-
vided to dissipate the heat generated within the package.
It is recommended that multiple vias in the printed circuit
board be used to conduct heat away from the IC and into
a copper plane with as much area as possible.
To prevent radiation and high frequency resonance prob-
lems, proper layout of the components connected to the
IC is essential, especially the power paths with higher di/
dt. The following high di/dt loops of different topologies
should be kept as tight as possible to reduce inductive
ringing:
• In boost configuration, the high di/dt loop contains
the output capacitor, the sensing resistor, the power
MOSFET and the Schottky diode.
• In flyback configuration, the high di/dt primary loop
contains the input capacitor, the primary winding, the
power MOSFET and the sensing resistor. The high di/
dt secondary loop contains the output capacitor, the
secondary winding and the output diode.
• In SEPIC configuration, the high di/dt loop contains
the power MOSFET, sense resistor, output capacitor,
Schottky diode and the coupling capacitor.
• In inverting configuration, the high di/dt loop contains
power MOSFET, sense resistor, Schottky diode and the
coupling capacitor.
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Table 2. Recommended Component Manufacturers
VENDOR COMPONENTS WEB ADDRESS
AVX Capacitors avx.com
BH Electronics Inductors,
Transformers
bhelectronics.com
Coilcraft Inductors coilcraft.com
Cooper Bussmann Inductors bussmann.com
Diodes, Inc Diodes diodes.com
Fairchild MOSFETs fairchildsemi.com
General
Semiconductor
Diodes generalsemiconductor.com
International Rectifier MOSFETs, Diodes irf.com
IRC Sense Resistors irctt.com
Kemet Capacitors kemet.com
Magnetics Inc Toroid Cores mag-inc.com
Microsemi Diodes microsemi.com
Murata-Erie Inductors,
Capacitors
murata.co.jp
Nichicon Capacitors nichicon.com
On Semiconductor Diodes onsemi.com
Panasonic Capacitors panasonic.com
Sanyo Capacitors sanyo.co.jp
Sumida Inductors sumida.com
Taiyo Yuden Capacitors t-yuden.com
TDK Capacitors,
Inductors
component.tdk.com
Thermalloy Heat Sinks aavidthermalloy.com
Tokin Capacitors nec-tokinamerica.com
Toko Inductors tokoam.com
United Chemi-Con Capacitors chemi-con.com
Vishay/Dale Resistors vishay.com
Vishay/Siliconix MOSFETs vishay.com
Vishay/Sprague Capacitors vishay.com
Würth Elektronik Inductors we-online.com
Zetex Small-Signal
Discretes
zetex.com
applicaTions inForMaTion
Check the stress on the power MOSFET by measuring its
drain-to-source voltage directly across the device termi-
nals (reference the ground of a single scope probe directly
to the source pad on the PC board). Beware of inductive
ringing, which can exceed the maximum specified voltage
rating of the MOSFET. If this ringing cannot be avoided,
and exceeds the maximum rating of the device, either
choose a higher voltage device or specify an avalanche-
rated power MOSFET.
The small-signal components should be placed away
from high frequency switching nodes. For optimum load
regulation and true remote sensing, the top of the output
voltage sensing resistor divider should connect indepen-
dently to the top of the output capacitor (Kelvin connec-
tion), staying away from any high dV/dt traces. Place the
divider resistors near the LT3757 in order to keep the high
impedance FBX node short.
Figure11 shows the suggested layout of the 8V to 16V
Input, 24V/2A Output Boost Converter.
Recommended Component Manufacturers
Some of the recommended component manufacturers
are listed in Table 2.
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Typical applicaTions
3.3V Input, 5V/10A Output Boost Converter
Boost Preregulator for Automotive Stop-Start/Idle
Efficiency vs Output Current
Transient VIN and VOUT Waveforms
SENSE
LT3757
VIN
VIN
3.3V CIN
22µF
6.3V
×2
VOUT
5V
10A
0.004Ω
1W
M1
41.2k
300kHz
GATE
FBX
GND
INTVCC
SHDN/UVLO
SYNC
RT
SS VC
49.9k
34k
0.1µF
6.8k
22nF 2.2nF
22Ω
L1
0.5µH
D1
3757 TA02a
34k
1%
15.8k
1%
COUT1
150µF
6.3V
×4
COUT2
22µF
6.3V
X5R
×4
+
CVCC
4.7µF
10V
X5R
CIN: TAIYO YUDEN JMK325BJ226MM
COUT1: PANASONIC EEFUEOJ151R
COUT2: TAIYO YUDEN JMK325BJ226MM
D1: MBRB2515L
L1: VISHAY SILICONIX IHLP-5050FD-01
M1: VISHAY SILICONIX SI4448DY
OUTPUT CURRENT (A)
EFFICIENCY (%)
3757 TA02b
0.001
20
30
40
50
60
70
80
90
100
0.01 0.1 1 10
SENSE
LT3757A
VIN
VIN
3V TO 36V 10µF
50V
X5R
×2
VOUT
9VMIN
2A
41.2k
300kHz
GATE
FBX
GND
INTVCC
SHDN/UVLO
SYNC
RT
SS
VC
1M
698k
0.1µF
10k
10nF 4.7µF
L1
3.3µH D1
3757 TA03a
M1
75k
8mΩ
16.2k
C1
10µF
50V
×4
+
10µF
50V
X5R
L1: COILTRONIX DR127-3R3
M1: VISHAY SILICONIX Si7848BDP
D1: VISHAY SILICONIX 50SQ04FN
C1: KEMET T495X106K050A
10ms/DIV
VOUT
5V/DIV
VIN
5V/DIV
0V
3757 TA03b
OUTPUT POWER = 10W
LT3757/LT3757A
29
3757afe
For more information www.linear.com/LT3757
Typical applicaTions
8V to 16V Input, 24V/2A Output Boost Converter
Efficiency vs Output Current Load Step Response at VIN = 12V
SENSE
LT3757
VIN
VIN
8V TO 16V CIN
10µF
25V
X5R
CVCC
4.7µF
10V
X5R
VOUT
24V
2A
RS
0.01Ω
1W
M1
RT
41.2k
300kHz
GATE
FBX
GND INTVCC
SHDN/UVLO
SYNC
RT
SS
VC
R3
200k
R4
43.2k
CSS
0.1µF
CC2
100pF
RC
22k
CC1
6.8nF
L1
10µH
D1
3757 TA04a
R2
226k
1%
R1
16.2k
1%
COUT1
47µF
35V
×4
COUT2
10µF
25V
X5R
+
CIN, COUT2: MURATA GRM31CR61E106KA12
COUT1: KEMET T495X476K035AS
D1: ON SEMI MBRS340T3G
L1: VISHAY SILICONIX IHLP-5050FD-01 10µH
M1: VISHAY SILICONIX Si4840BDP
OUTPUT CURRENT (A)
0.001
EFFICIENCY (%)
30
50
40
60
70
80
90
100
0.01 0.1 1
3757 TA04b
10
VIN = 8V
VIN = 16V
500µs/DIV
VOUT
500mV/DIV
(AC)
1.6A
0.4A
IOUT
1A/DIV
3757 TA04c
LT3757/LT3757A
30
3757afe
For more information www.linear.com/LT3757
2ms/DIV
VOUT
100V/DIV
3757 TA05b 5µs/DIV
VOUT
5V/DIV
(AC)
VSW
20V/DIV
3757 TA05c
Typical applicaTions
High Voltage Flyback Power Supply
Start-Up Waveforms Switching Waveforms
SENSE
LT3757
VIN
VSW
VIN
5V TO 12V CIN
47µF
16V
×4
INTVCC
COUT
68nF
×2
VOUT
350V
10mA
0.02Ω
22Ω
M1
140k
100kHz
GATE
FBX
GND
SHDN/UVLO
DANGER! HIGH VOLTAGE OPERATION BY HIGH VOLTAGE TRAINED PERSONNEL ONLY
SYNC
RT
SS
VC
•
•
105k
46.4k
0.1µF
220pF
100pF
6.8k
22nF
T1
1:10 D1
CIN: MURATA GRM32ER61C476K
COUT: TDK C3225X7R2J683K
D1: VISHAY SILICONIX GSD2004S DUAL DIODE CONNECTED IN SERIES
M1: VISHAY SILICONIX Si7850DP
T1: TDK DCT15EFD-U44S003
3757 TA05a
1M
1%
1M
1%
1.50M
1%
16.2k
1%
10nF
CVCC
47µF
25V
X5R
22Ω
LT3757/LT3757A
31
3757afe
For more information www.linear.com/LT3757
Typical applicaTions
5.5V to 36V Input, 12V/2A Output SEPIC Converter
Efficiency vs Output Current Load Step Waveforms
Start-Up Waveforms Frequency Foldback Waveforms When Output Short-Circuits
SENSE
LT3757A
VIN
V
IN
5.5V TO 36V CIN1
4.7µF
50V
×2
CDC
4.7µF
50V, X5R, ×2
4.7µF
10V
X5R
VOUT
12V
2A
0.01Ω
1W
M1
41.2k
300kHz
GATE
FBX
GND INTVCC
SHDN/UVLO
SYNC
RT
SS
CIN2
4.7µF
50V
×2
•
•
105k
46.4k
0.1µF 6.8nF
10k
L1A
L1B
IL1B
D1
CIN1, CDC: TAIYO YUDEN UMK316BJ475KL
CIN2: KEMET T495X475K050AS
COUT1: KEMET T495X476K020AS
COUT2: TAIYO YUDEN TMK432BJ106MM
D1: ON SEMI MBRS360T3G
L1A, L1B: COILTRONICS DRQ127-4R7 (*COUPLED INDUCTORS)
M1: VISHAY SILICONIX Si7460DP
3757 TA06a
105k
1%
15.8k
1%
COUT1
47µF
20V
×4
COUT2
10µF
25V
X5R
+
VSW
IL1A
VC
+
2ms/DIV
VOUT
5V/DIV
IL1A + IL1B
5A/DIV
3757 TA06d
VIN = 12V
50µs/DIV
VOUT
10V/DIV
VSW
20V/DIV
IL1A + IL1B
5A/DIV
3757 TA06e
VIN = 12V
OUTPUT CURRENT (A)
0.001
20
EFFICIENCY (%)
30
40
50
60
70
80
90
100
0.01 0.1 1
3757 TA06b
10
VIN = 16V
VIN = 8V
500µs/DIV
VOUT
2V/DIV
AC-COUPLED
IOUT
2A/DIV 0A
2A
3757 TA06c
VIN = 12V
LT3757/LT3757A
32
3757afe
For more information www.linear.com/LT3757
Typical applicaTions
5V to 12V Input, ±12V/0.4A Output SEPIC Converter
Nonisolated Inverting SLIC Supply
SENSE
LT3757
VIN
V
IN
5V TO 12V
CIN1
1µF
16V, X5R
CIN2
47µF
16V
CDC1
4.7µF
16V, X5R
CDC2
4.7µF
16V
X5R
COUT2
4.7µF
16V, X5R
×3
VOUT1
12V
0.4A
VOUT2
–12V
0.4A
COUT2
4.7µF
16V, X5R
×3
CVCC
4.7µF
10V
X5R
0.02Ω
M1
30.9k
400kHz
D1, D2: MBRS140T3
T1: COILTRONICS VP1-0076 (*PRIMARY = 4 WINDINGS IN PARALLEL)
M1: SILICONIX/VISHAY Si4840BDY
GATE
FBX
GND INTVCC
SHDN/UVLO
SYNC
RT
SS
•
+105k
46.4k
0.1µF 100pF
22k
6.8nF
T1
1,2,3,4
D1
GND
1.05k
1%
158Ω
1%
D2
5
6
•
•
3757 TA07
VC
SENSE
LT3757
VIN
VIN
5V TO 16V CIN
22µF
25V, X5R
×2
C2
10µF
50V
X5R
D1
DFLS160
CVCC
4.7µF
10V, X5R
C3
22µF
25V
X5R
C4
22µF
25V
X5R
COUT
3.3µF
100V
GND
C5
22µF
25V
X5R
VOUT1
–24V
200mA
VOUT1
–72V
200mA
0.012Ω
0.5W
M1
Si7850DP
63.4k
200kHz
GATE
FBX
GND INTVCC
SHDN/UVLO
SYNC
RT
SS
•
•
•
•
R2
105k
R1
46.4k
0.1µF
100pF
15.8k
464k
9.1k
10nF
T1
1,2,3 4
D2
DFLS160
5
D3
DFLS160
6
VP5-0155 (PRIMARY = 3 WINDINGS IN PARALLEL)
3757 TA08
VC
LT3757/LT3757A
33
3757afe
For more information www.linear.com/LT3757
3.00 ±0.10
(4 SIDES)
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2).
CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
0.40 ± 0.10
BOTTOM VIEW—EXPOSED PAD
1.65 ± 0.10
(2 SIDES)
0.75 ±0.05
R = 0.125
TYP
2.38 ±0.10
(2 SIDES)
15
106
PIN 1
TOP MARK
(SEE NOTE 6)
0.200 REF
0.00 – 0.05
(DD) DFN REV C 0310
0.25 ± 0.05
2.38 ±0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
1.65 ±0.05
(2 SIDES)2.15 ±0.05
0.50
BSC
0.70 ±0.05
3.55
±0.05
PACKAGE
OUTLINE
0.25 ± 0.05
0.50 BSC
DD Package
10-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1699 Rev C)
PIN 1 NOTCH
R = 0.20 OR
0.35 × 45°
CHAMFER
package DescripTion
Please refer to http://www.linear.com/product/LT3757#packaging for the most recent package drawings.
DD Package
10-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1699 Rev C)
LT3757/LT3757A
34
3757afe
For more information www.linear.com/LT3757
package DescripTion
MSE Package
10-Lead Plastic MSOP, Exposed Die Pad
(Reference LTC DWG # 05-08-1664 Rev I)
Please refer to http://www.linear.com/product/LT3757#packaging for the most recent package drawings.
MSOP (MSE) 0213 REV I
0.53 ±0.152
(.021 ±.006)
SEATING
PLANE
0.18
(.007)
1.10
(.043)
MAX
0.17 –0.27
(.007 – .011)
TYP
0.86
(.034)
REF
0.50
(.0197)
BSC
1234 5
4.90 ±0.152
(.193 ±.006)
0.497 ±0.076
(.0196 ±.003)
REF
8910
10
1
76
3.00 ±0.102
(.118 ±.004)
(NOTE 3)
3.00 ±0.102
(.118 ±.004)
(NOTE 4)
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
6. EXPOSED PAD DIMENSION DOES INCLUDE MOLD FLASH. MOLD FLASH ON E-PAD
SHALL NOT EXCEED 0.254mm (.010") PER SIDE.
0.254
(.010) 0° – 6° TYP
DETAIL “A”
DETAIL “A”
GAUGE PLANE
5.10
(.201)
MIN
3.20 – 3.45
(.126 – .136)
0.889 ±0.127
(.035 ±.005)
RECOMMENDED SOLDER PAD LAYOUT
1.68 ±0.102
(.066 ±.004)
1.88 ±0.102
(.074 ±.004)
0.50
(.0197)
BSC
0.305 ± 0.038
(.0120
±.0015)
TYP
BOTTOM VIEW OF
EXPOSED PAD OPTION
1.68
(.066)
1.88
(.074)
0.1016 ±0.0508
(.004 ±.002)
DETAIL “B”
DETAIL “B”
CORNER TAIL IS PART OF
THE LEADFRAME FEATURE.
FOR REFERENCE ONLY
NO MEASUREMENT PURPOSE
0.05 REF
0.29
REF
MSE Package
10-Lead Plastic MSOP, Exposed Die Pad
(Reference LTC DWG # 05-08-1664 Rev I)
LT3757/LT3757A
35
3757afe
For more information www.linear.com/LT3757
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
revision hisTory
REV DATE DESCRIPTION PAGE NUMBER
B 3/10 Deleted Bullet from Features and Last Line of Description
Updated Entire Page to Add H-Grade and Military Grade
Updated Electrical Characteristics Notes and Typical Performance Characteristics for H-Grade and Military Grade
Revised TA04a and Replaced TA04c in Typical Applications
Updated Related Parts
1
2
4 to 6
30
36
C 5/11 Revised MP-grade temperature range in Absolute Maximum Ratings and Order Information sections
Revised Note 2
Revised formula in Applications Information
Updated Typical Application drawing TA04a values
Revised Typical Application title TA06
2
4
19
30
32
D 07/12 Added LT3757A version Throughout
Updated Block Diagram 8
Updated Programming the Output Voltage section 12
Updated Loop Compensation section 13
Added an application circuit in the Typical Applications section 28
Updated the schematic and Load Step Waveforms in the Typical Applications section 31
E 06/17 Clarified Inductor and Sense Resistor Selection sections 15, 22
(Revision history begins at Rev B)
LT3757/LT3757A
36
3757afe
For more information www.linear.com/LT3757
LINEAR TECHNOLOGY CORPORATION 2008
LT 0617 REV E • PRINTED IN USA
www.linear.com/LT3757
relaTeD parTs
Typical applicaTion
PART NUMBER DESCRIPTION COMMENTS
LT3758/LT3758A 100V Flyback, Boost, SEPIC and Inverting Controllers 5.5V ≤ VIN ≤ 100V, with Small Packages and Powerful Gate Drive
LT3759 40V Flyback, Boost, SEPIC and Inverting Controller 1.6V ≤ VIN ≤ 42V, with Small Packages and Powerful Gate Drive
LT8300/LT8303 100V Isolated Flyback Converters in SOT-23 Monolithic No-Opto Flybacks with Integrated 240A/500mA Switch
LT8304/LT8304-1 100V Isolated Flyback Converter Monolithic No-Opto Flyback with Integrated 2A Switch, SO-8 Package
LT3748 100V Isolated Flyback Converter 5V ≤ VIN ≤ 100V, No-Opto Flyback, MSOP-16 with High Voltage Spacing
LT8301/LT8302 42V Isolated Flyback Converters Monolithic No-Opto Flybacks with Integrated 1.2A/3.6A Switch
LT3798 Offline Isolated No Opto-Coupler Flyback Controller
with Active PFC
VIN and VOUT Limited Only by External Components
LT3799/LT3799-1 Offline Isolated Flyback LED Controller with Active PFC VIN and VOUT Limited Only by External Components
LT3957A Boost, Flyback, SEPIC and Inverting Converter with 5A,
40V Switch
3V ≤ VIN ≤ 40V, 100kHz to 1MHz Programmable Operation Frequency,
5mm × 6mm QFN Package
LT3958 Boost, Flyback, SEPIC and Inverting Converter with
3.3A, 84V Switch
5V ≤ VIN ≤ 80V, 100kHz to 1MHz Programmable Operation Frequency,
5mm × 6mm QFN Package
High Efficiency Inverting Power Supply
Efficiency vs Output Current
OUTPUT CURRENT (A)
0.001
10
EFFICIENCY (%)
20
30
40
50
60
70
80
90
100
0.01 0.1 1
3757 TA09b
10
VIN = 16V
VIN = 5V
SENSE
LT3757
VIN
VIN
5V TO
15V CIN
47µF
16V
X5R
CDC
47µF
25V, X5R VOUT
–5V
3A to 5A
0.006Ω
1W
M1
Si7848BDP
41.2k
300kHz
GATE
FBX
GND INTVCC
SHDN/UVLO
SYNC
RT
SS
•
•
R2
105k
R1
46.4k
0.1µF
9.1k
10nF
L1
L2
D1
MBRD835L
L1, L2: COILTRONICS DRQ127-3R3 (*COUPLED INDUCTORS) 3757 TA09a
84.5k
16k
CVCC
4.7µF
10V
X5R
COUT
100µF
6.3V, X5R
×2
VC
