IT9010 VXIntegrator interface TECHNOLOGY Register-Based Interface Chip FEATURES * Interrupter Capability Dynamic or Static Configuration AMG:0) CLK A24/A32 Register Support LA(7:0) LAD(6:1) Device Dependant Register Support VA(31:1) LCS" , ; isters: vas" acs Integration of the following VXI registers: on vweite LDTACK! 2 Programmable Logical Address =z VDS0" > ID = Vpsl" LD(15:0) - . O VDTACK . w Device Type a MODID VUE SB Offset Co IACK* REGWR" => Status/Control <x Roane Wee 4 Status/ID (used for Interrupts) ~ + ceinati 5S RQC:1)* IDISEL* 5B e Power dissipation < 400mW @ 5V = DTISEL* 2) INTL] * Surface-mount or PGA package 3 INTL2 HRDRST* L = INTL3 SFIRST" a> VD(15:0) RST wn YAEN VDDIR CRBIT(13:11) me VINTCLR SUPPORTS D32 aM AUIOCEG DESCRIPTION The IT9010 register-based Interface chip integrates the required VXIbus registers, VXIbus address decoding, and VXI/Local bus arbitration into a single chip. This allows the designer to implement a VXIbus register-based interface with a minimum of support hardware, complexity, and board space. MODID support allows the chip to implement either Static or Dynamic logical address configuration. The IT9010 has the capability of decoding all 31 VXI bus address lines (A1-A31), allowing the user to con- figure the chip as either an A24 device or an A32 device. An on-board offset register will automatically map to, and decode, the correct VXI bus address lines as deter- mined by the configured device type (A24 or A32) and the amount of A24/A32 memory requested. Other features of the IT9010 include interrupter capability, A16 Device Dependent register decoding, and automatic configuration of the ID and Device Type registers from external switches, allowing the IT9010 to be programmed with or with- out a microprocessor. IT9010 FUNCTIONAL BLOCK DIAGRAM VAG) Sy wi Wt) >} grec AMG.) <> LOGIC MODID i CLK et LAD (6:1) vast LRW VWRITE* BUS ARBITER CONTROL SEQUENCER ADDRESS DECODE HRDRST vpso' UACS* VDSI* > SFIRST A A LOCATION DDSEL' IACK" MONITORS > UASEL IACKIN' VXI lACKOUT < 7 INTERRUPT 3 IRQQ:1)" <> CONTROL I< a INTL(3:1) VINTCLR vopIR < VXI > REGRO" VDBEN Bus 9 < LOCAL > REGWR VDIACK < CONTROL BUS > vxi/icl 53 e > LDIACK' Be 5 CONTROL Speer 56 E 5 onse o Oo * oO Vv H lo, lo, I VO(15:0) < o >| CONFIGURATION REGISTER lc 7 > LDI5:0) STATUS/ID WORD REGISTER AUTOCFG OFFSET REGISTER > RST GND 16 STATUS/CONTROL REGISTER 7 SFINE a> > SFAIL vec DEVICE TYPE REGISTER UAEN ID/LOGICAL ADDRESS REGISTER es > CRBIT(13:11) PINOUT lo rfl PGA FOOTPRINT (TOP VIEW) a 0 t [(OOOODO0DD00000O0O e]OO0O0 O00 C) C) P}OO0O O00 ]O ODOQOVDNOVV00O O MJO OODONOC0O00O O L|O OOOON0C0C00O O k TOP VEW 16 666 600 0 160-PIN PQFP (EIA) #10 O00 OOO O 610 O00 OOO O FIO ODOONO0CO00O O E1O OOOCDONDC0O00O O INDEX C) 210 O0COO000000 Oo o ]OOO 000 0 Sa 5}O00 O00 AWODODOOOOCO0O00000 1 + a 1234 5 6 7 $ WN 2 BM Is PQFP PGA PIN NAME | TYPE PIN | NAME | TYPE PIN NAME | TYPE PIN NAME | TYPE 1(B3) GND ~ 41(C15} GND 81(Q.14) GND = 124(P2) GND ~ 2(A1) LD8 vO 42(A16) IRQ?" Oo 82(R16) vos1* 122(R1) vD7 v0 3(A2) LD9 vo 43(B16) IRQ6* Oo 83(R15) voso* 123(Q1} vD6 vO 4(A3) LD10 vO 44(C16} iRQS* Oo 84(R14) VAS* 124(P1) VD5 WO 5(F6) LD11 Te) 45(F11) IRQ4* oO 85(L11} VAI 125(L6) vD4 vO 6(E5) LD12 Te) 46(E12) IRQS" Oo 86(M12) VA2 126(M5) vb3 vO 7(A4) L013 vO 47(D16) iRQ2* O 87(R13) VA3 127(N1) vD2 me) 8(D5) LD14 vO 48(E13) IRa1 Oo 88(N12) vaa 128(M4) vo1 vO 9(A5) L015 Te) 49(E16) CRBIT13 Oo 89(R12) VAS 129(M1) vpo Me) 10(E6) GND 50(F12) GND 90(M11} GND ~ 130(L5) GND 11(A6) LAO. (PU) 51(F16) CRBIT12 O 91(R11) VAG 1 | qa1@t VDBEN* O 12(06) LAI PU) 52(F13) CRBIT11 Oo 92(N11) VA7 132(L4) VDDIR Oo 13(F7) LA2 PU) 53(G11) -NC- 93(L10) VA8 133(K6) AM5 14(A7) LAg PU) 54(G16) VINTCLR 94(R10) Vag 134(K1) AM4 15(D7) LA4 KPU) 55(G13) UAEN oO 95(N10) VA10 135(K4) AMS 16(E7) LAS KPU) 56(G12) SFAIL Oo 96(M10) VAI 138(K5) AM2 17(F8) LAG PU} 57(H11) SFINH* Oo 97(L9) VA12 137(J6) AMI 18(A8) LA7 (PU) 58(H16) VOTACK oO 98(R9) VA13 138(J1) AMO 19(D8) UASEL* oO 59(H13) GND 99(N9) VA14 139(J4) GND 20(E8) vec 60(H12) vec 100(M9) vec _ 140(J5) Vcc 21(F9) RST oO 61(J11) GND 101(L8) VA15 ' 141(H6) AUTOCFG \ 22(A9} DDSEL* Oo 62(J16) MODID ' 102(R8) VAI6 1 142(H1) INTL3 ! 23(D9) IDISEL* oO 63(J13) -NC- 103(NB) VA17 143(H4) INTL2 \ 24(E9) DTISEL oO 64(J12) -NC- 104(M8) VA18 144(H5) INTLI \ 25(F10) UACS* 65(K11) vec 105(L7) VA19 145(G6) HRDRST* \ 26(A10) VXVLCL" Oo 66(K16) -NC- 106(R7) VA20 146(G1) vec 27(D10) REGWR* 0 67(K13) VA31 107(N7) VA21 147(G4) SFTRST* O(H) 28(E10) REGRD* oO 68(K12) VA30 108(M7) VA22 148(G5) -NC- 29(D11) LDTACK* oO 69(L13) VA29 109(N6) VA23 149(F4) CLK 30(A11) GND 70(L16) GND 110(R6) GND ~ 150(F1} GND 31(E11) ics 74(L12) VA28 \ 111(M6) GND ~ 151(F5} vec 32(A12) LAW i 72(M16) VA27 \ 112(R5) VD15 vO 152(E1) LDo vO 33(D12) LAD6 \ 73(M13) VA26 \ 113(N5) vb14 vO 153(E4) LDt vO 34(A13) LADS ' 74(N16) VA25 \ 114(R4) vD13 vO 154(D1) LD2 re) 35(D13} LAD4 75(N13) VA24 115(N4) vD12 vo 155(D4) LD3 Te) 36(A14) LADS 76(P16) IACKIN* 116(R3) vDi1 vO 156(C1) LD4 vO 37(C14} LAD2 77(P14) IACK* 117(P3) vD10 vO 157(C3) LDS vo 38(A15) LADI 78(Q16) IACKOUT* om} 118(R2) vb9 vo 158(B1) LD6 vO 39(B15) -NC- 79(Q15) VWRITE* 119(Q2} vD8 vO 159(B2) LD7 vO 40(B14) vec = 80(P15) vec 120(Q3} VCC 160(C2) vec PIN: PQFP (PGA) | = Standard Input O = Standard Output (I,, = 3.2 mA, |,,, = -2 mA) (PU) = Input with Pullup O(M) = Medium Drive Output (I,, = 8 mA, |, = -2 mA) O(H) = High Drive Output (I,, = 24 mA, |, = -8 MA) \/O = Bidirectional (I,, = 3.2 mA, | OK = -2mA) +5V SYSCLK* Orr Pp CLK LAD] kK syst > Hirst? tAD2 | ~4 LADS. [4 taba -4 LADS. [-4 (ADS -4 Ag > > J] acted cs AME> > J aicsio> vA Pd AS -. oY . : . vyyicl!, - > WE CRD" REGISTER READ* : : REGWR REGISTER WRITE rr roar Bo DDSEL* DEVICE DEPENDENT SELECT cor OC [pf ox ET 1538 INTL<3:1> /d_srinu* E SYSFALL* SFALL (DISEL* Ly . 74F38 On = ACK > ACK | p4 = \ACKINS = > AKIN" RST Of2 P4 + eeu EEEE EEE EEEEEEEEeeneseees | & IACKOUT |ACKOUT" cea | y A % CRATI3. - Toad PS 3 UAEN [- x 4 Rag of b4 = Of p SFRST P r A MODID MODID ob 825 DISEL Tafa ID REGISTER SWITCHES QEI LDTACK" P Of? 6 P_ VDBEN' P A DR VOOR au D7> >S B A VD<15:0> OF] D 74F245 Of p LD<15:0> Y A 6b 7 DR LAe.0> 74F244 D<15:8> >& 8 A DEVICE TYPE REGISTER SWITCHES 74F 245 119010 L___ TO/FROM DEVICE DEPENDENT REGISTERS LOGICAL ADDRESS DIP SWITCH REGISTER-BASED INTERFACE SCHEMATIC EXAMPLE ORDERING INFORMATION IT9010-PQFP VXIntegrator 159-Pin Plastic Quad Flatpack. IT9010-PGA VXIntegrator PQFP Mounted on a 160-Pin Pin Grid Array Adaptor. interface TECHNOLOGY ace logo are registered trademarks of Interface Technology, Inc ia 91740 (818) 914-2741 FAX (818) 335-834 Form 1022 ub opze71 VK A Dynatech Company