Low Voltage 2.5V/3.3V Differential ECL/ PECL/HSTL Fanout Buffer MC100ES6111 DATA SHEET Low Voltage 2.5/3.3 V Differential ECL/ PECL/HSTL Fanout Buffer The MC100ES6111 is a bipolar monolithic differential clock fanout buffer. Designed for most demanding clock distribution systems, the MC100ES6111 supports various applications that require distribution of precisely aligned differential clock signals. Using SiGe:C technology and a fully differential architecture, the device offers very low skew outputs and superior digital signal characteristics. Target applications for this clock driver is high performance clock distribution in computing, networking and telecommunication systems. LOW-VOLTAGE 1:10 DIFFERENTIAL ECL/PECL/HSTL CLOCK FANOUT DRIVER Features * * * * * * * * * * * * 1:10 differential clock distribution 35 ps maximum device skew Fully differential architecture from input to all outputs SiGe:C technology supports near-zero output skew Supports DC to 2.7 GHz operation of clock or data signals ECL/PECL compatible differential clock outputs ECL/PECL/HSTL compatible differential clock inputs Single 3.3 V, -3.3 V, 2.5 V or -2.5 V supply Standard 32-lead LQFP package 32-lead Pb-free package available Industrial temperature range Pin and function compatible to the MC100EP111 FA SUFFIX 32-LEAD LQFP PACKAGE CASE 873A-04 AC SUFFIX 32-LEAD LQFP PACKAGE Pb-FREE PACKAGE CASE 873A-04 Functional Description The MC100ES6111 is designed for low skew clock distribution systems and supports clock frequencies up to 2.7 GHz. The device accepts two clock sources. The CLKA input can be driven by ECL or PECL compatible signals, the CLKB input accepts HSTL or PECL compatible signals. The selected input signal is distributed to 10 identical, differential ECL/PECL outputs. If VBB is connected to the CLKA input and bypassed to GND by a 10 nF capacitor, the MC100ES6111 can be driven by single-ended ECL/PECL signals utilizing the VBB bias voltage output. In order to meet the tight skew specification of the device, both outputs of a differential output pair should be terminated, even if only one output is used. In the case where not all ten outputs are used, the output pairs on the same package side as the parts being used on that side should be terminated. The MC100ES6111 can be operated from a single 3.3 V or 2.5 V supply. As most other ECL compatible devices, the MC100ES6111 supports positive (PECL) and negative (ECL) supplies. The MC100ES6111 is pin and function compatible to the MC100EP111. MPC100ES6111 REVISION 6 OCTOBER 1, 2009 1 (c)2009 Integrated Device Technology, Inc. Q4 Q4 Q5 Q5 Q6 Q6 17 16 VCC Q2 26 15 Q7 Q2 27 14 Q7 Q1 28 13 Q8 Q1 29 12 Q8 Q0 30 11 Q9 Q0 31 10 Q9 VCC 32 9 VCC MC100ES6111 1 2 3 4 5 6 7 8 VEE CLK_SEL 18 CLKB CLKB CLKB 19 CLKB 1 20 VBB VCC 21 CLKA 0 22 CLKA CLKA CLKA 23 25 CLK_SEL VCC 24 VCC VCC Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3 Q4 Q4 Q5 Q5 Q6 Q6 Q7 Q7 Q8 Q8 Q9 Q9 Q3 LOW VOLTAGE 2.5V/3.3V DIFFERENTIAL ECL/PECL/HSTL FANOUT BUFFER Q3 MPC100ES6111 Data Sheet VBB Figure 1. MC100ES6111 Logic Diagram Figure 2. 32-Lead Package Pinout (Top View) Table 1. Pin Configuration Pin I/O Type Function CLKA, CLKA Input ECL/PECL Differential reference clock signal input CLKB, CLKB Input HSTL/PECL Alternative differential reference clock signal input CLK_SEL Input ECL/PECL Active clock input select Q[0-9], Q[0-9] Output ECL/PECL Differential clock outputs VEE(1) Supply Negative power supply VCC Supply Positive power supply. All VCC pins must be connected to the positive power supply for correct DC and AC operation. VBB Output DC Reference voltage output for single ended ECL or PECL operation 1. In ECL mode (negative power supply mode), VEE is either -3.3 V or -2.5 V and VCC is connected to GND (0 V). In PECL mode (positive power supply mode), VEE is connected to GND (0 V) and VCC is either +3.3 V or +2.5 V. In both modes, the input and output levels are referenced to the most positive supply (VCC). Table 2. Function Table Control Default CLK_SEL 0 MPC100ES6111 REVISION 6 OCTOBER 1, 2009 0 1 CLKA, CLKA input pair is active. CLKA can be CLKB, CLKB input pair is active. CLKB can be driven by ECL or PECL compatible signals. driven by HSTL or PECL compatible signals. 2 (c)2009 Integrated Device Technology, Inc. MPC100ES6111 Data Sheet LOW VOLTAGE 2.5V/3.3V DIFFERENTIAL ECL/PECL/HSTL FANOUT BUFFER Table 3. Absolute Maximum Ratings(1) Symbol Characteristics Min Max Unit VCC Supply Voltage -0.3 3.6 V VIN DC Input Voltage -0.3 VCC + 0.3 V DC Output Voltage -0.3 VCC + 0.3 V DC Input Current 20 mA DC Output Current 50 mA -65 125 C TA = -40 TJ = +110 C VOUT IIN IOUT TS TFunc Storage Temperature Functional Temperature Range Condition 1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied. Table 4. General Specifications Symbol Characteristics Min Typ Unit VTT Output Termination Voltage MM ESD Protection (Machine Model) 200 V HBM ESD Protection (Human Body Model) 4000 V CDM ESD Protection (Charged Device Model) 2000 V 200 LU Latch-up Immunity CIN Input Capacitance JA Thermal resistance junction to ambient JESD 51-3, single layer test board VCC - Max 2(1) JC Thermal Resistance Junction to Case TJ Operating Junction Temperature(2) (Continuous Operation) MTBF = 9.1 years V mA 4.0 JESD 51-6, 2S2P multilayer test board Condition pF Inputs 83.1 73.3 68.9 63.8 57.4 86.0 75.4 70.9 65.3 59.6 C/W C/W C/W C/W C/W Natural convection 100 ft/min 200 ft/min 400 ft/min 800 ft/min 59.0 54.4 52.5 50.4 47.8 60.6 55.7 53.8 51.5 48.8 C/W C/W C/W C/W C/W Natural convection 100 ft/min 200 ft/min 400 ft/min 800 ft/min 23.0 26.3 C/W MIL-SPEC 883E Method 1012.1 110 C 1. Output termination voltage VTT = 0 V for VCC = 2.5 V operation is supported but the power consumption of the device will increase 2. Operating junction temperature impacts device life time. Maximum continuous operating junction temperature should be selected according to the application life time requirements (See application note AN1545 and the application section in this data sheet for more information). The device AC and DC parameters are specified up to 110C junction temperature allowing the MC100ES6111 to be used in applications requiring industrial temperature range. It is recommended that users of the MC100ES6111 employ thermal modeling analysis to assist in applying the junction temperature specifications to their particular application. MPC100ES6111 REVISION 6 OCTOBER 1, 2009 3 (c)2009 Integrated Device Technology, Inc. MPC100ES6111 Data Sheet LOW VOLTAGE 2.5V/3.3V DIFFERENTIAL ECL/PECL/HSTL FANOUT BUFFER Table 5. PECL/HSTL DC Characteristics (VCC = 2.5 V 5% or VCC = 3.3 V 5%, VEE = GND, TJ = 0C to +110C) Symbol Characteristics Min Typ Max Unit Condition Control Input CLK_SEL VIL Input Voltage Low VCC - 1.810 VCC - 1.475 V VIH Input Voltage High VCC - 1.165 VCC - 0.880 V 100 A VIN = VIL or VIN = VIH IIN Input Current(1) Clock Input Pair CLKA, CLKA (PECL differential signals) VPP VCMR IIN Differential Input Voltage(2) 0.1 1.3 V Differential operation Differential Cross Point Voltage(3) 1.0 VCC - 0.3 V Differential operation 100 A VIN = VIL or VIN = VIH Input Current(1) Clock Input Pair CLKB, CLKB (HSTL/PECL differential signals) VDIF Differential Input Voltage(4) VCC = 3.3 V VCC = 2.5 V VX Differential Cross Point Voltage(5) IIN Input Current 0.4 0.4 V V 0 0.68 - 0.9 VCC - 1.1 V 200 A VIN = VX 0.2 V PECL Clock Outputs (Q0-9, Q0-9) VOH Output High Voltage VOL Output Low Voltage VCC = 3.3 V5% VCC = 2.5 V5% VCC - 1.2 VCC - 1.005 VCC - 0.7 V IOH = -30 mA(6) VCC - 1.9 VCC - 1.9 VCC - 1.705 VCC - 1.705 VCC - 1.5 VCC - 1.3 V IOL = -5 mA(6) 100 mA VCC - 1.2 V Supply Current and VBB IEE Maximum Quiescent Supply Current without Output Termination Current(7) VBB Output Reference Voltage VCC - 1.4 VEE pin IBB = 200 A 1. Input have internal pullup/pulldown resistors which affect the input current. 2. VPP (DC) is the minimum differential input voltage swing required to maintain device functionality. 3. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR (DC) range and the input swing lies within the VPP (DC) specification. 4. VDIF (DC) is the minimum differential HSTL input voltage swing required for device functionality. 5. VX (DC) is the crosspoint of the differential HSTL input signal. Functional operation is obtained when the crosspoint is within the VX (DC) range and the input swing lies within the VPP (DC) specification. 6. Equivalent to a termination of 50 to VTT. 7. ICC calculation: ICC = (number of differential output pairs used) x (IOH + IOL) + IEE ICC = (number of differential output pairs used) x (VOH - VTT)/Rload + (VOL - VTT)/Rload + IEE MPC100ES6111 REVISION 6 OCTOBER 1, 2009 4 (c)2009 Integrated Device Technology, Inc. MPC100ES6111 Data Sheet LOW VOLTAGE 2.5V/3.3V DIFFERENTIAL ECL/PECL/HSTL FANOUT BUFFER Table 6. ECL DC Characteristics (VEE = -2.5 V 5% or VEE = -3.3 V 5%, VCC = GND, TJ = 0C to +110C) Symbol Characteristics Min Typ Max Unit Condition Control Input CLK_SEL VIL Input Voltage Low -1.810 -1.475 V VIH Input Voltage High -1.165 -0.880 V 100 A VIN = VIL or VIN = VIH 0.1 1.3 V Differential operation VEE + 1.0 -0.3 V Differential operation 100 A VIN = VIL or VIN = VIH IIN Input Current(1) Clock Input Pair CLKA, CLKA, CLKB, CLKB (ECL differential signals) VPP VCMR IIN Differential Input Voltage(2) Differential Cross Point Voltage(3) Input Current(1) ECL Clock Outputs (Q0-9, Q0-9) VOH Output High Voltage VOL Output Low Voltage VEE = -3.3 V 5% VEE = -2.5 V 5% -1.2 -1.005 -0.7 V IOH = -30 mA(4) -1.9 -1.9 -1.705 -1.705 -1.5 -1.3 V IOL = -5 mA(4) 100 mA VCC - 1.2 V Supply Current and VBB IEE Maximum Quiescent Supply Current without Output Termination Current(5) VBB Output Reference Voltage VCC - 1.4 VEE pin IBB = 200 A 1. Input have internal pullup/pulldown resistors which affect the input current. 2. VPP (DC) is the minimum differential input voltage swing required to maintain device functionality. 3. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR (DC) range and the input swing lies within the VPP (DC) specification. 4. Equivalent to a termination of 50 to VTT. 5. ICC calculation: ICC = (number of differential output pairs used) x (IOH + IOL) + IEE ICC = (number of differential output pairs used) x (VOH - VTT)/Rload + (VOL - VTT)/Rload + IEE MPC100ES6111 REVISION 6 OCTOBER 1, 2009 5 (c)2009 Integrated Device Technology, Inc. MPC100ES6111 Data Sheet LOW VOLTAGE 2.5V/3.3V DIFFERENTIAL ECL/PECL/HSTL FANOUT BUFFER Table 7. AC Characteristics (ECL: VEE = -3.3 V 5% or VEE = -2.5 V 5%, VCC = GND) or (HSTL/PECL: VCC = 3.3 V 5% or VCC = 2.5 V 5%, VEE = GND, TJ = 0C to +110C)(1) Symbol Characteristics Min Typ Max Unit Condition 0.15 1.3 V VEE + 1.0 VCC - 0.3 V 2.7 GHz Differential 530 ps Differential 1.0 V VEE + 2.1 V 2.7 GHz Differential Differential Clock Input Pair CLKA, CLKA (PECL or ECL differential signals) VPP VCMR Differential Input Voltage(2) (peak-to-peak) Differential Input Crosspoint Voltage (3) PECL (4) fCLK Input Frequency tPD Propagation Delay CLKA or CLKB to Q0-9 280 400 Clock Input Pair CLKB, CLKB (HSTL/PECL differential signals) VDIF VX Differential Input Voltage (peak-to-peak)(5) Differential Input Crosspoint Voltage fCLK Input Frequency tPD Propagation Delay CLKB to Q0-9 0.4 (6) VEE + 0.1 VEE + 0.68 VEE + 0.9 280 400 530 ps 0.45 0.3 0.18 0.72 0.55 0.37 0.95 0.95 0.95 V V V ECL Clock Outputs (Q0-9, Q0-9) VO(P-P) Differential Output Voltage (peak-to-peak) fO < 300 MHz fO < 1.5 GHz fO < 2.7 GHz tsk(O) Output-to-Output Skew 35 ps Differential tsk(PP) Output-to-Output Skew (part-to-part) fO < 1.5 GHz fO > 1.5 GHz 150 250 ps ps Differential tJIT(CC) Output Cycle-to-Cycle Jitter tsk(P) Output Pulse Skew(7) tr, tf Output Rise/Fall Time RMS (1) 0.05 1 ps 75 ps 0.3 ns 20% to 80% 1. AC characteristics apply for parallel output termination of 50 to VTT. 2. VPP (AC) is the minimum differential ECL/PECL input voltage swing required to maintain AC characteristics including tpd and device-to-device skew. 3. VCMR (AC) is the crosspoint of the differential ECL/PECL input signal. Normal AC operation is obtained when the crosspoint is within the VCMR (AC) range and the input swing lies within the VPP (AC) specification. Violation of VCMR (AC) or VPP (AC) impacts the device propagation delay, device and part-to-part skew. 4. The MC100ES6111 is fully operational up to 3.0 GHz and is characterized up to 2.7 GHz. 5. VDIF (AC) is the minimum differential HSTL input voltage swing required to maintain AC characteristics including tPD and device-to-device skew. 6. VX (AC) is the crosspoint of the differential HSTL input signal. Normal AC operation is obtained when the crosspoint is within the VX (AC) range and the input swing lies within the VDIF (AC) specification. Violation of VX (AC) or VDIF (AC) impacts the device propagation delay, device and part-to-part skew. 7. Output pulse skew is the absolute difference of the propagation delay times: | tPLH - tPHL |. Differential Pulse Generator Z = 50 ZO = 50 RT = 50 ZO = 50 DUT MC100ES6111 RT = 50 VTT = GND VTT = GND Figure 3. MC100ES6111 AC Test Reference MPC100ES6111 REVISION 6 OCTOBER 1, 2009 6 (c)2009 Integrated Device Technology, Inc. MPC100ES6111 Data Sheet LOW VOLTAGE 2.5V/3.3V DIFFERENTIAL ECL/PECL/HSTL FANOUT BUFFER APPLICATIONS INFORMATION Understanding the Junction Temperature Range of the MC100ES6111 To make the optimum use of high clock frequency and low skew capabilities of the MC100ES6111, the MC100ES6111 is specified, characterized and tested for the junction temperature range of TJ = 0C to +110C. Because the exact thermal performance depends on the PCB type, design, thermal management and natural or forced air convection, the junction temperature provides an exact way to correlate the application specific conditions to the published performance data of this data sheet. The correlation of the junction temperature range to the application ambient temperature range and vice versa can be done by calculation: TJ = TA + Rthja Ptot Maintaining Lowest Device Skew The MC100ES6111 guarantees low output-to-output bank skew of 35 ps and a part-to-part skew of max. 250 ps. To ensure low skew clock signals in the application, both outputs of any differential output pair need to be terminated identically, even if only one output is used. When fewer than all nine output pairs are used, identical termination of all output pairs within the output bank is recommended. If an entire output bank is not used, it is recommended to leave all of these outputs open and unterminated. This will reduce the device power consumption while maintaining minimum output skew. Power Supply Bypassing The MC100ES6111 is a mixed analog/digital product. The differential architecture of the MC100ES6111 supports low noise signal operation at high frequencies. In order to maintain its superior signal quality, all VCC pins should be bypassed by high-frequency ceramic capacitors connected to GND. If the spectral frequencies of the internally generated switching noise on the supply pins cross the series resonant point of an individual bypass capacitor, its overall impedance begins to look inductive and thus increases with increasing frequency. The parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the noise bandwidth. Assuming a thermal resistance (junction to ambient) of 54.4C/W (2s2p board, 200 ft/min airflow, see Table 4) and a typical power consumption of 610 mW (all outputs terminated 50 ohms to VTT, VCC = 3.3 V, frequency independent), the junction temperature of the MC100ES6111 is approximately TA + 33C, and the minimum ambient temperature in this example case calculates to -33C (the maximum ambient temperature is 77C, see Table 8). Exceeding the minimum junction temperature specification of the MC100ES6111 does not have a significant impact on the device functionality. However, the continuous use of the MC100ES6111 at high ambient temperatures requires thermal management to not exceed the specified maximum junction temperature. Please see the Freescale application note AN1545 for a power consumption calculation guideline. VCC Table 8 . Ambient Temperature Range (Ptot = 610 mW) Rthja (2s2p board) TA, Min(1) TA, Max Natural convection 59.0C/W -36C 74C 100 ft/min 54.4C/W -33C 77C 200 ft/min 52.5C/W -32C 78C 400 ft/min 50.4C/W -30C 79C 800 ft/min 47.8C/W -29C 81C VCC 33...100 nF 0.1 nF MC100ES6111 Figure 4. VCC Power Supply Bypass 1. The MC100ES6111 device function is guaranteed from TA = -40C to TJ = 110C MPC100ES6111 REVISION 6 OCTOBER 1, 2009 7 (c)2009 Integrated Device Technology, Inc. MPC100ES6111 Data Sheet LOW VOLTAGE 2.5V/3.3V DIFFERENTIAL ECL/PECL/HSTL FANOUT BUFFER PACKAGE DIMENSIONS PAGE 1 OF 3 CASE 873A-04 ISSUE C 32-LEAD LQFP PACKAGE MPC100ES6111 REVISION 6 OCTOBER 1, 2009 8 (c)2009 Integrated Device Technology, Inc. MPC100ES6111 Data Sheet LOW VOLTAGE 2.5V/3.3V DIFFERENTIAL ECL/PECL/HSTL FANOUT BUFFER PACKAGE DIMENSIONS PAGE 2 OF 3 CASE 873A-04 ISSUE C 32-LEAD LQFP PACKAGE MPC100ES6111 REVISION 6 OCTOBER 1, 2009 9 (c)2009 Integrated Device Technology, Inc. MPC100ES6111 Data Sheet LOW VOLTAGE 2.5V/3.3V DIFFERENTIAL ECL/PECL/HSTL FANOUT BUFFER PACKAGE DIMENSIONS PAGE 3 OF 3 CASE 873A-04 ISSUE C 32-LEAD LQFP PACKAGE MPC100ES6111 REVISION 6 OCTOBER 1, 2009 10 (c)2009 Integrated Device Technology, Inc. MPC100ES6111 Data Sheet 6024 Silver Creek Valley Road San Jose, California 95138 LOW VOLTAGE 2.5V/3.3V DIFFERENTIAL ECL/PECL/HSTL FANOUT BUFFER Sales 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT Technical Support netcom@idt.com +480-763-2056 DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT's sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT's products are not intended for use in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. Copyright 2009. All rights reserved.