512MB, 1GB, 2GB Registered DIMM DDR SDRAM DDR SDRAM Registered Module 184pin Registered Module based on 512Mb B-die with 72-bit ECC 66 TSOP-II and 60 ball FBGA INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND. 1. For updates or additional information about Samsung products, contact your nearest Samsung office. 2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where Product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. * Samsung Electronics reserves the right to change products or specification without notice. Rev. 1.0 June 2005 512MB, 1GB, 2GB Registered DIMM DDR SDRAM Table of Contents 1.0 Ordering Information................................................................................................................... 4 2.0 Operating Frequencies................................................................................................................ 4 3.0 Feature.......................................................................................................................................... 4 4.0 Pin Configuration (Front side/back side) ................................................................................. 5 5.0 Pin Description ............................................................................................................................ 5 6.0 Functional Block Diagram .......................................................................................................... 6 6.1 512MB, 64M x 72 ECC Module (M312L6523BT(U)S)........................................................................... 6 6.2 1GB, 128M x 72 ECC Module (M312L2923BT(U)S)............................................................................ 7 6.3 1GB, 128M x 72 ECC Module (M312L2920BT(U)S)............................................................................ 8 6.4 2GB, 256M x 72 ECC Module (M312L5628BT(U)0) ............................................................................ 9 6.5 512MB, 64M x 72 ECC Module (M312L6523BG(Z)0)....................................................................................... 10 6.6 1GB, 128M x 72 ECC Module (M312L2923BG(Z)0) .......................................................................... 11 6.7 1GB, 128M x 72 ECC Module (M312L2920BG(Z)0)......................................................................................... 12 6.8 2GB, 256M x 72 ECC Module (M312L5720BG(Z)0)......................................................................................... 13 7.0 Absolute Maximum Ratings...................................................................................................... 14 8.0 Power & DC Operating Conditions (SSTL_2 In/Out) .............................................................. 14 9.0 DDR SDRAM IDD spec table ..................................................................................................... 15 9.1 M312L6523BT(U)S [ (64M x 8) * 9 , 512MB Module ]........................................................................ 15 9.2 M312L2923BT(U)S [ (64M x 8) * 18 , 1GB Module ] .......................................................................... 15 9.3 M312L2920BT(U)S [ (128M x 4) * 18 , 1GB Module ] ....................................................................................... 16 9.4 M312L5628BT(U)0 [ (st.256M x 4) * 18 , 2GB Module ] ..................................................................... 16 9.5 M312L6523BG(Z)0 [ (64M x 8) * 9 , 512MB Module ] ...................................................................................... 17 9.6 M312L2923BG(Z)0 [ (64M x 8) * 18 , 1GB Module ].......................................................................... 17 9.7 M312L2920BG(Z)0 [ (128M x 4) * 18 , 1GB Module ] ......................................................................... 18 9.8 M312L5720BG(Z)0 [ (128M x 4) * 36, 2GB Module ].......................................................................... 18 10.0 AC Operating Conditions........................................................................................................ 19 11.0 Input/Output Capacitance ....................................................................................................... 19 12.0 AC Timming Parameters & Specifications ............................................................................ 20 13.0 System Characteristics for DDR SDRAM .............................................................................. 21 14.0 Component Notes.................................................................................................................... 22 15.0 System Notes ........................................................................................................................... 23 16.0 Command Truth Table............................................................................................................. 24 17.0 Physical Dimensions............................................................................................................... 25 17.1 64M x 72 (M312L6523BT(U)S) .................................................................................................... 25 17.2 128Mx72 (M312L2923BT(U)S), 128Mx72 (M312L2920BT(U)S) ......................................................... 26 17.3 st.256Mx72 (M312L5628BT(U)0) ................................................................................................. 27 17.4 64Mx72 (M312L6523BG(Z)0) ...................................................................................................... 28 17.5 128Mx72 (M312L2923BG(Z)0), (M312L2920BG(Z)0) ...................................................................... 29 17.6 256Mx72 (M312L5720BG(Z)0) .................................................................................................... 30 Rev. 1.0 June 2005 512MB, 1GB, 2GB Registered DIMM DDR SDRAM Revision History Revision Month Year 1.0 June 2005 History - Merged TSOP and FBGA based RDIMM, Deleted 1.7" Height DIMM Rev. 1.0 June 2005 512MB, 1GB, 2GB Registered DIMM DDR SDRAM 184Pin Registered DIMM based on 512Mb B-die (x4, x8) 1.0 Ordering Information Part Number Density Organization Component Composition Height M312L6523BT(U)S-CA2/B0 512MB 64M x 72 64Mx8( K4H510838B) * 9EA 1,200mil M312L2923BT(U)S-CA2/B0 1GB 128M x 72 64Mx8( K4H510838B) * 18EA 1,200mil M312L2920BT(U)S-CA2/B0 1GB 128M x 72 128Mx4( K4H510438B) * 18EA 1,200mil M312L5628BT(U)0-CA2/B0 2GB 256M x 72 st.256Mx4( K4H1G0638B) * 18EA 1,200mil M312L6523BG(Z)0-CCC/B3 512MB 64Mx72 64Mx8( K4H510838B) * 9EA 1,125mil M312L2923BG(Z)0-CCC/B3 1GB 128M x 72 64Mx8( K4H510838B) * 18EA 1,125mil M312L2920BG(Z)0-CCC/B3 1GB 128M x 72 128Mx4( K4H510438B) * 18EA 1,125mil M312L5720BG(Z)0-CCC/B3 2GB 256M x 72 128Mx4( K4H510438B) * 36EA 1,200mil Note : Leaded and Lead-free(Pb-free) can be discriminated by PKG P/N (T : 66 TSOP with Leaded, U : 66 TSOP with Lead-free) (G : 60 FBGA with Leaded, Z : 60 FBGA with Lead-free) 2.0 Operating Frequencies CC(DDR400@CL=3) B3(DDR333@CL=2.5) A2(DDR266@CL=2) B0(DDR266@CL=2.5) - 133MHz 133MHz 100MHz Speed @CL2.5 166MHz 166MHz 133MHz 133MHz Speed @CL3 200MHz - - - CL-tRCD-tRP 3-3-3 2.5-3-3 2-3-3 2.5-3-3 Speed @CL2 3.0 Feature * VDD : 2.5V 0.2V, VDDQ : 2.5V 0.2V for DDR266, 333 * VDD : 2.6V 0.1V, VDDQ : 2.6V 0.1V for DDR400 * Double-data-rate architecture; two data transfers per clock cycle * Bidirectional data strobe [DQ] (x4,x8) & [L(U)DQS] (x16) * Differential clock inputs(CK and CK) * DLL aligns DQ and DQS transition with CK transition * Programmable Read latency : DDR266(2, 2.5 Clock), DDR333(2.5 Clock), DDR400(3 Clock) * Programmable Burst length (2, 4, 8) * Programmable Burst type (sequential & interleave) * Edge aligned data output, center aligned data input * Auto & Self refresh, 7.8us refresh interval(8K/64ms refresh) * Serial presence detect with EEPROM * SSTL_2 Interface * 66pin TSOP II and 60 ball FBGA (Leaded & Pb-Free(RoHS compliant)) package Rev. 1.0 June 2005 512MB, 1GB, 2GB Registered DIMM DDR SDRAM 4.0 Pin Configuration (Front side/back side) Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Front VREF DQ0 VSS DQ1 DQS0 DQ2 VDD DQ3 NC RESET VSS DQ8 DQ9 DQS1 VDDQ *CK1 *CK1 VSS DQ10 DQ11 CKE0 VDDQ DQ16 DQ17 DQS2 VSS A9 DQ18 A7 VDDQ DQ19 Pin 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 Front A5 DQ24 VSS DQ25 DQS3 A4 VDD DQ26 DQ27 A2 VSS A1 CB0 CB1 VDD DQS8 A0 CB2 VSS CB3 BA1 KEY DQ32 VDDQ DQ33 DQS4 DQ34 VSS BA0 DQ35 DQ40 Pin 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 Front VDDQ WE DQ41 CAS VSS DQS5 DQ42 DQ43 VDD *CS2 DQ48 DQ49 VSS *CK2 *CK2 VDDQ DQS6 DQ50 DQ51 VSS VDDID DQ56 DQ57 VDD DQS7 DQ58 DQ59 VSS NC SDA SCL Pin 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 Back VSS DQ4 DQ5 VDDQ DM0/DQS9 DQ6 DQ7 VSS NC NC NC VDDQ DQ12 DQ13 DM1/DQS10 VDD DQ14 DQ15 CKE1 VDDQ *BA2 DQ20 A12 VSS DQ21 A11 DM2/DQS11 VDD DQ22 A8 DQ23 Pin 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 Back VSS A6 DQ28 DQ29 VDDQ DM3/DQS12 A3 DQ30 VSS DQ31 CB4 CB5 VDDQ CK0 CK0 VSS DM8/DQS17 A10 CB6 VDDQ CB7 KEY VSS DQ36 DQ37 VDD DM4/DQS13 DQ38 DQ39 VSS DQ44 Pin 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 Back RAS DQ45 VDDQ CS0 CS1 DM5/DQS14 VSS DQ46 DQ47 *CS3 VDDQ DQ52 DQ53 *A13 VDD DM6/DQS15 DQ54 DQ55 VDDQ NC DQ60 DQ61 VSS DM7/DQS16 DQ62 DQ63 VDDQ SA0 SA1 SA2 VDDSPD Note : 1. * : These pins are not used in this module. 2. Pins 111, 158 are NC for 1row module & used for 2row module. 3. Pins 97, 107, 119, 129, 140, 149, 159, 169, 177 : DM (x8 base module) or DQS (x4 base module). 5.0 Pin Description Pin Name Function A0 ~ A12 Address input (Multiplexed) BA0 ~ BA1A Bank Select Address DQ0 ~ DQ63 Data input/output DQS0 ~ DQS17 Data Strobe input/output Pin Name DM0 ~ DM8 Function Data - in mask VDD Power supply (2.5V for DDR266/333, 2.6V for DDR400) VDDQ Power Supply for DQS (2.5V for DDR266/333, 2.6V for DDR400) VSS VREF Ground CK0,CK0 ~ CK2, CK2 Clock input CKE0, CKE1(for double banks) Clock enable input CS0, CS1(for double banks) Chip select input SDA Serial data I/O RAS Row address strobe SCL Serial clock VDDSPD Power supply for reference Serial EEPROM Power/Supply ( 2.3V to 3.6V ) CAS Column address strobe SA0 ~ 2 Address in EEPROM WE Write enable VDDID VDD, VDDQ level detection CB0 ~ CB7 Check bit(Data-in/data-out) NC No connection Note : VDDID defines relationship of VDD and VDDQ, and the default status of it is open (VDD=VDDQ) Rev. 1.0 June 2005 512MB, 1GB, 2GB Registered DIMM DDR SDRAM 6.0 Functional Block Diagram 6.1 512MB, 64M x 72 ECC Module (M312L6523BT(U)S) (Populated as 1 bank of x8 DDR SDRAM Module) RCS0 DQS0 DM0 DQS4 DM4 DM/ DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CS I/O 7 I/O 5 I/O 2 I/O 0 I/O 6 I/O 4 I/O 3 I/O 1 DM/ DQS DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 D0 DQS1 DM1 I/O 0 I/O 2 I/O 5 I/O 7 I/O 1 I/O 3 I/O 4 I/O 6 CS DQS D4 DQS5 DM5 DM/ DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 CS I/O 0 I/O 2 I/O 5 I/O 7 I/O 1 I/O 3 I/O 4 I/O 6 DQS DM/ DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 D1 DQS2 DM2 I/O 7 I/O 4 I/O 2 I/O 0 I/O 6 I/O 5 I/O 3 I/O 1 CS DQS D5 DQS6 DM6 DM/ DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 CS I/O 6 I/O 5 I/O 3 I/O 1 I/O 7 I/O 4 I/O 2 I/O 0 DQS DM/ DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 D2 DQS3 DM3 I/O 0 I/O 2 I/O 5 I/O 7 I/O 1 I/O 3 I/O 4 I/O 6 CS DQS D6 DQS7 DM7 DM/ DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 CS I/O 0 I/O 2 I/O 5 I/O 6 I/O 1 I/O 3 I/O 4 I/O 7 DQS DM/ DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 D3 I/O 6 I/O 4 I/O 2 I/O 0 I/O 7 I/O 5 I/O 3 I/O 1 DQS8 DM8 DM/ CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 CS I/O 5 I/O 4 I/O 2 I/O 0 I/O 7 I/O 6 I/O 3 I/O 1 DQS CS DQS Serial PD D7 SCL SDA WP A0 A1 A2 SA0 SA1 SA2 VDDSPD SPD VDD/VDDQ D0 - D8 D8 D0 - D8 VREF D0 - D8 VSS D0 - D8 PLL* CK0,CK0 * Wire per Clock Loading table/wiring Diagrams CS0 BA0-BA1 A0-A12 RAS CAS CKE0 WE PCK R E G I S T E R RCS0 RBA0 - RBA1 RA0 - RA12 RRAS RCAS RCKE0 RWE BA0 -BA1 : SDRAMs DQ0 - D8 A0 -A12 : SDRAMs D0 - D8 RAS : SDRAMs D0 - D8 CAS : SDRAMs D0 - D8 CKE : SDRAMs D0 - D8 WE: SDRAMs D0 - D8 Notes: 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. DQ/DQS/DM/CKE/CS relationships must be maintained as shown. 3. DQ, DQS, DM/DQS resistors: 22 Ohms. RESET PCK Rev. 1.0 June 2005 512MB, 1GB, 2GB Registered DIMM DDR SDRAM 6.2 1GB, 128M x 72 ECC Module (M312L2923BT(U)S) (Populated as 2 bank of x8 DDR SDRAM Module) RCS1 RCS0 DQS0 DM0 DQS4 DM4 DM/ DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CS I/O 7 I/O 5 I/O 2 I/O 0 I/O 6 I/O 4 I/O 3 I/O 1 DM/ DQS I/O 0 I/O 2 I/O 5 I/O 7 I/O 1 I/O 3 I/O 4 I/O 6 D0 CS DQS DM/ DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 D9 DQS1 DM1 I/O 7 I/O 5 I/O 2 I/O 0 I/O 6 I/O 4 I/O 3 I/O 1 CS DQS DM/ I/O 0 I/O 2 I/O 5 I/O 7 I/O 1 I/O 3 I/O 4 I/O 6 D4 CS DQS D13 DQS5 DM5 DM/ DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 CS I/O 7 I/O 5 I/O 2 I/O 0 I/O 6 I/O 4 I/O 3 I/O 1 DQS DM/ I/O 0 I/O 2 I/O 5 I/O 7 I/O 1 I/O 3 I/O 4 I/O 6 D1 CS DQS DM/ DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 D10 DQS2 DM2 I/O 7 I/O 4 I/O 2 I/O 0 I/O 6 I/O 5 I/O 3 I/O 1 CS DQS DM/ I/O 0 I/O 3 I/O 5 I/O 7 I/O 1 I/O 2 I/O 4 I/O 6 D5 CS DQS D14 DQS6 DM6 DM/ DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 CS I/O 6 I/O 5 I/O 3 I/O 1 I/O 7 I/O 4 I/O 2 I/O 0 DQS DM/ I/O 1 I/O 2 I/O 4 I/O 6 I/O 0 I/O 3 I/O 5 I/O 7 D2 CS DQS DM/ DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 D11 DQS3 DM3 I/O 7 I/O 5 I/O 2 I/O 0 I/O 6 I/O 4 I/O 3 I/O 1 CS DQS DM/ I/O 0 I/O 2 I/O 5 I/O 7 I/O 1 I/O 3 I/O 4 I/O 6 D6 CS DQS D15 DQS7 DM7 DM/ DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 CS I/O 7 I/O 5 I/O 2 I/O 1 I/O 6 I/O 4 I/O 3 I/O 0 DQS DM/ I/O 0 I/O 2 I/O 5 I/O 6 I/O 1 I/O 3 I/O 4 I/O 7 D3 CS DM/ DQS D12 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 I/O 6 I/O 4 I/O 2 I/O 0 I/O 7 I/O 5 I/O 3 I/O 1 CS DQS D7 DM/ I/O 1 I/O 3 I/O 5 I/O 7 I/O 0 I/O 2 I/O 4 I/O 6 CS DQS D16 DQS8 DM8 DM/ CS I/O 5 I/O 4 I/O 2 I/O 0 I/O 7 I/O 6 I/O 3 I/O 1 CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 DQS DM/ I/O 2 I/O 3 I/O 5 I/O 7 I/O 0 I/O 1 I/O 4 I/O 6 D8 CS DQS D17 Serial PD SCL SDA WP A0 A1 SA0 CS0 CS1 BA0-BA1 A0-A12 RAS CAS CKE0 CKE1 WE PCK R E G I S T E R SA1 VDDSPD SPD VDD/VDDQ D0 - D17 D0 - D17 A2 VREF D0 - D17 VSS D0 - D17 SA2 RCS0 RCS1 RBA0 - RBA1 RA0 - RA12 RRAS RCAS RCKE0 RCKE1 RWE RESET BA0 -BA1 : SDRAMs DQ0 - D17 A0 -A12 : SDRAMs D0 - D17 RAS : SDRAMs D0 - D17 CAS : SDRAMs DQ0 - D17 CKE : SDRAMs D0 - D8 CKE : SDRAMs D9 - D17 WE: SDRAMs D0 - D17 PLL* CK0,CK0 * Wire per Clock Loading table/wiring Diagrams Notes: 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. DQ/DQS/DM/CKE/CS relationships must be maintained as shown. 3. DQ, DQS, DM/DQS resistors: 22 Ohms. PCK Rev. 1.0 June 2005 512MB, 1GB, 2GB Registered DIMM DDR SDRAM 6.3 1GB, 128M x 72 ECC Module (M312L2920BT(U)S) (Populated as 1 bank of x4 DDR SDRAM Module) VSS RCS0 DQS0 DQ0 DQ1 DQ2 DQ3 DQS I/O 3 I/O 2 I/O 1 I/O 0 DQ8 DQ9 DQ10 DQ11 DQS I/O 3 I/O 2 I/O 1 I/O 0 DQ16 DQ17 DQ18 DQ19 DQS I/O 3 I/O 2 I/O 1 I/O 0 DQ24 DQ25 DQ26 DQ27 DQS I/O 3 I/O 2 I/O 1 I/O 0 DQ32 DQ33 DQ34 DQ35 DQS I/O 3 I/O 2 I/O 1 I/O 0 DQ40 DQ41 DQ42 DQ43 DQS I/O 3 I/O 2 I/O 1 I/O 0 DQ48 DQ49 DQ50 DQ51 DQS I/O 3 I/O 2 I/O 1 I/O 0 DQ56 DQ57 DQ58 DQ59 DQS I/O 3 I/O 2 I/O 1 I/O 0 CS DM D0 DQS1 CS DM CS DM CS DM CS DM CS DM CS DM CS DM DQS I/O 3 I/O 2 I/O 1 I/O 0 CS D8 DM DQS I/O 0 I/O 1 I/O 2 I/O 3 D11 DQ28 DQ29 DQ30 DQ31 DQS I/O 0 I/O 1 I/O 2 I/O 3 D12 DQ36 DQ37 DQ38 DQ39 DQS I/O 0 I/O 1 I/O 2 I/O 3 D13 DQ44 DQ45 DQ46 DQ47 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQ52 DQ53 DQ54 DQ55 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQ60 DQ61 DQ62 DQ63 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS16 (DM7) D7 DQS8 DQ20 DQ21 DQ22 DQ23 DQS15 (DM6) D6 DQS7 D10 DQS14 (DM5) D5 DQS6 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS13 (DM4) D4 DQS5 DQ12 DQ13 DQ14 DQ15 DQS12 (DM3) D3 DQS4 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS11 (DM2) D2 DQS3 DQ4 DQ5 DQ6 DQ7 DQS10 (DM1) D1 DQS2 CB0 CB1 CB2 CB3 DQS9 (DM0) DQS17 (DM8) CS DM D9 CS CS CS CS CS DM DM DM DM DM D14 CS Serial PD DM SCL D15 CS DM DQS I/O 0 I/O 1 I/O 2 I/O 3 A0 A1 A2 SA0 SA1 SA2 D16 VDDSPD VDD/VDDQ CB4 CB5 CB6 CB7 SDA WP CS DM SPD D0 - D17 D0 - D17 D17 VREF VSS D0 - D17 D0 - D17 Strap: see Note 4 S0 BA0-BA1 A0-A12 RAS CAS CKE0 WE PCK PCK R E G I S T E R PLL* CK0,CK0 * Wire per Clock Loading table/wiring Diagrams RS0 RBA0 - RBA1 BA0 -BA1 : SDRAMs DQ0 - D17 RA0 - RA12 A0 -A12 : SDRAMs D0 - D17 RRAS RAS : SDRAMs D0 - D17 RCAS CAS : SDRAMs DQ0 - D17 RCKE0 CKE : SDRAMs D0 - D17 RWE WE: SDRAMs D0 - D17 Notes: 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. DQ/DQS/DM/CKE/S relationships must be maintained as shown. 3. DQ, DQS, DM resistors: 22 Ohms. RESET Rev. 1.0 June 2005 512MB, 1GB, 2GB Registered DIMM DDR SDRAM 6.4 2GB, 256M x 72 ECC Module (M312L5628BT(U)0) (Populated as 2 bank of x4 DDR SDRAM Module) VSS RCS1 RCS0 DM0/DQS9 DQS0 CS DQ0 DQ1 DQ2 DQ3 DQS I/O 3 I/O 2 I/O 1 I/O 0 CS DQ8 DQ9 DQ10 DQ11 DQS I/O 3 I/O 2 I/O 1 I/O 0 CS DQ16 DQ17 DQ18 DQ19 DQS I/O 3 I/O 2 I/O 1 I/O 0 CS DQ24 DQ25 DQ26 DQ27 DQS I/O 3 I/O 2 I/O 1 I/O 0 CS DQ32 DQ33 DQ34 DQ35 DQS I/O 3 I/O 2 I/O 1 I/O 0 CS DQ40 DQ41 DQ42 DQ43 DQS I/O 3 I/O 2 I/O 1 I/O 0 DQS I/O 3 I/O 2 I/O 1 I/O 0 CS DQ48 DQ49 DQ50 DQ51 CS DQ56 DQ57 DQ58 DQ59 DQS I/O 3 I/O 2 I/O 1 I/O 0 CB0 CB1 CB2 CB3 DQS I/O 3 I/O 2 I/O 1 I/O 0 CS DM D0 DQS I/O 3 I/O 2 I/O 1 I/O 0 CS DM D18 DQS1 D1 DQS I/O 3 I/O 2 I/O 1 I/O 0 CS D19 D2 DQS I/O 3 I/O 2 I/O 1 I/O 0 CS DQS I/O 0 I/O 1 I/O 2 I/O 3 D10 DQ20 DQ21 DQ22 DQ23 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQ28 DQ29 DQ30 DQ31 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQ36 DQ37 DQ38 DQ39 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQ44 DQ45 DQ46 DQ47 DQS I/O 0 I/O 1 I/O 2 I/O 3 D14 DQ52 DQ53 DQ54 DQ55 DQS I/O 0 I/O 1 I/O 2 I/O 3 D15 DQ60 DQ61 DQ62 DQ63 DQS I/O 0 I/O 1 I/O 2 I/O 3 D16 CB4 CB5 CB6 CB7 DQS I/O 3 I/O 2 I/O 1 I/O 0 D17 DM D20 DM DQS I/O 0 I/O 1 I/O 2 I/O 3 D27 DQS I/O 0 I/O 1 I/O 2 I/O 3 D28 CS DM CS DM CS DM CS DM D11 DQS I/O 0 I/O 1 I/O 2 I/O 3 CS DM D29 DM3/DQS12 DM D3 DQS I/O 3 I/O 2 I/O 1 I/O 0 CS DM D21 CS DM D12 DQS I/O 0 I/O 1 I/O 2 I/O 3 CS DM D30 DM4/DQS13 DM D4 DQS I/O 3 I/O 2 I/O 1 I/O 0 CS DM D22 DQS5 CS DM D13 DQS I/O 0 I/O 1 I/O 2 I/O 3 CS DM D31 DM5/DQS14 DM D5 DQS I/O 3 I/O 2 I/O 1 I/O 0 CS DM D23 DQS6 CS DM DQS I/O 0 I/O 1 I/O 2 I/O 3 D32 DQS I/O 0 I/O 1 I/O 2 I/O 3 D33 CS DM DM6/DQS15 DM D6 DQS I/O 3 I/O 2 I/O 1 I/O 0 CS DM D24 DQS7 CS DM CS DM DM7/DQS16 DM D7 DQS I/O 3 I/O 2 I/O 1 I/O 0 CS DM D25 DQS8 CS DM DQS I/O 0 I/O 1 I/O 2 I/O 3 D34 DQS I/O 3 I/O 2 I/O 1 I/O 0 D35 CS DM DM8/DQS17 DM D8 DQS I/O 3 I/O 2 I/O 1 I/O 0 CS DM D26 VDDSPD Serial PD VDD/VDDQ SCL SDA WP PCK DQ12 DQ13 DQ14 DQ15 CS DM2/DQS11 DM DQS4 WE D9 DM DQS3 CS1 BA0-BA1 A0-A12 RAS CAS CKE0 CKE1 DQS I/O 0 I/O 1 I/O 2 I/O 3 DM1/DQS10 DM DQS2 CS0 DQ4 DQ5 DQ6 DQ7 R E G I S T E R RCS0 RCS1 RBA0 - RBA1 RA0 - RA12 VREF D0 - D35 SA0 SA1 SA2 VSS D0 - D35 RAS: SDRAMs D0 - D35 CAS: SDRAMs D0 - D35 CKE: SDRAMs D0 - D17 RWE CKE: SDRAMs D18 - D35 WE: SDRAMs D0 - D35 DM D0 - D35 A2 RRAS CS SPD A1 BA0-BAn: SDRAMs D0 - D35 A0-An: SDRAMs D0 - D35 DM D0 - D35 A0 RCAS RCKE0 RCKE1 CS CK0,CK0 PLL Notes: 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. DQ/DQS/DM/CKE/CS relationships must be maintained as shown. 3. DQ, DQS, DM/DQS resistors: 22 Ohms. RESET PCK Rev. 1.0 June 2005 512MB, 1GB, 2GB Registered DIMM DDR SDRAM 6.5 512MB, 64M x 72 ECC Module (M312L6523BG(Z)0) (Populated as 1 bank of x8 DDR SDRAM Module) RCS0 DQS0 DM0 DQS4 DM4 DM I/O 0 I/O 2 I/O 4 I/O 7 I/O 3 I/O 1 I/O 6 I/O 5 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CS DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DM I/O 7 I/O 5 I/O 3 I/O 0 I/O 4 I/O 6 I/O 1 I/O 2 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DM I/O 7 I/O 5 I/O 3 I/O 0 I/O 4 I/O 6 I/O 1 I/O 2 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DM I/O 7 I/O 5 I/O 3 I/O 0 I/O 4 I/O 6 I/O 1 I/O 2 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DM I/O 0 I/O 2 I/O 4 I/O 7 I/O 3 I/O 1 I/O 6 I/O 5 DQS D0 CS DQS D4 DQS5 DM5 DQS1 DM1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DM I/O 0 I/O 2 I/O 4 I/O 7 I/O 3 I/O 1 I/O 6 I/O 5 CS DQS D1 CS DQS D5 DQS6 DM6 DQS2 DM2 DM I/O 7 I/O 5 I/O 3 I/O 0 I/O 4 I/O 6 I/O 1 I/O 2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 CS DQS D2 CS DQS D6 DQS7 DM7 DQS3 DM3 DM I/O 7 I/O 5 I/O 3 I/O 0 I/O 4 I/O 6 I/O 1 I/O 2 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 CS DQS D3 DQS8 DM8 VDDSPD DM I/O 7 I/O 5 I/O 3 I/O 0 I/O 4 I/O 6 I/O 1 I/O 2 CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 CS DQS CS DQS D7 SPD VDD/VDDQ DDR SDRAMs D0 - D8 VREF DDR SDRAMs D0 - D8 VSS DDR SDRAMs D0 - D8 D8 Serial PD PLL* CK0,CK0 * Wire per Clock Loading table/wiring Diagrams CS0 BA0-BA1 A0-A12 RAS CAS CKE0 WE PCK PCK R E G I S T E R RCS0 RBA0 - RBA1 RA0 - RA12 RRAS RCAS RCKE0 RWE SCL SDA WP A0 A1 A2 SA0 SA1 SA2 BA0 -BA1 : DDR SDRAMs D0 - D8 A0 -A12 : DDR SDRAMs D0 - D8 RAS : DDR SDRAMs D0 - D8 CAS : DDR SDRAMs D0 - D8 CKE : DDR SDRAMs D0 - D8 WE: DDR SDRAMs D0 - D8 RESET Notes: 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. DQ/DQS/DM/CKE/CS relationships must be maintained as shown. 3. DQ, DQS, DM/DQS resistors: 22 Ohms. Rev. 1.0 June 2005 512MB, 1GB, 2GB Registered DIMM DDR SDRAM 6.6 1GB, 128M x 72 ECC Module (M312L2923BG(Z)0) (Populated as 2 bank of x8 DDR SDRAM Module) RCS1 RCS0 DQS0 DM0 DQS4 DM4 DM/ DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CS I/O 1 I/O 0 I/O 7 I/O 6 I/O 2 I/O 3 I/O 4 I/O 5 DM/ DQS I/O 6 I/O 7 I/O 0 I/O 1 I/O 5 I/O 4 I/O 3 I/O 2 D0 CS DQS DM/ DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 D9 DQS1 DM1 I/O 6 I/O 7 I/O 0 I/O 1 I/O 5 I/O 4 I/O 3 I/O 2 CS DQS DM/ I/O 1 I/O 0 I/O 7 I/O 6 I/O 2 I/O 3 I/O 4 I/O 5 D4 CS DQS D13 DQS5 DM5 DM/ DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 CS I/O 1 I/O 0 I/O 7 I/O 6 I/O 2 I/O 3 I/O 4 I/O 5 DQS DM/ I/O 6 I/O 7 I/O 0 I/O 1 I/O 5 I/O 4 I/O 3 I/O 2 D1 CS DQS DM/ DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 D10 DQS2 DM2 I/O 1 I/O 0 I/O 7 I/O 6 I/O 2 I/O 3 I/O 4 I/O 5 CS DQS DM/ I/O 6 I/O 7 I/O 0 I/O 1 I/O 5 I/O 4 I/O 3 I/O 2 D5 CS DQS D14 DQS6 DM6 DM/ DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 CS I/O 6 I/O 7 I/O 0 I/O 1 I/O 5 I/O 4 I/O 3 I/O 2 DQS DM/ I/O 1 I/O 0 I/O 7 I/O 6 I/O 2 I/O 3 I/O 4 I/O 5 D2 CS DQS DM/ DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 D11 DQS3 DM3 I/O 6 I/O 7 I/O 0 I/O 1 I/O 5 I/O 4 I/O 3 I/O 2 CS DQS DM/ I/O 1 I/O 0 I/O 7 I/O 6 I/O 2 I/O 3 I/O 4 I/O 5 D6 CS DQS D15 DQS7 DM7 DM/ DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 CS I/O 6 I/O 7 I/O 0 I/O 1 I/O 5 I/O 4 I/O 3 I/O 2 DQS DM/ I/O 1 I/O 0 I/O 7 I/O 6 I/O 2 I/O 3 I/O 4 I/O 5 D3 CS DM/ DQS D12 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 I/O 1 I/O 0 I/O 7 I/O 6 I/O 2 I/O 3 I/O 4 I/O 5 CS DQS D7 DM/ I/O 6 I/O 7 I/O 0 I/O 1 I/O 5 I/O 4 I/O 3 I/O 2 CS DQS D16 DQS8 DM8 DM/ CS I/O 1 I/O 0 I/O 7 I/O 6 I/O 2 I/O 3 I/O 4 I/O 5 CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 DQS DM/ I/O 6 I/O 7 I/O 0 I/O 1 I/O 5 I/O 4 I/O 3 I/O 2 D8 CS DQS D17 Serial PD SCL SDA WP A0 A1 SA0 CS0 CS1 BA0-BA1 A0-A12 RAS CAS CKE0 CKE1 WE PCK R E G I S T E R SA1 VDDSPD SPD VDD/VDDQ D0 - D17 D0 - D17 A2 VREF D0 - D17 VSS D0 - D17 SA2 RCS0 RCS1 RBA0 - RBA1 RA0 - RA12 RRAS RCAS RCKE0 RCKE1 RWE RESET BA0 -BA1 : DDR SDRAM DQ0 - D17 A0 -A12 : DDR SDRAM D0 - D17 RAS : DDR SDRAM D0 - D17 CAS : DDR SDRAM DQ0 - D17 CKE : DDR SDRAM D0 - D8 CKE : DDR SDRAM D9 - D17 WE: DDR SDRAM D0 - D17 PLL* CK0,CK0 * Wire per Clock Loading table/wiring Diagrams Notes: 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. DQ/DQS/DM/CKE/CS relationships must be maintained as shown. 3. DQ, DQS, DM/DQS resistors: 22 Ohms. PCK Rev. 1.0 June 2005 512MB, 1GB, 2GB Registered DIMM DDR SDRAM 6.7 1GB, 128M x 72 ECC Module (M312L2920BG(Z)0) (Populated as 1 bank of x4 DDR SDRAM Module) VSS RCS0 DQS0 DQ0 DQ1 DQ2 DQ3 DQS I/O 3 I/O 2 I/O 1 I/O 0 DQ8 DQ9 DQ10 DQ11 DQS I/O 3 I/O 2 I/O 1 I/O 0 DQ16 DQ17 DQ18 DQ19 DQS I/O 3 I/O 2 I/O 1 I/O 0 DQ24 DQ25 DQ26 DQ27 DQS I/O 3 I/O 2 I/O 1 I/O 0 DQ32 DQ33 DQ34 DQ35 DQS I/O 3 I/O 2 I/O 1 I/O 0 DQ40 DQ41 DQ42 DQ43 DQS I/O 3 I/O 2 I/O 1 I/O 0 DQ48 DQ49 DQ50 DQ51 DQS I/O 3 I/O 2 I/O 1 I/O 0 DQ56 DQ57 DQ58 DQ59 DQS I/O 3 I/O 2 I/O 1 I/O 0 CS DM D0 DQS1 CS DM CS DM CS DM CS DM CS DM CS DM CS DM DQS I/O 3 I/O 2 I/O 1 I/O 0 CS D8 DM DQS I/O 0 I/O 1 I/O 2 I/O 3 D11 DQ28 DQ29 DQ30 DQ31 DQS I/O 0 I/O 1 I/O 2 I/O 3 D12 DQ36 DQ37 DQ38 DQ39 DQS I/O 0 I/O 1 I/O 2 I/O 3 D13 DQ44 DQ45 DQ46 DQ47 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQ52 DQ53 DQ54 DQ55 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQ60 DQ61 DQ62 DQ63 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS16 (DM7) D7 DQS8 DQ20 DQ21 DQ22 DQ23 DQS15 (DM6) D6 DQS7 D10 DQS14 (DM5) D5 DQS6 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS13 (DM4) D4 DQS5 DQ12 DQ13 DQ14 DQ15 DQS12 (DM3) D3 DQS4 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS11 (DM2) D2 DQS3 DQ4 DQ5 DQ6 DQ7 DQS10 (DM1) D1 DQS2 CB0 CB1 CB2 CB3 DQS9 (DM0) DQS17 (DM8) BA0-BA1 A0-A12 RAS CAS CKE0 WE PCK PCK R E G I S T E R CB4 CB5 CB6 CB7 DQS I/O 0 I/O 1 I/O 2 I/O 3 CS CS CS CS CS DM DM DM DM DM D14 CS Serial PD DM SCL D15 SDA WP CS DM A0 A1 A2 SA0 SA1 SA2 D16 VDDSPD CS DM SPD D0 - D17 D0 - D17 D17 VREF D0 - D17 VSS D0 - D17 PLL* CK0,CK0 * Wire per Clock Loading table/wiring Diagrams RCS0_2 RBA0 - RBA1 RA0 - RA12 RRAS RCAS RCKE0A RCKE0B RWE DM VDD/VDDQ RCS0_1 CS0 CS D9 BA0 -BA1 : DDR SDRAM DQ0 - D17 A0 -A12 :DDR SDRAM D0 - D17 RAS : DDR SDRAM D0 - D17 CAS : DDR SDRAM DQ0 - D17 CKE : DDR SDRAM D0 - D8 CKE : DDR SDRAM D9 - D17 WE:DDR SDRAM D0 - D17 Notes: 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. DQ/DQS/DM/CKE/S relationships must be maintained as shown. 3. DQ, DQS, DM resistors: 22 Ohms. RESET Rev. 1.0 June 2005 512MB, 1GB, 2GB Registered DIMM DDR SDRAM 6.8 2GB, 256M x 72 ECC Module (M312L5720BG(Z)0) (Populated as 2 bank of x4 DDR SDRAM Module) VSS RCS1 RCS0 DQS9 (DM0) DQS0 CS DQ0 DQ1 DQ2 DQ3 DQS I/O 0 I/O 1 I/O 2 I/O 3 CS DQ8 DQ9 DQ10 DQ11 DQS I/O 0 I/O 1 I/O 2 I/O 3 CS DQ16 DQ17 DQ18 DQ19 DQS I/O 0 I/O 1 I/O 2 I/O 3 CS DQ24 DQ25 DQ26 DQ27 DQS I/O 0 I/O 1 I/O 2 I/O 3 CS DQ32 DQ33 DQ34 DQ35 DQS I/O 0 I/O 1 I/O 2 I/O 3 CS DQ40 DQ41 DQ42 DQ43 DQS I/O 0 I/O 1 I/O 2 I/O 3 CS DQ48 DQ49 DQ50 DQ51 DQS I/O 0 I/O 1 I/O 2 I/O 3 CS DQ56 DQ57 DQ58 DQ59 DQS I/O 0 I/O 1 I/O 2 I/O 3 CS CB0 CB1 CB2 CB3 DQS I/O 0 I/O 1 I/O 2 I/O 3 DM D0 DQS I/O 0 I/O 1 I/O 2 I/O 3 DM CS D18 DQS1 DM D1 DQS I/O 0 I/O 1 I/O 2 I/O 3 D19 D2 DQS I/O 0 I/O 1 I/O 2 I/O 3 DM CS D20 D3 DQS I/O 0 I/O 1 I/O 2 I/O 3 DM CS D21 D4 DQS I/O 0 I/O 1 I/O 2 I/O 3 DM CS D22 D5 DQS I/O 0 I/O 1 I/O 2 I/O 3 DM CS D23 D6 DQS I/O 0 I/O 1 I/O 2 I/O 3 DM CS D24 D7 DQS I/O 0 I/O 1 I/O 2 I/O 3 DM CS D25 D8 DQS I/O 0 I/O 1 I/O 2 I/O 3 DM CS DQ28 DQ29 DQ30 DQ31 DQS I/O 3 I/O 2 I/O 1 I/O 0 DQ36 DQ37 DQ38 DQ39 DQS I/O 3 I/O 2 I/O 1 I/O 0 DQ44 DQ45 DQ46 DQ47 DQS I/O 3 I/O 2 I/O 1 I/O 0 D14 DQ52 DQ53 DQ54 DQ55 DQS I/O 3 I/O 2 I/O 1 I/O 0 D15 DQ60 DQ61 DQ62 DQ63 DQS I/O 3 I/O 2 I/O 1 I/O 0 D16 CB4 CB5 CB6 CB7 DQS I/O 3 I/O 2 I/O 1 I/O 0 D17 DQS17 (DM8) DQS8 DM DQS I/O 3 I/O 2 I/O 1 I/O 0 DQS16 (DM7) DQS7 DM DQ20 DQ21 DQ22 DQ23 DQS15 (DM6) DQS6 DM D10 DQS14 (DM5) DQS5 DM DQS I/O 3 I/O 2 I/O 1 I/O 0 DQS13 (DM4) DQS4 DM DQ12 DQ13 DQ14 DQ15 DQS12 (DM3) DQS3 DM D9 DQS11 (DM2) DQS2 DM DQS I/O 3 I/O 2 I/O 1 I/O 0 DQS10 (DM1) DM CS DQ4 DQ5 DQ6 DQ7 D26 SCL WE PCK R E G I S T E R RCS0 RCS1 RBA0 - RBA1 RA0 - RA12 BA0-BA1: DDR SDRAM D0 - D35 A0-A12: DDR SDRAM D0 - D35 RRAS RAS: DDR RCAS RCKE0 CAS: DDR SDRAM D0 - D35 CKE: DDR SDRAM D0 - D17 RCKE1 CKE: DDR RWE WE: DDR SDRAM D0 - D35 SDRAM D18 - D35 SDRAM D0 - D35 CS DM DM DM D11 CS DM D12 CS DM D13 CS CS CS CS DM DM DM DM DQS I/O 3 I/O 2 I/O 1 I/O 0 D27 DQS I/O 3 I/O 2 I/O 1 I/O 0 D28 DQS I/O 3 I/O 2 I/O 1 I/O 0 DQS I/O 3 I/O 2 I/O 1 I/O 0 DQS I/O 3 I/O 2 I/O 1 I/O 0 CS CS CS DM DM DM D29 CS DM D30 CS DM D31 DQS I/O 3 I/O 2 I/O 1 I/O 0 D32 DQS I/O 3 I/O 2 I/O 1 I/O 0 D33 CS CS DQS I/O 3 I/O 2 I/O 1 I/O 0 D34 DQS I/O 3 I/O 2 I/O 1 I/O 0 D35 CS CS DM DM DM DM SPD VDD/VDDQ D0 - D35 SDA WP CS1 BA0-BA1 A0-A12 RAS CAS CKE0 CKE1 CS VDDSPD Serial PD CS0 CS D0 - D35 A0 A1 A2 VREF D0 - D35 SA0 SA1 SA2 VSS D0 - D35 PLL* CK0,CK0 * Wire per Clock Loading table/wiring Diagrams Notes: 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. DQ/DQS/DM/CKE/CS relationships must be maintained as shown. 3. DQ, DQS, DM/DQS resistors: 22 Ohms. RESET PCK Rev. 1.0 June 2005 512MB, 1GB, 2GB Registered DIMM DDR SDRAM 7.0 Absolute Maximum Ratings Parameter Symbol Value Unit Voltage on any pin relative to Vss VIN, VOUT -0.5 ~ 3.6 V Voltage on VDD supply relative to Vss VDD,VDDQ -1.0 ~ 3.6 V TSTG -55 ~ +150 C Power dissipation PD 1.5 * # of component W Short circuit current IOS 50 mA Storage temperature Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. 8.0 Power & DC Operating Conditions (SSTL_2 In/Out) Recommended operating conditions(Voltage referenced to VSS=0V, TA=0 to 70C) Parameter Symbol Min Max Unit Supply voltage(for device with a nominal VDD of 2.5V for DDR266/333) VDD 2.3 2.7 V Supply voltage(for device with a nominal VDD of 2.6V for DDR400) VDD 2.5 2.7 V I/O Supply voltage(for device with a nominal VDD of 2.5V for DDR266/333) VDDQ 2.3 2.7 V I/O Supply voltage(for device with a nominal VDD of 2.6V for DDR400) VDDQ 2.5 2.7 V I/O Reference voltage VREF 0.49*VDDQ 0.51*VDDQ V 1 I/O Termination voltage(system) VTT VREF-0.04 VREF+0.04 V 2 VIH(DC) VREF+0.15 VDDQ+0.3 V Input logic high voltage Note Input logic low voltage VIL(DC) -0.3 VREF-0.15 V Input Voltage Level, CK and CK inputs VIN(DC) -0.3 VDDQ+0.3 V Input Differential Voltage, CK and CK inputs VID(DC) 0.36 VDDQ+0.6 V 3 V-I Matching: Pullup to Pulldown Current Ratio VI(Ratio) 0.71 1.4 - 4 II -2 2 uA Output leakage current IOZ -5 5 uA Output High Current(Normal strengh driver) ;VOUT = VTT + 0.84V IOH -16.8 mA Output High Current(Normal strengh driver) ;VOUT = VTT - 0.84V IOL 16.8 mA Output High Current(Half strengh driver) ;VOUT = VTT + 0.45V IOH -9 mA Output High Current(Half strengh driver) ;VOUT = VTT - 0.45V IOL 9 mA Input leakage current Note : 1. VREF is expected to be equal to 0.5*VDDQ of the transmitting device, and to track variations in the dc level of same. Peak-to peak noise on VREF may not exceed +/-2% of the dc value. 2. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track variations in the DC level of VREF. 3. VID is the magnitude of the difference between the input level on CK and the input level on CK. 4. The ratio of the pullup current to the pulldown current is specified for the same temperature and voltage, over the entire temperature and voltage range, for device drain to source voltages from 0.25V to 1.0V. For a given output, it represents the maximum difference between pullup and pulldown drivers due to process variation. The full variation in the ratio of the maximum to minimum pullup and pulldown current will not exceed 1.7 for device drain to source voltages from 0.1 to 1.0. Rev. 1.0 June 2005 512MB, 1GB, 2GB Registered DIMM DDR SDRAM 9.0 DDR SDRAM IDD spec table 9.1 M312L6523BT(U)S [ (64M x 8) * 9 , 512MB Module ] (VDD=2.7V, T = 10C) Symbol A2(DDR266@CL=2) B0(DDR266@CL=2.5) Unit IDD0 1,490 1,490 mA IDD1 1,720 1,720 mA IDD2P 350 350 mA IDD2F 770 770 mA IDD2Q 480 480 mA IDD3P 570 570 mA IDD3N 950 950 mA IDD4R 1,850 1,850 mA IDD4W 1,900 1,900 mA IDD5 2,660 2,660 mA 350 350 mA 330 330 mA 3,560 3,560 mA IDD6 Normal Low power IDD7A Notes Optional * Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap. 9.2 M312L2923BT(U)S [ (64M x 8) * 18 , 1GB Module ] (VDD=2.7V, T = 10C) IDD6 Symbol A2(DDR266@CL=2) B0(DDR266@CL=2.5) Unit IDD0 2,190 2,190 mA IDD1 2,420 2,420 mA IDD2P 540 540 mA IDD2F 1,290 1,290 mA IDD2Q 810 810 mA IDD3P 990 990 mA IDD3N 1,650 1,650 mA IDD4R 2,550 2,550 mA IDD4W 2,600 2,600 mA IDD5 3,360 3,360 mA Normal 540 540 mA Low power 500 500 mA 4,260 4,260 mA IDD7A Notes Optional * Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap. Rev. 1.0 June 2005 512MB, 1GB, 2GB Registered DIMM DDR SDRAM 9.3 M312L2920BT(U)S [ (128M x 4) * 18 , 1GB Module ] (VDD=2.7V, T = 10C) Symbol A2(DDR266@CL=2) B0(DDR266@CL=2.5) Unit IDD0 2,610 2,610 mA IDD1 3,010 3,010 mA IDD2P 420 420 mA IDD2F 1,170 1,170 mA IDD2Q 690 690 mA IDD3P 870 870 mA IDD3N 1,530 1,530 mA IDD4R 3,330 3,330 mA IDD4W 3,420 3,420 mA IDD5 4,950 4,950 mA Normal 420 420 mA Low power 380 380 mA 6,750 6,750 mA IDD6 IDD7A Notes Optional * Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap. 9.4 M312L5628BT(U)0 [ (st.256M x 4) * 18 , 2GB Module ] (VDD=2.7V, T = 10C) IDD6 Symbol A2(DDR266@CL=2) B0(DDR266@CL=2.5) Unit IDD0 3,760 3,760 mA IDD1 4,210 4,210 mA IDD2P 760 760 mA IDD2F 1,960 1,960 mA IDD2Q 1,300 1,300 mA IDD3P 1,660 1,660 mA IDD3N 2,680 2,680 mA IDD4R 4,480 4,480 mA IDD4W 4,570 4,570 mA IDD5 6,100 6,100 mA Normal 760 760 mA Low power 680 680 mA 7,900 7,900 mA IDD7A Notes Optional * Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap. Rev. 1.0 June 2005 512MB, 1GB, 2GB Registered DIMM DDR SDRAM 9.5 M312L6523BG(Z)0 [ (64M x 8) * 9 , 512MB Module ] (VDD=2.7V, T = 10C) IDD6 Symbol CC (DDR400@CL=3) B3 (DDR333@CL=2.5) Unit IDD0 2,240 3,220 mA IDD1 2,420 3,400 mA IDD2P 420 590 mA IDD2F 1,020 1,420 mA IDD2Q 600 950 mA IDD3P 870 1,490 mA IDD3N 1,610 2,590 mA IDD4R 2,550 3,530 mA IDD4W 2,910 3,890 mA IDD5 3,140 4,120 mA 420 590 mA 410 560 mA 4,620 5,600 mA Normal Low power IDD7A Notes Optional * Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap. 9.6 M312L2923BG(Z)0 [ (64M x 8) * 18 , 1GB Module ] (VDD=2.7V, T = 10C) IDD6 Symbol CC (DDR400@CL=3) B3 (DDR333@CL=2.5) Unit IDD0 2,500 2,450 mA IDD1 2,770 2,680 mA IDD2P 590 590 mA IDD2F 1,420 1,420 mA IDD2Q 950 950 mA IDD3P 1,310 1,040 mA IDD3N 1,960 1,780 mA IDD4R 2,810 2,810 mA IDD4W 2,990 3,040 mA IDD5 3,400 3,580 mA Normal 590 590 mA Low power 560 560 mA 4,880 4,930 mA IDD7A Notes Optional * Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap. Rev. 1.0 June 2005 512MB, 1GB, 2GB Registered DIMM DDR SDRAM 9.7 M312L2920BG(Z)0 [ (128M x 4) * 18 , 1GB Module ] (VDD=2.7V, T = 10C) IDD6 Symbol CC (DDR400@CL=3) B3 (DDR333@CL=2.5) Unit IDD0 3,720 3,000 mA IDD1 4,080 3,450 mA IDD2P 470 470 mA IDD2F 1,290 1,290 mA IDD2Q 830 830 mA IDD3P 1,370 920 mA IDD3N 2,460 1,650 mA IDD4R 4,350 3,720 mA IDD4W 5,070 4,170 mA IDD5 5,520 5,250 mA Normal 470 670 mA Low power 430 430 mA 8,490 7,950 mA IDD7A Notes Optional * Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap. 9.8 M312L5720BG(Z)0 [ (128M x 4) * 36, 2GB Module ] (VDD=2.7V, T = 10C) IDD6 Symbol CC (DDR400@CL=3) B3 (DDR333@CL=2.5) Unit IDD0 5,680 4,030 mA IDD1 6,040 4,480 mA IDD2P 810 680 mA IDD2F 2,080 1,960 mA IDD2Q 1,530 1,400 mA IDD3P 2,610 1,580 mA IDD3N 4,420 2,680 mA IDD4R 6,310 4,750 mA IDD4W 7,030 5,200 mA IDD5 7,480 6,280 mA 810 680 mA 740 610 mA 10,450 8,980 mA Normal Low power IDD7A Notes Optional * Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap. Rev. 1.0 June 2005 512MB, 1GB, 2GB Registered DIMM DDR SDRAM 10.0 AC Operating Conditions Parameter/Condition Symbol Min Input High (Logic 1) Voltage, DQ, DQS and DM signals VIH(AC) VREF + 0.31 Max Unit Note V Input Low (Logic 0) Voltage, DQ, DQS and DM signals. VIL(AC) VREF - 0.31 V Input Differential Voltage, CK and CK inputs VID(AC) 0.7 VDDQ+0.6 V 1 Input Crossing Point Voltage, CK and CK inputs VIX(AC) 0.5*VDDQ-0.2 0.5*VDDQ+0.2 V 2 Note : 1. VID is the magnitude of the difference between the input level on CK and the input on CK. 2. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same. Vtt=0.5*VDDQ RT=50 Output Z0=50 VREF =0.5*VDDQ CLOAD=30pF Output Load Circuit (SSTL_2) 11.0 Input/Output Capacitance (TA= 25C, f=100MHz) Parameter Symbol Input capacitance(A0 ~ A12, BA0 ~ BA1,RAS,CAS,WE ) M312L6523BT(U), M312L2920BT(U) M312L2923BT(U) M312L5720BT(U) Unit Min Max Min Max CIN1 9 11 9 11 pF Input capacitance(CKE0) CIN2 9 11 9 11 pF Input capacitance( CS0) CIN3 9 11 9 11 pF Input capacitance( CLK0, CLK0 ) CIN4 11 12 11 12 pF Input capacitance(DM0~DM8) CIN5 10 11 14 16 pF Data & DQS input/output capacitance(DQ0~DQ63) Cout1 10 11 14 16 pF Data input/output capacitance (CB0~CB7) Cout2 10 11 14 16 pF Parameter Symbol Input capacitance(A0 ~ A12, BA0 ~ BA1,RAS,CAS,WE ) M312L6523BG(Z), M312L2920BG(Z) M312L2923BG(Z), M312L5720BG(Z) Unit Min Max Min Max CIN1 9 11 9 11 pF Input capacitance(CKE0) CIN2 9 11 9 11 pF Input capacitance( CS0) CIN3 9 11 9 11 pF Input capacitance( CLK0, CLK0 ) CIN4 11 12 11 12 pF Input capacitance(DM0~DM8) CIN5 10 11 13 15 pF Data & DQS input/output capacitance(DQ0~DQ63) Cout1 10 11 13 15 pF Data input/output capacitance (CB0~CB7) Cout2 10 11 13 15 pF Rev. 1.0 June 2005 512MB, 1GB, 2GB Registered DIMM DDR SDRAM 12.0 AC Timming Parameters & Specifications Symbol Parameter Row cycle time CC B3 A2 B0 (DDR400@CL=3.0) (DDR333@CL=2.5) (DDR266@CL=2.0) (DDR266@CL=2.5) Unit Min Max Min Max Min Max Min Max tRC 55 60 65 65 ns tRFC 70 72 75 75 ns Row active time tRAS 40 RAS to CAS delay tRCD 15 Refresh row cycle time Row precharge time Row active to Row active delay Write recovery time Last data in to Read command CL=2.5 Clock low level width 70K 18 45 70K 20 45 70K 20 ns ns tRP 15 18 20 20 ns 10 12 15 15 ns tWR 15 15 15 15 ns tWTR 2 1 1 1 tCK - - 7.5 12 7.5 12 10 12 ns tCK 6 12 6 12 7.5 12 7.5 12 ns 5 10 - - - - - - tCH 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 tCK CL=3.0 Clock high level width 42 tRRD CL=2.0 Clock cycle time 70K tCL 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 tCK tDQSCK -0.55 +0.55 -0.6 +0.6 -0.75 +0.75 -0.75 +0.75 ns Output data access time from CK/CK tAC -0.65 +0.65 -0.7 +0.7 -0.75 +0.75 -0.75 +0.75 ns Data strobe edge to ouput data edge tDQSQ - 0.4 - 0.45 - 0.5 - 0.5 ns Read Preamble tRPRE 0.9 1.1 0.9 1.1 0.9 1.1 0.9 1.1 tCK DQS-out access time from CK/CK Note Read Postamble tRPST 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 tCK CK to valid DQS-in tDQSS 0.72 1.28 0.75 1.25 0.75 1.25 0.75 1.25 tCK DQS-in setup time tWPRES 0 0 0 0 ns DQS-in hold time tCK 22 13 tWPRE 0.25 0.25 0.25 0.25 DQS falling edge to CK rising-setup time tDSS 0.2 0.2 0.2 0.2 tCK DQS falling edge from CK rising-hold time tDSH 0.2 0.2 0.2 0.2 tCK DQS-in high level width tDQSH 0.35 0.35 0.35 0.35 tCK DQS-in low level width tDQSL 0.35 0.35 0.35 0.35 tCK Address and Control Input setup time(fast) tIS 0.6 0.75 0.9 0.9 ns 15, 17~19 Address and Control Input hold time(fast) tIH 0.6 0.75 0.9 0.9 ns 15, 17~19 Address and Control Input setup time(slow) tIS 0.7 0.8 1.0 1.0 ns 16~19 ns 16~19 Address and Control Input hold time(slow) tIH 0.7 Data-out high impedence time from CK/CK tHZ -0.65 +0.65 -0.7 0.8 +0.7 -0.75 1.0 +0.75 -0.75 1.0 +0.75 ns 11 Data-out low impedence time from CK/CK tLZ -0.65 +0.65 -0.7 +0.7 -0.75 +0.75 -0.75 +0.75 ns 11 Mode register set cycle time tMRD 10 12 15 15 DQ & DM setup time to DQS tDS 0.4 0.45 0.5 0.5 ns ns j, k j, k DQ & DM hold time to DQS tDH 0.4 0.45 0.5 0.5 ns Control & Address input pulse width tIPW 2.2 2.2 2.2 2.2 ns 18 DQ & DM input pulse width tDIPW 1.75 1.75 1.75 1.75 ns 18 Exit self refresh to non-Read command tXSNR 75 75 75 75 ns Exit self refresh to read command tXSRD 200 Refresh interval time tREFI Output DQS valid window tQH tHP -tQHS Clock half period tHP tCLmin or tCHmin Data hold skew factor DQS write postamble time 200 7.8 tQHS - tHP -tQHS - tCLmin or tCHmin 0.5 0.6 200 7.8 - tHP -tQHS - tHP -tQHS - tCLmin or tCHmin - tCLmin or tCHmin 0.55 0.4 200 7.8 0.6 0.75 tWPST 0.4 0.4 0.6 0.4 Active to Read with Auto precharge command tRAP 15 18 20 20 Autoprecharge write recovery + Precharge time tDAL (tWR/tCK) + (tRP/tCK) (tWR/tCK) + (tRP/tCK) (tWR/tCK) + (tRP/tCK) (tWR/tCK) + (tRP/tCK) tCK 7.8 us 14 - ns 21 - ns 20, 21 0.75 ns 21 0.6 tCK 12 tCK 23 Rev. 1.0 June 2005 512MB, 1GB, 2GB Registered DIMM DDR SDRAM 13.0 System Characteristics for DDR SDRAM The following specification parameters are required in systems using DDR333, DDR266 & DDR200 devices to ensure proper system performance. these characteristics are for system simulation purposes and are guaranteed by design. Table 1 : Input Slew Rate for DQ, DQS, and DM AC CHARACTERISTICS DDR333 PARAMETER DQ/DM/DQS input slew rate measured between VIH(DC), VIL(DC) and VIL(DC), VIH(DC) DDR266 DDR200 SYMBOL MIN MAX MIN MAX MIN MAX Units Notes DCSLEW TBD TBD TBD TBD 0.5 4.0 V/ns a, m Table 2 : Input Setup & Hold Time Derating for Slew Rate Input Slew Rate tIS tIH Units Notes 0.5 V/ns 0 0 ps i 0.4 V/ns +50 0 ps i 0.3 V/ns +100 0 ps i Table 3 : Input/Output Setup & Hold Time Derating for Slew Rate Input Slew Rate tDS tDH Units Notes 0.5 V/ns 0 0 ps k 0.4 V/ns +75 +75 ps k 0.3 V/ns +150 +150 ps k Table 4 : Input/Output Setup & Hold Derating for Rise/Fall Delta Slew Rate Delta Slew Rate tDS tDH Units Notes +/- 0.0 V/ns 0 0 ps j +/- 0.25 V/ns +50 +50 ps j +/- 0.5 V/ns +100 +100 ps j Table 5 : Output Slew Rate Characteristice (X4, X8 Devices only) Slew Rate Characteristic Typical Range (V/ns) Minimum (V/ns) Maximum (V/ns) Notes Pullup Slew Rate 1.2 ~ 2.5 1.0 4.5 a,c,d,f,g,h Pulldown slew 1.2 ~ 2.5 1.0 4.5 b,c,d,f,g,h Table 6 : Output Slew Rate Characteristice (X16 Devices only) Slew Rate Characteristic Typical Range (V/ns) Minimum (V/ns) Maximum (V/ns) Notes Pullup Slew Rate 1.2 ~ 2.5 0.7 5.0 a,c,d,f,g,h Pulldown slew 1.2 ~ 2.5 0.7 5.0 b,c,d,f,g,h Table 7 : Output Slew Rate Matching Ratio Characteristics AC CHARACTERISTICS DDR266B DDR200 PARAMETER MIN MAX MIN MAX Notes Output Slew Rate Matching Ratio (Pullup to Pulldown) TBD TBD 0.67 1.5 e,m Rev. 1.0 June 2005 512MB, 1GB, 2GB Registered DIMM DDR SDRAM 14.0 Component Notes 1. All voltages referenced to Vss. 2. Tests for ac timing, IDD, and electrical, ac and dc characteristics, may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. 3. Figure 1 represents the timing reference load used in defining the relevant timing parameters of the part. It is not intended to be either a precise representation of the typical system environment nor a depiction of the actual load presented by a production tester. System designers will use IBIS or other simulation tools to correlate the timing reference load to a system environment. Manufacturers will correlate to their production test conditions (generally a coaxial transmission line terminated at the tester electronics). VDDQ 50 Output (Vout) 30pF Figure 1 : Timing Reference Load 4. AC timing and IDD tests may use a VIL to VIH swing of up to 1.5 V in the test environment, but input timing is still referenced to VREF (or to the crossing point for CK/CK), and parameter specifications are guaranteed for the specified ac input levels under normal use conditions. The minimum slew rate for the input signals is 1 V/ns in the range between VIL(ac) and VIH(ac). 5. The ac and dc input level specifications are as defined in the SSTL_2 Standard (i.e., the receiver will effectively switch as a result of the signal crossing the ac input level and will remain in that state as long as the signal does not ring back above (below) the dc input LOW (HIGH) level. 6. Inputs are not recognized as valid until VREF stabilizes. Exception: during the period before VREF stabilizes, CKE 0.2VDDQ is recognized as LOW. 7. Enables on.chip refresh and address counters. 8. IDD specifications are tested after the device is properly initialized. 9. The CK/CK input reference level (for timing referenced to CK/CK) is the point at which CK and CK cross; the input reference level for signals other than CK/CK, is VREF. 10. The output timing reference voltage level is VTT. 11. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referenced to a specific voltage level but specify when the device output is no longer driving (HZ), or begins driving (LZ). 12. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this parameter, but sys tem performance (bus turnaround) will degrade accordingly. 13. The specific requirement is that DQS be valid (HIGH, LOW, or at some point on a valid transition) on or before this CK edge. A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. when no writes were previ ously in progress on the bus, DQS will be tran sitioning from High- Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS. 14. A maximum of eight AUTO REFRESH commands can be posted to any given DDR SDRAM device. 15. For command/address input slew rate 1.0 V/ns 16. For command/address input slew rate 0.5 V/ns and < 1.0 V/ns 17. For CK & CK slew rate 1.0 V/ns 18. These parameters guarantee device timing, but they are not necessarily tested on each device. They may be guaranteed by device design or tester correlation. 19. Slew Rate is measured between VOH(ac) and VOL(ac). 20. Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can be greater than the minimum specification limits for tCL and tCH).....For example, tCL and tCH are = 50% of the period, less the half period jitter (tJIT(HP)) of the clock source, and less the half period jitter due to crosstalk (tJIT(crosstalk)) into the clock traces. 21. tQH = tHP - tQHS, where: tHP = minimum half clock period for any given cycle and is defined by clock high or clock low (tCH, tCL). tQHS accounts for 1) The pulse duration distortion of on-chip clock circuits; and 2) The worst case push-out of DQS on one tansition followed by the worst case pull-in of DQ on the next transition, both of which are, separately, due to data pin skew and output pattern effects, and p channel to n-channel variation of the output drivers. 22. tDQSQ - Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers for any given cycle. 23. tDAL = (tWR/tCK) + (tRP/tCK) For each of the terms above, if not already an integer, round to the next highest integer. Example: For DDR266B at CL=2.5 and tCK=7.5ns tDAL = (15 ns / 7.5 ns) + (20 ns/ 7.5ns) = (2) + (3) tDAL = 5 clocks Rev. 1.0 June 2005 512MB, 1GB, 2GB Registered DIMM DDR SDRAM 15.0 System Notes: a. Pullup slew rate is characteristized under the test conditions as shown in Figure 2. Test point Output 50 VSSQ Figure 2 : Pullup slew rate test load b. Pulldown slew rate is measured under the test conditions shown in Figure 3. VDDQ 50 Output Test point Figure 3 : Pulldown slew rate test load c. Pullup slew rate is measured between (VDDQ/2 - 320 mV +/- 250 mV) Pulldown slew rate is measured between (VDDQ/2 + 320 mV +/- 250 mV) Pullup and Pulldown slew rate conditions are to be met for any pattern of data, including all outputs switching and only one output switching. Example : For typical slew rate, DQ0 is switching For minmum slew rate, all DQ bits are switching from either high to low, or low to high. The remaining DQ bits remain the same as for previous state. d. Evaluation conditions Typical : 25 C (T Ambient), VDDQ = 2.5V(for DDR266/333) and 2.6V(for DDR400), typical process Minimum : 70 C (T Ambient), VDDQ = 2.3V(for DDR266/333) and 2.5V(for DDR400), slow - slow process Maximum : 0 C (T Ambient), VDDQ = 2.7V(for DDR266/333) and 2.7V(for DDR400), fast - fast process e. The ratio of pullup slew rate to pulldown slew rate is specified for the same temperature and voltage, over the entire temperature and voltage range. For a given output, it represents the maximum difference between pullup and pulldown drivers due to process variation. f. Verified under typical conditions for qualification purposes. g. TSOPII package divices only. h. Only intended for operation up to 266 Mbps per pin. i. A derating factor will be used to increase tIS and tIH in the case where the input slew rate is below 0.5V/ns as shown in Table 2. The Input slew rate is based on the lesser of the slew rates detemined by either VIH(AC) to VIL(AC) or VIH(DC) to VIL(DC), similarly for rising transitions. j. A derating factor will be used to increase tDS and tDH in the case where DQ, DM, and DQS slew rates differ, as shown in Tables 3 & 4. Input slew rate is based on the larger of AC-AC delta rise, fall rate and DC-DC delta rise, Input slew rate is based on the lesser of the slew rates determined by either VIH(AC) to VIL(AC) or VIH(DC) to VIL(DC), similarly for rising transitions. The delta rise/fall rate is calculated as: {1/(Slew Rate1)} - {1/(Slew Rate2)} For example : If Slew Rate 1 is 0.5 V/ns and slew Rate 2 is 0.4 V/ns, then the delta rise, fall rate is - 0.5ns/V . Using the table given, this would result in the need for an increase in tDS and tDH of 100 ps. k. Table 3 is used to increase tDS and tDH in the case where the I/O slew rate is below 0.5 V/ns. The I/O slew rate is based on the lesser on the lesser of the AC - AC slew rate and the DC- DC slew rate. The inut slew rate is based on the lesser of the slew rates deter mined by either VIH(ac) to VIL(ac) or VIH(DC) to VIL(DC), and similarly for rising transitions. m. DQS, DM, and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times. Signal transi tions through the DC region must be monotonic. Rev. 1.0 June 2005 512MB, 1GB, 2GB Registered DIMM DDR SDRAM 16.0 Command Truth Table COMMAND (V=Valid, X=Dont Care, H=Logic High, L=Logic Low) CKEn-1 CKEn CS RAS CAS WE BA0,1 A10/AP A0 ~ A9 A11, A12 Note Register Extended MRS H X L L L L OP CODE 1, 2 Register Mode Register Set H X L L L L OP CODE 1, 2 L L L H X Auto Refresh Entry Refresh Self Refresh Exit Bank Active & Row Addr. Read & Column Address Auto Precharge Disable Write & Column Address Auto Precharge Disable Auto Precharge Enable Auto Precharge Enable Burst Stop Bank Selection Precharge H L L H H H H X X X X L L H H V H X L H L H V H X L H L L V H X L H H L L H H H X Entry H L Exit L H Entry H L Exit L H All Banks Active Power Down H Precharge Power Down Mode DM H No operation (NOP) : Not defined H L L H L H X X X L V V V X X X X H X X X L H H H H X X X L V V V X X 3 3 3 X 3 Row Address (A0~A9, A11,A12) L Column Address H L Column Address H X V L X H X X X L H H H 4 4, 6 7 X 5 X X X H 4 4 X 8 9 9 Note : 1. OP Code : Operand Code. A0 ~ A12 & BA0 ~ BA1 : Program keys. (@EMRS/MRS) 2. EMRS/ MRS can be issued only at all banks precharge state. A new command can be issued 2 clock cycles after EMRS or MRS. 3. Auto refresh functions are same as the CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. 4. BA0 ~ BA1 : Bank select addresses. If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected. If BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected. If BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank C is selected. If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected. 5. If A10/AP is "High" at row precharge, BA0 and BA1 are ignored and all banks are selected. 6. During burst write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 7. Burst stop command is valid at every burst length. 8. DM sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0). 9. This combination is not defined for any function, which means "No Operation(NOP)" in DDR SDRAM. Rev. 1.0 June 2005 512MB, 1GB, 2GB Registered DIMM DDR SDRAM 17.0 Physical Dimensions 17.1 64M x 72 (M312L6523BT(U)S) Units : Inches (Millimeters) 5.25 0.005 (133.350 0.13) 0.118 Min (3.00 Min) 5.171 (131.350) 5.077 (128.950) 1.2 +/-0.06 (30.48 +/-0.15) REG 0.0787 R (2.00) 0.393 (10.00) 0.78 (19.80) 0.7 (17.80) PLL B 0.100 (2.30) A 2.500 +0.1/-0.0 A 0.10 M B C B A (4.00) (0.157) 0.157 Max (3.99 Max) REG 0.1496 (3.80) 2.175 0.071 (1.80) Detail A (2.50 0.2 ) 0.100 0.0079 0.250 (6.350) 0.050 0.0039 (1.270 0.10) 0.039 0.002 (1.000 0.050) 0.118 Min (3.00 Min) 0.0787 R (2.00) 0.0078 0.006 (0.20 0.15) 0.050 (1.270) Detail B 0.1575 0.004 (4.00 0.1) 0.10 M C A M B Tolerances : 0.005(.13) unless otherwise specified The used device is 64Mx8 DDR SDRAM, TSOPII SDRAM Part No : K4H510838B Rev. 1.0 June 2005 512MB, 1GB, 2GB Registered DIMM DDR SDRAM 17.2 128Mx72 (M312L2923BT(U)S), 128Mx72 (M312L2920BT(U)S) Units : Inches (Millimeters) 5.25 0.005 (133.350 0.13) 0.118 Min (3.00 Min) 5.171 (131.350) 5.077 (128.950) 1.2 +/-0.06 (30.48 +/-0.15) REG 0.0787 R (2.00) 0.393 (10.00) 0.78 (19.80) 0.7 (17.80) PLL B 0.100 (2.30) A 2.500 +0.1/-0.0 A 0.10 M B C B A (4.00) (0.157) 0.157 Max (3.99 Max) REG 0.1496 (3.80) 2.175 0.071 (1.80) Detail A (2.50 0.2 ) 0.100 0.0079 0.250 (6.350) 0.050 0.0039 (1.270 0.10) 0.039 0.002 (1.000 0.050) 0.118 Min (3.00 Min) 0.0787 R (2.00) 0.0078 0.006 (0.20 0.15) 0.050 (1.270) Detail B 0.1575 0.004 (4.00 0.1) 0.10 M C A M B Tolerances : 0.005(.13) unless otherwise specified The used device is 64Mx8, 128Mx4 DDRSDRAM, TSOPII SDRAM Part No. : K4H510838B, K4H510438B Rev. 1.0 June 2005 512MB, 1GB, 2GB Registered DIMM DDR SDRAM 17.3 st.256Mx72 (M312L5628BT(U)0) Units : Inches (Millimeters) 5.25 0.005 (133.350 0.13) 0.118 Min (3.00 Min) 5.171 (131.350) 5.077 (128.950) 0.7 0.393 (10.00) 0.78 (19.80) B 0.100 (2.30) A (17.80) 1.2 +/-0.06 (30.48 +/-0.15) Reg. 0.0787 R (2.00) 2.500 +0.1/-0.0 A 0.10 M B C B A PLL (4.00) (0.157) 0.268 Max (6.81 Max) 0.1496 (3.80) 2.175 0.071 (1.80) Detail A (2.50 0.2 ) 0.250 (6.350) 0.100 0.0079 0.050 0.0039 (1.270 0.10) 0.039 0.002 (1.000 0.050) 0.118 Min (3.00 Min) 0.0787 R (2.00) 0.0078 0.006 (0.20 0.15) 0.050 (1.270) Detail B 0.1575 0.004 (4.00 0.1) 0.10 M C A M B Tolerances : 0.005(.13) unless otherwise specified The used device is st.256Mx4 SDRAM, 66TSOPII SDRAM Part NO : K4H1G0638B Rev. 1.0 June 2005 512MB, 1GB, 2GB Registered DIMM DDR SDRAM 17.4 64Mx72 (M312L6523BG(Z)0) Units : Millimeters 133.35 A 128.95 A 1.27 +/-0.1 2x 3.00 MIN W1 12.00 2x DIA. 2.50 +0.1/-0.00 N a 1 6.35 b 64.77 P2 10.00 B2 19.80 B1 28.575 +/-0.15 B 4x 4.00+/-0.1 V1 92 2.99 MAX 49.53 P3 120.65 P1 93 184 6.35 X 2.175 X1 X2 4.175 D 1.0 +/-0.05 G V 2.50 0.20 +/-0.15 T 3.80 W 1.80 MAX 0.178 Detail A D1 E 1.27 Detail B Tolerances : 0.005(.13) unless otherwise specified The used device is 64Mx8 DDR SDRAM, FBGA DDR SDRAM Part No. : K4H510838B Rev. 1.0 June 2005 512MB, 1GB, 2GB Registered DIMM DDR SDRAM 17.5 128Mx72 (M312L2923BG(Z)0), (M312L2920BG(Z)0) Units : Millimeters 133.35 A 128.95 A 1.27 +/-0.1 2x 3.00 MIN W1 12.00 2x DIA. 2.50 +0.1/-0.00 N a 1 6.35 b 64.77 P2 10.00 B2 19.80 B1 28.575 +/-0.15 B 4x 4.00+/-0.1 V1 92 3.99 MAX 49.53 P3 120.65 P1 93 184 6.35 X 2.175 X1 X2 4.175 D 1.0 +/-0.05 G V 2.50 0.20 +/-0.15 T 3.80 W 1.80 MAX 0.178 Detail A D1 E 1.27 Detail B Tolerances : 0.005(.13) unless otherwise specified The used device is 64Mx8, 128Mx4 DDR SDRAM, FBGA DDR SDRAM Part No. : K4H510838B, K4H510438B Rev. 1.0 June 2005 512MB, 1GB, 2GB Registered DIMM DDR SDRAM 17.6 256Mx72 (M312L5720BG(Z)0) Units : Millimeters 133.35 A 128.95 A 1.27 +/-0.1 2x 3.00 MIN W1 12.0 10.0 1 2x DIA. 2.50 +0.1/-0.00 N 6.35 a 64.77 P2 b 10.00 B2 19.80 B1 30.48 +/-0.15 B 4x 4.00+/-0.1 V1 92 3.99 MAX 49.53 P3 120.65 P1 93 184 6.35 X 2.175 X1 X2 4.175 D 1.0 +/-0.05 V 2.50 +/-0.2 G 0.20 +/-0.15 T 3.80 W 1.80 MAX 0.178 Detail A D1 E 1.27 Detail B Tolerances : 0.005(.13) unless otherwise specified The used device is 128Mx4 DDR SDRAM, FBGA DDR SDRAM Part No : K4H510438B Rev. 1.0 June 2005