CY7C1354B-225BZI - Cypress Semiconductor

9-Mb (256K x 36/512K x 18) Pipelined SRAM

with NoBL™ Architecture

CY7C1354B

CY7C1356B

Cypress Semiconductor Corporation • 3901 North First Street • San Jose,CA 95134 • 408-943-2600

Document #: 38-05114 Rev. *C Revised June 16, 2004

Features

• Pin-compatible and functionally equivalent to ZBT

• Supports 225-MHz bus operations with zero wait states

— Available speed grades are 225, 200, and 166 MHz

• Internally self-timed output buffer control to eliminate

the need to use asynchronous OE

• Fully registered (inputs and outputs) for pipelined op-

eration

• Byte Write capability

• Separate VDDQ for 3.3V or 2.5V I/O

• Single 3.3V power supply

• Fast clock-to-output times

— 2.8 ns (for 225-MHz device)

— 3.2ns (for 200-MHz device)

— 3.5 ns (for 166-MHz device)

• Clock Enable (CEN) pin to suspend operation

• Synchronous self-timed writes

• Available in 100 TQFP, 119 BGA, and 165 fBGA packag-

• IEEE 1149.1 JTAG Boundary Scan

•Burst capability–linear or interleaved burst order

• “ZZ” Sleep Mode option and Stop Clock option

Functional Description

The CY7C1354B and CY7C1356B are 3.3V, 256K x 36 and

512K x 18 Synchronous pipelined burst SRAMs with No Bus

Latency™ (NoBL) logic, respectively. They are designed to

support unlimited true back-to-back Read/Write operations

with no wait states. The CY7C1354B and CY7C1356B are

equipped with the advanced (NoBL) logic required to enable

consecutive Read/Write operations with data being trans-

ferred on every clock cycle. This feature dramatically improves

the throughput of data in systems that require frequent

Write/Read transitions. The CY7C1354B and CY7C1356B are

pin compatible and functionally equivalent to ZBT devices.

All synchronous inputs pass through input registers controlled

by the rising edge of the clock. All data outputs pass through

output registers controlled by the rising edge of the clock. The

clock input is qualified by the Clock Enable (CEN) signal,

which when deasserted suspends operation and extends the

previous clock cycle.

Write operations are controlled by the Byte Write Selects

(BWa–BWd for CY7C1354B and BWa–BWb for CY7C1356B)

and a Write Enable (WE) input. All writes are conducted with

on-chip synchronous self-timed write circuitry.

Three synchronous Chip Enables (CE1, CE2, CE3) and an

asynchronous Output Enable (OE) provide for easy bank

selection and output three-state control. In order to avoid bus

contention, the output drivers are synchronously three-stated

during the data portion of a write sequence.

A0, A1, A

MODE

CE1

CE2

CE3

READ LOGIC

DQs

DQP

MEMORY

ARRAY

INPUT

ADDRESS

WRITE ADDRESS

WRITE REGISTRY

AND DATA COHERENCY

CONTROL LOGIC

BURST

LOGIC A0'

A1'

D0 Q1

ADV/LD

INPUT

CLK

WRITE

DRIVERS

SLEEP

CONTROL

Logic Block Diagram-CY7C1354B (256K x 36)

CY7C1354B

CY7C1356B

Document #: 38-05114 Rev. *C Page 2 of 29

Selection Guide

CY7C1354B-225

CY7C1356B-225

CY7C1354B-200

CY7C1356B-200

CY7C1354B-166

CY7C1356B-166 Unit

Maximum Access Time 2.8 3.2 3.5 ns

Maximum Operating Current 250 220 180 mA

Maximum CMOS Standby Current 35 35 35 mA

Shaded areas contain advance information.

Please contact your local Cypress sales representative for availability of these parts.

A0, A1, A

MODE

CE1

CE2

CE3

READ LOGIC

DQs

DQP

MEMORY

ARRAY

INPUT

ADDRESS

WRITE ADDRESS

WRITE REGISTRY

AND DATA COHERENCY

CONTROL LOGIC

BURST

LOGIC A0'

A1'

D0 Q1

ADV/LD

INPUT

CLK

WRITE

DRIVERS

Sleep

Control

Logic Block Diagram-CY7C1356B (512K x 18)

CY7C1354B

CY7C1356B

Document #: 38-05114 Rev. *C Page 3 of 29

Pin Configurations

DDQ

DQb

DDQ

DQb

DQa

DDQ

DQa

DDQ

DQc

DDQ

DQc

DQd

DDQ

DQd

DDQ

BWa

CLK

CEN

E(18)

100

ADV/LD

CY7C1354B

100-pin TQFP Packages

DDQ

DQP

DQa

DDQ

DQa

DDQ

DQa

DDQ

DQb

DDQ

DQb

DDQ

DQb

DQPb

DDQ

BWb

BWa

CLK

CEN

E(18)

100

ADV/LD

MODE

CY7C1356B

BWd

MODE

BWc

DQc

DQPc

DQd

DQPb

DQb

DQa

DQPa

DQb

(256K × 36)

(512K × 18)

BWb

DQc

E(288)

E(144)

E(72)

E(36)

E(288)

E(144)

E(72)

E(36)

DQPd

CY7C1354B

CY7C1356B

Document #: 38-05114 Rev. *C Page 4 of 29

Pin Configurations (continued)

2345671

DQa

VDDQ

DQc

DQd

DQc

DQd

AA AAE(18) VDDQ

CE2A

VDDQ

DQc

DQd

TMS

VDD

E(72)

DQPd

ADV/LD ACE

3NC

VDD AANC

VSS VSS

NC DQPb

DQb

DQa

DQb

DQa

NCTDI TDO VDDQ

TCK

VSS

MODE

CE1VSS

OE VSS VDDQ

BWcA

VSS

VDDQ

VDD NC VDD

VSS

CLK

NC BWa

CEN VSS VDDQ

VSS

NCA

A0 VSS

VDD NC

CY7C1354B (256K × 36) – 14 × 22 BGA

DQPcDQb

AE(36)

DQcDQb

DQc

DQb

DQa

DQPa

DQd

BWd

119-ball BGA Pinout

BWb

2345671

E(36)

DQa

VDDQ

NCDQb

DQb

AA AAE(18) VDDQ

CE2A

VDDQ

E(72)

DQb

TMS

VDD

DQPb

ADV/LD ACE3NC

VDD AANC

VSS VSS

NC NCDQPa

DQa

NCTDI TDO VDDQ

TCK

VSS

MODE

CE1VSS NC

OE VSS VDDQ

BWbAV

SS NC

VSS

WE NC

VDDQ

VDD NC VDD

NCVSS

CLK

NC NC

BWa

CEN VSS NC VDDQ

VSS NC

A0 VSS NC

VDD NC

CY7C1356B (512K x 18)–14 x 22 BGA

CY7C1354B

CY7C1356B

Document #: 38-05114 Rev. *C Page 5 of 29

Pin Configurations (continued)

234 5671

TDO

E(288)

DQPc

DQc

DQPd

DQd

ACE1BWb CE3

BWcCEN

ACE2

DQc

DQd

MODE

DQc

DQd

E(36)

E(72)

VDDQ

BWdBWaCLK WE

VSS VSS VSS VSS

VDDQ VSS

VDD VSS

VSS

VDDQ

VDD VSS

VDD VSS VSS

VDDQ VDD

VSS

VDD

VSS

VDD VSS VSS

VSS

VDD

VDD VSS

VDD VSS VSS

TCKA0

VSS

TDI

DQcVSS

DQc

VSS

DQd

VDDQ

VSS

TMS

891011

AAADV/LD NC

OE E(18) AE(144)

VSS VDDQ NC DQPb

VDDQ

VDD DQb

DQb

DQa

VDD VDDQ

VDD VDDQ DQb

VDD

DQa

VDD VDDQ DQa

VDDQ

VDD

VDD VDDQ

VDD VDDQ DQa

VDDQ

VSS

DQb

DQa

DQPa

DQa

VDDQ

234 5671

TDO

E(288)

DQPb

DQb

ACE1NC CE3

BWbCEN

ACE2

DQb

MODE

DQb

E(36)

E(72)

VDDQ

NC BWaCLK WE

VSS VSS VSS VSS

VDDQ VSS

VDD VSS

VSS

VDDQ

VDD VSS

VDD VSS VSS

VDDQ VDD

VSS

VDD

VSS

VDD VSS VSS

VSS

VDD

VDD VSS

VDD VSS VSS

TCKA0

VSS

TDI

DQbVSS

NC VSS

DQb

VSS

DQb

VDDQ

VSS

TMS

891011

ADV/LD A

OE E(18) AE(144)

VSS VDDQ NC DQPa

VDDQ

VDD NC

DQa

VDD VDDQ

VDD VDDQ DQa

VDD

NCVDD VDDQ DQa

VDDQ

VDD

VDD VDDQ

VDD VDDQ NC

VDDQ

VSS

DQa

VDDQ

CY7C1356B (512K × 18) – 13 × 15 fBGA

CY7C1354B (256K × 36) – 13 × 15 fBGA

165-Ball fBGA Pinout

CY7C1354B

CY7C1356B

Document #: 38-05114 Rev. *C Page 6 of 29

Pin Definitions

Pin Name I/O Type Pin Description

Input-

Synchronous

Address Inputs used to select one of the address locations. Sampled at the rising edge of

the CLK.

BWa

BWb

BWc

BWd

Input-

Synchronous

Byte Write Select Inputs, active LOW. Qualified with WE to conduct writes to the SRAM. Sam-

pled on the rising edge of CLK. BWa controls DQa and DQPa, BWb controls DQb and DQPb, BWc

controls DQc and DQPc, BWd controls DQd and DQPd.

WE Input-

Synchronous

Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This

signal must be asserted LOW to initiate a write sequence.

ADV/LD Input-

Synchronous

Advance/Load Input used to advance the on-chip address counter or load a new address.

When HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a

new address can be loaded into the device for an access. After being deselected, ADV/LD should

be driven LOW in order to load a new address.

CLK Input-

Clock

Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN.

CLK is only recognized if CEN is active LOW.

CE1Input-

Synchronous

Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with

CE2 and CE3 to select/deselect the device.

CE2Input-

Synchronous

Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with

CE1 and CE3 to select/deselect the device.

CE3Input-

Synchronous

Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with

CE1 and CE2 to select/deselect the device.

OE Input-

Asynchronous

Output Enable, active LOW. Combined with the synchronous logic block inside the device to

control the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as outputs.

When deasserted HIGH, I/O pins are three-stated, and act as input data pins. OE is masked

during the data portion of a Write sequence, during the first clock when emerging from a dese-

lected state and when the device has been deselected.

CEN Input-

Synchronous

Clock Enable Input, active LOW. When asserted LOW the clock signal is recognized by the

SRAM. When deasserted HIGH the clock signal is masked. Since deasserting CEN does not

deselect the device, CEN can be used to extend the previous cycle when required.

DQa

DQb

DQc

DQd

I/O-

Synchronous

Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered

by the rising edge of CLK. As outputs, they deliver the data contained in the memory location

specified by addresses during the previous clock rise of the Read cycle. The direction of the pins

is controlled by OE and the internal control logic. When OE is asserted LOW, the pins can behave

as outputs. When HIGH, DQa–DQd are placed in a three-state condition. The outputs are auto-

matically three-stated during the data portion of a write sequence, during the first clock when

emerging from a deselected state, and when the device is deselected, regardless of the state of

OE.

DQPa

DQPb

DQPc

DQPd

I/O-

Synchronous

Bidirectional Data Parity I/O lines. Functionally, these signals are identical to DQ[a:d]. During

write sequences, DQPa is controlled by BWa, DQPb is controlled by BWb, DQPc is controlled

by BWc, and DQPd is controlled by BWd.

MODE Input Strap Pin Mode Input. Selects the burst order of the device. Tied HIGH selects the interleaved burst order.

Pulled LOW selects the linear burst order. MODE should not change states during operation.

When left floating MODE will default HIGH, to an interleaved burst order.

TDO JTAG serial output

Synchronous

Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK.

TDI JTAG serial input

Synchronous

Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK.

TMS Test Mode Select

Synchronous

This pin controls the Test Access Port state machine. Sampled on the rising edge of TCK.

TCK JTAG-Clock Clock input to the JTAG circuitry.

VDD Power Supply Power supply inputs to the core of the device.

VDDQ I/O Power Supply Power supply for the I/O circuitry.

VSS Ground Ground for the device. Should be connected to ground of the system.

CY7C1354B

CY7C1356B

Document #: 38-05114 Rev. *C Page 7 of 29

Introduction

Functional Overview

The CY7C1354B and CY7C1356B are synchronous-pipelined

Burst NoBL SRAMs designed specifically to eliminate wait

states during Write/Read transitions. All synchronous inputs

pass through input registers controlled by the rising edge of

the clock. The clock signal is qualified with the Clock Enable

input signal (CEN). If CEN is HIGH, the clock signal is not

recognized and all internal states are maintained. All

synchronous operations are qualified with CEN. All data

outputs pass through output registers controlled by the rising

edge of the clock. Maximum access delay from the clock rise

(tCO) is 2.8 ns (225-MHz device).

Accesses can be initiated by asserting all three Chip Enables

(CE1, CE2, CE3) active at the rising edge of the clock. If Clock

Enable (CEN) is active LOW and ADV/LD is asserted LOW,

the address presented to the device will be latched. The

access can either be a Read or Write operation, depending on

the status of the Write Enable (WE). BW[d:a] can be used to

conduct Byte Write operations.

Write operations are qualified by the Write Enable (WE). All

Writes are simplified with on-chip synchronous self-timed

Write circuitry.

Three synchronous Chip Enables (CE1, CE2, CE3) and an

asynchronous Output Enable (OE) simplify depth expansion.

All operations (Reads, Writes, and Deselects) are pipelined.

ADV/LD should be driven LOW once the device has been

deselected in order to load a new address for the next

operation.

Single Read Accesses

A read access is initiated when the following conditions are

satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,

and CE3 are ALL asserted active, (3) the Write Enable input

signal WE is deasserted HIGH, and (4) ADV/LD is asserted

LOW. The address presented to the address inputs is latched

into the address register and presented to the memory core

and control logic. The control logic determines that a read

access is in progress and allows the requested data to

propagate to the input of the output register. At the rising edge

of the next clock the requested data is allowed to propagate

through the output register and onto the data bus within 2.8 ns

(225-MHz device) provided OE is active LOW. After the first

clock of the read access the output buffers are controlled by

OE and the internal control logic. OE must be driven LOW in

order for the device to drive out the requested data. During the

second clock, a subsequent operation (Read/Write/Deselect)

can be initiated. Deselecting the device is also pipelined.

Therefore, when the SRAM is deselected at clock rise by one

of the chip enable signals, its output will three-state following

the next clock rise.

Burst Read Accesses

The CY7C1354B and CY7C1356B have an on-chip burst

counter that allows the user the ability to supply a single

address and conduct up to four Reads without reasserting the

address inputs. ADV/LD must be driven LOW in order to load

a new address into the SRAM, as described in the Single Read

Access section above. The sequence of the burst counter is

determined by the MODE input signal. A LOW input on MODE

selects a linear burst mode, a HIGH selects an interleaved

burst sequence. Both burst counters use A0 and A1 in the

burst sequence, and will wrap around when incremented suffi-

ciently. A HIGH input on ADV/LD will increment the internal

burst counter regardless of the state of chip enables inputs or

WE. WE is latched at the beginning of a burst cycle. Therefore,

the type of access (Read or Write) is maintained throughout

the burst sequence.

Single Write Accesses

Write access are initiated when the following conditions are

satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,

and CE3 are ALL asserted active, and (3) the Write signal WE

is asserted LOW. The address presented to A0∠A16 is loaded

into the Address Register. The write signals are latched into

the Control Logic block.

On the subsequent clock rise the data lines are automatically

three-stated regardless of the state of the OE input signal. This

allows the external logic to present the data on DQ and DQP

(DQa,b,c,d/DQPa,b,c,d for CY7C1354B and DQa,b/DQPa,b for

CY7C1356B). In addition, the address for the subsequent

access (Read/Write/Deselect) is latched into the address

asserted).

On the next clock rise the data presented to DQ and DQP

(DQa,b,c,d/DQPa,b,c,d for CY7C1354B and DQa,b/DQPa,b for

CY7C1356B) (or a subset for byte write operations, see Write

Cycle Description table for details) inputs is latched into the

device and the Write is complete.

The data written during the Write operation is controlled by BW

(BWa,b,c,d for CY7C1354B and BWa,b for CY7C1356B)

signals. The CY7C1354B/56B provides Byte Write capability

that is described in the Write Cycle Description table. Asserting

the Write Enable input (WE) with the selected Byte Write

Select (BW) input will selectively write to only the desired

bytes. Bytes not selected during a Byte Write operation will

remain unaltered. A synchronous self-timed write mechanism

has been provided to simplify the Write operations. Byte Write

capability has been included in order to greatly simplify

NC – No connects. This pin is not connected to the die.

E(18,36,

72, 144,

288)

–These pins are not connected. They will be used for expansion to the 18M, 36M, 72M, 144M

and 288M densities.

ZZ Input-

Asynchronous

ZZ “sleep” Input. This active HIGH input places the device in a non-time critical “sleep” condition

with data integrity preserved. During normal operation, this pin can be connected to VSS or left

floating.

Pin Definitions (continued)

Pin Name I/O Type Pin Description

CY7C1354B

CY7C1356B

Document #: 38-05114 Rev. *C Page 8 of 29

Read/Modify/Write sequences, which can be reduced to

simple Byte Write operations.

Because the CY7C1354B and CY7C1356B are common I/O

devices, data should not be driven into the device while the

outputs are active. The Output Enable (OE) can be deasserted

HIGH before presenting data to the DQ and DQP

(DQa,b,c,d/DQPa,b,c,d for CY7C1354B and DQa,b/DQPa,b for

CY7C1356B) inputs. Doing so will three-state the output

drivers. As a safety precaution, DQ and DQP (DQa,b,c,d/

DQPa,b,c,d for CY7C1354B and DQa,b/DQPa,b for

CY7C1356B) are automatically three-stated during the data

portion of a write cycle, regardless of the state of OE.

Burst Write Accesses

The CY7C1354B/56B has an on-chip burst counter that allows

the user the ability to supply a single address and conduct up

to four WRITE operations without reasserting the address

inputs. ADV/LD must be driven LOW in order to load the initial

address, as described in the Single Write Access section

above. When ADV/LD is driven HIGH on the subsequent clock

rise, the chip enables (CE1, CE2, and CE3) and WE inputs are

ignored and the burst counter is incremented. The correct BW

(BWa,b,c,d for CY7C1354B and BWa,b for CY7C1356B) inputs

must be driven in each cycle of the burst write in order to write

the correct bytes of data.

Sleep Mode

The ZZ input pin is an asynchronous input. Asserting ZZ

places the SRAM in a power conservation “sleep” mode. Two

clock cycles are required to enter into or exit from this “sleep”

mode. While in this mode, data integrity is guaranteed.

Accesses pending when entering the “sleep” mode are not

considered valid nor is the completion of the operation

guaranteed. The device must be deselected prior to entering

the “sleep” mode. CE1, CE2, and CE3, must remain inactive for

the duration of tZZREC after the ZZ input returns LOW.

Interleaved Burst Address Table

(MODE = Floating or VDD)

First

Address

Second

Address

Third

Address

Fourth

Address

A1,A0 A1,A0 A1,A0 A1,A0

00 01 10 11

01 00 11 10

10 11 00 01

11 10 01 00

Linear Burst Address Table

(MODE = GND)

First

Address

Second

Address

Third

Address

Fourth

Address

A1,A0 A1,A0 A1,A0 A1,A0

00 01 10 11

01 10 11 00

10 11 00 01

11 00 01 10

ZZ Mode Electrical Characteristics

Parameter Description Test Conditions Min. Max Unit

IDDZZ Sleep mode standby current ZZ > VDD − 0.2V 35 mA

tZZS Device operation to ZZ ZZ > VDD − 0.2V 2tCYC ns

tZZREC ZZ recovery time ZZ < 0.2V 2tCYC ns

tZZI ZZ active to sleep current This parameter is sampled 2tCYC ns

tRZZI ZZ Inactive to exit sleep current This parameter is sampled 0 ns

CY7C1354B

CY7C1356B

Document #: 38-05114 Rev. *C Page 9 of 29

Truth Table[1, 2, 3, 4, 5, 6, 7]

Operation

Address

Used CE ZZ ADV/LD WE BWx OE CEN CLK DQ

Deselect Cycle None H L L X X X L L-H Three-State

Continue

Deselect Cycle

None X L H X X X L L-H Three-State

Read Cycle

(Begin Burst)

External L L L H X L L L-H Data Out (Q)

Read Cycle

(Continue Burst)

Next X L H X X L L L-H Data Out (Q)

NOP/Dummy

Read

(Begin Burst)

External L L L H X H L L-H Three-State

Dummy Read

(Continue Burst)

Next X L H X X H L L-H Three-State

Write Cycle

(Begin Burst)

External L L L L L X L L-H Data In (D)

Write Cycle

(Continue Burst)

Next X L H X L X L L-H Data In (D)

NOP/WRITE

ABORT

(Begin Burst)

None L L L L H X L L-H Three-State

WRITE ABORT

(Continue Burst)

Next X L H X H X L L-H Three-State

IGNORE

CLOCK EDGE

(Stall)

Current X L X X X X H L-H -

Sleep MODE None X H X X X X X X Three-State

Notes:

1. X = “Don't Care”, 1 = Logic HIGH, 0 = Logic LOW, CE stands for ALL Chip Enables active. BWx = 0 signifies at least one Byte Write Select is active, BWx =

Valid signifies that the desired Byte Write Selects are asserted, see Write Cycle Description table for details.

2. Write is defined by WE and BW[a:d]. See Write Cycle Description table for details.

3. When a write cycle is detected, all I/Os are three-stated, even during Byte Writes.

4. The DQ and DQP pins are controlled by the current cycle and the OE signal.

5. CEN = H inserts wait states.

6. Device will power-up deselected and the I/Os in a three-state condition, regardless of OE.

7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQs and DQP[a:d] = Three-state when

OE is inactive or when the device is deselected, and DQs = data when OE is active.

CY7C1354B

CY7C1356B

Document #: 38-05114 Rev. *C Page 10 of 29

IEEE 1149.1 Serial Boundary Scan (JTAG)

The CY7C1354B/CY7C1354B incorporates a serial boundary

scan Test Access Port (TAP) in the BGA package only. The

TQFP package does not offer this functionality. This port

operates in accordance with IEEE Standard 1149.1-1900, but

does not have the set of functions required for full 1149.1

compliance. These functions from the IEEE specification are

excluded because their inclusion places an added delay in the

critical speed path of the SRAM. Note that the TAP controller

functions in a manner that does not conflict with the operation

of other devices using 1149.1 fully compliant TAPs. The TAP

operates using JEDEC standard 3.3V I/O logic levels.

Disabling the JTAG Feature

It is possible to operate the SRAM without using the JTAG

feature. To disable the TAP controller, TCK must be tied LOW

(VSS) to prevent clocking of the device. TDI and TMS are inter-

nally pulled up and may be unconnected. They may alternately

be connected to VDD through a pull-up resistor. TDO should

be left unconnected. Upon power-up, the device will come up

in a reset state which will not interfere with the operation of the

device.

Test Access Port–Test Clock

The test clock is used only with the TAP controller. All inputs

are captured on the rising edge of TCK. All outputs are driven

from the falling edge of TCK.

Test Mode Select

The TMS input is used to give commands to the TAP controller

and is sampled on the rising edge of TCK. It is allowable to

leave this pin unconnected if the TAP is not used. The pin is

pulled up internally, resulting in a logic HIGH level.

Test Data-In (TDI)

The TDI pin is used to serially input information into the

registers and can be connected to the input of any of the

registers. The register between TDI and TDO is chosen by the

instruction that is loaded into the TAP instruction register. For

information on loading the instruction register, see the TAP

Controller State Diagram. TDI is internally pulled up and can

be unconnected if the TAP is unused in an application. TDI is

connected to the Most Significant Bit (MSB) on any register.

Test Data Out (TDO)

The TDO output pin is used to serially clock data-out from the

registers. The output is active depending upon the current

state of the TAP state machine (see TAP Controller State

Partial Write Cycle Description[1, 2, 3, 8]

Function (CY7C1354B) WE BWdBWcBWbBWa

Read H X X X X

Write –No bytes written L H H H H

Write Byte a– (DQa and DQPa) LHHHL

Write Byte b – (DQb and DQPb) LHHLH

Write Bytes b, a L H H L L

Write Byte c – (DQc and DQPc) LHLHH

Write Bytes c, a L H L H L

Write Bytes c, b L H L L H

Write Bytes c, b, a L H L L L

Write Byte d – (DQd and DQPd) LLHHH

Write Bytes d, a L L H H L

Write Bytes d, b LLHLH

Write Bytes d, b, a L L H L L

Write Bytes d, c L L L H H

Write Bytes d, c, a L L L H L

Write Bytes d, c, b L L L L H

Write All Bytes L L L L L

Note:

8. Table only lists a partial listing of the byte write combinations. Any combination of BW[a:d] is valid. Appropriate write will be done based on which byte write is active.

Function (CY7C1356B) WE BWbBWa

Read Hxx

Write – No Bytes Written L H H

Write Byte a − (DQa and DQPa) LHL

Write Byte b – (DQb and DQPb) LLH

Write Both Bytes L L L

CY7C1354B

CY7C1356B

Document #: 38-05114 Rev. *C Page 11 of 29

Diagram). The output changes on the falling edge of TCK.

TDO is connected to the Least Significant Bit (LSB) of any

Performing a TAP Reset

A Reset is performed by forcing TMS HIGH (VDD) for five rising

edges of TCK. This RESET does not affect the operation of

the SRAM and may be performed while the SRAM is

operating. At power-up, the TAP is reset internally to ensure

that TDO comes up in a High-Z state.

TAP Registers

Registers are connected between the TDI and TDO pins and

allow data to be scanned into and out of the SRAM test

circuitry. Only one register can be selected at a time through

the instruction registers. Data is serially loaded into the TDI pin

on the rising edge of TCK. Data is output on the TDO pin on

the falling edge of TCK.

Instruction Register

Three-bit instructions can be serially loaded into the instruction

TDI and TDO pins as shown in the TAP Controller Block

Diagram. Upon power-up, the instruction register is loaded

with the IDCODE instruction. It is also loaded with the IDCODE

instruction if the controller is placed in a reset state as

described in the previous section.

When the TAP controller is in the Capture-IR state, the two

least significant bits are loaded with a binary “01” pattern to

allow for fault isolation of the board level serial test path.

Bypass Register

To save time when serially shifting data through registers, it is

sometimes advantageous to skip certain states. The bypass

and TDO pins. This allows data to be shifted through the

SRAM with minimal delay. The bypass register is set LOW

(VSS) when the BYPASS instruction is executed.

Boundary Scan Register

The boundary scan register is connected to all the input and

output pins on the SRAM. Several no connect (NC) pins are

also included in the scan register to reserve pins for higher

density devices. The ×36 configuration has a 69-bit-long

The boundary scan register is loaded with the contents of the

RAM Input and Output ring when the TAP controller is in the

Capture-DR state and is then placed between the TDI and

TDO pins when the controller is moved to the Shift-DR state.

The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instruc-

tions can be used to capture the contents of the Input and

Output ring.

The Boundary Scan Order tables show the order in which the

bits are connected. Each bit corresponds to one of the bumps

on the SRAM package. The MSB of the register is connected

to TDI, and the LSB is connected to TDO.

Identification (ID) Register

The ID register is loaded with a vendor-specific, 32-bit code

during the Capture-DR state when the IDCODE command is

loaded in the instruction register. The IDCODE is hardwired

into the SRAM and can be shifted out when the TAP controller

is in the Shift-DR state. The ID register has a vendor code and

other information described in the Identification Register

Definitions table.

TAP Instruction Set

Eight different instructions are possible with the three-bit

instruction register. All combinations are listed in the

Instruction Code table. Three of these instructions are listed

as RESERVED and should not be used. The other five instruc-

tions are described in detail below.

The TAP controller used in this SRAM is not fully compliant to

the 1149.1 convention because some of the mandatory 1149.1

instructions are not fully implemented. The TAP controller

cannot be used to load address, data, or control signals into

the SRAM and cannot preload the Input or Output buffers. The

SRAM does not implement the 1149.1 commands EXTEST or

INTEST or the PRELOAD portion of SAMPLE/PRELOAD;

rather it performs a capture of the Inputs and Output ring when

these instructions are executed.

Instructions are loaded into the TAP controller during the

Shift-IR state when the instruction register is placed between

TDI and TDO. During this state, instructions are shifted

through the instruction register through the TDI and TDO pins.

To execute the instruction once it is shifted in, the TAP

controller needs to be moved into the Update-IR state.

EXTEST

EXTEST is a mandatory 1149.1 instruction which is to be

executed whenever the instruction register is loaded with all

0s. EXTEST is not implemented in the TAP controller, and

therefore this device is not compliant to the 1149.1 standard.

The TAP controller does recognize an all-0 instruction. When

an EXTEST instruction is loaded into the instruction register,

the SRAM responds as if a SAMPLE/PRELOAD instruction

has been loaded. There is one difference between the two

instructions. Unlike the SAMPLE/PRELOAD instruction,

EXTEST places the SRAM outputs in a High-Z state.

IDCODE

The IDCODE instruction causes a vendor-specific, 32-bit code

to be loaded into the instruction register. It also places the

instruction register between the TDI and TDO pins and allows

the IDCODE to be shifted out of the device when the TAP

controller enters the Shift-DR state. The IDCODE instruction

is loaded into the instruction register upon power-up or

whenever the TAP controller is given a test logic reset state.

SAMPLE Z

The SAMPLE Z instruction causes the boundary scan register

to be connected between the TDI and TDO pins when the TAP

controller is in a Shift-DR state. It also places all SRAM outputs

into a High-Z state.

SAMPLE/PRELOAD

SAMPLE/PRELOAD is a 1149.1 mandatory instruction. The

PRELOAD portion of this instruction is not implemented, so

the TAP controller is not fully 1149.1-compliant.

When the SAMPLE/PRELOAD instructions are loaded into the

instruction register and the TAP controller is in the Capture-DR

state, a snapshot of data on the inputs and output pins is

captured in the boundary scan register.

CY7C1354B

CY7C1356B

Document #: 38-05114 Rev. *C Page 12 of 29

The user must be aware that the TAP controller clock can only

operate at a frequency up to 10 MHz, while the SRAM clock

operates more than an order of magnitude faster. Because

there is a large difference in the clock frequencies, it is

possible that during the Capture-DR state, an input or output

will undergo a transition. The TAP may then try to capture a

signal while in transition (metastable state). This will not harm

the device, but there is no guarantee as to the value that will

be captured. Repeatable results may not be possible.

To guarantee that the boundary scan register will capture the

correct value of a signal, the SRAM signal must be stabilized

long enough to meet the TAP controller's capture set-up plus

hold times (tCS and tCH). The SRAM clock input might not be

captured correctly if there is no way in a design to stop (or

slow) the clock during a SAMPLE/PRELOAD instruction. If this

is an issue, it is still possible to capture all other signals and

simply ignore the value of the CK and CK captured in the

boundary scan register.

Once the data is captured, it is possible to shift out the data by

putting the TAP into the Shift-DR state. This places the

boundary scan register between the TDI and TDO pins.

Note that since the PRELOAD part of the command is not

implemented, putting the TAP into the Update to the

Update-DR state while performing a SAMPLE/PRELOAD

instruction will have the same effect as the Pause-DR

command.

Bypass

When the BYPASS instruction is loaded in the instruction

advantage of the BYPASS instruction is that it shortens the

boundary scan path when multiple devices are connected

together on a board.

Reserved

These instructions are not implemented but are reserved for

future use. Do not use these instructions.

CY7C1354B

CY7C1356B

Document #: 38-05114 Rev. *C Page 13 of 29

TAP Controller State Diagram

Note:

9. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.

TEST-LOGIC

RESET

TEST-LOGIC/

IDLE

SELECT

DR-SCAN

CAPTURE-DR

SHIFT-DR

EXIT1-DR

PAUSE-DR

EXIT2-DR

UPDATE-DR

SELECT

IR-SCAN

CAPTURE-DR

SHIFT-IR

EXIT1-IR

PAUSE-IR

EXIT2-IR

UPDATE-IR

CY7C1354B

CY7C1356B

Document #: 38-05114 Rev. *C Page 14 of 29

TAP Electrical Characteristics Over the Operating Range[10, 11]

Parameter Description Test Conditions Min. Max. Unit

VOH1 Output HIGH Voltage IOH = 2.0 mA, VDDQ = 3.3V 2.0 V

IOH = 2.0 mA, VDDQ = 2.5V 1.7 V

VOH2 Output HIGH Voltage IOH = 100 µA, VDDQ = 3.3V 2.0 V

IOH = 100 µA, VDDQ = 2.5V 2.0 V

VOL1 Output LOW Voltage IOL = 2.0 mA 0.7 V

VOL2 Output LOW Voltage IOL = 100 µA0.2V

VIH Input HIGH Voltage 1.7 VDD + 0.3 V

VIL Input LOW Voltage –0.3 0.7 V

IXInput Load Current GND ≤ VI ≤ VDDQ –30 30 µA

IXInput Load Current TMS and TDI GND ≤ VI ≤ VDDQ –30 30 µA

TAP AC Switching Characteristics Over the Operating Range [12, 13]

Parameter Description Min. Max. Unit

tTCYC TCK Clock Cycle Time 100 ns

tTF TCK Clock Frequency 10 MHz

tTH TCK Clock HIGH 40 ns

tTL TCK Clock LOW 40 ns

Set-up Times

tTMSS TMS Set-up to TCK Clock Rise 10 ns

tTDIS TDI Set-up to TCK Clock Rise 10 ns

tCS Capture Set-up to TCK Rise 10 ns

Notes:

10. All voltage referenced to ground.

11. Overshoot: VIH(AC) < VDD + 1.5V for t < tTCYC/2; undershoot: VIL(AC) > –0.5V for t < tTCYC/2.

12. tCS and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register.

13. Test conditions are specified using the load in TAP AC test conditions. tR/tF = 1 ns.

012..

3031

Boundary Scan Register

Identification Register

012..

.68

012

Instruction Register

Bypass Register

Selection

Circuitry

Selection

Circuitry

TAP Controller

TDI TDO

TCK

TMS

CY7C1354B

CY7C1356B

Document #: 38-05114 Rev. *C Page 15 of 29

Hold Times

tTMSH TMS Hold after TCK Clock Rise 10 ns

tTDIH TDI Hold after Clock Rise 10 ns

tCH Capture Hold after clock rise 10 ns

Output Times

tTDOV TCK Clock LOW to TDO Valid 20 ns

tTDOX TCK Clock LOW to TDO Invalid 0 ns

TAP Timing and Test Conditions

TAP AC Switching Characteristics Over the Operating Range (continued)[12, 13]

Parameter Description Min. Max. Unit

(a)

TDO

CL= 20 pF

Z0= 50Ω

GND

50Ω

Test Clock

Test Mode Select

TCK

TMS

Test Data-In

TDI

Test Data-Out

tTCYC

tTMSH

tTL

tTH

tTMSS

tTDIS tTDIH

tTDOV tTDOX

TDO

1.5V for 3.3V VDDQ

1.25V for 2.5V VDDQ 3.0V

VSS

ALL INPUT PULSES

1.5V

1.5 ns

Identification Register Definitions

Instruction Field CY7C1354B CY7C1356B Description

Revision Number (31:29) 001 001 Reserved for version number.

Cypress Device ID (28:12) 01010001000100110 01010001000010110 Reserved for future use.

Cypress JEDEC ID (11:1) 00000110100 00000110100 Allows unique identification of SRAM vendor.

ID Register Presence (0) 1 1 Indicate the presence of an ID register.

CY7C1354B

CY7C1356B

Document #: 38-05114 Rev. *C Page 16 of 29

Scan Register Sizes

Instruction 3

Bypass 1

ID 32

Boundary Scan 69

Identification Codes

Instruction Code Description

EXTEST 000 Captures the Input/Output ring contents. Places the boundary scan register between the TDI and

TDO. Forces all SRAM outputs to High-Z state. This instruction is not 1149.1-compliant.

IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and TDO. This

operation does not affect SRAM operation.

SAMPLE Z 010 Captures the Input/Output contents. Places the boundary scan register between TDI and TDO.

Forces all SRAM output drivers to a High-Z state.

RESERVED 011 Do Not Use: This instruction is reserved for future use.

SAMPLE/PRELOAD 100 Captures the Input/Output ring contents. Places the boundary scan register between TDI and TDO.

Does not affect the SRAM operation. This instruction does not implement 1149.1 preload function

and is therefore not 1149.1-compliant.

RESERVED 101 Do Not Use: This instruction is reserved for future use.

RESERVED 110 Do Not Use: This instruction is reserved for future use.

BYPASS 111 Places the bypass register between TDI and TDO. This operation does not affect SRAM operation.

Boundary Scan Exit Order (×36)

Bit # 119-Ball ID 165-Ball ID

1K4 B6

2H4 B7

3M4 A7

4F4 B8

5B4 A8

6G4 A9

7C3 B10

8B3 A10

9D6 C11

10 H7 E10

11 G6 F10

12 E6 G10

13 D7 D10

14 E7 D11

15 F6 E11

16 G7 F11

17 H6 G11

18 T7 H11

19 K7 J10

20 L6 K10

21 N6 L10

22 P7 M10

23 N7 J11

24 M6 K11

25 L7 L11

26 K6 M11

27 P6 N11

28 T4 R11

29 A3 R10

30 C5 P10

31 B5 R9

32 A5 P9

33 C6 R8

34 A6 P8

35 P4 R6

36 N4 P6

37 R6 R4

38 T5 P4

39 T3 R3

40 R2 P3

41 R3 R1

42 P2 N1

43 P1 L2

44 L2 K2

45 K1 J2

46 N2 M2

Boundary Scan Exit Order (×36) (continued)

Bit # 119-Ball ID 165-Ball ID

CY7C1354B

CY7C1356B

Document #: 38-05114 Rev. *C Page 17 of 29

47 N1 M1

48 M2 L1

49 L1 K1

50 K2 J1

51 Not Bonded

(Preset to 1)

Not Bonded

(Preset to 1)

52 H1 G2

53 G2 F2

54 E2 E2

55 D1 D2

56 H2 G1

57 G1 F1

58 F2 E1

59 E1 D1

60 D2 C1

61 C2 B2

62 A2 A2

63 E4 A3

64 B2 B3

65 L3 B4

66 G3 A4

67 G5 A5

68 L5 B5

69 B6 A6

Boundary Scan Exit Order (×18)

Bit # 119-Ball ID 165-Ball ID

1K4 B6

2H4 B7

3M4 A7

4F4 B8

5B4 A8

6G4 A9

7C3 B10

8B3A10

9T2 A11

10 Not Bonded

(Preset to 0)

Not Bonded

(Preset to 0)

11 Not Bonded

(Preset to 0)

Not Bonded

(Preset to 0)

12 Not Bonded

(Preset to 0)

Not Bonded

(Preset to 0)

13 D6 C11

14 E7 D11

15 F6 E11

Boundary Scan Exit Order (×36) (continued)

Bit # 119-Ball ID 165-Ball ID

16 G7 F11

17 H6 G11

18 T7 H11

19 K7 J10

20 L6 K10

21 N6 L10

22 P7 M10

23 Not Bonded

(Preset to 0)

Not Bonded

(Preset to 0)

24 Not Bonded

(Preset to 0)

Not Bonded

(Preset to 0)

25 Not Bonded

(Preset to 0)

Not Bonded

(Preset to 0)

26 Not Bonded

(Preset to 0)

Not Bonded

(Preset to 0)

27 Not Bonded

(Preset to 0)

Not Bonded

(Preset to 0)

28 T6 R11

29 A3 R10

30 C5 P10

31 B5 R9

32 A5 P9

33 C6 R8

34 A6 P8

35 P4 R6

36 N4 P6

37 R6 R4

38 T5 P4

39 T3 R3

40 R2 P3

41 R3 R1

42 Not Bonded

(Preset to 0)

Not Bonded

(Preset to 0)

43 Not Bonded

(Preset to 0)

Not Bonded

(Preset to 0)

44 Not Bonded

(Preset to 0)

Not Bonded

(Preset to 0)

45 Not Bonded

(Preset to 0)

Not Bonded

(Preset to 0)

46 P2 N1

47 N1 M1

48 M2 L1

49 L1 K1

50 K2 J1

51 Not Bonded

(Preset to 1)

Not Bonded

(Preset to 1)

52 H1 G2

Boundary Scan Exit Order (×18) (continued)

Bit # 119-Ball ID 165-Ball ID

CY7C1354B

CY7C1356B

Document #: 38-05114 Rev. *C Page 18 of 29

53 G2 F2

54 E2 E2

55 D1 D2

56 Not Bonded

(Preset to 0)

Not Bonded

(Preset to 0)

57 Not Bonded

(Preset to 0)

Not Bonded

(Preset to 0)

58 Not Bonded

(Preset to 0)

Not Bonded

(Preset to 0)

59 Not Bonded

(Preset to 0)

Not Bonded

(Preset to 0)

60 Not Bonded

(Preset to 0)

Not Bonded

(Preset to 0)

61 C2 B2

62 A2 A2

63 E4 A3

64 B2 B3

65 Not Bonded

(Preset to 0

Not Bonded

(Preset to 0)

66 G3 Not Bonded

(Preset to 0)

67 Not Bonded

(Preset to 0

68 L5 B5

69 B6 A6

Boundary Scan Exit Order (×18) (continued)

Bit # 119-Ball ID 165-Ball ID

CY7C1354B

CY7C1356B

Document #: 38-05114 Rev. *C Page 19 of 29

Maximum Ratings

(Above which the useful life may be impaired. For user guide-

lines, not tested.)

Storage Temperature .................................–65°C to +150°C

Ambient Temperature with

Power Applied.............................................–55°C to +125°C

Supply Voltage on VDD Relative to GND........ –0.5V to +4.6V

DC to Outputs in Three-State.............. –0.5V to VDDQ + 0.5V

DC Input Voltage....................................–0.5V to VDD + 0.5V

Current into Outputs (LOW)......................................... 20 mA

Static Discharge Voltage.......................................... > 2001V

(per MIL-STD-883, Method 3015)

Latch-up Current.................................................... > 200 mA

Operating Range

Range

Ambient

Temperature VDD VDDQ

Commercial 0°C to +70°C 3.3V – 5%/+10% 2.5V – 5%

to VDD

Industrial –40°C to +85°C

Electrical Characteristics Over the Operating Range[14, 15]

Parameter Description Test Conditions Min. Max. Unit

VDD Power Supply Voltage 3.135 3.6 V

VDDQ I/O Supply Voltage VDDQ = 3.3V 3.135 VDD V

VDDQ = 2.5V 2.375 2.625 V

VOH Output HIGH Voltage VDD = Min., IOH = −4.0 mA, VDDQ = 3.3V 2.4 V

VDD = Min., IOH = −1.0 mA, VDDQ = 2.5V 2.0 V

VOL Output LOW Voltage VDD = Min., IOL= 8.0 mA, VDDQ = 3.3V 0.4 V

VDD = Min., IOL= 1.0 mA, VDDQ = 2.5V 0.4 V

VIH Input HIGH Voltage VDDQ = 3.3V 2.0 VDD + 0.3V V

VDDQ = 2.5V 1.7 VDD + 0.3V V

VIL Input LOW Voltage[14] VDDQ = 3.3V –0.3 0.8 V

VDDQ = 2.5V –0.3 0.7 V

IXInput Load Current GND ≤ VI ≤ VDDQ –5 5 µA

Input Current of MODE –30 30 µA

IOZ Output Leakage Current GND ≤ VI ≤ VDDQ, Output Disabled –5 5 µA

IDD VDD Operating Supply VDD = Max., IOUT = 0 mA,

f = fMAX = 1/tCYC

4.4-ns cycle, 225 MHz 250 mA

5-ns cycle, 200 MHz 220 mA

6-ns cycle, 166 MHz 180 mA

ISB1 Automatic CE

Power-down

Current—TTL Inputs

Max. VDD, Device Deselected,

VIN ≥ VIH or VIN ≤ VIL, f = fMAX =

1/tCYC

All speed grades 50 mA

ISB2 Automatic CE

Power-down

Current—CMOS Inputs

Max. VDD, Device Deselected,

VIN ≤ 0.3V or VIN > VDDQ − 0.3V,

f = 0

All speed grades 35 mA

ISB3 Automatic CE

Power-down

Current—CMOS Inputs

Max. VDD, Device Deselected,

VIN ≤ 0.3V or VIN > VDDQ − 0.3V,

f = fMAX = 1/tCYC

All speed grades 50 mA

ISB4 Automatic CE

Power-down

Current—TTL Inputs

Max. VDD, Device Deselected,

VIN ≥ VIH or VIN ≤ VIL, f = 0

All speed grades 40 mA

Shaded areas contain advance information.

Notes:

14. Overshoot: VIH(AC) < VDD +1.5V (Pulse width less than tCYC/2), undershoot: VIL(AC)> –2V (Pulse width less than tCYC/2).

15. TPower-up: Assumes a linear ramp from 0V to VDD (min.) within 200 ms. During this time VIH < VDD and VDDQ < VDD.

CY7C1354B

CY7C1356B

Document #: 38-05114 Rev. *C Page 20 of 29

Capacitance[16]

Parameter Description Test Conditions BGA Max. fBGA Max. TQFP Max. Unit

CIN Input Capacitance TA = 25°C, f = 1 MHz,

VDD = 3.3V VDDQ = 2.5V

555pF

CCLK Clock Input Capacitance 5 5 5 pF

CI/O Input/Output Capacitance 7 7 5 pF

AC Test Loads and Waveforms

Thermal Resistance[16]

Parameters Description Test Conditions BGA Typ. fBGA Typ. TQFP Typ. Unit Notes

ΘJA Thermal Resistance

(Junction to Ambient)

Test conditions follow

standard test methods and

procedures for measuring

thermal impedance, per EIA

/ JESD51.

25 27 25 °C/W 17

ΘJC Thermal Resistance

(Junction to Case)

669°C/W 17

Switching Characteristics Over the Operating Range [21, 22]

Parameter Description

-225 -200 -166

Unit

Min. Max. Min. Max. Min. Max.

tPower[17] VCC (typical) to the First Access Read or

Write

111ms

Clock

tCYC Clock Cycle Time 4.4 56ns

FMAX Maximum Operating Frequency 225 200 166 MHz

tCH Clock HIGH 1.8 2.0 2.4 ns

tCL Clock LOW 1.8 2.0 2.4 ns

Output Times

tCO Data Output Valid after CLK Rise 2.8 3.2 3.5 ns

tEOV OE LOW to Output Valid 2.8 3.2 3.5 ns

tDOH Data Output Hold after CLK Rise 1.25 1.5 1.5 ns

tCHZ Clock to High-Z[18, 19, 20] 1.25 2.81.53.21.53.5 ns

tCLZ Clock to Low-Z[18, 19, 20] 1.25 1.5 1.5 ns

tEOHZ OE HIGH to Output High-Z[18, 19, 20] 2.8 3.2 3.5 ns

tEOLZ OE LOW to Output Low-Z[18, 19, 20] 000ns

Shaded areas contain advance information.

Notes:

16. Tested initially and after any design or process changes that may affect these parameters.

17. This part has a voltage regulator internally; tpower is the time power needs to be supplied above VDD minimum initially, before a Read or Write operation can be

initiated.

18. tCHZ, tCLZ, tEOLZ, and tEOHZ are specified with AC test conditions shown in (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.

19. At any given voltage and temperature, tEOHZ is less than tEOLZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same

data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed

to achieve High-Z prior to Low-Z under the same system conditions.

20. This parameter is sampled and not 100% tested.

21. Timing reference level is 1.5V when VDDQ = 3.3V and is 1.25V when VDDQ = 2.5V.

22. Test conditions shown in (a) of AC Test Loads unless otherwise noted.

R=1667/317Ω

R = 1538/351Ω

5pF

INCLUDING

JIG AND

SCOPE

(a) (b)

OUTPUT

RL= 50Ω

Z0= 50Ω

VL= 1.5V/1.25V

VDDQ ALL INPUT PULSES[16]

90%

10%

90%

10%

<1.0 ns <1.0 ns

(c)

VDD

1.5/1.25V

CY7C1354B

CY7C1356B

Document #: 38-05114 Rev. *C Page 21 of 29

Set-up Times

tAS Address Set-up before CLK Rise 1.4 1.5 1.5 ns

tDS Data Input Set-up before CLK Rise 1.4 1.5 1.5 ns

tCENS CEN Set-up before CLK Rise 1.4 1.5 1.5 ns

tWES WE, BWx Set-up before CLK Rise 1.4 1.5 1.5 ns

tALS ADV/LD Set-up before CLK Rise 1.4 1.5 1.5 ns

tCES Chip Select Set-up 1.4 1.5 1.5 ns

tAH Address Hold after CLK Rise 0.4 0.5 0.5 ns

Hold Times

tDH Data Input Hold after CLK Rise 0.4 0.5 0.5 ns

tCENH CEN Hold after CLK Rise 0.4 0.5 0.5 ns

tWEH WE, BWx Hold after CLK Rise 0.4 0.5 0.5 ns

tALH ADV/LD Hold after CLK Rise 0.4 0.5 0.5 ns

tCEH Chip Select Hold after CLK Rise 0.4 0.5 0.5 ns

Switching Characteristics Over the Operating Range (continued)[21, 22]

Parameter Description

-225 -200 -166

Unit

Min. Max. Min. Max. Min. Max.

CY7C1354B

CY7C1356B

Document #: 38-05114 Rev. *C Page 22 of 29

Switching Waveforms

WRITE

D(A1)

123456789

CLK

tCYC

CEH

CES

CEN

CENH

CENS

BWX

ADV/LD

DDRESS A1 A2 A3 A4 A5 A6 A7

Data

Out (DQ)

CLZ

D(A1) D(A2) D(A5)Q(A4)Q(A3)

D(A2+1)

DOH

CHZ

WRITE

D(A2) BURST

WRITE

D(A2+1)

READ

Q(A3) READ

Q(A4) BURST

READ

Q(A4+1)

WRITE

D(A5) READ

Q(A6) WRITE

D(A7) DESELE

OEV

OELZ

OEHZ

DOH

DON’T CARE UNDEFINED

Q(A

Q(A4+1)

Read/WriteTiming[23,24,25]

CY7C1354B

CY7C1356B

Document #: 38-05114 Rev. *C Page 23 of 29

Switching Waveforms (continued)

READ

Q(A3)

45678910

CLK

CEN

BWX

ADV/LD

ADDRESS A3 A4 A5

D(A4)

Data

In-Out (DQ)

Q(A5)

WRITE

D(A4) STALLWRITE

D(A1)

123

READ

Q(A2) STALL NOP READ

Q(A5) DESELECT CONTINUE

DESELECT

DON’T CARE UNDEFINED

CHZ

D(A1) Q(A2) Q(A3)

NOP,STALL AND DESELECT CYCLES[23,24,26]

CY7C1354B

CY7C1356B

Document #: 38-05114 Rev. *C Page 24 of 29

Note:

23. For this waveform ZZ is tied low.

24. When CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH,CE1 is HIGH or CE2 is LOW or CE3 is HIGH.

25. Order of the Burst sequence is determined by the status of the MODE (0=Linear, 1=Interleaved).Burst operations are optional.

26. The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrated CEN being used to create a pause. A write is not performed during this cycle

27. Device must be deselected when entering ZZ mode. See cycle description table for all possible signal conditions to deselect the device.

28. I/Os are in High-Z when exiting ZZ sleep mode..

Ordering Information

Speed

(MHz) Ordering Code

Package

Name Package Type

Operating

Range

225 CY7C1354B-225AC A101 100-lead Thin Quad Flat Pack (14 x 20 x 1.4 mm) Commercial

CY7C1356B-225AC

CY7C1354B-225AI A101 100-lead Thin Quad Flat Pack (14 x 20 x 1.4 mm) Industrial

CY7C1356B-225AI

CY7C1354B-225BGC BG119 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Commercial

CY7C1356B-225BGC

CY7C1354B-225BGI BG119 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Industrial

CY7C1356B-225BGI

CY7C1354B-225BZC BB165A 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.2 mm) Commercial

CY7C1356B-225BZC

CY7C1354B-225BZI BB165A 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.2 mm) Industrial

CY7C1356B-225BZI

Switching Waveforms (continued)

tZZ

ISUPPLY

CLK

tZZREC

LL INPUTS

(except ZZ)

DON’T CARE

IDDZZ

tZZI

tRZZI

Outputs (Q) High-Z

DESELECT or READ Only

ZZ Mode Timing [27,28]

CY7C1354B

CY7C1356B

Document #: 38-05114 Rev. *C Page 25 of 29

of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize

its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

200 CY7C1354B-200AC A101 100-lead Thin Quad Flat Pack (14 x 20 x 1.4 mm) Commercial

CY7C1356B-200AC

CY7C1354B-200AI A101 100-lead Thin Quad Flat Pack (14 x 20 x 1.4 mm) Industrial

CY7C1356B-200AI

CY7C1354B-200BGC BG119 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Commercial

CY7C1356B-200BGC

CY7C1354B-200BGI BG119 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Industrial

CY7C1356B-200BGI

CY7C1354B-200BZC BB165A 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.2 mm) Commercial

CY7C1356B-200BZC

CY7C1354B-200BZI BB165A 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.2 mm) Industrial

CY7C1356B-200BZI

166 CY7C1354B-166AC A101 100-lead Thin Quad Flat Pack (14 x 20 x 1.4 mm) Commercial

CY7C1356B-166AC

CY7C1354B-166AI A101 100-lead Thin Quad Flat Pack (14 x 20 x 1.4 mm) Industrial

CY7C1356B-166AI

CY7C1354B-166BGC BG119 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Commercial

CY7C1356B-166BGC

CY7C1354B-166BGI BG119 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Industrial

CY7C1356B-166BGI

CY7C1354B-166BZC BB165A 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.2 mm) Commercial

CY7C1356B-166BZC

CY7C1354B-166BZI BB165A 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.2 mm) Industrial

CY7C1356B-166BZI

Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts.

Ordering Information

Speed

(MHz) Ordering Code

Package

Name Package Type

Operating

Range

CY7C1354B

CY7C1356B

Document #: 38-05114 Rev. *C Page 26 of 29

Package Diagrams

DIMENSIONS ARE IN MILLIMETERS.

0.30±0.08

0.65

20.00±0.10

22.00±0.20

1.40±0.05

12°±1°

1.60 MAX.

0.05 MIN.

0.60±0.15

0° MIN.

0.25

0°-7°

(8X)

STAND-OFF

R 0.08 MIN.

TYP.

0.20 MAX.

0.15 MAX.

0.20 MAX.

R0.08MIN.

0.20 MAX.

14.00±0.10

16.00±0.20

0.10

SEE DETAIL A

DETAIL A

100

31 50

GAUGE PLANE

1.00 REF.

0.20 MIN.

SEATING PLANE

100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101

51-85050-*A

CY7C1354B

CY7C1356B

Document #: 38-05114 Rev. *C Page 27 of 29

Package Diagrams (continued)

51-85115-*B

119-Lead BGA (14 x 22 x 2.4mm) BG119

CY7C1354B

CY7C1356B

Document #: 38-05114 Rev. *C Page 28 of 29

NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation. ZBT is a trademark of Integrated Device

Technology. All product and company names mentioned in this document are the trademarks of their respective holders.

Package Diagrams (continued)

51-85122-*C

165-Ball FBGA (13 x 15 x 1.2 mm) BB165A

CY7C1354B

CY7C1356B

Document #: 38-05114 Rev. *C Page 29 of 29

Document History Page

Document Title: CY7C1354B/CY7C1356B 9-Mb (256K x 36/512K x 18) Pipelined SRAM with

NoBL™ Architecture

Document Number: 38-05114

REV. ECN No. Issue Date

Orig. of

Change Description of Change

** 117904 08/28/02 RCS New Data Sheet

*A 126207 08/27/03 DPM Removed Preliminary status

Removed 250-MHz Speed bin

Added 225-MHz speed bin

Increased TCO, TEOV, TCHZ, TEOHZ for 200 MHz to 3.2 ns from 3.0 ns

Updated JTAG revision number and device depth

Updated JTAG boundary scan orders

Added tPower specification

Changed footnotes ordering

Added Industrial operating range

Changed Capacitance table to have TQFP, BGA, and fBGA columns.

*B 205060 See ECN NJY Removed footnote 13 “Minimum voltage equals –2.0V for pulse durations of less than 20 ns.”

Removed footnote 14 “TA is the case temperature.”

Changed footnote 15 from “Overshoot: VIH(AC) < VDD + 1.5V for t < tTCYC/2; undershoot:

VIL(AC) < 0.5V for t < tTCYC/2; power-up: VIH < 2.6V and VDD < 2.4V and VDDQ < 1.4V for t <

200 ms. “to footnote 13“Overshoot: VIH(AC) < VDD +1.5V (Pulse width less than tCYC/2),

undershoot: VIL(AC)> -2V (Pulse width less than tCYC/2). “

Added footnote 14 “TPower-up: Assumes a linear ramp from 0V to VDD (min.) within 200ms.

During this time VIH < VDD and VDDQ < VDD. “

Added footnote 20 “Timing reference level is 1.5V when VDDQ = 3.3V and is 1.25V when

VDDQ = 2.5V.”

Changed footnote 21 from “Test conditions shown in (a), (b) and (c) of AC Test Loads. “to

“Test conditions shown in (a) of AC Test Loads unless otherwise noted. “

Updated ZZ Mode Electrical Characteristics.

Updated ISB1 and ISB3 currents in Electrical Characteristics table.

Modified functional block diagram.

Modified Truth Table and Write Cycle Descriptions.

Updated Ordering Information.

*C 230388 See ECN VBL Modified ID code

Changed balls B4 and A5 from BWd and BWb to NC and ball A4 from BWc

to BWb for 165-ball FBGA package for CY7C1356B

Changed balls C11 from DQPb to DQPa and balls D11,E11,F11 and G11

from DQb to DQa for CY7C1356B.

Update Ordering Info section: changed BZC to BZI in Industrial part