ADSP-21365WYSWZ-2B - Analog Devices, Inc.

SHARC

Processors

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

SUMMARY

High performance, 32-bit/40-bit, floating-point processor

optimized for high performance processing

Single-instruction, multiple-data (SIMD) computational

architecture

On-chip memory—3M bit of on-chip SRAM

Code compatible with all other members of the SHARC family

The ADSP-2136x processors are available with a 333 MHz

core instruction rate and unique peripherals such as the

digital audio interface, S/PDIF transceiver, DTCP (digital

transmission content protection protocol), serial ports,

8-channel asynchronous sample rate converter, precision

clock generators, and more. For complete ordering infor-

mation, see Ordering Guide on Page 53.

IOP REGISTERS

(MEMORY-MAPPED)

I/O PROCESSOR

AND PERIPHERALS

JTAG TEST & EMULATION

PM ADDRESS BUS

DM ADDRESS BUS

PM DATA BUS

DM DATA BUS

TIMER

CORE PROCESSOR

PROGRAM

SEQUENCER

SIGNAL

ROUTING

UNIT

ADDR DATA

DAG1

8 u4 u 32

DAG2

8 u4 u 32

PX REGISTER

INSTRUCTION

CACHE

32 u 48-BIT

ADDR DATA ADDR DATA ADDR DATA

BLOCK0

4 BLOCKS OF ON-CHIP MEMORY

BLOCK1

SRAM

1M BIT ROM

2M BIT

SRAM

0.5M BIT

SRAM

0.5M BIT

ROM

2M BIT

SRAM

1M BIT

BLOCK2 BLOCK3

PROCESSING

ELEMENT

(PEX)

PROCESSING

ELEMENT

(PEY)

SPI

SPORTS

IDP

PCG

TIMERS

SRC

S/PDIF

DTCP

IOA IOD IOA IOD IOA IOD IOA IOD

Figure 1. Functional Block Diagram—Processor Core

SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable.

However, no responsibility is assumed by Analog Devices for its use, nor for any

infringements of patents or other rights of third parties that may result from its use.

Specifications subject to change without notice. No license is granted by implication One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.

or otherwise under any patent or patent rights of Analog Devices. Trademarks and Tel: 781.329.4700 www.analog.com

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

KEY FEATURES—PROCESSOR CORE

At 333 MHz (3.0 ns) core instruction rate, the ADSP-2136x

performs 2 GFLOPS/666 MMACS

3M bit on-chip SRAM (1M bit in blocks 0 and 1, and 0.50M bit

in blocks 2 and 3) for simultaneous access by the core pro-

cessor and DMA

4M bit on-chip ROM (2M bit in block 0 and 2M bit in block 1)

Dual data address generators (DAGs) with modulo and bit-

reverse addressing

Zero-overhead looping with single-cycle loop setup, provid-

ing efficient program sequencing

Single-instruction multiple-data (SIMD) architecture

provides:

Two computational processing elements

Concurrent execution

Code compatibility with other SHARC family members at

the assembly level

Parallelism in buses and computational units allows single

cycle execution (with or without SIMD) of a multiply

operation, an ALU operation, a dual memory read or

write, and an instruction fetch

Transfers between memory and core at a sustained

5.4 GBps bandwidth at 333 MHz core instruction rate

INPUT/OUTPUT FEATURES

DMA controller supports:

25 DMA channels for transfers between

ADSP-2136x internal memory and a variety of peripherals

32-bit DMA transfers at peripheral clock speed, in parallel

with full-speed processor execution

Asynchronous parallel port provides access to asynchronous

external memory

16 multiplexed address/data lines support 24-bit address

external address range with 8-bit data or 16-bit address

external address range with 16-bit data

55 Mbps transfer rate

External memory access in a dedicated DMA channel

8-bit to 32-bit and 16-bit to 32-bit packing options

Programmable data cycle duration: 2 CCLK to 31 CCLK

Digital audio interface (DAI) includes six serial ports, two pre-

cision clock generators, an input data port, three timers, an

S/PDIF transceiver, a DTCP cipher, an 8-channel asynchro-

nous sample rate converter, an SPI port, and a signal

routing unit

Six dual data line serial ports that operate at up to

41.67 Mbps on each data line—each has a clock, frame

sync, and two data lines that can be configured as either a

receiver or transmitter pair

Left-justified sample pair and I

S support, programmable

direction for up to 24 simultaneous receive or transmit

channels using two I

S-compatible stereo devices per

serial port

TDM support for telecommunications interfaces including

128 TDM channel support for newer telephony interfaces

such as H.100/H.110

Up to 12 TDM stream support, each with 128 channels per

frame

Companding selection on a per channel basis in TDM mode

Input data port provides an additional input path to the pro-

cessor core, configurable as eight channels of serial data or

seven channels of serial data, and up to a 20-bit wide paral-

lel data channel

Signal routing unit provides configurable and flexible con-

nections between all DAI components—six serial ports,

one SPI port, eight channels of asynchronous sample rate

converters, an S/PDIF receiver/transmitter, three timers,

an SPI port,10 interrupts, six flag inputs, six flag outputs,

and 20 SRU I/O pins (DAI_Px)

Two serial peripheral interfaces (SPI): primary on dedicated

pins, secondary on DAI pins provide:

Master or slave serial boot through primary SPI

Full-duplex operation

Master slave mode multimaster support

Open drain outputs

Programmable baud rates, clock polarities, and phases

3 muxed flag/IRQ lines

1 muxed flag/timer expired line

DEDICATED AUDIO COMPONENTS

S/PDIF-compatible digital audio receiver/transmitter

supports:

EIAJ CP-340 (CP-1201), IEC-958, AES/EBU standards

Left-justified, I

S, or right-justified serial data input with

16-, 18-, 20-, or 24-bit word widths (transmitter)

Two channel mode and single channel double frequency

(SCDF) mode

Sample rate converter (SRC) contains a serial input port,

de-emphasis filter, sample rate converter (SRC), and serial

output port providing up to –140 dB SNR performance (see

Table 2 on Page 4)

Supports left-justified, I

S, TDM, and right-justified

24-, 20-, 18-, and 16-bit serial formats (input)

Pulse-width modulation provides:

16 PWM outputs configured as four groups of four outputs

Supports center-aligned or edge-aligned PWM waveforms

Can generate complementary signals on two outputs in

paired mode or independent signals in nonpaired mode

ROM-based security features include:

JTAG access to memory permitted with a 64-bit key

Protected memory regions that can be assigned to limit

access under program control to sensitive code

PLL has a wide variety of software and hardware multi-

plier/divider ratios

Dual voltage: 3.3 V I/O, 1.2 V, or 1.0 V core

Available in 136-ball BGA and 144-lead LQFP_EP packages

(see Ordering Guide on Page 53)

Rev. B | Page 2 of 56 | June 2007

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

CONTENTS

General Description ..................................................4

SHARC Family Core Architecture .............................5

Memory and I/O Interface Features ............................6

Development Tools .............................................. 10

Additional Information ......................................... 11

Pin Function Descriptions ........................................ 12

Address Data Pins as FLAGs .................................. 15

Address/Data Modes ............................................ 15

Boot Modes ........................................................ 15

Core Instruction Rate to CLKIN Ratio Modes ............. 15

ADSP-2136x Specifications ....................................... 16

Operating Conditions ........................................... 16

Electrical Characteristics ........................................ 16

Package Information ............................................ 17

Maximum Power Dissipation ................................. 17

Absolute Maximum Ratings ................................... 17

ESD Sensitivity .................................................... 17

Timing Specifications ........................................... 17

Output Drive Currents .......................................... 45

Test Conditions ................................................... 45

Capacitive Loading ............................................... 45

Thermal Characteristics ........................................ 46

144-Lead LQFP Pin Configurations ............................. 47

136-Ball BGA Pin Configurations ............................... 48

Outline Dimensions ................................................ 51

Surface Mount Design .......................................... 52

Ordering Guide ...................................................... 53

REVISION HISTORY

6/07—Rev A. to Rev B.

Revised Figure 1 ....................................................... 1

This version of the data sheet adds the new LQFP_EP package

which has been fully qualified. See Ordering Guide ..........53

Revised Table 6........................................................15

Revised Table 7........................................................15

Added T

information to Operating Conditions ..............16

Added additional PLL multiplier value information to Timing

Specifications..........................................................18

Added LQFP_EP information to Thermal Characteristics ..46

Corrected 144-Lead LQFP Pin Configurations ................47

Corrected 136-Ball BGA Pin Configurations...................48

Rev. B | Page 3 of 56 | June 2007

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

GENERAL DESCRIPTION

The ADSP-2136x SHARC processor is a member of the SIMD

SHARC family of DSPs that feature Analog Devices’ Super Har-

vard Architecture. The processor is source code-compatible

with the ADSP-2126x and ADSP-2116x DSPs, as well as with

first generation ADSP-2106x SHARC processors in SISD (sin-

gle-instruction, single-data) mode. The ADSP-2136x is a

32-bit/40-bit floating-point processor optimized for high

performance automotive audio applications with a large on-

chip SRAM and ROM, multiple internal buses to eliminate I/O

bottlenecks, and an innovative digital audio interface (DAI).

As shown in the functional block diagram on Page 1, the

ADSP-2136x uses two computational units to deliver a signifi-

cant performance increase over the previous SHARC processors

on a range of signal processing algorithms. Fabricated in a state-

of-the-art, high speed, CMOS process, the ADSP-2136x proces-

sor achieves an instruction cycle time of 3.0 ns at 333 MHz.

With its SIMD computational hardware, the ADSP-2136x can

perform two GFLOPS running at 333 MHz.

Table 2 shows the features of the individual product offerings

and Table 1 shows performance benchmarks for the processors

running at 333 MHz.

Table 1. Benchmarks (at 333 MHz)

Benchmark Algorithm

1024 Point Complex FFT (Radix 4, with reversal) 27.9 μs

FIR Filter (per tap)

1.5 ns

IIR Filter (per biquad)

6.0 ns

Matrix Multiply (pipelined)

[3×3] × [3×1] 13.5 ns

[4×4] × [4×1] 23.9 ns

Divide (y/x) 10.5 ns

Inverse Square Root 16.3 ns

Assumes two files in multichannel SIMD mode

Speed

(at 333 MHz)

The ADSP-2136x continues SHARC’s industry-leading stan-

dards of integration for DSPs, combining a high performance

32-bit DSP core with integrated, on-chip system features.

The block diagram on Page 1, illustrates the following architec-

tural features:

• Two processing elements, each of which comprises an

ALU, multiplier, shifter, and data register file

• Data address generators (DAG1, DAG2)

• Program sequencer with instruction cache

• PM and DM buses capable of supporting four 32-bit data

transfers between memory and the core at every core pro-

cessor cycle

• Three programmable interval timers with PWM genera-

tion, PWM capture/pulse width measurement, and

external event counter capabilities

•On-chip SRAM (3M bit)

• On-chip ROM (4M bit)

• JTAG test access port

Table 2. ADSP-2136x SHARC Processor Family Features

Feature

ADSP-21362

ADSP-21363

ADSP-21364

ADSP-21365

ADSP-21366

RAM 3M bit 3M bit 3M bit 3M bit 3M bit

ROM 4M bit 4M bit 4M bit 4M bit 4M bit

Audio

Decoders in

ROM

No No No Yes Yes

Pulse-Width

Modulation

Yes Yes Yes Yes Yes

S/PDIF Yes No Yes Yes Yes

DTCP

Yes No No Yes No

SRC

Performance

128 dB No SRC 140 dB 128 dB 128 dB

Audio decoding algorithms include PCM, Dolby Digital EX, Dolby Prologic IIx,

DTS 96/24, Neo:6, DTS ES, MPEG-2 AAC, MP3, and functions like Bass

management, delay, speaker equalization, graphic equalization, and more.

Decoder/post-processor algorithm combination support varies depending upon

the chip version and the system configurations. Please visit www.analog.com for

complete information.

The ADSP-21362 and ADSP-21365 processors provide the Digital Transmission

Content Protection protocol, a proprietary security protocol. Contact your

Analog Devices sales office for more information.

The block diagram on Page 7 illustrates the following architec-

tural features:

• DMA controller

• Six full duplex serial ports

• Two SPI-compatible interface ports—primary on dedi-

cated pins, secondary on DAI pins

• 8-bit or 16-bit parallel port that supports interfaces to off-

chip memory peripherals

• Digital audio interface that includes two precision clock

generators (PCG), an input data port (IDP), an S/PDIF

receiver/transmitter, eight channels asynchronous sample

rate converter, DTCP cipher, six serial ports, eight serial

interfaces, a 20-bit parallel input port, 10 interrupts, six flag

outputs, six flag inputs, three timers, and a flexible signal

routing unit (SRU)

Figure 2 shows a sample SPORT configuration using the preci-

sion clock generators to interface with an I

S ADC and an I

DAC with a much lower jitter clock than the serial port would

generate itself. Many other SRU configurations are possible.

Rev. B | Page 4 of 56 | June 2007

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

June 2007

bandwidth between memory and the processing elements.

When using the DAGs to transfer data in SIMD mode, two data

values are transferred with each access of memory or

the register file.

Independent, Parallel Computation Units

Within each processing element is a set of computational units.

The computational units consist of an arithmetic/logic unit

(ALU), multiplier, and shifter. These units perform all opera-

tions in a single cycle. The three units within each processing

element are arranged in parallel, maximizing computational

throughput. Single multifunction instructions execute parallel

ALU and multiplier operations. In SIMD mode, the parallel

ALU and multiplier operations occur in both processing

elements. These computation units support IEEE 32-bit,

single-precision floating-point, 40-bit extended-precision

floating-point, and 32-bit fixed-point data formats.

Data Register File

A general-purpose data register file is contained in each pro-

cessing element. The register files transfer data between the

computation units and the data buses, and store intermediate

results. These 10-port, 32-register (16 primary, 16 secondary)

Figure 2. ADSP-2136x System Sample Configuration

DAI

S PI

IDP

SRC

SPDIF

SPORT0-5

S CLK0

S D0A

S FS0

S D0B

SRU

DAI_P1

DA I_ P2

DA I_ P3

DAI_P18

DAI_P19

DA I_ P2 0

CLOCK

FLAG3-1

CLKIN

XTAL

CLK_CFG1-0

BOOTCFG1-0

ADDR PARALLEL

PORT

RAM

I/O DEVICE

DATA

CLKOUT

ALE

AD 1 5- 0 LATCH

RES ET JT A G

ADSP-2136x

ADDRESS

DATA

CONTROL

CSFLAG0

TIMERS

PCGB

PCGA

CLK

ADC

(OPTIONAL)

CLK

S DAT

DAC

(OPTIONAL)

CLK

S DAT

SHARC FAMILY CORE ARCHITECTURE

The ADSP-2136x is code-compatible at the assembly level with

the ADSP-2126x, ADSP-21160, and ADSP-21161, and with the

first generation ADSP-2106x SHARC processors. The

ADSP-2136x shares architectural features with the ADSP-2126x

and ADSP-2116x SIMD SHARC processors, as detailed in the

following sections.

SIMD Computational Engine

The ADSP-2136x contains two computational processing ele-

ments that operate as a single-instruction multiple-data (SIMD)

engine. The processing elements are referred to as PEX and PEY

and each contains an ALU, multiplier, shifter, and register file.

PEX is always active, and PEY may be enabled by setting the

PEYEN mode bit in the MODE1 register. When this mode is

enabled, the same instruction is executed in both processing ele-

ments, but each processing element operates on different data.

This architecture is efficient at executing math intensive signal

processing algorithms.

Entering SIMD mode also has an effect on the way data is trans-

ferred between memory and the processing elements. When in

SIMD mode, twice the data bandwidth is required to sustain

computational operation in the processing elements. Because of

this requirement, entering SIMD mode also doubles the

Rev. B | Page 5 of 56 |

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

Harvard architecture, allow unconstrained data flow between

computation units and internal memory. The registers in PEX

are referred to as R0–R15 and in PEY as S0–S15.

Single-Cycle Fetch of Instruction and Four Operands

The ADSP-2136x features an enhanced Harvard architecture in

which the data memory (DM) bus transfers data and the pro-

gram memory (PM) bus transfers both instructions and data

(see Figure 1 on Page 1). With the processor’s separate program

and data memory buses and on-chip instruction cache, the pro-

cessor can simultaneously fetch four operands (two over each

data bus) and one instruction (from the cache), all in a

single cycle.

Instruction Cache

The ADSP-2136x includes an on-chip instruction cache that

enables three-bus operation for fetching an instruction and four

data values. The cache is selective—only the instructions whose

fetches conflict with PM bus data accesses are cached. This

cache allows full-speed execution of core, looped operations

such as digital filter multiply-accumulates, and FFT butterfly

processing.

Data Address Generators with Zero-Overhead Hardware

Circular Buffer Support

The ADSP-2136x’s two data address generators (DAGs) are

used for indirect addressing and implementing circular data

buffers in hardware. Circular buffers allow efficient program-

ming of delay lines and other data structures required in digital

Table 3. ADSP-2136x Internal Memory Space

signal processing, and are commonly used in digital filters and

Fourier transforms. The two DAGs contain sufficient registers

to allow the creation of up to 32 circular buffers (16 primary

address pointer wraparound, reduce overhead, increase perfor-

mance, and simplify implementation. Circular buffers can start

and end at any memory location.

Flexible Instruction Set

The 48-bit instruction word accommodates a variety of parallel

operations, for concise programming. For example, the

ADSP-2136x can conditionally execute a multiply, an add, and a

subtract in both processing elements while branching and fetch-

ing up to four 32-bit values from memory—all in a single

instruction.

MEMORY AND I/O INTERFACE FEATURES

The ADSP-2136x adds the following architectural features to

the SIMD SHARC family core.

On-Chip Memory

The ADSP-2136x contains three megabits of internal SRAM

and four megabits of internal ROM. Each block can be config-

ured for different combinations of code and data storage (see

Table 3). Each memory block supports single-cycle, indepen-

dent accesses by the core processor and I/O processor. The

processor’s memory architecture, in combination with its sepa-

rate on-chip buses, allows two data transfers from the core and

one from the I/O processor, in a single cycle.

IOP Registers 0x0000 0000–0003 FFFF

Long Word (64 Bits)

Extended Precision Normal or

Instruction Word (48 Bits) Normal Word (32 Bits) Short Word (16 Bits)

BLOCK 0 ROM

0x0004 0000–0x0004 7FFF

BLOCK 0 ROM

0x0008 0000–0x0008 AAA9

BLOCK 0 ROM

0x0008 0000–0x0008 FFFF

BLOCK 0 ROM

0x0010 0000–0x0011 FFFF

Reserved

0x0004 8000–0x0004 BFFF

Reserved

0x0009 0000–0x0009 7FFF

Reserved

0x0012 0000–0x0012 FFFF

BLOCK 0 SRAM

0x0004 C000–0x0004 FFFF

BLOCK 0 SRAM

0x0009 0000–0x0009 5554

BLOCK 0 SRAM

0x0009 8000–0x0009 FFFF

BLOCK 0 SRAM

0x0013 0000–0x0013 FFFF

BLOCK 1 ROM

0x0005 0000–0x0005 7FFF

BLOCK 1 ROM

0x000A 0000–0x000A AAA9

BLOCK 1 ROM

0x000A 0000–0x000A FFFF

BLOCK 1 ROM

0x0014 0000–0x0015 FFFF

Reserved

0x0005 8000–0x0005 BFFF

Reserved

0x000B 0000–0x000B 7FFF

Reserved

0x0016 0000–0x0016 FFFF

BLOCK 1 SRAM

0x0005 C000–0x0005 FFFF

BLOCK 1 SRAM

0x000B 0000–0x000B 5554

BLOCK 1 SRAM

0x000B 8000–0x000B FFFF

BLOCK 1 SRAM

0x0017 0000–0x0017 FFFF

BLOCK 2 SRAM

0x0006 0000–0x0006 1FFF

BLOCK 2 SRAM

0x000C 0000–0x000C 2AA9

BLOCK 2 SRAM

0x000C 0000–0x000C 3FFF

BLOCK 2 SRAM

0x0018 0000–0x0018 7FFF

Reserved

0x0006 2000–0x0006 FFFF

Reserved

0x000C 4000–0x000D FFFF

Reserved

0x0018 8000–0x001B FFFF

BLOCK 3 SRAM

0x0007 0000–0x0007 1FFF

BLOCK 3 SRAM

0x000E 0000–0x000E 2AA9

BLOCK 3 SRAM

0x000E 0000–0x000E 3FFF

BLOCK 3 SRAM

0x001C 0000–0x001C 7FFF

Rev. B | Page 6 of 56 | June 2007

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

Table 3. ADSP-2136x Internal Memory Space (Continued)

June 2007

DAI- associated peripherals for a much wider variety of applica-

tions by using a larger set of algorithms than is possible with

nonconfigurable signal paths.

The DAI also includes six serial ports, an S/PDIF receiver/trans-

mitter, a DTCP cipher, a precision clock generator (PCG), eight

channels of asynchronous sample rate converters, an input data

port (IDP), an SPI port, six flag outputs and six flag inputs, and

Figure 3. ADSP-2136x I/O Processor and

PRECISION CLOCK

GENERATORS (2)

SPI PORT (1)

SERIAL PORTS (6)

INPUT

DATA PORTS (8)

TIMERS (3)

DMA CONTROLLER

IOPREGISTERS

(MEMORYMAPPED)

CONTROL,STATUS,ANDDATABUFFERS

PARALLEL PORT

GPIO FLAGS/IRQ/TIMEXP

SIGNALROUTINGUNIT

ADDRESS/DATA BUS/ GPIO

CONTROL/GPIO

DIGITAL AUDIO INTERFACE

25 CHANNELS

TO PROCESSOR BUSES AND

SYSTEM MEMORY

SRC (8 CHANNELS)

SPDIF (Rx/Tx)

DTCP CIPHER

PWM (16)

BUS (32)

SPI PORT (1)

I/O PROCESSOR

IOP Registers 0x0000 0000–0003 FFFF

Long Word (64 Bits)

Extended Precision Normal or

Instruction Word (48 Bits) Normal Word (32 Bits) Short Word (16 Bits)

Reserved

0x0007 2000–0x0007 FFFF

Reserved

0x000E 4000–0x000F FFFF

Reserved

0x001C 8000–0x001F FFFF

Reserved

0x0020 0000–0xFFFF FFFF

The SRAM can be configured as a maximum of 96K words of

32-bit data, 192K words of 16-bit data, 64K words of 48-bit

instructions (or 40-bit data), or combinations of different word

sizes up to three megabits. All of the memory can be accessed as

16-bit, 32-bit, 48-bit, or 64-bit words. A 16-bit floating-point

storage format is supported that effectively doubles the amount

of data that may be stored on-chip. Conversion between the 32-

bit floating-point and 16-bit floating-point formats is per- IO DATA IO ADDRESS

formed in a single instruction. While each memory block can

store combinations of code and data, accesses are most efficient

when one block stores data using the DM bus for transfers, and

the other block stores instructions and data using the PM bus

for transfers.

Using the DM bus and PM buses, with one bus dedicated to

each memory block, assures single-cycle execution with two

data transfers. In this case, the instruction must be available in

the cache.

DMA Controller

The ADSP-2136x’s on-chip DMA controllers allow data trans-

fers without processor intervention. The DMA controller

operates independently and invisibly to the processor core,

allowing DMA operations to occur while the core is simulta-

neously executing its program instructions. DMA transfers can

occur between the processor’s internal memory and its serial

ports, the SPI-compatible (serial peripheral interface) ports, the

IDP (input data port), the parallel data acquisition port (PDAP),

or the parallel port. Twenty-five channels of DMA are available

on the processors—two for the SPI interface, 12 via the serial

ports, eight via the input data port, two for DTCP (or memory-

to-memory data transfer when DTCP is not used), and one via

the processor’s parallel port. Programs can be downloaded to

the processors using DMA transfers. Other DMA features

include interrupt generation upon completion of DMA trans-

fers, and DMA chaining for automatic linked DMA transfers.

Digital Audio Interface (DAI)

The digital audio interface (DAI) provides the ability to connect

various peripherals to any of the DSP’s DAI pins (DAI_P20–1).

Programs make these connections using the signal routing unit

(SRU, shown in Figure 3).

The SRU is a matrix routing unit (or group of multiplexers) that

enables the peripherals provided by the DAI to be intercon-

BUS (18)

Peripherals Block Diagram

nected under software control. This allows easy use of the

Rev. B | Page 7 of 56 |

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

three timers. The IDP provides an additional input path to the

ADSP-2136x core, configurable as either eight channels of I

serial data or as seven channels plus a single 20-bit wide syn-

chronous parallel data acquisition port. Each data channel has

its own DMA channel that is independent from the processor’s

serial ports.

For complete information on using the DAI, see the

ADSP-2136x SHARC Processor Hardware Reference.

Serial Ports

The ADSP-2136x features six synchronous serial ports that pro-

vide an inexpensive interface to a wide variety of digital and

mixed-signal peripheral devices such as Analog Devices’

AD183x family of audio codecs, ADCs, and DACs. The serial

ports are made up of two data lines, a clock, and a frame sync.

The data lines can be programmed to either transmit or receive

and each data line has a dedicated DMA channel.

Serial ports are enabled via 12 programmable and simultaneous

receive or transmit pins that support up to 24 transmit or 24

receive channels of audio data when all six SPORTS are enabled,

or six full duplex TDM streams of 128 channels per frame.

The serial ports operate at a maximum data rate of 41.67 Mbps.

Serial port data can be automatically transferred to and from

on-chip memory via dedicated DMA channels. Each of the

serial ports can work in conjunction with another serial port to

provide TDM support. One SPORT provides two transmit sig-

nals while the other SPORT provides the two receive signals.

The frame sync and clock are shared.

Serial ports operate in four modes:

• Standard DSP serial mode

• Multichannel (TDM) mode

• I

S mode

• Left-justified sample pair mode

Left-justified sample pair mode is a mode where in each frame

sync cycle two samples of data are transmitted/received—one

sample on the high segment of the frame sync, the other on the

low segment of the frame sync. Programs have control over var-

ious attributes of this mode.

Each of the serial ports supports the left-justified sample pair

and I

S protocols (I

S is an industry-standard interface com-

monly used by audio codecs, ADCs, and DACs, such as the

Analog Devices AD183x family), with two data pins, allowing

four left-justified sample pairs or I

S channels (using two stereo

devices) per serial port, with a maximum of up to 24 I

S chan-

nels. The serial ports permit little-endian or big-endian

transmission formats and word lengths selectable from 3 bits to

32 bits. For the left-justified sample pair and I

S modes, data-

word lengths are selectable between 8 bits and 32 bits. Serial

ports offer selectable synchronization and transmit modes as

well as optional μ-law or A-law companding selection on a per

channel basis. Serial port clocks and frame syncs can be inter-

nally or externally generated.

Parallel Port

The parallel port provides interfaces to SRAM and peripheral

devices. The multiplexed address and data pins (AD15–0) can

access 8-bit devices with up to 24 bits of address, or 16-bit

devices with up to 16 bits of address. In either mode, 8-bit or

16-bit, the maximum data transfer rate is 55 Mbps.

DMA transfers are used to move data to and from internal

memory. Access to the core is also facilitated through the paral-

lel port register read/write functions. The RD, WR, and ALE

(address latch enable) pins are the control pins for the

parallel port.

Serial Peripheral (Compatible) Interface

The processors contain two serial peripheral interface ports

(SPIs). The SPI is an industry-standard synchronous serial link,

enabling the ADSP-2136x SPI-compatible port to communicate

with other SPI-compatible devices. The SPI consists of two data

pins, one device select pin, and one clock pin. It is a full-duplex

synchronous serial interface, supporting both master and slave

modes. The SPI port can operate in a multimaster environment

by interfacing with up to four other SPI-compatible devices,

either acting as a master or slave device. The ADSP-2136x SPI-

compatible peripheral implementation also features program-

mable baud rate, clock phase, and polarities. The SPI-

compatible port uses open drain drivers to support a multimas-

ter configuration and to avoid data contention.

S/PDIF-Compatible Digital Audio Receiver/Transmitter

and Synchronous/Asynchronous Sample Rate Converter

The S/PDIF transmitter has no separate DMA channels. It

receives audio data in serial format and converts it into a

biphase encoded signal. The serial data input to the transmitter

can be formatted as left-justified, I

S, or right-justified with

word widths of 16, 18, 20, or 24 bits.

The serial data, clock, and frame sync inputs to the S/PDIF

transmitter are routed through the signal routing unit (SRU).

They can come from a variety of sources such as the SPORTs,

external pins, the precision clock generators (PCGs), or the

sample rate converters (SRC) and are controlled by the SRU

control registers.

The sample rate converter (SRC) contains four SRC blocks and

is the same core as that used in the AD1896 192 kHz stereo

asynchronous sample rate converter and provides up to 140 dB

SNR (see Table 2 on Page 4 for details). The SRC block is used

to perform synchronous or asynchronous sample rate conver-

sion across independent stereo channels, without using internal

processor resources. The four SRC blocks can also be config-

ured to operate together to convert multichannel audio data

without phase mismatches. Finally, the SRC is used to clean up

audio data from jittery clock sources such as the S/PDIF

receiver. The S/PDIF and SRC are not available on the

ADSP-21363 models.

Digital Transmission Content Protection

The DTCP specification defines a cryptographic protocol for

protecting audio entertainment content from illegal copying,

intercepting, and tampering as it traverses high performance

Rev. B | Page 8 of 56 | June 2007

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

digital buses, such as the IEEE 1394 standard. Only legitimate

entertainment content delivered to a source device via another

approved copy protection system (such as the DVD content

scrambling system) will be protected by this copy protection

system. This feature is available on the ADSP-21362 and

ADSP-21365 processors only. Licensing through DTLA is

required for these products. Visit www.dtcp.com for more

information.

Pulse-Width Modulation

The PWM module is a flexible, programmable, PWM waveform

generator that can be programmed to generate the required

switching patterns for various applications related to motor and

engine control or audio power control. The PWM generator can

generate either center-aligned or edge-aligned PWM wave-

forms. In addition, it can generate complementary signals on

two outputs in paired mode or independent signals in non-

paired mode (applicable to a single group of four PWM

waveforms).

The entire PWM module has four groups of four PWM outputs

each. Therefore, this module generates 16 PWM outputs in

total. Each PWM group produces two pairs of PWM signals on

the four PWM outputs.

The PWM generator is capable of operating in two distinct

modes while generating center-aligned PWM waveforms: single

update mode or double update mode. In single update mode the

duty cycle values are programmable only once per PWM period.

This results in PWM patterns that are symmetrical about the

midpoint of the PWM period. In double update mode, a second

updating of the PWM registers is implemented at the midpoint

of the PWM period. In this mode, it is possible to produce

asymmetrical PWM patterns that produce lower harmonic dis-

tortion in three-phase PWM inverters.

Timers

The ADSP-2136x has a total of four timers: a core timer that can

generate periodic software interrupts and three general-purpose

timers that can generate periodic interrupts and be indepen-

dently set to operate in one of three modes:

• Pulse waveform generation mode

• Pulse width count/capture mode

• External event watchdog mode

The core timer can be configured to use FLAG3 as a timer

expired signal, and each general-purpose timer has one bidirec-

tional pin and four registers that implement its mode of

operation: a 6-bit configuration register, a 32-bit count register,

a 32-bit period register, and a 32-bit pulse width register. A sin-

gle control and status register enables or disables all three

general-purpose timers independently.

ROM-Based Security

The ADSP-2136x has a ROM security feature that provides

hardware support for securing user software code by preventing

unauthorized reading from the internal code when enabled.

When using this feature, the processor does not boot-load any

external code, executing exclusively from internal SRAM/ROM.

Additionally, the processor is not freely accessible via the JTAG

port. Instead, a unique 64-bit key, which must be scanned in

through the JTAG or test access port will be assigned to each

customer. The device will ignore a wrong key. Emulation fea-

tures and external boot modes are only available after the

correct key is scanned.

Program Booting

The internal memory of the ADSP-2136x boots at system

power-up from an 8-bit EPROM via the parallel port, an SPI

master, an SPI slave, or an internal boot. Booting is determined

by the boot configuration (BOOTCFG1–0) pins (see Table 7 on

Page 15). Selection of the boot source is controlled via the SPI as

either a master or slave device, or it can immediately begin exe-

cuting from ROM.

Phase-Locked Loop

The processors use an on-chip phase-locked loop (PLL) to gen-

erate the internal clock for the core. On power up, the

CLKCFG1–0 pins are used to select ratios of 32:1, 16:1, and 6:1

(see Table 8 on Page 15). After booting, numerous other ratios

can be selected via software control.

The ratios are made up of software configurable numerator val-

ues from 1 to 64 and software configurable divisor values of 1, 2,

4, and 8.

Power Supplies

The ADSP-2136x has a separate power supply connection for

the internal (V

DDINT

), external (V

DDEXT

), and analog (A

VDD

VSS

)

power supplies. The internal and analog supplies must meet the

1.2 V requirement for K, B, and Y grade models, and the 1.0 V

requirement for Y models. (For information on the temperature

ranges offered for this product, see Operating Conditions on

Page 16, Package Information on Page 17, and Ordering Guide

on Page 53. The external supply must meet the 3.3 V require-

ment. All external supply pins must be connected to the same

power supply.

Note that the analog supply pin (A

VDD

) powers the processor’s

internal clock generator PLL. To produce a stable clock, it is rec-

ommended that PCB designs use an external filter circuit for the

VDD

pin. Place the filter components as close as possible to the

VDD

VSS

pins. For an example circuit, see Figure 4. (A recom-

mended ferrite chip is the muRata BLM18AG102SN1D). To

reduce noise coupling, the PCB should use a parallel pair of

power and ground planes for V

DDINT

and GND. Use wide traces

to connect the bypass capacitors to the analog power (A

VDD

) and

ground (A

VSS

) pins. Note that the A

VDD

and A

VSS

pins specified in

Figure 4 are inputs to the processor and not the analog ground

plane on the board—the A

VSS

pin should connect directly to dig-

ital ground (GND) at the chip.

Target Board JTAG Emulator Connector

Analog Devices DSP Tools product line of JTAG emulators uses

the IEEE 1149.1 JTAG test access port of the processor to moni-

tor and control the target board processor during emulation.

Analog Devices’ DSP Tools product line of JTAG emulators

provides emulation at full processor speed, allowing inspection

Rev. B | Page 9 of 56 | June 2007

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

VDDINT

HI Z FERRITE

BEAD CHIP

AVDD

AVSS

100nF 10nF 1nF ADSP-213xx

LOCATE ALL COMPONENTS

CLOSETO A

VDD AND AVSS PINS

Figure 4. Analog Power (A

VDD

) Filter Circuit

and modification of memory, registers, and processor stacks.

The processor’s JTAG interface ensures that the emulator will

not affect target system loading or timing.

For complete information on Analog Devices’ SHARC DSP

Tools product line of JTAG emulator operation, see the appro-

priate Emulator Hardware User’s Guide.

DEVELOPMENT TOOLS

The ADSP-2136x is supported with a complete set of

CROSSCORE

†

software and hardware development tools,

including Analog Devices emulators and VisualDSP++

‡

devel-

opment environment. The same emulator hardware that

supports other SHARC processors also fully emulates the

ADSP-2136x.

The VisualDSP++ project management environment lets pro-

grammers develop and debug an application. This environment

includes an easy to use assembler (which is based on an alge-

braic syntax), an archiver (librarian/library builder), a linker, a

loader, a cycle-accurate instruction-level simulator, a C/C++

compiler, and a C/C++ runtime library that includes DSP and

mathematical functions. A key point for these tools is C/C++

code efficiency. The compiler has been developed for efficient

translation of C/C++ code to DSP assembly. The SHARC has

architectural features that improve the efficiency of compiled

C/C++ code.

The VisualDSP++ debugger has a number of important fea-

tures. Data visualization is enhanced by a plotting package that

offers a significant level of flexibility. This graphical representa-

tion of user data enables the programmer to quickly determine

the performance of an algorithm. As algorithms grow in com-

plexity, this capability can have increasing significance on the

designer’s development schedule, increasing productivity. Sta-

tistical profiling enables the programmer to nonintrusively poll

the processor as it is running the program. This feature, unique

to VisualDSP++, enables the software developer to passively

gather important code execution metrics without interrupting

the real-time characteristics of the program. Essentially, the

developer can identify bottlenecks in software quickly and

efficiently. By using the profiler, the programmer can focus on

those areas in the program that impact performance and take

corrective action.

†

CROSSCORE is a registered trademark of Analog Devices, Inc.

‡

VisualDSP++ is a registered trademark of Analog Devices, Inc.

Debugging both C/C++ and assembly programs with the

VisualDSP++ debugger, programmers can:

• View mixed C/C++ and assembly code (interleaved source

and object information)

• Insert breakpoints

• Set conditional breakpoints on registers, memory,

and stacks

• Trace instruction execution

• Perform linear or statistical profiling of program execution

• Fill, dump, and graphically plot the contents of memory

• Perform source level debugging

• Create custom debugger windows

The VisualDSP++ IDDE lets programmers define and manage

DSP software development. Its dialog boxes and property pages

let programmers configure and manage all of the SHARC devel-

opment tools, including the color syntax highlighting in the

VisualDSP++ editor. This capability permits programmers to:

• Control how the development tools process inputs and

generate outputs

• Maintain a one-to-one correspondence with the tool’s

command line switches

The VisualDSP++ Kernel (VDK) incorporates scheduling and

resource management tailored specifically to address the mem-

ory and timing constraints of DSP programming. These

capabilities enable engineers to develop code more effectively,

eliminating the need to start from the very beginning, when

developing new application code. The VDK features include

threads, critical and unscheduled regions, semaphores, events,

and device flags. The VDK also supports priority-based, pre-

emptive, cooperative, and time-sliced scheduling approaches. In

addition, the VDK was designed to be scalable. If the application

does not use a specific feature, the support code for that feature

is excluded from the target system.

Because the VDK is a library, a developer can decide whether to

use it or not. The VDK is integrated into the VisualDSP++

development environment, but can also be used via standard

command line tools. When the VDK is used, the development

environment assists the developer with many error-prone tasks

and assists in managing system resources, automating the gen-

eration of various VDK-based objects, and visualizing the

system state, when debugging an application that uses the VDK.

VisualDSP++ component software engineering (VCSE) is

Analog Devices’ technology for creating, using, and reusing

software components (independent modules of substantial

functionality) to quickly and reliably assemble software applica-

tions. It allows downloading components from the Web,

dropping them into the application, and publishing component

archives from within VisualDSP++. VCSE supports component

implementation in C/C++ or assembly language.

Use the expert linker to visually manipulate the placement of

code and data on the embedded system. View memory utiliza-

tion in a color-coded graphical form, easily move code and data

to different areas of the processor or external memory with a

Rev. B | Page 10 of 56 | June 2007

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

drag of the mouse and examine runtime stack and heap usage.

The expert linker is fully compatible with the existing linker def-

inition file (LDF), allowing the developer to move between the

graphical and textual environments.

In addition to the software and hardware development tools

available from Analog Devices, third parties provide a wide

range of tools supporting the SHARC processor family. Hard-

ware tools include SHARC processor PC plug-in cards. Third

party software tools include DSP libraries, real-time operating

systems, and block diagram design tools.

Designing an Emulator-Compatible DSP Board (Target)

The Analog Devices family of emulators are tools that every

DSP developer needs to test and debug hardware and software

systems. Analog Devices has supplied an IEEE 1149.1 JTAG test

access port (TAP) on each JTAG processor. Nonintrusive in-

circuit emulation is assured by the use of the processor’s JTAG

interface—the emulator does not affect target system loading or

timing. The emulator uses the TAP to access the internal fea-

tures of the processor, allowing the developer to load code, set

breakpoints, observe variables, observe memory, and examine

registers. The processor must be halted to send data and com-

mands, but once an operation has been completed by the

emulator, the DSP system is set running at full speed with no

impact on system timing.

To use these emulators, the target board must include a header

that connects the DSP’s JTAG port to the emulator.

For details on target board design issues including mechanical

layout, single processor connections, multiprocessor scan

chains, signal buffering, signal termination, and emulator pod

logic, see the Analog Devices JTAG Emulation Technical Refer-

ence (EE-68) on the Analog Devices website

(www.analog.com)—use site search on “EE-68.” This document

is updated regularly to keep pace with improvements to emula-

tor support.

Evaluation Kit

Analog Devices offers a range of EZ-KIT Lite

†

evaluation plat-

forms to use as a cost-effective method to learn more about

developing or prototyping applications with Analog Devices

processors, platforms, and software tools. Each EZ-KIT Lite

platform includes an evaluation board along with an evaluation

suite of the VisualDSP++ development and debugging environ-

ment with the C/C++ compiler, assembler, and linker. Also

included are sample application programs, power supply, and a

USB cable. All evaluation versions of the software tools are lim-

ited for use only with the EZ-KIT Lite product.

The USB controller on the EZ-KIT Lite board connects the

board to the USB port of the user’s PC, enabling the

VisualDSP++ evaluation suite to emulate the on-board proces-

sor in-circuit. This permits the customer to download, execute,

and debug programs for the EZ-KIT Lite system. It also allows

in-circuit programming of the on-board flash device to store

user-specific boot code, enabling the board to run as a stand-

alone unit without being connected to the PC.

†

EZ-KIT Lite is a registered trademark of Analog Devices, Inc.

With a full version of VisualDSP++ installed (sold separately),

engineers can develop software for the EZ-KIT Lite or any cus-

tom defined system. Connecting one of Analog Devices’ JTAG

emulators to the EZ-KIT Lite board enables high speed, non-

intrusive emulation.

ADDITIONAL INFORMATION

This data sheet provides a general overview of the

ADSP-2136x architecture and functionality. For detailed infor-

mation on the ADSP-2136x family core architecture and

instruction set, refer to the ADSP-2136x SHARC Processor

Hardware Reference and the ADSP-2136x SHARC Processor

Programming Reference.

Rev. B | Page 11 of 56 | June 2007

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

PIN FUNCTION DESCRIPTIONS

The ADSP-2136x pin definitions are listed below. Inputs identi-

fied as synchronous (S) must meet timing requirements with

respect to CLKIN (or with respect to TCK for TMS and TDI).

Inputs identified as asynchronous (A) can be asserted asynchro-

nously to CLKIN (or to TCK for TRST). Tie or pull unused

inputs to V

DDEXT

or GND, except for the following:

Table 4. Pin Descriptions

• DAI_Px, SPICLK, MISO, MOSI, EMU, TMS, TRST, TDI,

and AD15–0 (NOTE: These pins have pull-up resistors.)

The following symbols appear in the Type column of Table 4:

A = asynchronous, G = ground, I = input, O = output,

P = power supply, S = synchronous, (A/D) = active drive,

(O/D) = open drain, and T = three-state, (pd) = pull-down resis-

tor, (pu) = pull-up resistor.

Pin Type

State During and

After Reset Function

AD15–0

ALE

FLAG3–0

DAI_P20–1

I/O/T

(pu)

(pd)

I/O/A

I/O/T

(pu)

Three-state with

pull-up enabled

Three-state, driven

high

Three-state, driven

high

Three-state, driven

low

Three-state

Three-state with

programmable

pull-up

Parallel Port Address/Data. The ADSP-2136x parallel port and its corresponding

DMA unit output addresses and data for peripherals on these multiplexed pins. The

multiplex state is determined by the ALE pin. The parallel port can operate in either

8-bit or 16-bit mode. Each AD pin has a 22.5 kΩ internal pull-up resistor. See

Address/Data Modes on Page 15 for details of the AD pin operation.

For 8-bit mode: ALE is automatically asserted whenever a change occurs in the upper

16 external address bits, A23–8; ALE is used in conjunction with an external latch to

retain the values of the A23–8.

For detailed information on I/O operations and pin multiplexing, see the ADSP-2136x

SHARC Processor Hardware Reference.

Parallel Port Read Enable. RD is asserted low whenever the processor reads 8-bit or

16-bit data from an external memory device. When AD15–0 are flags, this pin remains

deasserted. RD has a 22.5 kΩ internal pull-up resistor.

Parallel Port Write Enable. WR is asserted low whenever the processor writes 8-bit or

16-bit data to an external memory device. When AD15–0 are flags, this pin remains

deasserted. WR has a 22.5 kΩ internal pull-up resistor.

Parallel Port Address Latch Enable. ALE is asserted whenever the processor drives

a new address on the parallel port address pins. On reset, ALE is active high. However,

it can be reconfigured using software to be active low. When AD15–0 are flags, this

pin remains deasserted. ALE has a 20 kΩ internal pull-down resistor.

Flag Pins. Each flag pin is configured via control bits as either an input or output. As

an input, it can be tested as a condition. As an output, it can be used to signal external

peripherals. These pins can be used as an SPI interface slave select output during SPI

mastering. These pins are also multiplexed with the IRQx and the TIMEXP signals. For

detailed information on I/O operations and pin multiplexing, see the ADSP-2136x

SHARC Processor Hardware Reference.

Digital Audio Interface Pins. These pins provide the physical interface to the SRU.

The SRU configuration registers define the combination of on-chip peripheral inputs

or outputs connected to the pin and to the pin’s output enable. The configuration

registers of these peripherals then determines the exact behavior of the pin. Any input

or output signal present in the SRU may be routed to any of these pins. The SRU

provides the connection from the serial ports, input data port, precision clock gener-

ators and timers, sample rate converters and SPI to the DAI_P20–1 pins. These pins

have internal 22.5 kΩ pull-up resistors which are enabled on reset. These pull-ups can

be disabled in the DAI_PIN_PULLUP register.

Rev. B | Page 12 of 56 | June 2007

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

Table 4. Pin Descriptions (Continued)

Pin Type

State During and

After Reset Function

SPICLK

SPIDS

MOSI

MISO

BOOTCFG1–0

CLKIN

XTAL

CLKCFG1–0

I/O

(pu)

I/O (O/D)

(pu)

I/O (O/D)

(pu)

Three-state with

pull-up enabled

Input only

Three-state with

pull-up enabled

Three-state with

pull-up enabled

Input only

Output only

Input only

Serial Peripheral Interface Clock Signal. Driven by the master, this signal controls

the rate at which data is transferred. The master may transmit data at a variety of baud

rates. SPICLK cycles once for each bit transmitted. SPICLK is a gated clock that is active

during data transfers, only for the length of the transferred word. Slave devices ignore

the serial clock if the slave select input is driven inactive (HIGH). SPICLK is used to shift

out and shift in the data driven on the MISO and MOSI lines. The data is always shifted

out on one clock edge and sampled on the opposite edge of the clock. Clock polarity

and clock phase relative to data are programmable into the SPICTL control register

and define the transfer format. SPICLK has a 22.5 kΩ internal pull-up resistor.

Serial Peripheral Interface Slave Device Select. An active low signal used to select

the processor as an SPI slave device. This input signal behaves like a chip select, and

is provided by the master device for the slave devices. In multimaster mode the

processor’s SPIDS signal can be driven by a slave device to signal to the processor (as

SPI master) that an error has occurred, as some other device is also trying to be the

master device. If asserted low when the device is in master mode, it is considered a

multimaster error. For a single-master, multiple-slave configuration where flag pins

are used, this pin must be tied or pulled high to V

DDEXT

on the master device. For

processor to processor SPI interaction, any of the master processor’s flag pins can be

used to drive the SPIDS signal on the SPI slave device.

SPI Master Out Slave In. If the ADSP-2136x is configured as a master, the MOSI pin

becomes a data transmit (output) pin, transmitting output data. If the processor is

configured as a slave, the MOSI pin becomes a data receive (input) pin, receiving input

data. In a SPI interconnection, the data is shifted out from the MOSI output pin of the

master and shifted into the MOSI input(s) of the slave(s). MOSI has a 22.5 kΩ internal

pull-up resistor.

SPI Master In Slave Out. If the ADSP-2136x is configured as a master, the MISO pin

becomes a data receive (input) pin, receiving input data. If the processor is configured

as a slave, the MISO pin becomes a data transmit (output) pin, transmitting output

data. In an SPI interconnection, the data is shifted out from the MISO output pin of the

slave and shifted into the MISO input pin of the master. MISO has a 22.5 kΩ internal

pull-up resistor. MISO can be configured as O/D by setting the OPD bit in the SPICTL

Note: Only one slave is allowed to transmit data at any given time. To enable broadcast

transmission to multiple SPI-slaves, the processor’s MISO pin may be disabled by

setting (=1) Bit 5 (DMISO) of the SPICTL register.

Boot Configuration Select. This pin is used to select the boot mode for the processor.

The BOOTCFG pins must be valid before reset is asserted. See Table 7 for a description

of the boot modes.

Local Clock In. Used in conjunction with XTAL. CLKIN is the ADSP-2136x clock input.

It configures the ADSP-2136x to use either its internal clock generator or an external

clock source. Connecting the necessary components to CLKIN and XTAL enables the

internal clock generator. Connecting the external clock to CLKIN while leaving XTAL

unconnected configures the processors to use the external clock source such as an

external clock oscillator. The core is clocked either by the PLL output or this clock input

depending on the CLKCFG1–0 pin settings. CLKIN may not be halted, changed, or

operated below the specified frequency.

Crystal Oscillator Terminal. Used in conjunction with CLKIN to drive an external

crystal.

Core/CLKIN Ratio Control. These pins set the start up clock frequency. See Table 8

for a description of the clock configuration modes. Note that the operating frequency

can be changed by programming the PLL multiplier and divider in the PMCTL register

at any time after the core comes out of reset.

Rev. B | Page 13 of 56 | June 2007

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

Table 4. Pin Descriptions (Continued)

Pin Type

State During and

After Reset Function

RSTOUT/CLKOUT

RESET

TCK

TMS

TDI

TDO

TRST

EMU

DDINT

DDEXT

VDD

VSS

GND

I/A

I/S

(pu)

I/S

(pu)

I/A

(pu)

O (O/D)

(pu)

Output only

Input only

Three-state with

pull-up enabled

Three-state with

pull-up enabled

Three-state

Three-state with

pull-up enabled

Three-state with

pull-up enabled

Local Clock Out/Reset Out. Drives out the core reset signal to an external device.

CLKOUT can also be configured as a reset out pin. The functionality can be switched

between the PLL output clock and reset out by setting Bit 12 of the PMCTREG register.

The default is reset out.

Processor Reset. Resets the ADSP-2136x to a known state. Upon deassertion, there is

a 4096 CLKIN cycle latency for the PLL to lock. After this time, the core begins program

execution from the hardware reset vector address. The RESET input must be asserted

(low) at power-up.

Test Clock (JTAG). Provides a clock for JTAG boundary scan. TCK must be asserted

(pulsed low) after power-up or held low for proper operation of the processors.

Test Mode Select (JTAG). Used to control the test state machine. TMS has a 22.5 kΩ

internal pull-up resistor.

Test Data Input (JTAG). Provides serial data for the boundary scan logic. TDI has a

22.5 kΩ internal pull-up resistor.

Test Data Output (JTAG). Serial scan output of the boundary scan path.

Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed low)

after power-up or held low for proper operation of the ADSP-2136x. TRST has a

22.5 kΩ internal pull-up resistor.

Emulation Status. Must be connected to the processor’s JTAG emulators target board

connector only. EMU has a 22.5 kΩ internal pull-up resistor.

Core Power Supply. Nominally +1.2 V dc for the K, B grade models, and 1.0 V dc for

the Y grade models, and supplies the processor’s core (13 pins).

I/O Power Supply. Nominally +3.3 V dc (6 pins).

Analog Power Supply. Nominally +1.2 V dc for the K, B grade models, and 1.0 V dc for

the Y grade models, and supplies the processor’s internal PLL (clock generator). This

pin has the same specifications as V

DDINT

, except that added filtering circuitry is

required. For more information, see Power Supplies on Page 9.

Analog Power Supply Return.

Power Supply Return. (54 pins)

RD, WR, and ALE are three-stated (and not driven) only when RESET is active.

Output only is a three-state driver with its output path always enabled.

Input only is a three-state driver with both output path and pull-up disabled.

Three-state is a three-state driver with pull-up disabled.

Rev. B | Page 14 of 56 | June 2007

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

ADDRESS DATA PINS AS FLAGS

To use these pins as flags (FLAGS15–0) set (=1) Bit 20 of the

SYSCTL register to disable the parallel port. Then set (=1)

Bits 22 to 25 in the SYSCTL register accordingly.

Table 5. AD15–0 to Flag Pin Mapping

AD Pin Flag Pin AD Pin Flag Pin

AD0 FLAG8 AD8 FLAG0

AD1 FLAG9 AD9 FLAG1

AD2 FLAG10 AD10 FLAG2

AD3 FLAG11 AD11 FLAG3

AD4 FLAG12 AD12 FLAG4

AD5 FLAG13 AD13 FLAG5

AD6 FLAG14 AD14 FLAG6

AD7 FLAG15 AD15 FLAG7

ADDRESS/DATA MODES

The following table shows the functionality of the AD pins for

8-bit and 16-bit transfers to the parallel port. For 8-bit data

transfers, ALE latches Address Bits A23–A8 when asserted, fol-

lowed by Address Bits A7–A0 and Data Bits D7–D0 when

deasserted. For 16-bit data transfers, ALE latches Address Bits

A15–A0 when asserted, followed by Data Bits D15–D0 when

deasserted.

Table 6. Address/Data Mode Selection

BOOT MODES

Table 7. Boot Mode Selection

BOOTCFG1–0 Booting Mode

00 SPI Slave Boot

01 SPI Master Boot

10 Parallel Port Boot via EPROM

11 Internal

CORE INSTRUCTION RATE TO CLKIN RATIO MODES

For details on processor timing, see Timing Specifications and

Figure 6 on Page 18.

Table 8. Core Instruction Rate/CLKIN Ratio Selection

CLKCFG1–0 Core to CLKIN Ratio

00 6:1

01 32:1

10 16:1

11 Reserved (Bypass)

PP Data AD7–0 AD15–8

Mode ALE Function Function

8-bit Asserted A15–8 A23–16

8-bit Deasserted D7–0 A7–0

16-bit Asserted A7–0 A15–8

16-bit Deasserted D7–0 D15–8

Rev. B | Page 15 of 56 | June 2007

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

ADSP-2136x SPECIFICATIONS

OPERATING CONDITIONS

Parameter

Description

K Grade B Grade Y Grade

Min Max Min Max Min Max Unit

DDINT

VDD

DDEXT

CLKIN

4, 5

Internal (Core) Supply Voltage

Analog (PLL) Supply Voltage

External (I/O) Supply Voltage

High Level Input Voltage @ V

DDEXT

= max

Low Level Input Voltage @ V

DDEXT

= min

High Level Input Voltage @ V

DDEXT

= max

Low Level Input Voltage @ V

DDEXT

= min

Junction Temperature 136-Ball CSP-BGA

Junction Temperature 144-Lead LQFP_EP

1.14 1.26

3.13 3.47

2.0 V

DDEXT

+ 0.5

–0.5 +0.8

1.74 V

DDEXT

+ 0.5

–0.5 +1.19

0 +110

1.14 1.26

3.13 3.47

2.0 V

DDEXT

+ 0.5

–0.5 +0.8

1.74 V

DDEXT

+ 0.5

–0.5 +1.19

–40 +125

0.95 1.05

3.13 3.47

2.0 V

DDEXT

+ 0.5

–0.5 +0.8

1.74 V

DDEXT

+ 0.5

–0.5 +1.19

–40 +125

°C

Specifications subject to change without notice.

Applies to input and bidirectional pins: AD15–0, FLAG3–0, DAI_Px, SPICLK, MOSI, MISO, SPIDS, BOOTCFGx, CLKCFGx, RESET, TCK, TMS, TDI, TRST.

Applies to input pin CLKIN.

See Thermal Characteristics on Page 46 for information on thermal specifications.

See Estimating Power for the ADSP-21362 SHARC Processors (EE-277) for further information.

ELECTRICAL CHARACTERISTICS

Parameter

Description Test Conditions Min Max Unit

4, 5

ILPU

OZH

6, 7

OZL

OZLPU

INTYP

8, 9

11, 12

High Level Output Voltage

Low Level Output Voltage

High Level Input Current

Low Level Input Current

Low Level Input Current Pull-Up

Three-State Leakage Current

Three-State Leakage Current Pull-Up

Supply Current (Internal)

Supply Current (Analog)

Input Capacitance

@ V

DDEXT

= min, I

= –1.0 mA

@ V

DDEXT

= min, I

= 1.0 mA

@ V

DDEXT

= max, V

= V

DDEXT

max

@ V

DDEXT

= max, V

= 0 V

@ V

DDEXT

= max, V

= 0 V

@ V

DDEXT

= max, V

= V

DDEXT

max

@ V

DDEXT

= max, V

= 0 V

@ V

DDEXT

= max, V

= 0 V

CCLK

= min, V

DDINT

= nom

VDD

= max

= 1 MHz, T

CASE

= 25°C, V

= 1.2 V

2.4

0.4

200

800

4.7

µA

Specifications subject to change without notice.

Applies to output and bidirectional pins: AD15–0, RD, WR, ALE, FLAG3–0, DAI_Px, SPICLK, MOSI, MISO, EMU, TDO, CLKOUT, XTAL.

See Output Drive Currents on Page 45 for typical drive current capabilities.

Applies to input pins: SPIDS, BOOTCFGx, CLKCFGx, TCK, RESET, CLKIN.

Applies to input pins with 22.5 kΩ internal pull-ups: TRST, TMS, TDI.

Applies to three-stateable pins: FLAG3–0.

Applies to three-stateable pins with 22.5 kΩ pull-ups: AD15–0, DAI_Px, SPICLK, EMU, MISO, MOSI.

Typical internal current data reflects nominal operating conditions.

See Estimating Power for the ADSP-21362 SHARC Processors (EE-277) for further information.

Characterized, but not tested.

Applies to all signal pins.

Guaranteed, but not tested.

Rev. B | Page 16 of 56 | June 2007

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

PACKAGE INFORMATION

The information presented in Figure 5 provides details about

the package branding for the ADSP-2136x processor. For a

complete listing of product availability, see Ordering Guide on

Page 53.

vvvvvv.x n.n

tppZ-cc

ADSP-2136x

yyww country_of_origin

Figure 5. Typical Package Brand

Table 9. Package Brand Information

Brand Key Field Description

t Temperature Range

pp Package Type

Z RoHS Compliant Option

cc See Ordering Guide

vvvvvv.x Assembly Lot Code

n.n Silicon Revision

yyww Date Code

ABSOLUTE MAXIMUM RATINGS

Stresses greater than those listed below may cause permanent

damage to the device. These are stress ratings only; functional

operation of the device at these or any other conditions greater

than those indicated in the operational sections of this specifica-

tion is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect device reliability.

Parameter

Internal (Core) Supply Voltage (V

DDINT

) –0.3 V to +1.5 V

Analog (PLL) Supply Voltage (A

VDD

) –0.3 V to +1.5 V

External (I/O) Supply Voltage (V

DDEXT

) –0.3 V to +4.6 V

Input Voltage –0.5 V to +3.8 V

Output Voltage Swing –0.5 V to V

DDEXT

+ 0.5 V

Load Capacitance 200 pF

Storage Temperature Range –65°C to +150°C

Junction Temperature Under Bias 125°C

Rating

MAXIMUM POWER DISSIPATION

See Estimating Power for the ADSP-21362 SHARC Processors

(EE-277) for detailed thermal and power information regarding

maximum power dissipation. For information on package ther-

mal specifications, see Thermal Characteristics on Page 46.

ESD SENSITIVITY

ESD (electrostatic discharge) sensitive

device. Charged devices and circuit boards can

discharge without detection. Although this

product features patented or proprietary

circuitry, damage may occur on devices

subjected to high energy ESD. Therefore,

proper ESD precautions should be take to

avoid performance degradation or loss of

functionality.

TIMING SPECIFICATIONS

The ADSP-2136x’s internal clock (a multiple of CLKIN) pro-

vides the clock signal for timing internal memory, processor

core, serial ports, and parallel port (as required for read/write

strobes in asynchronous access mode). During reset, program

the ratio between the processor’s internal clock frequency and

external (CLKIN) clock frequency with the CLKCFG1–0 pins

(see Table 8 on Page 15). To determine switching frequencies

for the serial ports, divide down the internal clock, using the

programmable divider control of each port (DIVx for the

serial ports).

The ADSP-2136x’s internal clock switches at higher frequencies

than the system input clock (CLKIN). To generate the internal

clock, the processor uses an internal phase-locked loop (PLL).

This PLL-based clocking minimizes the skew between the sys-

tem clock (CLKIN) signal and the processor’s internal clock (the

clock source for the parallel port logic and I/O pads).

Note the definitions of various clock periods that are a function

of CLKIN and the appropriate ratio control shown in Table 10

and Table 11.

Table 10. ADSP-2136x Clock Generation Operation

Timing

Requirements Description Calculation

CLKIN Input Clock 1/t

CCLK Core Clock 1/t

CCLK

Rev. B | Page 17 of 56 | June 2007

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

Table 11. Clock Periods

Timing

Requirements Description

CLKIN Clock Period

CCLK

(Processor) Core Clock Period

PCLK

(Peripheral) Clock Period = 2 × t

CCLK

SCLK

Serial Port Clock Period = (t

CCLK

) × SR

SPICLK

SPI Clock Period = (t

CCLK

) × SPIR

where:

SR = serial port-to-peripheral clock ratio (wide range, determined by SPORT

CLKDIV)

SPIR = SPI-to-peripheral clock ratio (wide range, determined by SPIBAUD

DAI_Px = serial port clock

SPICLK = SPI clock

Figure 6 shows core to CLKIN ratios of 6:1, 16:1, and 32:1 with

external oscillator or crystal. Note that more ratios are possible

and can be set through software using the power management

control register (PMCTL). For more information, see the

ADSP-2136x SHARC Processor Programming Reference, the

ADSP-2136x SHARC Processor Hardware Reference and Manag-

ing the Core PLL on Third-Generation SHARC Processors (EE-

290).

Use the exact timing information given. Do not attempt to

derive parameters from the addition or subtraction of others.

While addition or subtraction would yield meaningful results

DIVEN

÷1, 2, 4, 8

PLLM

DELAY

PLLICLK

XTAL

OSC

CLK_CFG [1:0]

(6:1, 16:1, 32:1)

INDIV

÷1, 2

RESET

CLKIN

for an individual device, the values given in this data sheet

reflect statistical variations and worst cases. Consequently, it is

not meaningful to add parameters to derive longer times. See

Figure 39 on Page 45 under Test Conditions for voltage

reference levels.

Note that in the user application, the PLL multiplier value

should be selected in such a way that the VCO frequency never

exceeds 800 MHz. The VCO frequency is calculated as follows:

VCO

= 2 × PLLM × f

INPUT

where:

• f

VCO

is the VCO frequency.

• PLLM is the multiplier value programmed.

• f

INPUT

is the input frequency to the PLL.

• f

INPUT

= CLKIN when the input divider is disabled and

• f

INPUT

= CLKIN ÷ 2 when the input divider is enabled.

Timing Requirements apply to signals that are controlled by cir-

cuitry external to the processor, such as the data input for a read

operation. Timing requirements guarantee that the processor

operates correctly with other devices.

Switching Characteristics specify how the processor changes its

signals. Circuitry external to the processor must be designed for

compatibility with these signal characteristics. Switching char-

acteristics describe what the processor will do in a given

circumstance. Use switching characteristics to ensure that any

timing requirement of a device connected to the processor (such

as memory) is satisfied.

CCLK

(CORE CLOCK)

÷2 PCLK

(PERIPHERAL CLOCK)

CLKOUT

RESETOUT

Figure 6. Core Clock and System Clock Relationship to CLKIN

Rev. B | Page 18 of 56 | June 2007

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

Power-Up Sequencing

The timing requirements for processor startup are given in

Table 12.

Table 12. Power-Up Sequencing Timing Requirements (Processor Startup)

Parameter

Timing Requirements

RSTVDD

IVDDEVDD

CLKVDD

CLKRST

PLLRST

RESET Low Before V

DDINT

DDEXT

DDINT

On Before V

DDEXT

CLKIN Valid After V

DDINT

DDEXT

Valid

CLKIN Valid Before RESET Deasserted

PLL Control Setup Before RESET Deasserted

Min

–50

Max

+200

Unit

µs

Switching Characteristic

CORERST

Core Reset Deasserted After RESET Deasserted 4096t

+ 2 t

CCLK

3, 4

Valid V

DDINT

DDEXT

assumes that the supplies are fully ramped to their 1.2 volt rails and 3.3 volt rails. Voltage ramp rates can vary from microseconds to hundreds of

milliseconds depending on the design of the power supply subsystem.

Assumes a stable CLKIN signal, after meeting worst-case start-up timing of crystal oscillators. Refer to your crystal oscillator manufacturer’s data sheet for start-up time.

Assume a 25 ms maximum oscillator start-up time if using the XTAL pin and internal oscillator circuit in conjunction with an external crystal.

Applies after the power-up sequence is complete. Subsequent resets require a minimum of 4 CLKIN cycles for RESET to be held low in order to properly initialize and

propagate default states at all I/O pins.

The 4096 cycle count depends on t

SRST

specification in Table 14. If setup time is not met, 1 additional CLKIN cycle may be added to the core reset time, resulting in 4097

cycles maximum.

RESET

tRSTVDD

VDDINT

VDDEXT

CLKIN

CLK_CFG1-0

RSTOUT

tPLLRST

tCLKRST

tCLKVDD

tIVDDEVDD

tCORERST

Figure 7. Power-Up Sequencing

Rev. B | Page 19 of 56 | June 2007

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

Clock Input

Table 13. Clock Input

Parameter

333 MHz

Unit

Min Max

Timing Requirements

CLKIN Period

CKL

CLKIN Width Low

CKH

CLKIN Width High

CKRF

CLKIN Rise/Fall (0.4 V to 2.0 V)

CCLK

CCLK Period

CKJ

3,4

CLKIN Jitter Tolerance

7.5

3.0

–250

100

+250

Applies only for CLKCFG1–0 = 00 and default values for PLL control bits in PMCTL.

Any changes to PLL control bits in the PMCTL register must meet core clock timing specification t

CCLK

Actual input jitter should be combined with ac specifications for accurate timing analysis.

Jitter specification is maximum peak-to-peak time interval error (TIE) jitter.

CLKIN

Figure 8. Clock Input

Clock Signals

The ADSP-2136x can use an external clock or a crystal. See the

CLKIN pin description in Table 4 on Page 12. The user applica-

tion program can configure theADSP-2136x to use its internal

clock generator by connecting the necessary components to the

CLKIN and XTAL pins. Figure 9 shows the component connec-

tions used for a fundamental frequency crystal operating in

parallel mode.

Note that the clock rate is achieved using a 16.67 MHz crystal

and a PLL multiplier ratio 16:1 (CCLK:CLKIN achieves a clock

speed of 266.72 MHz). To achieve the full core clock rate, pro-

grams need to configure the multiplier bits in the

PMCTL register.

tCK

tCKH tCKL

tCKJ

47�*

C1 C2

22pF 22pF

1M�*

XTAL

CLKIN

24.576MHz

ADSP-2136X

R2 SHOULD BE CHOSEN TO LIMIT CRYSTAL

DRIVE POWER. REFER TO CRYSTAL

MANUFACTURER’SSPECIFICATIONS

*TYPICAL VALUES

Figure 9. 333 MHz Operation (Fundamental Mode Crystal)

Rev. B | Page 20 of 56 | June 2007

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

Reset

Table 14. Reset

Parameter

Timing Requirements

WRST

RESET Pulse Width Low

SRST

RESET Setup Before CLKIN Low

Min

Max Unit

Applies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 100 μs while RESET is low, assuming stable

and CLKIN (not including start-up time of external clock oscillator).

CLKIN

RESET

tWRST tSRST

Figure 10. Reset

Interrupts

The following timing specification applies to the FLAG0,

FLAG1, and FLAG2 pins when they are configured as IRQ0,

IRQ1, and IRQ2 interrupts.

Table 15. Interrupts

Parameter Min Max Unit

Timing Requirement

IPW

IRQx Pulse Width 2 × t

PCLK

+2 ns

DAI20

FLAG2

(IRQ2

0) tIPW

Figure 11. Interrupts

Rev. B | Page 21 of 56 | June 2007

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

Core Timer

The following timing specification applies to FLAG3 when it is

configured as the core timer (CTIMER).

Table 16. Core Timer

Parameter Min Max Unit

Switching Characteristic

WCTIM

CTIMER Pulse Width 2 × t

PCLK

– 1 ns

FLAG3

(CTIMER)

tWCTIM

Figure 12. Core Timer

Timer PWM_OUT Cycle Timing

The following timing specification applies to Timer0, Timer1,

and Timer2 in PWM_OUT (pulse-width modulation) mode.

Timer signals are routed to the DAI_P20–1 pins through the

SRU. Therefore, the timing specifications provided below are

valid at the DAI_P20–1 pins.

Table 17. Timer PWM_OUT Timing

Parameter Min Max Unit

Switching Characteristic

PWMO

Timer Pulse Width Output 2 t

PCLK

– 1 2(2

– 1) t

PCLK

DAI_P20

(TIMER2

tPWM O

Figure 13. Timer PWM_OUT Timing

Rev. B | Page 22 of 56 | June 2007

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

Timer WDTH_CAP Timing

The following timing specification applies to Timer0, Timer1,

and Timer2 in WDTH_CAP (pulse width count and capture)

mode. Timer signals are routed to the DAI_P20–1 pins through

the SRU. Therefore, the timing specification provided below are

valid at the DAI_P20–1 pins.

Table 18. Timer Width Capture Timing

Parameter Min Max Unit

Timing Requirement

PWI

Timer Pulse Width 2 t

PCLK

2(2

– 1) t

PCLK

DAI_P20-1

(TIMER2-0)

tPWI

Figure 14. Timer Width Capture Timing

DAI Pin to Pin Direct Routing

For direct pin connections only (for example, DAI_PB01_I to

DAI_PB02_O).

Table 19. DAI Pin to Pin Routing

Parameter Min Max Unit

Timing Requirement

DPIO

Delay DAI Pin Input Valid to DAI Output Valid 1.5 10 ns

DAI_Pn

DAI_Pm

tDPIO

Figure 15. DAI Pin to Pin Direct Routing

Rev. B | Page 23 of 56 | June 2007

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

Precision Clock Generator (Direct Pin Routing)

This timing is only valid when the SRU is configured such that

the precision clock generator (PCG) takes its inputs directly

from the DAI pins (via pin buffers) and sends its outputs

directly to the DAI pins. For the other cases, where the PCG’s

Table 20. Precision Clock Generator (Direct Pin Routing)

inputs and outputs are not directly routed to/from DAI pins (via

pin buffers) there is no timing data available. All timing param-

eters and switching characteristics apply to external DAI pins

(DAI_P01 – DAI_P20).

Parameter

K and B Grade

Min Max

Y Grade

Max Unit

Timing Requirements

PCGIP

Input Clock Period

STRIG

PCG Trigger Setup Before Falling

Edge of PCG Input Clock

HTRIG

PCG Trigger Hold After Falling

Edge of PCG Input Clock

Switching Characteristics

DPCGIO

PCG Output Clock and Frame Sync

Active Edge Delay After PCG Input

Clock

DTRIGCLK

PCG Output Clock Delay After PCG

Trigger

DTRIGFS

PCG Frame Sync Delay After PCG

Trigger

PCGOP

Output Clock Period

4.5

2.5 10

2.5 + ((2.5 + D) × t

PCGIP

) 10 + ((2.5 + D) × t

PCGIP

)

2.5 + ((2.5 + D – PH) × t

PCGIP

) 10 + ((2.5 + D – PH) × t

PCGIP

)

2 × t

PCGIP

12 + ((2.5 + D) × t

PCGIP

)

12 + ((2.5 + D – PH) × t

PCGIP

)

D = FSxDIV, PH = FSxPHASE. For more information, see the ADSP-2136x SHARC Processor Hardware Reference, “Precision Clock Generators” chapter.

In normal mode, t

PCGOP

(min) = 2 × t

PCGIP

DAI_Pn

PCG_TRIGx_I

DAI_Pm

PCG_EXTx_I

(CLKIN)

DAI_Py

PCG_CLKx_O

DAI_Pz

PCG_FSx_O

tSTRIG tHTRIG

tDPCGIO

tDTRIGFS

tPCGIP

tPCGOP

tDTRIGCLK tDPCGIO

Figure 16. Precision Clock Generator (Direct Pin Routing)

Rev. B | Page 24 of 56 | June 2007

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

Flags

The timing specifications provided below apply to the FLAG3–0

and DAI_P20–1 pins, the parallel port, and the serial peripheral

interface (SPI). See Table 4, “Pin Descriptions,” on Page 12 for

more information on flag use.

Table 21. Flags

Parameter

Timing Requirement

FIPW

FLAG3–0 IN Pulse Width

Min

2 × t

PCLK

+ 3

Max Unit

Switching Characteristic

FOPW

FLAG3–0 OUT Pulse Width 2 × t

PCLK

– 1 ns

DAI_P20

(FLAG3

0IN)

(DATA31

DAI_P20

(FLAG3

0OUT)

(DATA31

tFIPW

tFOPW

Figure 17. Flags

Rev. B | Page 25 of 56 | June 2007

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

Memory Read—Parallel Port

Use these specifications for asynchronous interfacing to memo-

ries (and memory-mapped peripherals) when the ADSP-2136x

is accessing external memory space.

Table 22. 8-Bit Memory Read Cycle

Parameter

K and B Grade

Min Max

Y Grade

Min Max Unit

Timing Requirements

DRS

AD7–0 Data Setup Before RD High

DRH

AD7–0 Data Hold After RD High

DAD

AD15–8 Address to AD7–0 Data Valid

Switching Characteristics

ALEW

ALE Pulse Width

ADAS

AD15–0 Address Setup Before ALE Deasserted

RRH

Delay Between RD Rising Edge to Next

Falling Edge

ALERW

ALE Deasserted to Read Asserted

RWALE

Read Deasserted to ALE Asserted

ADAH

AD15–0 Address Hold After ALE Deasserted

ALEHZ

ALE Deasserted to AD7–0 Address in High Z

RD Pulse Width

RDDRV

AD7–0 ALE Address Drive After Read High

ADRH

AD15–8 Address Hold After RD High

DAWH

AD15–8 Address to RD High

3.3

D + t

PCLK

– 5.0

2 × t

PCLK

– 2.0

PCLK

– 2.5

H + t

PCLK

– 1.4

2 × t

PCLK

– 3.8

F + H + 0.5

PCLK

– 2.3

PCLK

+ 3.0

D – 2.0

F + H + t

PCLK

– 2.3

D + t

PCLK

– 4.0

4.5

D + t

PCLK

– 5.0

2 × t

PCLK

– 2.0

PCLK

– 2.5

H + t

PCLK

– 1.4

2 × t

PCLK

– 3.8

F + H + 0.5

PCLK

– 2.3

PCLK

+ 3.8

D – 2.0

F + H + t

PCLK

– 2.3

D + t

PCLK

– 4.0

D = (data cycle duration = the value set by the PPDUR Bits (5–1) in the PPCTL register) × t

PCLK

H = t

PCLK

(if a hold cycle is specified, else H = 0)

F = 7 × t

PCLK

(if FLASH_MODE is set, else F = 0)

PCLK

= (peripheral) clock period = 2 × t

CCLK

The timing specified here is sufficient to satisfy either t

DAD

or t

DRS

as they are independent.

On reset, ALE is an active high cycle. However, it can be configured by software to be active low.

Rev. B | Page 26 of 56 | June 2007

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

ALE

AD15-8

AD7-0

VALID

ADDRESS

tADAS

tALEW

tRW

tADAH

tADRH

tDRS tDRH

tDAD

tALERW

tRWALE

VALID

DATA

VALID

ADDRESS

tRDDRV

tALEHZ

VALID ADDRESS

VALID

DATA

tRRH

tDAWH

VALID ADDRESS

NOTE: MEMORY READS ALWAYS OCCUR IN GROUPS OF FOUR

BETWEEN ALE CYCLES.THIS FIGURE ONLY SHOWS TWO MEMORY

READS IN ORDER TO PROVIDE THE NECESSARY TIMING INFORMATION.

Figure 18. Read Cycle for 8-Bit Memory Timing

Rev. B | Page 27 of 56 | June 2007

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

Table 23. 16-Bit Memory Read Cycle

Parameter

K and B Grade

Min Max

Y Grade

Min Max Unit

Timing Requirements

DRS

AD15–0 Data Setup Before RD High

DRH

AD15–0 Data Hold After RD High

Switching Characteristics

ALEW

ALE Pulse Width

ADAS

AD15–0 Address Setup Before ALE Deasserted

ALERW

ALE Deasserted to Read Asserted

RRH

Delay Between RD Rising Edge to Next Falling

Edge

RWALE

Read Deasserted to ALE Asserted

RDDRV

ALE Address Drive After Read High

ADAH

AD15–0 Address Hold After ALE Deasserted

ALEHZ

ALE Deasserted to Address/Data15–0 in High Z

RD Pulse Width

3.3

2 × t

PCLK

– 2.0

PCLK

– 2.5

2 × t

PCLK

– 3.8

H + t

PCLK

– 1.4

F + H + 0.5

F + H + t

PCLK

– 2.3

PCLK

– 2.3

PCLK

+ 3.0

D – 2.0

4.5

2 × t

PCLK

– 2.0

PCLK

– 2.5

2 × t

PCLK

– 3.8

H + t

PCLK

– 1.4

F + H + 0.5

F + H + t

PCLK

– 2.3

PCLK

– 2.3

PCLK

+ 3.8

D – 2.0

D = (data cycle duration = the value set by the PPDUR Bits (5–1) in the PPCTL register) × t

PCLK

H = t

PCLK

(if a hold cycle is specified, else H = 0)

F = 7 × t

PCLK

(if FLASH_MODE is set, else F = 0)

PCLK

= (peripheral) clock period = 2 × t

CCLK

On reset, ALE is an active high cycle. However, it can be configured by software to be active low.

This parameter is only available when in EMPP = 0 mode.

AD15

tDRS tDRH

tALEHZ

tADAH

tADAS

VALID ADDRESS VALID DATA VALID DATA

tALEW

tRW

tALERW

tRRH

ALE

tRWALE

tRDDRV

VALID

ADDRESS

NOTE: FOR 16-BIT MEMORY READS, WHEN EMPP � 0, ONLY ONE RD PULSE OCCURS BETWEEN ALE CYCLES.

WHEN EMPP = 0, MULTIPLE RD PULSES OCCUR BETWEEN ALE CYCLES. FOR COMPLETE INFORMATION,

SEE THE ADSP-2136X SHARC PROCESSOR HARDWARE REFERENCE.

Figure 19. Read Cycle for 16-Bit Memory Timing

Rev. B | Page 28 of 56 | June 2007

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

Memory Write—Parallel Port

Use these specifications for asynchronous interfacing to memo-

ries (and memory-mapped peripherals) when the

ADSP-2136x is accessing external memory space.

Table 24. 8-Bit Memory Write Cycle

Parameter

K and B Grade

Min

Y Grade

Min Unit

Switching Characteristics:

ALEW

ALE Pulse Width

ADAS

AD15–0 Address Setup Before ALE Deasserted

ALERW

ALE Deasserted to Write Asserted

RWALE

Write Deasserted to ALE Asserted

WRH

Delay Between WR Rising Edge to Next WR Falling Edge

ADAH

AD15–0 Address Hold After ALE Deasserted

WR Pulse Width

ADWL

AD15–8 Address to WR Low

ADWH

AD15–8 Address Hold After WR High

DWS

AD7–0 Data Setup Before WR High

DWH

AD7–0 Data Hold After WR High

DAWH

AD15–8 Address to WR High

2 × t

PCLK

– 2.0

PCLK

– 2.8

2 × t

PCLK

– 3.8

H + 0.5

F + H + t

PCLK

– 2.3

PCLK

– 0.5

D – F – 2.0

PCLK

– 2.8

D – F + t

PCLK

– 4.0

D – F + t

PCLK

– 4.0

2 × t

PCLK

– 2.0

PCLK

– 2.8

2 × t

PCLK

– 3.8

H + 0.5

F + H + t

PCLK

– 2.3

PCLK

– 0.5

D – F – 2.0

PCLK

– 3.5

D – F + t

PCLK

– 4.0

D – F + t

CLK

– 4.0

D = (data cycle duration = the value set by the PPDUR Bits (5–1) in the PPCTL register) × t

PCLK

H = t

PCLK

(if a hold cycle is specified, else H = 0)

F = 7 × t

PCLK

(if FLASH_MODE is set, else F = 0). If FLASH_MODE is set, D must be ≥ 9 × t

PCLK

= (peripheral) clock period = 2 × t

CCLK

On reset, ALE is an active high cycle. However, it can be configured by software to be active low.

AD15

8 VALID

ADDRESS VALID ADDRESS

tADAS

AD7

ALE

tADAH

tADWH

tADWL

VALID DATA

tDAWH

tWRH

tRWALE

VALID

ADDRESS VALID DATA

tALEW

tALERW

tWW

tDWS

tDWH

VALID ADDRESS

NOTE: MEMORY WRITES ALWAYS OCCUR IN GROUPS OF FOUR

BETWEEN ALE CYCLES.THIS FIGURE ONLY SHOWS TWO MEMORY

WRITES IN ORDER TO PROVIDE THE NECESSARY TIMING INFORMATION.

Figure 20. Write Cycle for 8-Bit Memory Timing

Rev. B | Page 29 of 56 | June 2007

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

Table 25. 16-Bit Memory Write Cycle

Parameter

K and B Grade

Min

Y Grade

Min Unit

Switching Characteristics

ALEW

ALE Pulse Width

ADAS

AD15–0 Address Setup Before ALE Deasserted

ALERW

ALE Deasserted to Write Asserted

RWALE

Write Deasserted to ALE Asserted

WRH

Delay Between WR Rising Edge to Next WR Falling Edge

ADAH

AD15–0 Address Hold After ALE Deasserted

WR Pulse Width

DWS

AD15–0 Data Setup Before WR High

DWH

AD15–0 Data Hold After WR High

2 × t

PCLK

– 2.0

PCLK

– 2.5

2 × t

PCLK

– 3.8

H + 0.5

F + H + t

PCLK

– 2.3

PCLK

– 2.3

D – F – 2.0

D – F + t

PCLK

– 4.0

2 × t

PCLK

– 2.0

PCLK

– 2.5

2 × t

PCLK

– 3.8

H + 0.5

F + H + t

PCLK

– 2.3

PCLK

– 2.3

D – F – 2.0

D – F + t

PCLK

– 4.0

D = (data cycle duration = the value set by the PPDUR Bits (5–1) in the PPCTL register) × t

PCLK

H = t

PCLK

(if a hold cycle is specified, else H = 0)

F = 7 × t

PCLK

(if FLASH_MODE is set, else F = 0). If FLASH_MODE is set, D must be ≥ 9 × t

PCLK

= (peripheral) clock period = 2 × t

CCLK

On reset, ALE is an active high cycle. However, it can be configured by software to be active low.

This parameter is only available when in EMPP = 0 mode.

AD15

0 VALID

ADDRESS VALID DATA

tADAS

ALE

tADAH

tWRH

tRWALE

tALEW tALERW

tWW

tDWS

tDWH

VALID DATA VALID

ADDRESS

NOTE: FOR 16-BIT MEMORY WRITES,WHENEMPP � 0, ONLY ONE WR PULSE OCCURS BETWEEN ALE CYCLES.

WHEN EMPP = 0, MULTIPLE WR PULSES OCCUR BETWEEN ALE CYCLES. FOR COMPLETE INFORMATION,

SEE THE ADSP-2136X SHARC PROCESSOR HARDWARE REFERENCE.

Figure 21. Write Cycle for 16-Bit Memory Timing

Rev. B | Page 30 of 56 | June 2007

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

Serial Ports

To determine whether communication is possible between two Serial port signals (SCLK, FS, data channel A, data channel B)

devices at clock speed n, the following specifications must be are routed to the DAI_P20–1 pins using the SRU. Therefore, the

confirmed: 1) frame sync delay and frame sync setup and hold, timing specifications provided below are valid at the

2) data delay and data setup and hold, and 3) SCLK width. DAI_P20–1 pins.

Table 26. Serial Ports—External Clock

Parameter

K and B Grade

Min Max

Y Grade

Max Unit

Timing Requirements

SFSE

FS Setup Before SCLK

(Externally Generated FS in Either Transmit or Receive Mode)

HFSE

FS Hold After SCLK

(Externally Generated FS in Either Transmit or Receive Mode)

SDRE

Receive Data Setup Before Receive SCLK

HDRE

Receive Data Hold After SCLK

SCLKW

SCLK Width

SCLK

SCLK Period

Switching Characteristics

DFSE

FS Delay After SCLK

(Internally Generated FS in Either Transmit or Receive Mode)

HOFSE

FS Hold After SCLK

(Internally Generated FS in Either Transmit or Receive Mode)

DDTE

Transmit Data Delay After Transmit SCLK

HDTE

Transmit Data Hold After Transmit SCLK

2.5

9.5

Referenced to sample edge.

Referenced to drive edge.

Table 27. Serial Ports—Internal Clock

Parameter

K and B Grade

Min Max

Y Grade

Max Unit

Timing Requirements

SFSI

FS Setup Before SCLK

(Externally Generated FS in Either Transmit or Receive Mode)

HFSI

FS Hold After SCLK

(Externally Generated FS in Either Transmit or Receive Mode)

SDRI

Receive Data Setup Before SCLK

HDRI

Receive Data Hold After SCLK

Switching Characteristics

DFSI

FS Delay After SCLK (Internally Generated FS in Transmit Mode)

HOFSI

FS Hold After SCLK (Internally Generated FS in Transmit Mode)

DFSIR

FS Delay After SCLK (Internally Generated FS in Receive Mode)

HOFSIR

FS Hold After SCLK (Internally Generated FS in Receive Mode)

DDTI

Transmit Data Delay After SCLK

HDTI

Transmit Data Hold After SCLK

SCLKIW

Transmit or Receive SCLK Width

2.5

–1.0

0.5t

SCLK

– 2 0.5t

SCLK

+ 2

3.5

9.5

4.0

0.5t

SCLK

+ 2

Referenced to the sample edge.

Referenced to drive edge.

Rev. B | Page 31 of 56 | June 2007

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

Table 28. Serial Ports—Enable and Three-State

Parameter Min

K and B Grade

Max

Y Grade

Max Unit

Switching Characteristics

DDTEN

Data Enable from External Transmit SCLK

DDTTE

Data Disable from External Transmit SCLK

DDTIN

Data Enable from Internal Transmit SCLK

–1

7 8.5

Referenced to drive edge.

Table 29. Serial Ports—External Late Frame Sync

Parameter Min

K and B Grade

Max

Y Grade

Max Unit

Switching Characteristics

DDTLFSE

Data Delay from Late External Transmit FS or

External Receive FS with MCE = 1, MFD = 0

DDTENFS

Data Enable for MCE = 1, MFD = 0 0.5

9 10.5 ns

The t

DDTLFSE

and t

DDTENFS

parameters apply to left-justified sample pair as well as DSP serial mode, and MCE = 1, MFD = 0.

EXTERNAL RECEIVE FS WITH MCE = 1, MFD = 0

DRIVE SAMPLE DRIVE

DAI_P20

(SCLK)

DAI_P20

(FS)

DAI_P20

(DATA CHANNEL A/B)

DAI_P20

(SCLK)

DAI_P20

(FS)

DAI_P20

(DATA CHANNEL A/B)

DRIVE SAMPLE DRIVE

LATE EXTERNAL TRANSMIT FS

1STBIT 2ND BIT

1ST BIT 2ND BIT

tHFSE/I

tSFSE/I

tDDTE/I

tDDTENFS

tDDTLFSE

tHDTE/I

tSFSE/I

tDDTE/I

tDDTENFS

tDDTLFSE

tHDTE/I

tHFSE/I

NOTE: SERIAL PORT SIGNALS (SCLK, FS, DATA CHANNEL A/B) ARE ROUTED TO THE DAI_P20-1 PINS

USING THE SRU. THE TIMING SPECIFICATIONS PROVIDED HERE ARE VALID AT THE DAI_P20-1 PINS.

Figure 22. External Late Frame Sync

This figure reflects changes made to support left-justified sample pair mode.

Rev. B | Page 32 of 56 | June 2007

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

DATA RECEIVE—INTERNAL CLOCK DATA RECEIVE

—

TERNAL CLOCK

DRIVE EDGE SAMPLE EDGE DRIVE EDGE SAMPLE EDGE

DAI_P20

(SCLK)

DAI_P20

(FS)

DAI_P20

(DATA CHANNEL A/B)

DAI_P20

(SCLK)

DAI_P20

(FS)

DAI_P20

1 DAI_P20

(DATA CHANNEL A/B) (DATA CHANNEL A/B)

NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF SCLK (EXTERNAL), SCLK (INTERNAL) CAN BE USED AS THE ACTIVE SAMPLING EDGE.

tSDRI tHDRI

tSFSI tHFSI

tDFSIR

tHOFSR

tSCLKIW

tSDRE tHDRE

tSFSE tHFSE

tDFSE

tSCLKW

tHOFSE

tDDTI

DRIVE EDGE SAMPLE EDGE DRIVE EDGE SAMPLE EDGE

DATA TRANSMIT—INTERNAL CLOCK DATA TRANSMIT—EXTERNAL CLOCK

tSFSI tHFSI tHOFSE

tDFSI

tHOFSI

tSCLKIW

tHDTI

tDDTE

tSFSE tHFSE

tDFSE

tSCLKW

tHDTE

DAI_P20

(SCLK)

DAI_P20

(FS)

DAI_P20

(DATA CHANNEL A/B)

DAI_P20

(SCLK)

DAI_P20

(FS)

NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF SCLK (EXTERNAL), SCLK (INTERNAL) CAN BE USED AS THE ACTIVE SAMPLING EDGE.

DRIVE EDGE DRIVE EDGE

SCLK DAI_P20

SCLK (EXT)

tDDTTE

tDDTEN

DAI_P20

(DATA CHANNEL A/B)

DRIVE EDGE

DAI_P20

SCLK (INT) tDDTIN

DAI_P20

(DATA CHANNEL A/B)

Figure 23. Serial Ports

Rev. B | Page 33 of 56 | June 2007

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

Input Data Port (IDP)

The timing requirements for the IDP are given in Table 30. IDP

signals (SCLK, FS, SDATA) are routed to the DAI_P20–1 pins

using the SRU. Therefore, the timing specifications provided

below are valid at the DAI_P20–1 pins.

Table 30. IDP

Parameter Min Max Unit

Timing Requirements

SISFS

FS Setup Before SCLK Rising Edge 3 ns

SIHFS

FS Hold After SCLK Rising Edge 3 ns

SISD

SData Setup Before SCLK Rising Edge 3 ns

SIHD

SData Hold After SCLK Rising Edge 3 ns

IDPCLKW

Clock Width 9 ns

IDPCLK

Clock Period 24 ns

DATA, SCLK, FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG’s input can be either CLKIN or any of the DAI pins.

SAMPLE EDGE

DAI_P20

(SCLK)

DAI_P20

(FS)

tSISFS tSIHFS

tIDPCLK

DAI_P20

(SDATA)

tIDPCLKW

tSISD tSIHD

Figure 24. IDP Master Timing

Rev. B | Page 34 of 56 | June 2007

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

Parallel Data Acquisition Port (PDAP)

The timing requirements for the PDAP are provided in

Table 31. PDAP is the parallel mode operation of Channel 0 of

the IDP. For details on the operation of the IDP, see the IDP

chapter of the ADSP-2136x SHARC Processor Hardware Refer-

Table 31. Parallel Data Acquisition Port (PDAP)

ence. Note that the most significant 16 bits of external PDAP

data can be provided through either the parallel port AD15–0 or

the DAI_P20–5 pins. The remaining 4 bits can only be sourced

through DAI_P4–1. The timing below is valid at the

DAI_P20–1 pins or at the AD15–0 pins.

Parameter Min Max Unit

Timing Requirements

SPCLKEN

PDAP_CLKEN Setup Before PDAP_CLK Sample Edge

HPCLKEN

PDAP_CLKEN Hold After PDAP_CLK Sample Edge

PDSD

PDAP_DAT Setup Before SCLK PDAP_CLK Sample Edge

PDHD

PDAP_DAT Hold After SCLK PDAP_CLK Sample Edge

PDCLKW

Clock Width

PDCLK

Clock Period

Switching Characteristics

PDHLDD

Delay of PDAP Strobe After Last PDAP_CLK Capture Edge for a Word

PDSTRB

PDAP Strobe Pulse Width

2.5

3.0

2.5

7.0

2 × t

PCLK

– 1

2 × t

PCLK

– 1.5

Source pins of DATA are ADDR7–0, DATA7–0, or DAI pins. Source pins for SCLK and FS are: 1) DAI pins, 2) CLKIN through PCG, or 3) DAI pins through PCG.

DAI_P20

(PDAP_CLK)

DAI_P20

(PDAP_CLKEN)

DATA

DAI_P20

(PDAP_STROBE)

SAMPLE EDGE

tPDSD tPDHD

tSPCLKEN tHPCLKEN

tPDCLKW

tPDSTRB

tPDHLDD

tPDCLK

Figure 25. PDAP Timing

Rev. B | Page 35 of 56 | June 2007

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

Pulse-Width Modulation Generators

Table 32. PWM Timing

Parameter Min Max Unit

Switching Characteristics

PWMW

PWM Output Pulse Width

PWMP

PWM Output Period

PCLK

– 2

2 × t

PCLK

– 1.5

– 2) × t

PCLK

– 2

– 1) × t

PCLK

PWM

OUTPUTS

tPWMW

tPWMP

Figure 26. PWM Timing

Sample Rate Converter—Serial Input Port

The SRC input signals (SCLK, FS, and SDATA) are routed from

the DAI_P20–1 pins using the SRU. Therefore, the timing spec-

ifications provided in Table 33 are valid at the DAI_P20–1 pins.

This feature is not available on the ADSP-21363 models.

Table 33. SRC, Serial Input Port

Parameter Min Max Unit

Timing Requirements

SRCSFS

FS Setup Before SCLK Rising Edge 3 ns

SRCHFS

FS Hold After SCLK Rising Edge 3 ns

SRCSD

SData Setup Before SCLK Rising Edge 3 ns

SRCHD

SData Hold After SCLK Rising Edge 3 ns

SRCCLKW

Clock Width 36 ns

SRCCLK

Clock Period 80 ns

DATA, SCLK, FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG’s input can be either CLKIN or any of the DAI pins.

SAMPLE EDGE

DAI_P20

(SCLK)

DAI_P20

(FS)

tSRCSFS tSRCHFS

tSRCCLK

DAI_P20

(SDATA)

tSRCCLKW

tSRCSD tSRCHD

Figure 27. SRC Serial Input Port Timing

Rev. B | Page 36 of 56 | June 2007

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

Sample Rate Converter—Serial Output Port

For the serial output port, the frame-sync is an input and should

meet setup and hold times with regard to SCLK on the output

port. The serial data output, SDATA, has a hold time and delay

specification with regard to SCLK. Note that SCLK rising edge is

the sampling edge and the falling edge is the drive edge.

Table 34. SRC, Serial Output Port

Parameter Min

K and B Grade

Max

Y Grade

Max Unit

Timing Requirements

SRCSFS

FS Setup Before SCLK Rising Edge

SRCHFS

FS Hold After SCLK Rising Edge

Switching Characteristics

SRCTDD

Transmit Data Delay After SCLK Falling Edge

SRCTDH

Transmit Data Hold After SCLK Falling Edge

10.5 12.5

DATA, SCLK, FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG’s input can be either CLKIN or any of the DAI pins.

DAI_P20

(SCLK)

DAI_P20

(FS)

tSRCSFS tSRCHFS

DAI_P20

(SDATA)

tSRCTDD

tSRCTDH

SAMPLE EDGE

tSRCCLK

tSRCCLKW

Figure 28. SRC Serial Output Port Timing

Rev. B | Page 37 of 56 | June 2007

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

SPDIF Transmitter

Serial data input to the SPDIF transmitter can be formatted as

left-justified, I

S, or right-justified with word widths of 16, 18,

20, or 24 bits. The following sections provide timing for the

transmitter. This feature is not available on the

ADSP-21363 models.

LRCLK

SCLK

SDATA

SPDIF Transmitter—Serial Input Waveforms

Figure 29 shows the right-justified mode. LRCLK is HI for the

left channel and LO for the right channel. Data is valid on the

rising edge of SCLK. The MSB is delayed 12-bit clock periods

(in 20-bit output mode) or 16-bit clock periods (in 16-bit output

mode) from an LRCLK transition, so that when there are

64 SCLK periods per LRCLK period, the LSB of the data will be

right-justified to the next LRCLK transition.

LEFT CHANNEL RIGHT CHANNEL

MSB-1 MSB-2 LSB+2 LSB+1 LSB MSB MSB-1 MSB-2 LSB+2 LSB+1 LSBLSB MSB

Figure 29. Right -Justified Mode

Figure 30 shows the default I

S-justified mode. LRCLK is LO for

the left channel and HI for the right channel. Data is valid on the

rising edge of SCLK. The MSB is left-justified to an LRCLK

transition but with a single SCLK period delay.

RIGHT CHANNEL

LRCLK

SCLK

SDATA MSB-1 MSB-2 LSB+2 LSB+1 LSB

LEFT CHANNEL

MSB MSB-1 MSB-2 LSB+2 LSB+1 LSB MSBMSB

Figure 30. I

S-Justified Mode

Figure 31 shows the left-justified mode. LRCLK is HI for the left

channel and LO for the right channel. Data is valid on the rising

edge of SCLK. The MSB is left-justified to an LRCLK transition

with no MSB delay.

LRCLK

SCLK

SDATA

LEFT CHANNEL RIGHT CHANNEL

MSB-1 MSB-2 LSB+2 LSB+1 LSB MSB MSB-1 MSB-2 LSB+2 LSB+1 LSB MSB MSB+1

MSB

Figure 31. Left-Justified Mode

Rev. B | Page 38 of 56 | June 2007

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

SPDIF Transmitter Input Data Timing

The timing requirements for the input port are given in

Table 35. Input signals (SCLK, FS, and SDATA) are routed to

the DAI_P20–1 pins using the SRU. Therefore, the timing spec-

ifications provided below are valid at the DAI_P20–1 pins.

Table 35. SPDIF Transmitter Input Data Timing

Parameter

K and B Grade

Min

Y Grade

Min Max Unit

Timing Requirements

SISFS

FS Setup Before SCLK Rising Edge

SIHFS

FS Hold After SCLK Rising Edge

SISD

SData Setup Before SCLK Rising Edge

SIHD

SData Hold After SCLK Rising Edge

SISCLKW

Clock Width

SISCLK

Clock Period

SITXCLKW

Transmit Clock Width

SITXCLK

Transmit Clock Period

9.5

DATA, SCLK, FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG’s input can be either CLKIN or any of the DAI pins.

DAI_P20

(SCLK)

DAI_P20

(FS)

SAMPLE EDGE

tSISD

tSISFS

tSISCLKW

DAI_P20

(SDATA)

DAI_P20

(TXCLK)

tSIHD

tSIHFS

tSITXCLKW tSITXCLK

Figure 32. SPDIF Transmitter Input Timing

Oversampling Clock (TXCLK) Switching Characteristics

SPDIF Transmitter has an over sampling clock. This TXCLK

input is divided down to generate the biphase clock.

Table 36. Oversampling Clock (TXCLK) Switching Characteristics

Parameter Min Max Unit

TXCLK Frequency for TXCLK = 768 × FS

TXCLK Frequency for TXCLK = 512 × FS

TXCLK Frequency for TXCLK = 384 × FS

TXCLK Frequency for TXCLK = 256 × FS

Frame Rate

147.5

98.4

73.8

49.2

192.0

MHz

kHz

Rev. B | Page 39 of 56 | June 2007

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

SPDIF Receiver

The following section describes timing as it relates to the SPDIF

receiver. This feature is not available on the ADSP-21363

models.

Internal Digital PLL Mode

In the internal digital phase-locked loop mode the internal PLL

(digital PLL) generates the 512 × FS clock.

Table 37. SPDIF Receiver Output Timing (Internal Digital PLL Mode)

Parameter Min Max Unit

Switching Characteristics

DFSI

LRCLK Delay After SCLK 5 ns

HOFSI

LRCLK Hold After SCLK –2 ns

DDTI

Transmit Data Delay After SCLK 5 ns

HDTI

Transmit Data Hold After SCLK –2 ns

SCLKIW

Transmit SCLK Width 38 ns

CCLK

Core Clock Period 5 ns

SCLK frequency is 64 × FS where FS = the frequency of LRCLK.

DRIVE EDGE SAMPLE EDGE

DAI_P20

(SCLK)

DAI_P20

(FS)

DAI_P20

(DATA CHANNEL A/B)

tSCLKIW

tDFSI

tDDTI

tHOFSI

tHDTI

Figure 33. SPDIF Receiver Internal Digital PLL Mode Timing

Rev. B | Page 40 of 56 | June 2007

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

SPI Interface—Master

The ADSP-2136x contains two SPI ports. The primary has dedi-

cated pins and the secondary is available through the DAI. The

timing provided in Table 38 and Table 39 applies to both.

Table 38. SPI Interface Protocol—Master Switching and Timing Specifications

Parameter

K and B Grade

Min Max

Y Grade

Min Max Unit

Timing Requirements

SSPIDM

Data Input Valid to SPICLK Edge (Data Input Setup Time)

SSPIDM

Data Input Valid to SPICLK Edge (Data Input Setup Time) (SPI2)

HSPIDM

SPICLK Last Sampling Edge to Data Input Not Valid

Switching Characteristics

SPICLKM

Serial Clock Cycle

SPICHM

Serial Clock High Period

SPICLM

Serial Clock Low Period

DDSPIDM

SPICLK Edge to Data Out Valid (Data Out Delay Time)

DDSPIDM

SPICLK Edge to Data Out Valid (Data Out Delay Time) (SPI2)

HDSPIDM

SPICLK Edge to Data Out Not Valid (Data Out Hold Time)

SDSCIM

FLAG3–0IN (SPI Device Select) Low to First SPICLK Edge

SDSCIM

FLAG3–0IN (SPI Device Select) Low to First SPICLK Edge (SPI2)

HDSM

Last SPICLK Edge to FLAG3–0IN High

SPITDM

Sequential Transfer Delay

5.2

8.2

8 × t

PCLK

– 2

4 × t

PCLK

– 2

4 × t

PCLK

– 2

3.0

8.0

4 × t

PCLK

– 2.5

4 × t

PCLK

– 2.5

4 × t

PCLK

– 2

4 × t

PCLK

– 1

6.2

9.5

8 × t

PCLK

– 2

4 × t

PCLK

– 2

4 × t

PCLK

– 2

3.0

9.5

4 × t

PCLK

– 3.0

4 × t

PCLK

– 3.0

4 × t

PCLK

– 2

4 × t

PCLK

– 1

FLAG3-0

(OUTPUT)

SPICLK

(CP = 0)

(OUTPUT)

SPICLK

(CP = 1)

(OUTPUT)

MOSI

(OUTPUT)

MISO

(INPUT)

MOSI

(OUTPUT)

MISO

(INPUT)

CPHASE= 1

CPHASE= 0

LSB

VALID

MSB

VALID

tSSPIDM

tHSPIDM

tHDSPIDM

LSBMSB

tHSPIDM

tDDSPIDM

tSPICHM tSPICLM

tSPICLM

tSPICL KM

tSPICHM

tHDSM tSPITDM

tHDSPIDM

LSB

VALID

LSBMSB

MSB

VALID

tHSPIDM

tDDSPIDM

tSSPIDM

tSDSCIM

tSSPIDM

Figure 34. SPI Master Timing

Rev. B | Page 41 of 56 | June 2007

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

SPI Interface—Slave

Table 39. SPI Interface Protocol—Slave Switching and Timing Specifications

Parameter

K and B Grade

Min Max

Y Grade

Max Unit

Timing Requirements

SPICLKS

Serial Clock Cycle

SPICHS

Serial Clock High Period

SPICLS

Serial Clock Low Period

SDSCO

SPIDS Assertion to First SPICLK Edge

CPHASE = 0

CPHASE = 1

HDS

Last SPICLK Edge to SPIDS Not Asserted, CPHASE = 0

SSPIDS

Data Input Valid to SPICLK Edge (Data Input Setup Time)

HSPIDS

SPICLK Last Sampling Edge to Data Input Not Valid

SDPPW

SPIDS Deassertion Pulse Width (CPHASE = 0)

Switching Characteristics

DSOE

SPIDS Assertion to Data Out Active

DSOE

SPIDS Assertion to Data Out Active (SPI2)

DSDHI

SPIDS Deassertion to Data High Impedance

DSDHI

SPIDS Deassertion to Data High Impedance (SPI2)

DDSPIDS

SPICLK Edge to Data Out Valid (Data Out Delay Time)

HDSPIDS

SPICLK Edge to Data Out Not Valid (Data Out Hold Time)

DSOV

SPIDS Assertion to Data Out Valid (CPHASE = 0)

4 × t

PCLK

– 2

2 × t

PCLK

– 2

2 × t

PCLK

– 2

2 × t

PCLK

2 × t

PCLK

2 × t

PCLK

2 × t

PCLK

0 5

0 8

0 5

0 8.6

9.5

2 × t

PCLK

5 × t

PCLK

5.5

11.0

5 × t

PCLK

The timing for these parameters applies when the SPI is routed through the signal routing unit. For more information, see the ADSP-2136x SHARC Processor Hardware Reference,

“Serial Peripheral Interface Port” chapter.

Rev. B | Page 42 of 56 | June 2007

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

SPIDS

(INPUT)

SPICLK

(CP = 0)

(INPUT)

SPICLK

(CP = 1)

(INPUT)

(OUTPUT)

CPHASE= 1

MISO

MOSI

(INPUT)

(OUTPUT)

CPHASE= 0

MOSI

(INPUT)

tHSPIDS

tDDSPIDS

tDSDHI

LSBMSB

MSBVALID

tDSOE

tDDSPIDS

tHDSPIDS

tSSPIDS

tSDSCO

tSPICHS tSPICLS

tSPICLS

tSPICLKS tHDS

tSPICHS

tSSPIDS tHSPIDS

tDSDHI

LSBVALID

MSB

MSBVALID

tDSOE

tDDSPIDS

tSSPIDS

LSBVALID

LSB

tSDPPW

tDSOV tHDSPIDS

Figure 35. SPI Slave Timing

Rev. B | Page 43 of 56 | June 2007

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

JTAG Test Access Port and Emulation

Table 40. JTAG Test Access Port and Emulation

Parameter

Timing Requirements

TCK

TCK Period

STAP

TDI, TMS Setup Before TCK High

HTAP

TDI, TMS Hold After TCK High

SSYS

System Inputs Setup Before TCK High

HSYS

System Inputs Hold After TCK High

TRSTW

TRST Pulse Width

Min

Max Unit

Switching Characteristics

DTDO

TDO Delay from TCK Low

DSYS

System Outputs Delay After TCK Low

÷ 2 + 7

System Inputs = AD15–0, SPIDS, CLKCFG1–0, RESET, BOOTCFG1–0, MISO, MOSI, SPICLK, DAI_Px, FLAG3–0.

System Outputs = MISO, MOSI, SPICLK, DAI_Px, AD15–0, RD, WR, FLAG3–0, CLKOUT, EMU, ALE.

SYSTEM

OUTPUTS

TCK

TMS

TDI

TDO

SYSTEM

INPUTS

tSTAP

tTCK

tHTAP

tDTDO

tSSYS tHSYS

tDSYS

Figure 36. IEEE 1149.1 JTAG Test Access Port

Rev. B | Page 44 of 56 | June 2007

)

(

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

The ac signal specifications (timing parameters) appear in

Table 14 on Page 21 through Table 40 on Page 44. These include

output disable time, output enable time, and capacitive loading.

The timing specifications for the SHARC apply for the voltage

reference levels in Figure 38.

Figure 37 shows typical I-V characteristics for the output driv- Output delays and holds are based on standard capacitive loads:

ers of the ADSP-2136x. The curves represent the current drive 30 pF on all pins (see Figure 38). Figure 42 shows graphically

capability of the output drivers as a function of output voltage. how output delays and holds vary with load capacitance. The

SOUU

))

RRR

((

VNTmA

DDEXT

OUTPUT DRIVE CURRENTS CAPACITIVE LOADING

graphs of Figure 40, Figure 41, and Figure 42 may not be linear

outside the ranges shown for Typical Output Delay vs. Load

Capacitance and Typical Output Rise Time (20% to 80%,

V = Min) vs. Load Capacitance.

3.47V,

45°C

3.3V, +25°C

Nns

LLTM()

VOH 3.3V, +25°C

3.11V, +125°C

VOL

3.47V,

45°C

y = 0.0467x + 1.6323 RIS

FALL

y = 0.045x + 1.524

10 8

40 4

0 0.5 1.0 1.5 2.0 2.5 3.0 3.5

SWEEP (VDDEXT)VOLTAGE (V)

Figure 37. ADSP-2136x Typical Drive

TEST CONDITIONS

Timing is measured on signals when they cross the 1.5 V level as

described in Figure 39. All delays (in nanoseconds) are mea-

sured between the point that the first signal reaches 1.5 V and

the point that the second signal reaches 1.5 V.

0 50 100 150 200 250

LOAD CAPACITANCE (pF)

Figure 40. Typical Output Rise/Fall Time

(20% to 80%, V

DDEXT

= Max)

RISE

y = 0.049x + 1.5105 FALL

y= 0.0482x + 1.4604

50�

TO 6

1.5V

OUTPUT

30pF

June 2007

Figure 38. Equivalent Device Loading for AC Measurements

0 50 100 150 200 250

(Includes All Fixtures)

LOAD CAPACITANCE (pF)

Figure 41. Typical Output Rise/Fall Time

OR 1.5V 1.5V

OUTPUT

INPUT (20% to 80%, V

DDEXT

= Min)

Figure 39. Voltage Reference Levels for AC Measurements

Rev. B | Page 45 of 56 |

Table 41 through Table 43 airflow measurements comply with

JEDEC standards JESD51-2 and JESD51-6 and the junction-to-

board measurement complies with JESD51-8. Test board and

thermal via design comply with JEDEC standards JESD51-9

(BGA) and JESD51-5 (LQFP_EP). The junction-to-case mea-

surement complies with MIL-STD-883. All measurements use a

2S2P JEDEC test board.

The ADSP-2136x processor is rated for performance over the

temperature range specified in Operating Conditions

on Page 16.

OOO

PDD

ELL

AYRH(ns)

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

THERMAL CHARACTERISTICS

Industrial applications using the BGA package require thermal

vias, to an embedded ground plane, in the PCB. Refer to JEDEC

standard JESD51-9 for printed circuit board thermal ball land

and thermal via design information.

Industrial applications using the LQFP_EP package require

thermal trace squares and thermal vias, to an embedded ground

plane, in the PCB. Refer to JEDEC standard JESD51-5 for more

information.

To determine the junction temperature of the device while on

the application PCB, use:

where:

= junction temperature (°C)

= case temperature (°C) measured at the top center of the

package

= junction-to-top (of package) characterization parameter

is the typical value from Table 41 through Table 43.

= power dissipation Estimating Power for the ADSP-21362

SHARC Processors (EE-277) for more information.

Values of θ

are provided for package comparison and PCB

design considerations.

Values of θ

are provided for package comparison and PCB

design considerations when an exposed pad is required. Note

that the thermal characteristics values provided in Table 41

0 20050 100 150

Y= 0.0488x

1.5923

throughTable 43 are modeled values.

LOAD CAPACITANCE (pF)

Figure 42. Typical Output Delay or Hold vs. Load Capacitance

Table 41. Thermal Characteristics for BGA (No Thermal vias

in PCB)

Parameter Condition Typical Unit

Airflow = 0 m/s 25.40 °C/W

JMA

Airflow = 1 m/s 21.90 °C/W

JMA

Airflow = 2 m/s 20.90 °C/W

5.07 °C/W

Airflow = 0 m/s 0.140 °C/W

JMT

Airflow = 1 m/s 0.330 °C/W

JMT

Airflow = 2 m/s 0.410 °C/W

Table 42. Thermal Characteristics for BGA (Thermal vias in

(at Ambient Temperature) PCB)

Parameter Condition Typical Unit

Airflow = 0 m/s 23.40 °C/W

JMA

Airflow = 1 m/s 20.00 °C/W

JMA

Airflow = 2 m/s 19.20 °C/W

5.00 °C/W

Airflow = 0 m/s 0.130 °C/W

JMT

Airflow = 1 m/s 0.300 °C/W

JMT

Airflow = 2 m/s 0.360 °C/W

Table 43. Thermal Characteristics for LQFP_EP (with

Exposed Pad Soldered to PCB)

Parameter Condition Typical Unit

Airflow = 0 m/s 16.80 °C/W

JMA

Airflow = 1 m/s 14.20 °C/W

JMA

Airflow = 2 m/s 13.50 °C/W

7.25 °C/W

Airflow = 0 m/s 0.51 °C/W

JMT

Airflow = 1 m/s 0.72 °C/W

JMT

Airflow = 2 m/s 0.80 °C/W

TJ = TT + (ΨJT × PD )

Rev. B | Page 46 of 56 | June 2007

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

144-LEAD LQFP PIN CONFIGURATIONS

The following table shows the ADSP-2136x’s pin names and

their default function after reset (in parentheses).

Table 44. LQFP Pin Assignments

Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No.

DDINT

1 V

DDINT

37 V

DDEXT

73 GND 109

CLKCFG0 2 GND 38 GND 74 V

DDINT

110

CLKCFG1 3 RD 39 V

DDINT

75 GND 111

BOOTCFG0 4 ALE 40 GND 76 V

DDINT

112

BOOTCFG1 5 AD15 41 DAI_P10 (SD2B) 77 GND 113

GND 6 AD14 42 DAI_P11 (SD3A) 78 V

DDINT

114

DDEXT

7 AD13 43 DAI_P12 (SD3B) 79 GND 115

GND 8 GND 44 DAI_P13 (SCLK3) 80 V

DDEXT

116

DDINT

9 V

DDEXT

45 DAI_P14 (SFS3) 81 GND 117

GND 10 AD12 46 DAI_P15 (SD4A) 82 V

DDINT

118

DDINT

11 V

DDINT

47 V

DDINT

83 GND 119

GND 12 GND 48 GND 84 V

DDINT

120

DDINT

13 AD11 49 GND 85 RESET 121

GND 14 AD10 50 DAI_P16 (SD4B) 86 SPIDS 122

FLAG0 15 AD9 51 DAI_P17 (SD5A) 87 GND 123

FLAG1 16 AD8 52 DAI_P18 (SD5B) 88 V

DDINT

124

AD7 17 DAI_P1 (SD0A) 53 DAI_P19 (SCLK5) 89 SPICLK 125

GND 18 V

DDINT

54 V

DDINT

90 MISO 126

DDINT

19 GND 55 GND 91 MOSI 127

GND 20 DAI_P2 (SD0B) 56 GND 92 GND 128

DDEXT

21 DAI_P3 (SCLK0) 57 V

DDEXT

93 V

DDINT

129

GND 22 GND 58 DAI_P20 (SFS5) 94 V

DDEXT

130

DDINT

23 V

DDEXT

59 GND 95 A

VDD

131

AD6 24 V

DDINT

60 V

DDINT

96 A

VSS

132

AD5 25 GND 61 FLAG2 97 GND 133

AD4 26 DAI_P4 (SFS0) 62 FLAG3 98 CLKOUT 134

DDINT

27 DAI_P5 (SD1A) 63 V

DDINT

99 EMU 135

GND 28 DAI_P6 (SD1B) 64 GND 100 TDO 136

AD3 29 DAI_P7 (SCLK1) 65 V

DDINT

101 TDI 137

AD2 30 V

DDINT

66 GND 102 TRST 138

DDEXT

31 GND 67 V

DDINT

103 TCK 139

GND 32 V

DDINT

68 GND 104 TMS 140

AD1 33 GND 69 V

DDINT

105 GND 141

AD0 34 DAI_P8 (SFS1) 70 GND 106 CLKIN 142

WR 35 DAI_P9 (SD2A) 71 V

DDINT

107 XTAL 143

DDINT

36 V

DDINT

72 V

DDINT

108 V

DDEXT

144

Rev. B | Page 47 of 56 | June 2007

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

136-BALL BGA PIN CONFIGURATIONS

The following table shows the ADSP-2136x’s pin names and

their default function after reset (in parentheses).

Table 45. BGA Pin Assignments

Ball Name Ball No. Ball Name Ball No. Ball Name Ball No. Ball Name Ball No.

CLKCFG0 A01 CLKCFG1 B01 BOOTCFG1 C01 V

DDINT

D01

XTAL A02 GND B02 BOOTCFG0 C02 GND D02

TMS A03 V

DDEXT

B03 GND C03 GND D04

TCK A04 CLKIN B04 GND C12 GND D05

TDI A05 TRST B05 GND C13 GND D06

CLKOUT A06 A

VSS

B06 V

DDINT

C14 GND D09

TDO A07 A

VDD

B07 GND D10

EMU A08 V

DDEXT

B08 GND D11

MOSI A09 SPICLK B09 GND D13

MISO A10 RESET B10 V

DDINT

D14

SPIDS A11 V

DDINT

B11

DDINT

A12 GND B12

GND A13 GND B13

GND A14 GND B14

DDINT

E01 FLAG1 F01 AD7 G01 AD6 H01

GND E02 FLAG0 F02 V

DDINT

G02 V

DDEXT

H02

GND E04 GND F04 V

DDEXT

G13 DAI_P18 (SD5B) H13

GND E05 GND F05 DAI_P19 (SCLK5) G14 DAI_P17 (SD5A) H14

GND E06 GND F06

GND E09 GND F09

GND E10 GND F10

GND E11 GND F11

GND E13 FLAG2 F13

FLAG3 E14 DAI_P20 (SFS5) F14

Rev. B | Page 48 of 56 | June 2007

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

Table 45. BGA Pin Assignments (Continued)

Ball Name Ball No. Ball Name Ball No. Ball Name Ball No. Ball Name Ball No.

AD5 J01 AD3 K01 AD2 L01 AD0 M01

AD4 J02 V

DDINT

K02 AD1 L02 WR M02

GND J04 GND K04 GND L04 GND M03

GND J05 GND K05 GND L05 GND M12

GND J06 GND K06 GND L06 DAI_P12 (SD3B) M13

GND J09 GND K09 GND L09 DAI_P13 (SCLK3) M14

GND J10 GND K10 GND L10

GND J11 GND K11 GND L11

DDINT

J13 GND K13 GND L13

DAI_P16 (SD4B) J14 DAI_P15 (SD4A) K14 DAI_P14 (SFS3) L14

AD15 N01 AD14 P01

ALE N02 AD13 P02

RD N03 AD12 P03

DDINT

N04 AD11 P04

DDEXT

N05 AD10 P05

AD8 N06 AD9 P06

DDINT

N07 DAI_P1 (SD0A) P07

DAI_P2 (SD0B) N08 DAI_P3 (SCLK0) P08

DDEXT

N09 DAI_P5 (SD1A) P09

DAI_P4 (SFS0) N10 DAI_P6 (SD1B) P10

DDINT

N11 DAI_P7 (SCLK1) P11

DDINT

N12 DAI_P8 (SFS1) P12

GND N13 DAI_P9 (SD2A) P13

DAI_P10 (SD2B) N14 DAI_P11 (SD3A) P14

Rev. B | Page 49 of 56 | June 2007

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

14 1312 11 10 9 87 6 5 4 32 1

AVSS

VDDINT

VDDEXT I/O SIGNALS

AVDD

GND*

KEY

*USE THE CENTER BLOCK OF GROUND PINS TO PROVIDE

THERMAL PATHWAYS TO YOUR PRINTED

CIRCUIT BOARD’S GROUND PLANE.

Figure 43. BGA Pin Assignments (Bottom View, Summary)

1 2 34 5 6 7 8910 11 12 1314

KEY

AVSS

VDDINT

VDDEXT I/O SIGNALS

AVDD

GND*

*USE THE CENTER BLOCK OF GROUND PINS TO PROVIDE

THERMAL PATHWAYS TO YOUR PRINTED

CIRCUIT BOARD’S GROUND PLANE.

Figure 44. BGA Pin Assignments (Top View, Summary)

Rev. B | Page 50 of 56 | June 2007

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

OUTLINE DIMENSIONS

The ADSP-2136x is available in 136-ball BGA and 144-lead

exposed pad (LQFP_EP) packages.

0.15

0.05 0.08

COPLANARITY

1.45

1.40

1.35

VIEW A

ROTATED 90° CCW

22.20

1.60 MAX

SEATING

PLANE

0.75

0.60

0.45

20.20

20.00 SQ

19.80

22.00 SQ

21.80

TOP VIEW

(PINS DOWN)

108

144 109

PIN 1

VIEW A

0.20

0.09

7°

3.5°

0°

0.50

BSC

LEAD PITCH

0.27

0.22

0.17

BOTTOM VIEW

(PINS UP)

EXPOSED*

PAD

108

144

109

COMPLIANT TO JEDEC STANDARDS MS-026-BFB-HD

*EXPOSED PAD IS COINCIDENT WITH BOTTOM SURFACE AND

DOES NOT PROTRUDE BEYOND IT. EXPOSED PAD IS CENTERED.

Figure 45. 144-Lead Low Profile Quad Flat Package, Exposed Pad [LQFP_EP] (SW-144-1)–

Dimensions shown in millimeters

8.80 SQ

Rev. B | Page 51 of 56 | June 2007

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

12.10 A1 CORNER

0.80 BSC

10.40

BSC SQ BOTTOM VIEW

INDEX AREA

12.00 SQ

13 11 97531

11.90 14 12 10 8 6 4 2

BALL A1 B

INDICATOR D

TOP VIEW G

DETAIL A

1.70 MAX 1.31

DETAIL A

1.21

1.10

0.25 MIN

0.12 MAX

COPLANARITY

*0.50

0.45 SEATING

0.40 PLANE

BALL DIAMETER

*COMPLIANT WITH JEDEC STANDARDS MO-205-AE

WITH EXCEPTION TO BALL DIAMETER.

Figure 46. 136-Ball Chip Scale Package Ball Grid Array [CSP_BGA]

(BC-136)

Dimensions shown in millimeters

SURFACE MOUNT DESIGN

Table 46 is provided as an aide to PCB design. For industry-

standard design recommendations, refer to IPC-7351, Generic

Requirements for Surface Mount Design and Land Pattern

Standard.

Table 46. BGA Data for Use with Surface Mount Design

Package Ball Attach Type Solder Mask Opening Ball Pad Size

136-Ball CSP-BGA (BC-136) Solder Mask Defined 0.40 mm diameter 0.53 mm diameter

Rev. B | Page 52 of 56 | June 2007

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

ORDERING GUIDE

Model

Temperature

Range

Instruction

Rate

On-Chip

SRAM ROM

Operating

Voltage

Internal/

External

Package

Description Package Option

ADSP-21362KBC-1AA

0°C to +70°C 333 MHz 3M Bit 4M Bit 1.2 V/3.3 V 136-Ball CSP-BGA BC-136

ADSP-21362KBCZ-1AA

2, 3

0°C to +70°C 333 MHz 3M Bit 4M Bit 1.2 V/3.3 V 136-Ball CSP-BGA BC-136

ADSP-21362KSWZ-1AA

0°C to +70°C 333 MHz 3M Bit 4M Bit 1.2 V/3.3 V 136-Ball CSP-BGA BC-136

ADSP-21362BBC-1AA

–40°C to +85°C 333 MHz 3M Bit 4M Bit 1.2 V/3.3 V 136-Ball CSP-BGA BC-136

ADSP-21362BBCZ-1AA

2, 3

–40°C to +85°C 333 MHz 3M Bit 4M Bit 1.2 V/3.3 V 136-Ball CSP-BGA BC-136

ADSP-21362WBBCZ-1A

2, 3

–40°C to +85°C 333 MHz 3M Bit 4M Bit 1.2 V/3.3 V 136-Ball CSP-BGA BC-136

ADSP-21362BSWZ-1AA

2, 3

–40°C to +85°C 333 MHz 3M Bit 4M Bit 1.2 V/3.3 V 144-Lead LQFP_EP SW-144-1

ADSP-21362WBSWZ-1A

2, 3, 4

–40°C to +85°C 333 MHz 3M Bit 4M Bit 1.2 V/3.3 V 144-Lead LQFP_EP SW-144-1

ADSP-21362YSWZ-2AA

2, 3

–40°C to +105°C 200 MHz 3M Bit 4M Bit 1.0 V/3.3 V 144-Lead LQFP_EP SW-144-1

ADSP-21362WYSWZ-2A

2, 3, 4

–40°C to +105°C 200 MHz 3M Bit 4M Bit 1.0 V/3.3 V 144-Lead LQFP_EP SW-144-1

ADSP-21363KBC-1AA 0°C to +70°C 333 MHz 3M Bit 4M Bit 1.2 V/3.3 V 136-Ball CSP-BGA BC-136

ADSP-21363KBCZ-1AA

0°C to +70°C 333 MHz 3M Bit 4M Bit 1.2 V/3.3 V 136-Ball CSP-BGA BC-136

ADSP-21363KSWZ-1AA

0°C to +70°C 333 MHz 3M Bit 4M Bit 1.2 V/3.3 V 144-Lead LQFP_EP SW-144-1

ADSP-21363BBC-1AA –40°C to +85°C 333 MHz 3M Bit 4M Bit 1.2 V/3.3 V 136-Ball CSP-BGA BC-136

ADSP-21363BBCZ-1AA

–40°C to +85°C 333 MHz 3M Bit 4M Bit 1.2 V/3.3 V 136-Ball CSP-BGA BC-136

ADSP-21363WBBCZ-1A

–40°C to +85°C 333 MHz 3M Bit 4M Bit 1.2 V/3.3 V 136-Ball CSP-BGA BC-136

ADSP-21363WBSWZ-1A

3, 4

–40°C to +85°C 333 MHz 3M Bit 4M Bit 1.2 V/3.3 V 144-Lead LQFP_EP SW-144-1

ADSP-21363BSWZ-1AA

–40°C to +85°C 200 MHz 3M Bit 4M Bit 1.2 V/3.3 V 144-Lead LQFP_EP SW-144-1

ADSP-21363YSWZ-2AA

3, 4

–40°C to +105°C 200 MHz 3M Bit 4M Bit 1.0 V/3.3 V 144-Lead LQFP_EP SW-144-1

ADSP-21363WYSWZ-2A

3, 4

–40°C to +105°C 200 MHz 3M Bit 4M Bit 1.0 V/3.3 V 144-Lead LQFP_EP SW-144-1

ADSP-21364KBC-1AA 0°C to +70°C 333 MHz 3M Bit 4M Bit 1.2 V/3.3 V 136-Ball CSP-BGA BC-136

ADSP-21364KBCZ-1AA

0°C to +70°C 333 MHz 3M Bit 4M Bit 1.2 V/3.3 V 136-Ball CSP-BGA BC-136

ADSP-21364KSWZ-1AA

0°C to +70°C 333 MHz 3M Bit 4M Bit 1.2 V/3.3 V 144-Lead LQFP_EP SW-144-1

ADSP-21364BBC–1AA –40°C to +85°C 333 MHz 3M Bit 4M Bit 1.2 V/3.3 V 136-Ball CSP-BGA BC-136

ADSP-21364BBCZ-1AA

–40°C to +85°C 333 MHz 3M Bit 4M Bit 1.2 V/3.3 V 136-Ball CSP-BGA BC-136

ADSP-21364WBBCZ-1A

–40°C to +85°C 333 MHz 3M Bit 4M Bit 1.2 V/3.3 V 136-Ball CSP-BGA BC-136

ADSP-21364BSWZ-1AA

–40°C to +85°C 333 MHz 3M Bit 4M Bit 1.2 V/3.3 V 144-Lead LQFP_EP SW-144-1

ADSP-21364WBSWZ-1A

3, 4

–40°C to +85°C 333 MHz 3M Bit 4M Bit 1.2 V/3.3 V 144-Lead LQFP_EP SW-144-1

ADSP-21364YSWZ-2AA

–40°C to +105°C 200 MHz 3M Bit 4M Bit 1.0 V/3.3 V 144-Lead LQFP_EP SW-144-1

ADSP-21364WYSWZ-2A

3, 4

–40°C to +105°C 200 MHz 3M Bit 4M Bit 1.0 V/3.3 V 144-Lead LQFP_EP SW-144-1

ASDP-21365KBC-1AA

2, 5, 6

0°C to +70°C 333 MHz 3M Bit 4M Bit 1.2 V/3.3 V 136-Ball CSP-BGA BC-136

ASDP-21365KBCZ-1AA

2, 3, 5, 6

0°C to +70°C 333 MHz 3M Bit 4M Bit 1.2 V/3.3 V 136-Ball CSP-BGA BC-136

ASDP-21365BBC-1AA

2, 5, 6

–40°C to +85°C 333 MHz 3M Bit 4M Bit 1.2 V/3.3 V 136-Ball CSP-BGA BC-136

ASDP-21365BBCZ-1AA

2, 3, 5, 6

–40°C to +85°C 333 MHz 3M Bit 4M Bit 1.2 V/3.3 V 136-Ball CSP-BGA BC-136

ASDP-21365WBBCZ-1A

2, 3, 5, 6

–40°C to +85°C 333 MHz 3M Bit 4M Bit 1.2 V/3.3 V 136-Ball CSP-BGA BC-136

ADSP-21365BSWZ-1AA

2, 3, 5, 6

–40°C to +85°C 333 MHz 3M Bit 4M Bit 1.2 V/3.3 V 144-Lead LQFP_EP SW-144-1

ADSP-21365WBSWZ-1A

2, 4, 5, 6

–40°C to +85°C 333 MHz 3M Bit 4M Bit 1.2 V/3.3 V 144-Lead LQFP_EP SW-144-1

ADSP-21365YSWZ-2AA

2, 3, 5, 6

-–40°C to +105°C 200 MHz 3M Bit 4M Bit 1.0 V/3.3 V 144-Lead LQFP_EP SW-144-1

ADSP-21365WYSWZ-2B

2, 3, 4, 5, 6

–40°C to +105°C 200 MHz 3M Bit 4M Bit 1.0 V/3.3 V 144-Lead LQFP_EP SW-144-1

ADSP-21365YSWZ-2BA

2, 3, 5, 6

–40°C to +105°C 200 MHz 3M Bit 4M Bit 1.0 V/3.3 V 144-Lead LQFP_EP SW-144-1

ADSP-21365YSWZ-2CA

2, 3, 5, 6

–40°C to +105°C 200 MHz 3M Bit 4M Bit 1.0 V/3.3 V 144-Lead LQFP_EP SW-144-1

ADSP-21365WYSWZ-2A

2, 3, 5, 6

–40°C to +105°C 200 MHz 3M Bit 4M Bit 1.0 V/3.3 V 144-Lead LQFP_EP SW-144-1

ADSP-21365WYSWZ-2C

2, 3, 4, 5, 6

–40°C to +105°C 200 MHz 3M Bit 4M Bit 1.0 V/3.3 V 144-Lead LQFP_EP SW-144-1

Rev. B | Page 53 of 56 | June 2007

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

Model

Temperature

Range

Instruction

Rate

On-Chip

SRAM ROM

Operating

Voltage

Internal/

External

Package

Description Package Option

ADSP-21366KBC-1AA

5, 6

0°C to +70°C 333 MHz 3M Bit 4M Bit 1.2 V/3.3 V 136-Ball CSP-BGA BC-136

ADSP-21366KBCZ-1AA

3, 5, 6

0°C to +70°C 333 MHz 3M Bit 4M Bit 1.2 V/3.3 V 136-Ball CSP-BGA BC-136

ADSP-21366KSWZ-1AA

3, 5, 6

0°C to +70°C 333 MHz 3M Bit 4M Bit 1.2 V/3.3 V 144-Lead LQFP_EP SW-144-1

ADSP-21366BBC–1AA

5, 6

–40°C to +85°C 333 MHz 3M Bit 4M Bit 1.2 V/3.3 V 136-Ball CSP-BGA BC-136

ADSP-21366BBCZ-1AA

3, 5, 6

–40°C to +85°C 333 MHz 3M Bit 4M Bit 1.2 V/3.3 V 136-Ball CSP-BGA BC-136

ADSP-21366WBBCZ-1A

3, 5, 6

–40°C to +85°C 333 MHz 3M Bit 4M Bit 1.2 V/3.3 V 136-Ball CSP-BGA BC-136

ADSP-21366BSWZ-1AA

3, 5, 6

–40°C to +85°C 333 MHz 3M Bit 4M Bit 1.2 V/3.3 V 144-Lead LQFP_EP SW-144-1

ADSP-21366WBSWZ-1A

3, 4, 5, 6

–40°C to +85°C 333 MHz 3M Bit 4M Bit 1.2 V/3.3 V 144-Lead LQFP_EP SW-144-1

ADSP-21366YSWZ-2AA

3, 5, 6

–40°C to +105°C 200 MHz 3M Bit 4M Bit 1.0 V/3.3 V 144-Lead LQFP_EP SW-144-1

ADSP-21366WYSWZ-2A

3, 4, 5, 6

–40°C to +105°C 200 MHz 3M Bit 4M Bit 1.0 V/3.3 V 144-Lead LQFP_EP SW-144-1

Referenced temperature is ambient temperature.

License from DTLA required for these products.

Z = RoHS compliant part.

W = For quoting purposes only. Contact local sales office for specific ordering information.

Available with a wide variety of audio algorithm combinations sold as part of a chipset and bundled with necessary software. For a complete list, visit our website at

www.analog.com/SHARC.

License from Dolby Laboratories, Inc. and Digital Theater Systems (DTS) required for these products.

Rev. B | Page 54 of 56 | June 2007

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

Rev. B | Page 55 of 56 | June 2007

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

registered trademarks are the property of their respective owners.

D06359-0-6/07(B)

Rev. B | Page 56 of 56 | June 2007