CS42438 108 dB, 192 kHz 6-in, 8-out TDM CODEC Features General Description z Six 24-bit A/D, Eight 24-bit z ADC Dynamic Range D/A Converters - 105 dB Differential - 102 dB Single-Ended z DAC Dynamic Range - 108 dB Differential - 105 dB Single-Ended z ADC/DAC THD+N - -98 dB Differential - -95 dB Single-Ended z Compatible with industry standard Time Division Multiplexed (TDM) Serial Interface z System Sampling Rates up to 192 kHz z Programmable ADC High Pass Filter for DC Offset Calibration z Logarithmic Digital Volume Control z Hardware Mode or Software IC/SPI z Supports logic levels between 5 V and 1.8 V TDM Serial Audio Input Auxilliary Serial Audio Input Input Master Clock Six fully differential or single-ended inputs are available on stereo ADC1, ADC2 and ADC3. When operating in SingleEnded Mode, an internal MUX before ADC3 allows selection from up to four single-ended inputs. Digital volume control is provided for each ADC channel, with selectable overflow detection. All eight DAC channels provide digital volume control and can operate with differential or single-ended outputs. An auxiliary serial input is available for an additional two channels of PCM data. The CS42438 is ideal for audio systems requiring wide dynamic range, negligible distortion and low noise, such as A/V receivers, DVD receivers and automotive audio systems. ORDERING INFORMATION CS42438-CMZ CS42438-DMZ CS42438-DM CDB42438 Digital Supply = 3.3 V Volume Controls High Pass Filter 52-pin MQFP 52-pin MQFP 52-pin MQFP Internal Voltage Reference Digital Filters Modulators Multibit DAC1-4 and Analog Filters Digital Filters Multibit Oversampling ADC1&2 Digital Filters Multibit Oversampling ADC3 8 Differential or Single-Ended Outputs 8 4 4 4:2* TDM Serial Audio Output High Pass Filter -10 to 70 C -40 to 85 C -40 to 85 C Evaluation Board Analog Supply = 3.3 V to 5 V Register Configuration TDM Serial Interface Reset Level Translator Hardware Mode or I2C/SPI Software Mode Control Data Level Translator Control Port & Serial Audio Port Supply = 1.8 V to 5 V The CS42438 CODEC provides six multi-bit analog-to-digital and eight multi-bit digital-to-analog Delta-Sigma converters. The CODEC is capable of operation with either differential or single-ended inputs and outputs, in a 52-pin MQFP package. Differential or Single-Ended Analog Inputs 2 2 *Optional MUX allows selection from up to 4 single-ended inputs. Advance Product Information Cirrus Logic, Inc. http://www.cirrus.com This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice. Copyright (c) Cirrus Logic, Inc. 2004 (All Rights Reserved) JUL `04 DS646A1 1 CS42438 TABLE OF CONTENTS 1 2 3 4 5 DIGITAL I/O PIN CHARACTERISTICS ..................................................................................... 6 PIN DESCRIPTION - SOFTWARE MODE ................................................................................ 7 PIN DESCRIPTIONS - HARDWARE MODE ............................................................................ 9 TYPICAL CONNECTION DIAGRAMS .................................................................................... 11 CHARACTERISTICS AND SPECIFICATIONS ....................................................................... 13 SPECIFIED OPERATING CONDITIONS ............................................................................... 13 ABSOLUTE MAXIMUM RATINGS ......................................................................................... 13 ANALOG INPUT CHARACTERISTICS (CS42438-CM) ......................................................... 14 ANALOG INPUT CHARACTERISTICS (CS42438-DM) ......................................................... 15 ADC DIGITAL FILTER CHARACTERISTICS ......................................................................... 16 ANALOG OUTPUT CHARACTERISTICS (CS42438-CM) ..................................................... 17 ANALOG OUTPUT CHARACTERISTICS (CS42438-DM) ..................................................... 19 COMBINED DAC INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE ................ 21 SWITCHING SPECIFICATIONS - ADC/DAC PORT .............................................................. 22 SWITCHING CHARACTERISTICS - AUX PORT................................................................... 23 SWITCHING SPECIFICATIONS - CONTROL PORT - IC MODE......................................... 24 SWITCHING SPECIFICATIONS - CONTROL PORT - SPI FORMAT ................................... 25 DC ELECTRICAL CHARACTERISTICS................................................................................. 26 DIGITAL INTERFACE SPECIFICATIONS & CHARACTERISTICS ....................................... 26 6 APPLICATIONS ....................................................................................................................... 27 6.1 Overview .......................................................................................................................... 27 6.2 Analog Inputs ................................................................................................................... 28 6.2.1 Line Level Inputs ................................................................................................. 28 6.2.2 ADC3 Analog Input ............................................................................................. 29 6.2.3 High Pass Filter and DC Offset Calibration ......................................................... 30 6.3 Analog Outputs ................................................................................................................ 31 6.3.1 Initialization ......................................................................................................... 31 6.3.2 Line Level Outputs and Filtering ......................................................................... 31 6.3.3 Digital Volume Control ........................................................................................ 33 6.4 System Clocking .............................................................................................................. 33 6.5 CODEC Digital Interface .................................................................................................. 34 6.5.1 TDM .................................................................................................................... 34 6.5.2 I/O Channel Allocation ........................................................................................ 34 6.6 AUX Port Digital Interface Formats .................................................................................. 34 6.6.1 IS ........................................................................................................................ 35 6.6.2 Left Justified ........................................................................................................ 35 6.7 Control Port Description and Timing ................................................................................ 36 6.7.1 SPI Mode ............................................................................................................ 36 6.7.2 IC Mode ............................................................................................................. 37 6.8 Recommended Power-up Sequence ............................................................................... 38 6.8.1 Hardware Mode ................................................................................................... 38 6.8.2 Software Mode .................................................................................................... 38 6.9 Reset and Power-up ....................................................................................................... 38 6.10 Power Supply, Grounding, and PCB layout ................................................................... 39 7 REGISTER QUICK REFERENCE ........................................................................................... 40 8 REGISTER DESCRIPTION ..................................................................................................... 42 8.1 Memory Address Pointer (MAP) ....................................................................................... 42 8.2 Chip I.D. and Revision Register (address 01h) (Read Only) ............................................ 42 8.3 Power Control (address 02h) ............................................................................................ 43 8.4 Functional Mode (address 03h) ........................................................................................ 44 8.5 Interface Formats (address 04h)....................................................................................... 44 2 CS42438 8.6 Misc Control (address 05h) .............................................................................................. 45 8.7 Transition Control (address 06h) ...................................................................................... 46 8.8 DAC Channel Mute (address 07h) ................................................................................... 48 8.9 AOUTX Volume Control (addresses 08h- 0Fh) ............................................................ 48 8.10 DAC Channel Invert (address 10h) ................................................................................ 49 8.11 AINX Volume Control (address 11h - 16h) ..................................................................... 49 8.12 ADC Channel Invert (address 17h) ................................................................................ 49 8.13 Status Control (address 18h).......................................................................................... 50 8.14 Status (address 19h) (Read Only)................................................................................. 50 8.15 Status Mask (address 1Ah) ............................................................................................ 51 9 PARAMETER DEFINITIONS ................................................................................................... 52 10 REFERENCES ....................................................................................................................... 53 11 PACKAGE DIMENSIONS ..................................................................................................... 54 THERMAL CHARACTERISTICS ........................................................................................... 55 12 APPENDIX A: EXTERNAL FILTERS .................................................................................... 56 12.1 ADC Input Filter ............................................................................................................. 56 12.1.1 Passive Input Filter ........................................................................................... 57 12.1.2 Passive Input Filter w/Attenuation ..................................................................... 57 12.2 DAC Output Filter .......................................................................................................... 59 13 APPENDIX B: ADC FILTER PLOTS ..................................................................................... 60 14 APPENDIX C: DAC FILTER PLOTS ..................................................................................... 62 15 REVISION HISTORY ............................................................................................................. 64 3 CS42438 LIST OF FIGURES Figure 1. Typical Connection Diagram (Software Mode) .............................................................. 11 Figure 2. Typical Connection Diagram (Hardware Mode) ............................................................. 12 Figure 3. Output Test Load ........................................................................................................... 20 Figure 4. Maximum Loading.......................................................................................................... 20 Figure 5. TDM Serial Audio Interface Timing ................................................................................ 22 Figure 6. Serial Audio Interface Slave Mode Timing ..................................................................... 23 Figure 7. Control Port Timing - IC Format.................................................................................... 24 Figure 8. Control Port Timing - SPI Format................................................................................... 25 Figure 9. Full-Scale Input .............................................................................................................. 29 Figure 10. ADC3 Input Topology................................................................................................... 29 Figure 11. Audio Output Initialization Flow Chart .......................................................................... 32 Figure 12. Full-Scale Output ......................................................................................................... 33 Figure 13. TDM Serial Audio Format............................................................................................. 34 Figure 14. AUX IS Format............................................................................................................ 35 Figure 15. AUX Left Justified Format ............................................................................................ 35 Figure 16. Control Port Timing in SPI Mode.................................................................................. 36 Figure 17. Control Port Timing, IC Write ...................................................................................... 37 Figure 18. Control Port Timing, IC Read...................................................................................... 37 Figure 19. Single to Differential Active Input Filter ........................................................................ 56 Figure 20. Single-Ended Active Input Filter................................................................................... 56 Figure 21. Passive Input Filter....................................................................................................... 57 Figure 22. Passive Input Filter w/Attenuation................................................................................ 58 Figure 23. Active Analog Output Filter .......................................................................................... 59 Figure 24. Passive Analog Output Filter........................................................................................ 59 Figure 25. Single Speed Mode Stopband Rejection ..................................................................... 60 Figure 26. Single Speed Mode Transition Band............................................................................ 60 Figure 27. Single Speed Mode Transition Band (Detail) ............................................................... 60 Figure 28. Single Speed Mode Passband Ripple.......................................................................... 60 Figure 29. Double Speed Mode Stopband Rejection .................................................................... 60 Figure 30. Double Speed Mode Transition Band .......................................................................... 60 Figure 31. Double Speed Mode Transition Band (Detail).............................................................. 61 Figure 32. Double Speed Mode Passband Ripple ........................................................................ 61 Figure 33. Quad Speed Mode Stopband Rejection....................................................................... 61 Figure 34. Quad Speed Mode Transition Band............................................................................. 61 Figure 35. Quad Speed Mode Transition Band (Detail) ................................................................ 61 Figure 36. Quad Speed Mode Passband Ripple........................................................................... 61 Figure 37. Single Speed Stopband Rejection ............................................................................... 62 Figure 38. Single Speed Transition Band...................................................................................... 62 Figure 39. Single Speed Transition Band (detail).......................................................................... 62 Figure 40. Single Speed Passband Ripple.................................................................................... 62 Figure 41. Double Speed Stopband Rejection .............................................................................. 62 Figure 42. Double Speed Transition Band .................................................................................... 62 Figure 43. Double Speed Transition Band (detail) ........................................................................ 63 Figure 44. Double Speed Passband Ripple .................................................................................. 63 Figure 45. Quad Speed Stopband Rejection................................................................................. 63 Figure 46. Quad Speed Transition Band....................................................................................... 63 Figure 47. Quad Speed Transition Band (detail)........................................................................... 63 Figure 48. Quad Speed Passband Ripple..................................................................................... 63 4 CS42438 LIST OF TABLES Table 1. I/O Power Rails........................................................................................................................ 6 Table 2. Hardware Configurable Settings............................................................................................ 27 Table 3. AIN5 Analog Input Selection.................................................................................................. 30 Table 4. AIN6 Analog Input Selection.................................................................................................. 30 Table 5. MCLK Frequency Settings..................................................................................................... 33 Table 6. Serial Audio Interface Channel Allocations ........................................................................... 34 Table 7. MCLK Frequency Settings..................................................................................................... 44 Table 8. Example AOUT Volume Settings .......................................................................................... 48 Table 9. Example AIN Volume Settings .............................................................................................. 49 Table 10. Revision History................................................................................................................... 64 5 CS42438 1 DIGITAL I/O PIN CHARACTERISTICS Various pins on the CS42438 are powered from separate power supply rails. The logic level for each input should adhere to the corresponding power rail and should not exceed the maximum ratings. Power Rail VLC VLS Pin Name RST SCL/CCLK SDA/CDOUT AD0/CS AD1/CDIN MCLK I/O Receiver Input Input Input/ 1.8 V - 5.0 V, Output CMOS/Open Drain Input Input Input - LRCK Input/ Output SCLK Input/ Output ADC_SDOUT Output VA Driver DAC_SDIN Input AUX_LRCK Output AUX_SCLK Output AUX_SDIN Input MUTEC Output 1.8 V - 2.5 V and 3.3/5.0 V TTL Compatible 1.8 V - 2.5 V and 3.3/5.0 V TTL Compatible, with Hysteresis 1.8 V - 2.5 V and 3.3/5.0 V TTL Compatible, with Hysteresis 1.8 V - 2.5 V and 3.3/5.0 V TTL Compatible 1.8 V - 2.5 V and 3.3/5.0 V TTL Compatible 1.8 V - 2.5 V and 3.3/5.0 V TTL Compatible 1.8 V - 5.0 V, CMOS 1.8 V - 5.0 V, CMOS 1.8 V - 5.0 V, CMOS - 1.8 V - 2.5 V and 3.3/5.0 V TTL Compatible 1.8 V - 5.0 V, CMOS 1.8 V - 5.0 V, CMOS - - 1.8 V - 2.5 V and 3.3/5.0 V TTL Compatible 1.8 V - 2.5 V and 3.3/5.0 V TTL Compatible 1.8 V - 2.5 V and 3.3/5.0 V TTL Compatible 1.8 V - 5.0 V, CMOS Table 1. I/O Power Rails 6 - CS42438 AIN2+ AIN2- AIN3- AIN3+ AIN4- AIN4+ VA FILT+ AGND AIN5-/AIN5B AIN5+/AIN5A AIN6-/AIN6B AIN6+/AIN6A 2 PIN DESCRIPTION - SOFTWARE MODE 52 51 50 49 48 47 46 45 44 43 42 41 40 SCL/CCLK 1 39 AIN1+ SDA/CDOUT 2 38 AIN1- AD0/CS AD1/CDIN 3 37 VA 4 VQ RST VLC 5 36 35 34 33 AOUT8AOUT7+ AGND FS 6 7 VD 8 32 DGND 9 31 AOUT7- VLS 10 30 AOUT6- SCLK 11 12 29 AOUT6+ MCLK ADC_SDOUT 13 28 27 AOUT5- CS42438 AOUT8+ AOUT5+ AOUT4+ AOUT4- AOUT3+ AOUT3- AOUT2- AOUT2+ AOUT1+ AOUT1- DGND AUX_SDIN AUX_SCLK DAC_SDIN AUX_LRCK 14 15 16 17 18 19 20 21 22 23 24 25 26 Pin Name # Pin Description SCL/CCLK 1 Serial Control Port Clock (Input) - Serial clock for the control port interface. SDA/CDOUT 2 Serial Control Data I/O (Input/Output) - Input/Output for I2C data. Output for SPI data. AD0/CS 3 Address Bit [0]/ Chip Select (Input) - Chip address bit in I2C Mode. Control signal used to select the chip in SPI mode. AD1/CDIN 4 Address Bit [1]/ SPI Data Input (Input) - Chip address bit in I2C Mode. Input for SPI data. RST 5 Reset (Input) - The device enters a low power mode and all internal registers are reset to their default settings when low. VLC 6 Control Port Power (Input) - Determines the required signal level for the RST, MFREQ pins. FS 7 Frame Sync (Input) - Signals the start of a new TDM frame in the TDM digital interface format. VD 8 Digital Power (Input) - Positive power supply for the digital section. DGND 9,18 Digital Ground (Input) - VLS 10 Serial Port Interface Power (Input) - Determines the required signal level for the serial port interfaces. SCLK 11 Serial Clock (Input) - Serial clock for the serial audio interface. Input frequency must be 256xFs. MCLK 12 Master Clock (Input) - Clock source for the delta-sigma modulators and digital filters. ADC_SDOUT 13 Serial Audio Data Output (Output) - TDM output for two's complement serial audio data. DAC_SDIN 14 DAC Serial Audio Data Input (Input) - TDM Input for two's complement serial audio data. AUX_LRCK 15 Auxiliary Left/Right Clock (Output) - Determines which channel, Left or Right, is currently active on the Auxiliary serial audio data line. AUX_SCLK 16 Auxiliary Serial Clock (Output) - Serial clock for the Auxiliary serial audio interface. 7 CS42438 AUX_SDIN 17 Auxiliary Serial Input (Input) - The CS42438 provides an additional serial input for two's complement serial audio data. AOUT1 +,AOUT2 +,AOUT3 +,AOUT4 +,AOUT5 +,AOUT6 +,- 20,19 Differential Analog Output (Output) - The full-scale differential analog output level is specified in 21,22 the Analog Characteristics specification table. Each positive leg of the differential outputs may also 24,23 be used single-ended. 25,26 28,27 29,30 AGND 35,48 Analog Ground (Input) - VQ 36 Quiescent Voltage (Output) - Filter connection for internal quiescent reference voltage. VA 37,46 Analog Power (Input) - Positive power supply for the analog section. AIN1 +,AIN2 +,AIN3 +,AIN4 +,AIN5 +,AIN6 +,- 39,38 41,40 43,42 45,44 50,49 52,51 AIN5 A,B AIN6 A,B 50,49 Single-Ended Analog Input (Input) - In Single-Ended Mode, an internal analog mux allows selec52,51 tion between 2 channels for both analog inputs AIN5 and AIN6 (see section 8.6.6-8.6.8 for details). The unused leg of each input is internally connected to common mode. The full-scale input level is specified in the Analog Characteristics specification table. FILT+ 8 47 Differential Analog Input (Input) - Signals are presented differentially to the delta-sigma modulators. The full-scale input level is specified in the Analog Characteristics specification table. Singleended inputs may be applied to the positive terminals when the ADCx SINGLE bit is enabled. Once in Single-Ended Mode, the negative terminal of AIN1-AIN4 must be externally driven to common mode. See below for a description of AIN5-AIN6 in Single-Ended Mode. Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits. CS42438 AIN2+ AIN2- AIN3- AIN3+ AIN4- AIN4+ FILT+ VA AIN5-/AIN5B AGND AIN5+/AIN5A AIN6-/AIN6B AIN6+/AIN6A 3 PIN DESCRIPTIONS - HARDWARE MODE 52 51 50 49 48 47 46 45 44 43 42 41 40 AIN5_MUX 1 39 AIN1+ AIN6_MUX 2 38 AIN1- MFREQ ADC3_HPF 3 37 VA 4 VQ RST VLC 5 36 35 34 33 AOUT8- FS 6 7 VD 8 32 AOUT7+ DGND 9 31 AOUT7- VLS 10 30 AOUT6- SCLK 11 12 29 AOUT6+ 28 27 AOUT5- 13 AOUT8+ AOUT5+ AOUT4+ AOUT4- AOUT3+ AOUT3- AOUT2- AOUT2+ AOUT1- AOUT1+ DGND AUX_SDIN AUX_SCLK AUX_LRCK 14 15 16 17 18 19 20 21 22 23 24 25 26 DAC_SDIN MCLK ADC_SDOUT/ ADC3_SINGLE CS42438 AGND Pin Name # Pin Description AIN5_MUX AIN6_MUX 1 2 Analog Input Multiplexer (Input) - Allows selection between the A and B single-ended inputs of ADC3. See sections 8.6.7 and 8.6.8 for details. MFREQ 3 MCLK Frequency (Input) - Sets the required frequency range of the input Master Clock. See section 6.4 for the appropriate settings. ADC3_HPF 4 ADC3 High-Pass Filter Freeze (Input) - When this pin is driven high, the internal high-pass filter will be disabled for ADC3.The current DC offset value will be frozen and continue to be subtracted from the conversion result. See "ADC Digital Filter Characteristics" on page 16. RST 5 Reset (Input) - The device enters a low power mode and all internal registers are reset to their default settings when low. VLC 6 Control Port Power (Input) - Determines the required signal level for the RST, MFREQ pins. FS 7 Frame Sync (Input) - Signals the start of a new TDM frame in the TDM digital interface format. VD 8 Digital Power (Input) - Positive power supply for the digital section. VLS 10 Serial Port Interface Power (Input) - Determines the required signal level for the serial port interfaces. SCLK 11 Serial Clock (Input) - Serial clock for the serial audio interface. Input frequency must be 256xFs. ADC_SDOUT/ ADC3_SINGLE 13 Serial Audio Data Output (Output) - TDM output for two's complement serial audio data. Start-up Option for Hardware Mode: Pull-up to VLS enables Single-Ended Mode for AIN5-AIN6. DAC_SDIN 14 DAC Serial Audio Data Input (Input) - Input for two's complement serial audio data. AUX_LRCK 15 Auxiliary Left/Right Clock (Output) - Determines which channel, Left or Right, is currently active on the Auxiliary serial audio data line. AUX_SCLK 16 Auxiliary Serial Clock (Output) - Serial clock for the Auxiliary serial audio interface. 9 CS42438 AUX_SDIN 17 Auxiliary Serial Input (Input) - The CS42438 provides an additional serial input for two's complement serial audio data. AOUT1 +,AOUT2 +,AOUT3 +,AOUT4 +,AOUT5 +,AOUT6 +,- 20,19 Differential Analog Output (Output) - The full-scale differential analog output level is specified in 21,22 the Analog Characteristics specification table. Each positive leg of the differential outputs may also 24,23 be used single-ended. 25,26 28,27 29,30 AGND 35,48 Analog Ground (Input) - VQ 36 Quiescent Voltage (Output) - Filter connection for internal quiescent reference voltage. VA 37,46 Analog Power (Input) - Positive power supply for the analog section. AIN1 +,AIN2 +,AIN3 +,AIN4 +,AIN5 +,AIN6 +,- 39,38 41,40 43,42 45,44 50,49 52,51 AIN5 A,B AIN6 A,B 50,49 Single-Ended Analog Input (Input) - In Single-Ended Mode, an internal analog mux allows selec52,51 tion between 2 channels for both analog inputs AIN5 and AIN6 (see section 8.6.6-8.6.8 for details). The unused leg of each input is internally connected to common mode. The full-scale input level is specified in the Analog Characteristics specification table. FILT+ 10 47 Differential Analog Input (Input) - Signals are presented differentially to the delta-sigma modulators. The full-scale input level is specified in the Analog Characteristics specification table. Singleended inputs may be applied to the positive terminals when the ADCx SINGLE pin is enabled. Once in Single-Ended Mode, the negative terminal of AIN1-AIN4 must be externally driven to common mode. See below for a description of AIN5-AIN6 in Single-Ended Mode. Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits. CS42438 4 TYPICAL CONNECTION DIAGRAMS +3.3 V 10 F 0.01 F 0.01 F + + +3.3 V to +5 V 10 F 0.01 F VD VA VA VLS 0.01 F AUX_SCLK AUX_LRCK AUX_SDIN CS5341 A/D Converter AOUT1+ AOUT1- Analog Output Filter 2 AOUT2+ AOUT2- Analog Output Filter 2 AOUT3+ AOUT3- Analog Output Filter 2 AOUT4+ AOUT4- Analog Output Filter 2 AOUT5+ AOUT5- Analog Output Filter 2 AOUT6+ AOUT6- Analog Output Filter 2 AOUT7+ AOUT7- Analog Output Filter 2 AOUT8+ AOUT8- Analog Output Filter 2 AIN1+ AIN1AIN2+ AIN2- Input Filter 1 Analog Input 1 Input Filter 1 Analog Input 2 Input Filter 1 Analog Input 3 Input Filter 1 Analog Input 4 MCLK AIN3+ SCLK +1.8 V to +5.0 V AIN3- FS DAC_SDIN Digital Audio Processor AIN4+ AIN4- ADC_SDOUT AIN5+/AIN5A AIN5-/AIN5B AIN6+/AIN6A AIN6-/AIN6B RST MicroController SCL/CCLK SDA/CDOUT AD1/CDIN AD0/CS ** 2 k ** 2 k +1.8 V to +5 V VLC 0.1 F Input Filter 1 Analog Input 5 Input Filter 1 Analog Input 6 Input Filter 1 Analog Input 5A Input Filter 1 Analog Input 5B Input Filter 1 Analog Input 6A Input Filter 1 Analog Input 6B VQ FILT+ ** Resistors are required for I2C control port operation + DGND DGND AGND AGND Connect DGND and AGND at Codec 0.1 F + 100 F 0.1 F 4.7 F 1. See the ADC Input Filter section in the Appendix. 2. See the DAC Output Filter section in the Appendix. Figure 1. Typical Connection Diagram (Software Mode) 11 CS42438 +3.3 V 10 F + 0.01 F 0.01 F + +3.3 V to +5 V 10 F 0.01 F VD VA VA VLS 0.01 F AUX_SCLK AUX_LRCK AUX_SDIN CS5341 A/D Converter AOUT1+ AOUT1- Analog Output Filter 2 AOUT2+ AOUT2- Analog Output Filter 2 AOUT3+ AOUT3- Analog Output Filter 2 AOUT4+ AOUT4- Analog Output Filter 2 AOUT5+ AOUT5- Analog Output Filter 2 AOUT6+ AOUT6- Analog Output Filter 2 AOUT7+ AOUT7- Analog Output Filter 2 AOUT8+ AOUT8- Analog Output Filter 2 AIN1+ AIN1AIN2+ AIN2- Input Filter 1 Analog Input 1 Input Filter 1 Analog Input 2 Input Filter 1 Analog Input 3 Input Filter 1 Analog Input 4 MCLK AIN3+ SCLK +1.8 V to +5.0 V AIN3- FS DAC_SDIN AIN4+ VLS * Digital Audio Processor AIN4ADC_SDOUT/ ADC3_SINGLE * AIN5+/AIN5A AIN5-/AIN5B AIN6+/AIN6A AIN6-/AIN6B RST AIN6_MUX Input Filter 1 Analog Input 5 Input Filter 1 Analog Input 6 Input Filter 1 Analog Input 5A Input Filter 1 Analog Input 5B Input Filter 1 Analog Input 6A Input Filter 1 Analog Input 6B AIN5_MUX ADC3_HPF MFREQ VLC VQ 0.1 F FILT+ + * MUX configuration settings for AIN5-AIN6. See the ADC Input MUX section. DGND DGND AGND AGND Connect DGND and AGND at Codec 0.1 F + 100 F 0.1 F 1. See the ADC Input Filter section in the Appendix. 2. See the DAC Output Filter section in the Appendix. Figure 2. Typical Connection Diagram (Hardware Mode) 12 4.7 F CS42438 5 CHARACTERISTICS AND SPECIFICATIONS (All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical performance characteristics and specifications are derived from measurements taken at nominal supply voltages and TA = 25 C.) SPECIFIED OPERATING CONDITIONS (AGND=DGND=0 V, all voltages with respect to ground.) Parameters DC Power Supply Analog 3.3 V 5.0 V 3.3 V 1.8 V 2.5 V 3.3 V 5.0 V 1.8 V 2.5 V 3.3 V 5.0 V (Note 1) Digital Serial Audio Interface Control Port Interface Ambient Temperature Commercial Automotive -CM -DM Symbol Min Typ Max Units VA 3.14 4.75 3.14 1.71 2.37 3.14 4.75 1.71 2.37 3.14 4.75 3.3 5 3.3 1.8 2.5 3.3 5 1.8 2.5 3.3 5 3.47 5.25 3.47 1.89 2.63 3.47 5.25 1.89 2.63 3.47 5.25 V V V V V V V V V V V -10 -40 - +70 +85 C C VD VLS VLC TA ABSOLUTE MAXIMUM RATINGS (AGND = DGND = 0 V; all voltages with respect to ground.) Parameters DC Power Supply Input Current Analog Input Voltage Digital Input Voltage (Note 3) Ambient Operating Temperature (power applied) Storage Temperature Analog Digital Serial Port Interface Control Port Interface (Note 2) (Note 3) Serial Port Interface Control Port Interface CS42438-CM CS42438-DM Symbol VA VD VLS VLC Iin VIN VIND-S VIND-C TA TA Tstg Min -0.3 -0.3 -0.3 -0.3 AGND-0.7 -0.3 -0.3 -20 -50 -65 Max 6.0 6.0 6.0 6.0 10 VA+0.7 VLS+ 0.4 VLC+ 0.4 +85 +95 +150 Units V V V V mA V V V C C C WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. Notes: 1. Analog input/output performance will slightly degrade at VA = 3.3 V. 2. Any pin except supplies. Transient currents of up to 100 mA on the analog input pins will not cause SCR latch-up. 3. The maximum over/under voltage is limited by the input current. 13 CS42438 ANALOG INPUT CHARACTERISTICS (CS42438-CM) (Test Conditions (unless otherwise specified): VLS = VLC = VD = 3.3 V, VA = 5 V; Full scale input sine wave: 1 kHz through the active input filter on page 56; Measurement Bandwidth is 10 Hz to 20 kHz unless otherwise specified.) Differential Parameter Single Speed Mode Dynamic Range Fs=48 kHz A-weighted unweighted Total Harmonic Distortion + Noise -1 dB (Note 4) -20 dB -60 dB Double Speed Mode Dynamic Range Fs=96 kHz A-weighted unweighted 40 kHz bandwidth unweighted Total Harmonic Distortion + Noise -1 dB (Note 4) -20 dB -60 dB 40 kHz bandwidth -1 dB Quad Speed Mode Dynamic Range Fs=192 kHz A-weighted unweighted 40 kHz bandwidth unweighted Total Harmonic Distortion + Noise -1 dB (Note 4) -20 dB -60 dB 40 kHz bandwidth -1 dB All Speed Modes Interchannel Isolation DC Accuracy Interchannel Gain Mismatch Gain Drift Analog Input Full-scale Input Voltage Differential Input Impedance (Note 5) Single-Ended Input Impedance (Note 6) Common Mode Rejection Ratio (CMRR) 14 Single-Ended Min Typ Max Min Typ Max Unit 99 96 - 105 102 -98 -82 -42 -92 - 96 93 - 102 99 -95 -79 -39 -89 - dB dB dB dB dB 99 96 - 105 102 99 -98 -82 -42 -90 -92 - 96 93 102 99 96 -95 -79 -39 -90 -89 - dB dB dB dB dB dB dB 99 96 - 105 102 99 -98 -82 -42 -87 -92 - 96 93 102 99 96 -95 -79 -39 -87 - dB dB dB dB dB dB dB - 90 - - 90 - dB - 0.1 100 - - 0.1 100 - dB ppm/C - - -89 - 1.06*VA 1.12*VA 1.18*VA 0.53*VA 0.56*VA 0.59*VA 37 18 82 - Vpp k k dB CS42438 ANALOG INPUT CHARACTERISTICS (CS42438-DM) (Test Conditions (unless otherwise specified):VLS = VLC = VD = 3.3 V, VA = 5 V; Full scale input sine wave: 1 kHz through the active input filter on page 56; Measurement Bandwidth is 10 Hz to 20 kHz unless otherwise specified.) Differential Parameter Single Speed Mode Dynamic Range Fs=48 kHz A-weighted unweighted Total Harmonic Distortion + Noise -1 dB (Note 4) -20 dB -60 dB Double Speed Mode Dynamic Range Fs=96 kHz A-weighted unweighted 40 kHz bandwidth unweighted Total Harmonic Distortion + Noise -1 dB (Note 4) -20 dB -60 dB 40 kHz bandwidth -1 dB Quad Speed Mode Dynamic Range Fs=192 kHz A-weighted unweighted 40 kHz bandwidth unweighted Total Harmonic Distortion + Noise -1 dB (Note 4) -20 dB -60 dB 40 kHz bandwidth -1 dB All Speed Modes Interchannel Isolation DC Accuracy Interchannel Gain Mismatch Gain Drift Analog Input Full-scale Input Voltage Differential Input Impedance (Note 5) Single-Ended Input Impedance (Note 6) Common Mode Rejection Ratio (CMRR) Single-Ended Min Typ Max Min Typ Max Unit 97 94 - 105 102 -98 -82 -42 -90 - 94 91 - 102 99 -95 -79 -39 -87 - dB dB dB dB dB 97 94 - 105 102 99 -98 -82 -42 -87 -90 - 94 91 - 102 99 96 -95 -79 -39 -87 -87 - dB dB dB dB dB dB dB 97 94 - 105 102 99 -98 -82 -42 -87 -90 - 94 91 - 102 99 96 -95 -79 -39 -87 -87 - dB dB dB dB dB dB dB - 90 - - 90 - dB - 0.1 100 - - 0.1 100 - dB ppm/C 1.04*VA 1.12*VA 1.20*VA 0.52*VA 0.56*VA 0.60*VA 37 18 82 - Vpp k k dB Notes: 4. Referred to the typical full-scale voltage. 5. Measured between AINx+ and AINx-. 6. Measured between AINxx and AGND. 15 CS42438 ADC DIGITAL FILTER CHARACTERISTICS Parameter (Note 7, 8) Min Typ Max Unit 0 - 0.4896 Fs - - 0.035 dB 0.5688 - - Fs 70 - - dB - 12/Fs - s 0 - 0.4896 Fs - - 0.025 dB 0.5604 - - Fs 69 - - dB - 9/Fs - s 0 - 0.2604 Fs - - 0.025 dB 0.5000 - - Fs 60 - - dB - 5/Fs - s Single Speed Mode (Note 8) Passband (Frequency Response) to -0.1 dB corner Passband Ripple Stopband Stopband Attenuation Total Group Delay Double Speed Mode (Note 8) Passband (Frequency Response) to -0.1 dB corner Passband Ripple Stopband Stopband Attenuation Total Group Delay Quad Speed Mode (Note 8) Passband (Frequency Response) Passband Ripple Stopband Stopband Attenuation Total Group Delay to -0.1 dB corner High Pass Filter Characteristics Frequency Response -3.0 dB -0.13 dB - 1 20 - Hz Hz Phase Deviation @ 20 Hz - 10 - Deg Passband Ripple - - 0 dB Filter Settling Time - 105/Fs 0 s Notes: 7. Filter response is guaranteed by design. 8. Response is clock dependent and will scale with Fs. Note that the response plots (Figures 25 to 36) have been normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs. 16 CS42438 ANALOG OUTPUT CHARACTERISTICS (CS42438-CM) (Test Conditions (unless otherwise specified):VLS = VLC = VD = 3.3 V, VA = 5 V; Measurement Bandwidth is 10 Hz to 20 kHz unless otherwise specified; Full scale 997 Hz output sine wave (see Note 10); Single-ended test load: RL = 3 k, CL = 10 pF.) Parameter Single-Speed Mode Fs = 48 kHz Dynamic Range 18 to 24-Bit A-weighted unweighted 16-Bit A-weighted unweighted Total Harmonic Distortion + Noise 18 to 24-Bit 0 dB -20 dB -60 dB 16-Bit 0 dB -20 dB -60 dB Double-Speed Mode Fs = 96 kHz Dynamic Range 18 to 24-Bit A-weighted unweighted 16-Bit A-weighted unweighted Total Harmonic Distortion + Noise 18 to 24-Bit 0 dB -20 dB -60 dB 16-Bit 0 dB -20 dB -60 dB Quad-Speed Mode Fs = 192 kHz Dynamic Range 18 to 24-Bit A-weighted unweighted 16-Bit A-weighted unweighted Total Harmonic Distortion + Noise 18 to 24-Bit 0 dB -20 dB -60 dB 16-Bit 0 dB -20 dB -60 dB Min Differential Typ 102 99 - 108 105 99 96 - 99 96 - 105 102 96 93 - dB dB dB dB - -98 -85 -45 -93 -76 -36 -92 - - -95 -82 -42 -90 -73 -33 -89 - dB dB dB dB dB dB 102 99 - 108 105 99 96 - 99 96 - 105 102 96 93 - dB dB dB dB - -98 -85 -45 -93 -76 -36 -92 - - -95 -82 -42 -90 -73 -33 -89 - dB dB dB dB dB dB 102 99 - 108 105 99 96 - 99 96 - 105 102 96 93 - dB dB dB dB - -98 -85 -45 -93 -76 -36 -92 - - -95 -82 -42 -90 -73 -33 -89 - dB dB dB dB dB dB Max Min Single-Ended Typ Max Unit 17 CS42438 All Speed Modes Interchannel Isolation (1 kHz) Analog Output Full Scale Output 1.235*VA Interchannel Gain Mismatch Gain Drift Output Impedance DC Current draw from an AOUT pin - 100 - - 100 - dB 1.300*VA 1.365*VA 0.618*VA 0.650*VA 0.683*VA Vpp 0.1 0.25 0.1 0.25 dB 100 100 ppm/C 100 100 10 10 A (Note 9) AC-Load Resistance (RL) (Note 11) 3 - - 3 - - k Load Capacitance (CL) (Note 11) - - 100 - - 100 pF 18 CS42438 ANALOG OUTPUT CHARACTERISTICS (CS42438-DM) (Test Conditions (unless otherwise specified): VLS = VLC = VD = 3.3 V,VA = 5 V; Measurement Bandwidth is 10 Hz to 20 kHz unless otherwise specified; Full scale 997 Hz output sine wave (see Note 10); Single-ended test load: RL = 3 k, CL = 10 pF.) Parameter Single-Speed Mode Fs = 48 kHz Dynamic Range 18 to 24-Bit A-weighted unweighted 16-Bit A-weighted unweighted Total Harmonic Distortion + Noise 18 to 24-Bit 0 dB -20 dB -60 dB 16-Bit 0 dB -20 dB -60 dB Double-Speed Mode Fs = 96 kHz Dynamic Range 18 to 24-Bit A-weighted unweighted 16-Bit A-weighted unweighted Total Harmonic Distortion + Noise 18 to 24-Bit 0 dB -20 dB -60 dB 16-Bit 0 dB -20 dB -60 dB Quad-Speed Mode Fs = 192 kHz Dynamic Range 18 to 24-Bit A-weighted unweighted 16-Bit A-weighted unweighted Total Harmonic Distortion + Noise 18 to 24-Bit 0 dB -20 dB -60 dB 16-Bit 0 dB -20 dB -60 dB Min Differential Typ 100 97 - 108 105 99 96 - 97 94 - 105 102 96 93 - dB dB dB dB - -98 -85 -45 -93 -76 -36 -90 - - -95 -82 -42 -90 -73 -33 -87 - dB dB dB dB dB dB 100 97 - 108 105 99 96 - 97 94 - 105 102 96 93 - dB dB dB dB - -98 -85 -45 -93 -76 -36 -90 - - -95 -82 -42 -90 -73 -33 -87 - dB dB dB dB dB dB 100 97 - 108 105 99 96 - 97 94 - 105 102 96 93 - dB dB dB dB - -98 -85 -45 -93 -76 -36 -90 - - -95 -82 -42 -90 -73 -33 -87 - dB dB dB dB dB dB Max Min Single-Ended Typ Max Unit 19 CS42438 All Speed Modes Interchannel Isolation (1 kHz) Analog Output Full Scale Output 1.210*VA Interchannel Gain Mismatch Gain Drift Output Impedance DC Current draw from an AOUT pin - 100 - - 100 - dB 1.300*VA 1.392*VA 0.605*VA 0.650*VA 0.696*VA Vpp 0.1 0.25 0.1 0.25 dB 100 100 ppm/C 100 100 10 10 A (Note 9) AC-Load Resistance (RL) (Note 11) 3 - - 3 - - k Load Capacitance (CL) (Note 11) - - 100 - - 100 pF Notes: 9. Guaranteed by design. The DC current draw represents the allowed current draw from the AOUT pin due to typical leakage through the electrolytic DC blocking capacitors. 10. One-half LSB of triangular PDF dither is added to data. 11. Guaranteed by design. See Figure 3. RL and CL reflect the recommended minimum resistance and maximum capacitance required for the internal op-amp's stability and signal integrity. In this circuit topology, CL will effectively move the dominant pole of the two-pole amp in the output stage. Increasing this value beyond the recommended 100 pf can cause the internal op-amp to become unstable. See Appendix A for a recommended output filter. DAC1-4 AOUTxx 3.3 F Analog Output + RL CL Capacitive Load -- C L (pF) 125 100 75 Safe Operating Region 50 25 AGND 2.5 3 Figure 3. Output Test Load 20 5 10 15 Resistive Load -- RL (k ) Figure 4. Maximum Loading 20 CS42438 COMBINED DAC INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE Min Typ Max Unit 0 0 - 0.4780 0.4996 Fs Fs -.01 - +0.08 dB 0.5465 - - Fs 50 - - dB - 10/Fs - s Fs = 32 kHz Fs = 44.1 kHz Fs = 48 kHz - - to -0.1 dB corner to -3 dB corner 0 0 - 0.4650 0.4982 Fs Fs -0.05 - +.2 dB 0.5770 - - Fs 55 - - dB - 5/Fs - s 0 0 - 0.397 0.476 Fs Fs 0 - +0.00004 dB Parameter (Note 7, 12) Single Speed Mode Passband (Frequency Response) to -0.05 dB corner to -3 dB corner Frequency Response 10 Hz to 20 kHz StopBand StopBand Attenuation (Note 13) Group Delay De-emphasis Error (Note 14) +1.5/+0 dB +0.05/-0.25 dB -0.2/-0.4 dB Double Speed Mode Passband (Frequency Response) Frequency Response 10 Hz to 20 kHz StopBand StopBand Attenuation (Note 13) Group Delay Quad Speed Mode Passband (Frequency Response) to -0.1 dB corner to -3 dB corner Frequency Response 10 Hz to 20 kHz StopBand StopBand Attenuation (Note 13) Group Delay 0.7 - - Fs 51 - - dB - 2.5/Fs - s Notes: 12. Response is clock dependent and will scale with Fs. Note that the response plots (Figures 37 to 48) have been normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs. 13. Single and Double Speed Mode Measurement Bandwidth is from Stopband to 3 Fs. Quad Speed Mode Measurement Bandwidth is from Stopband to 1.34 Fs. 14. De-emphasis is only available in Single Speed Mode. 21 CS42438 SWITCHING SPECIFICATIONS - ADC/DAC PORT (Inputs: Logic 0 = DGND, Logic 1 = VLS, ADC_SDOUT CLOAD = 15 pF.) Parameters Symbol Min Max Units 1 - ms 0.512 50 MHz 45 55 % 4 50 100 50 100 200 kHz kHz kHz Slave Mode RST pin Low Pulse Width (Note 15) MCLK Frequency MCLK Duty Cycle (Note 16) Input Sample Rate (FS pin) Single-Speed Mode Double-Speed Mode Quad-Speed Mode Fs Fs Fs SCLK Duty Cycle 45 55 % SCLK High Time tsckh 8 - ns SCLK Low Time tsckl 8 - ns FS Rising Edge to SCLK Rising Edge tfss 5 - ns SCLK Rising Edge to FS Falling Edge tfsh 16 - ns SCLK Falling Edge to ADC_SDOUT Output Valid tdpd - 5 ns DAC_SDIN Setup Time Before SCLK Rising Edge tds 3 - ns DAC_SDIN Hold Time After SCLK Rising Edge tdh 5 - ns DAC_SDIN Hold Time After SCLK Rising Edge tdh1 5 - ns ADC_SDOUT Hold Time After SCLK Rising Edge tdh2 10 - ns ADC_SDOUT Valid Before SCLK Rising Edge tdval 15 - ns Notes: 15. After powering up the CS42438, RST should be held low after the power supplies and clocks are settled. 16. See Table 7 on page 44 for suggested MCLK frequencies. FS (input) tfss tfsh tsckh tsckl SCLK (input) tds tdh1 DAC_SDIN tdh2 ADC_SDOUT MSB-1 MSB MSB tdval MSB-1 Figure 5. TDM Serial Audio Interface Timing 22 CS42438 SWITCHING CHARACTERISTICS - AUX PORT (Inputs: Logic 0 = DGND, Logic 1 = VLS.) Parameters Symbol Min Max Units Master Mode Output Sample Rate (AUX_LRCK) All Speed Modes Fs - LRCK kHz AUX_SCLK Frequency - 64*LRCK kHz AUX_SCLK Duty Cycle 45 55 % AUX_LRCK Edge to SCLK Rising Edge tlcks - 5 ns AUX_SCLK Falling Edge to ADC_SDOUT Output Valid tdpd - 5 ns AUX_SDIN Setup Time Before SCLK Rising Edge tds 3 - ns AUX_SDIN Hold Time After SCLK Rising Edge tdh 5 - ns AUX_LRCK tlcks tsckh tsckl AUX_SCLK tds AUX_SDIN tdh MSB MSB-1 Figure 6. Serial Audio Interface Slave Mode Timing 23 CS42438 SWITCHING SPECIFICATIONS - CONTROL PORT - IC MODE (VLC = 1.8 V - 5.0 V, VLS = VD = 3.3 V, VA = 5.0 V; Inputs: Logic 0 = DGND, Logic 1 = VLC, SDA CL = 30 pF) Parameter Symbol Min Max Unit SCL Clock Frequency fscl - 100 kHz RST Rising Edge to Start tirs 500 - ns Bus Free Time Between Transmissions tbuf 4.7 - s Start Condition Hold Time (prior to first clock pulse) thdst 4.0 - s Clock Low time tlow 4.7 - s Clock High Time thigh 4.0 - s Setup Time for Repeated Start Condition tsust 4.7 - s thdd 0 - s tsud 250 - ns SDA Hold Time from SCL Falling (Note 17) SDA Setup time to SCL Rising Rise Time of SCL and SDA (Note 18) trc - 1 s Fall Time SCL and SDA (Note 18) tfc - 300 ns Setup Time for Stop Condition tsusp 4.7 - s Acknowledge Delay from SCL Falling tack 300 1000 ns Notes: 17. Data must be held for sufficient time to bridge the transition time, tfc, of SCL. 18. Guaranteed by design. RST t irs Stop R e p e a te d Sta rt Start t rd t fd Stop SDA t buf t t hdst t high t fc hdst SCL t lo w t hdd t sud t ack t sust Figure 7. Control Port Timing - IC Format 24 t rc t susp CS42438 SWITCHING SPECIFICATIONS - CONTROL PORT - SPI FORMAT (VLC = 1.8 V - 5.0 V, VLS = VD = 3.3 V, VA = 5.0 V; Inputs: Logic 0 = DGND, Logic 1 = VLC, CDOUT CL = 30 pF) Parameter Symbol Min Max Units CCLK Clock Frequency fsck 0 6.0 MHz RST Rising Edge to CS Falling tsrs 20 - ns CS Falling to CCLK Edge tcss 20 - ns CS High Time Between Transmissions tcsh 1.0 - s CCLK Low Time tscl 66 - ns CCLK High Time tsch 66 - ns CDIN to CCLK Rising Setup Time tdsu 40 - ns tdh 15 - ns CCLK Falling to CDOUT Stable tpd - 50 ns Rise Time of CDOUT tr1 - 25 ns Fall Time of CDOUT tf1 - 25 ns CCLK Rising to DATA Hold Time (Note 19) Rise Time of CCLK and CDIN (Note 20) tr2 - 100 ns Fall Time of CCLK and CDIN (Note 20) tf2 - 100 ns Notes: 19. Data must be held for sufficient time to bridge the transition time of CCLK. 20. For fsck <1 MHz. RST tsrs CS tcsh tcss tsch tscl tr2 CCLK tf2 tdsu tdh MSB CDIN tpd CDOUT MSB Figure 8. Control Port Timing - SPI Format 25 CS42438 DC ELECTRICAL CHARACTERISTICS (AGND = 0 V; all voltages with respect to ground.) Parameters Symbol Min Typ Max Units IA - 80 - mA IDT - 60.6 - mA - 600 850 mW PSRR - 60 40 - dB dB - 1.25 - mW Nominal Voltage Output Impedance DC current source/sink (Note 25) - 0.5*VA 23 - 10 V k FILT+ Nominal Voltage - VA - V Normal Operation (Note 21) Power Supply Current VA = 5.0 V VLS = VLC = VD = 3.3 V (Note 22) Power Dissipation VLS = VLC = VD = 3.3 V, VA = 5 V Power Supply Rejection Ratio (Note 23) 1 kHz 60 Hz Power-down Mode (Note 24) Power Dissipation VLS = VLC = VD = 3.3 V, VA = 5 V VQ Characteristics A Notes: 21. Normal operation is defined as RST = HI with a 997 Hz, 0 dBFS input to the DAC and AUX port, and a 1 kHz, -1 dB analog input to the ADC port sampled at the highest Fs for each speed mode. DAC outputs are open, unless otherwise specified. 22. IDT measured with no external loading on pin 2 (SDA). 23. Valid with the recommended capacitor values on FILT+ and VQ. Increasing the capacitance will also increase the PSRR. 24. Power Down Mode is defined as RST = LO with all clocks and data lines held static and no analog input. 25. Guaranteed by design. The DC current draw represents the allowed current draw from the VQ pin due to typical leakage through the electrolytic de-coupling capacitors. DIGITAL INTERFACE SPECIFICATIONS & CHARACTERISTICS Parameters (Note 26) Symbol VOH Min VLS-1.0 VLC-1.0 Typ - Max - Units V V Serial Port Control Port VOL - - 0.4 0.4 V V Serial Port Control Port VIH 0.7xVLS 0.7xVLC - - V V Serial Port Control Port VIL - - 0.2xVLS 0.2xVLC V V - - 10 10 A pF High-Level Output Voltage at Io=2 mA Serial Port Control Port Low-Level Output Voltage at Io=2 mA High-Level Input Voltage Low-Level Input Voltage Input Leakage Current Input Capacitance (Note 18) Iin Notes: 26. See "Digital I/O Pin Characteristics" on page 6 for serial and control port power rails. 27. Control Port signals in software mode include: SCL/CCLK, SDA/CDOUT, AD0/CS, AD1/CDIN, and RST. Control Port signals in hardware mode include: AIN5_MUX, AIN6_MUX, MFREQ, and RST. 26 CS42438 6 APPLICATIONS 6.1 Overview The CS42438 is a highly integrated mixed signal 24-bit audio CODEC comprised of 6 analog-to-digital converters (ADC), implemented using multi-bit Delta-Sigma techniques, and 8 digital-to-analog converters (DAC) also implemented using multi-bit Delta-Sigma techniques. Other functions integrated within the CODEC include independent digital volume controls for each DAC, digital de-emphasis filters for the DAC, digital volume control with gain on each ADC channel, ADC highpass filters, and an on-chip voltage reference. All serial data is transmitted through two independent serial ports: the DAC serial port and the ADC serial port. Each serial port can be configured independently to operate at different sample and clock rates, but both must run synchronous to each other. The serial audio interface ports allow up to 8 DAC channels and 8 ADC channels in a Time-Division Multiplexed (TDM) interface format. The CS42438 features an Auxiliary Port used to accommodate an additional two channels of PCM data on the SDOUT data line in the TDM digital interface format. See "AUX Port Digital Interface Formats" on page 34 for details. The CS42438 operates in one of three oversampling modes based on the input sample rate. Mode selection is determined automatically based on the MCLK frequency setting. Single-Speed mode (SSM) supports input sample rates up to 50 kHz and uses a 128x oversampling ratio. Double-Speed mode (DSM) supports input sample rates up to 100 kHz and uses an oversampling ratio of 64x. Quad-Speed mode (QSM) supports input sample rates up to 200 kHz and uses an oversampling ratio of 32x. NOTE: QSM is only available in software mode (see section 6.4 on page 33 for details). All functions can be configured through software via a serial control port operable in SPI mode or in IC mode. A hardware, stand-alone mode is also available, allowing configuration of the codec on a more limited basis. See Table 2 for the default configuration in Hardware Mode. Figure 1 on page 11 and Figure 2 on page 12 show the recommended connections for the CS42438 in software and hardware mode, respectively. See section 8 on page 42 for the default register settings and options in Software Mode. Hardware Mode Feature Summary Function Power Down ADC Power Down DAC Power Down Device MCLK Frequency Select Freeze Control AUX Serial Port Interface Format ADC1/ADC2 High Pass Filter Freeze ADC3 High Pass Filter Freeze DAC De-Emphasis ADC1/ADC2 Single-Ended Mode Default Configuration All ADC's are enabled All DAC's are enabled Device is powered up Selectable between 256Fs and 512Fs N/A Left-Justified High Pass Filter is always enabled High Pass Filter can be enabled/disabled No De-Emphasis applied Disabled Hardware Control "MFREQ" pin 3 "ADC3_HPF" pin 4 - Note see section 6.4 see section 6.2.3 - Table 2. Hardware Configurable Settings 27 CS42438 Hardware Mode Feature Summary Function ADC3 Single-Ended Mode Default Configuration Selectable between Differential and Single-Ended Selects between AIN5A and AIN5B when ADC3 in Single-Ended Mode Selects between AIN6A and AIN6B when ADC3 in Single-Ended Mode All DAC Volume = 0 dB, unmuted, not inverted All ADC Volume = 0 dB All DAC's Soft Ramp on Zero Cross All ADC's Soft Ramp on Zero Cross Enabled N/A AIN5 Multiplexer AIN6 Multiplexer DAC Volume Control/Mute/Invert ADC Volume Control DAC Soft Ramp/Zero Cross ADC Soft Ramp/Zero Cross DAC Auto-Mute Status Interrupt Hardware Control "ADC_SDOUT/ ADC3_SINGLE" pin 13 "AIN5_MUX" pin 1 Note see section 6.2.2 see section 6.2.2 "AIN6_MUX" pin 2 see section 6.2.2 - - - - - - - - Table 2. Hardware Configurable Settings 6.2 Analog Inputs 6.2.1 Line Level Inputs AINx+ and AINx- are the line level differential analog inputs internally biased to VQ, approximately VA/2. Figure 9 on page 29 shows the full-scale analog input levels. The CS42438 also accommodates single-ended signals on all inputs, AIN1-AIN6. See "ADC Input Filter" on page 56 for the recommended input filters. Hardware Mode AIN Volume Control and ADC Overflow status are not accessible in Hardware Mode. Singleended operation is only supported for ADC3. See section 6.2.2 below. Software Mode For single-ended operation on ADC1-ADC3 (AIN1 to AIN6), the ADCx_SINGLE bit in the register "Misc Control (address 05h)" on page 45 must be set appropriately (see Figure 20 on page 56 for required external components). The gain/attenuation of the signal can be adjusted for each AINx independently through the "AINX Volume Control (address 11h - 16h)" on page 49. The ADC output data is in 2's complement binary format. For inputs above positive full scale or below negative full scale, the ADC will output 7FFFFFH or 800000H, respectively and cause the ADC Overflow bit in the register "Status (address 19h) (Read Only)" on page 50 to be set to a `1'. 28 CS42438 5.0 V 3.9 V VA 2.5 V AINx+ 2.5 V AINx- 1.1 V 3.9 V 1.1 V Full-Scale Differential Input Level = (AINx+) - (AINx-) = 5.6 VPP = 1.98 VRMS Figure 9. Full-Scale Input 6.2.2 ADC3 Analog Input ADC3 accommodates differential as well as single-ended inputs. In Single-Ended mode, an internal MUX selects from up to 4 single-ended inputs. AIN5A ADC3 Single-Ended Input Filter AIN5_MUX AIN5B ADC3 SINGLE Single-Ended Input Filter 1 0 1 50 AIN5+/- Differential Input Filter 0 + AIN5 49 0 VQ - 1 AIN6_MUX 1 0 1 52 AIN6+/- Differential Input Filter 0 AIN6 51 0 VQ AIN6A AIN6B + - 1 Single-Ended Input Filter Single-Ended Input Filter Figure 10. ADC3 Input Topology Hardware Mode Single-Ended mode is selected using a pull-up on the ADC_SDOUT/ADC3_SINGLE pin during startup. Analog input selection is then made via the AINx_MUX pins. See Tables 3-4 below for ADC3 setup options. Refer to Figure 10 on page 29 for the internal ADC3 analog input topology. 29 CS42438 Configuration Setting ADC_SDOUT (pin 13) 47 k Pull-down 47 k Pull-up 47 k Pull-up AIN5_MUX (pin 1) X Low High AIN5 Input Selection Differential Input (pins 50 & 49) AIN5A Input (pin 50) AIN5B Input (pin 49) Table 3. AIN5 Analog Input Selection Configuration Setting ADC_SDOUT (pin 13) 47 k Pull-down 47 k Pull-up 47 k Pull-up AIN6_MUX (pin 2) X Low High AIN6 Input Selection Differential Input (pins 52 & 51) AIN5A Input (pin 52) AIN5B Input (pin 51) Table 4. AIN6 Analog Input Selection Software Mode Single-Ended mode is selected using the ADC3_SINGLE bit. Analog input selection is then made via the AINx_MUX bits. See register "Misc Control (address 05h)" on page 45 for all bit selections. Refer to Figure 10 on page 29 for the internal ADC3 analog input topology. 6.2.3 High Pass Filter and DC Offset Calibration The high pass filter continuously subtracts a measure of the DC offset from the output of the decimation filter. If the high pass filter is disabled during normal operation, the current value of the DC offset for the corresponding channel is frozen and this DC offset will continue to be subtracted from the conversion result. This feature makes it possible to perform a system DC offset calibration by: 1) Running the CS42438 with the high pass filter enabled until the filter settles. See the Digital Filter Characteristics for filter settling time. 2) Disabling the high pass filter and freezing the stored DC offset. Hardware Mode The high pass filters for ADC1 and ADC2 are permanently enabled in Hardware Mode. The high pass filter for ADC3 is enabled by driving the ADC3_HPF (pin 4) high. Software Mode The high pass filter for ADC1/ADC2 can be enabled and disabled. The high pass filter for ADC3 can be independently enabled and disabled. The high pass filters are controlled using the HPF_FREEZE bit in the register "Misc Control (address 05h)" on page 45. 30 CS42438 6.3 Analog Outputs 6.3.1 Initialization The initialization and Power-Down sequence flow chart is shown in Figure 11 on page 32. The CS42438 enters a Power-Down state upon initial power-up. The interpolation & decimation filters, Delta-Sigma modulators and control port registers are reset. The internal voltage reference, multi-bit digital-to-analog and analog-to-digital converters and switched-capacitor lowpass filters are powered down. The device will remain in the Power-Down state until the RST pin is brought high. The control port is accessible once RST is high and the desired register settings can be loaded per the interface descriptions in the "Control Port Description and Timing" on page 36. In hardware mode operation, the hardware mode pins must be setup before RST is brought high. All features will default to the hardware mode defaults as listed in Table 2. Once MCLK is valid, VQ will quickly charge to VA/2, and the internal voltage reference, FILT+, will begin powering up to normal operation. Power is applied to the D/A converters and switchedcapacitor filters, and the analog outputs are clamped to the quiescent voltage, VQ. Once LRCK is valid, MCLK occurrences are counted over one LRCK period to determine the MCLK/LRCK frequency ratio. After an approximate 2000 sample period delay, normal operation begins. 6.3.2 Line Level Outputs and Filtering The CS42438 contains on-chip buffer amplifiers capable of producing line level differential as well as single-ended outputs on AOUT1-AOUT8. These amplifiers are biased to a quiescent DC level of approximately VQ. The Delta-Sigma conversion process produces high frequency noise beyond the audio passband, most of which is removed by the on-chip analog filters. The remaining out-of-band noise can be attenuated using an off-chip low pass filter. See "DAC Output Filter" on page 59 for recommended output filter. The active filter configuration accounts for the normally differing AC loads on the AOUTx+ and AOUTx- differential output pins. Also shown is a passive filter configuration which minimizes costs and the number of components. Figure 12 shows the full-scale analog output levels. All outputs are internally biased to VQ, approximately VA/2. 31 CS42438 No Power 1. VQ = ? 2. Aout bias = ? 3. No audio signal generated. PDN bit = '1'b? Yes Power-Down 1. VQ discharge to 0 V. 2. Aout bias = Hi-Z. 3. No audio signal generated. 4. Control Port Registers retain settings. No Power-Down (Power Applied) 1. VQ = 0 V. 2. Aout = Hi-Z. 3. No audio signal generated. 4. Control Port Registers reset to default. Power-Up 1. VQ = VA/2. 2. Aout bias = VQ. Yes RST = Low? No Control Port Accessed No Sub-Clocks Applied 1. LRCK valid. 2. SCLK valid. 3. Audio samples processed. Control Port Access Detected? Yes No Hardware Mode H/W pins setup to desired settings. Valid MCLK/LRCK Ratio? Software Mode Registers setup to desired settings. Yes No No Valid MCLK Applied? Valid MCLK Applied? 2000 LRCK delay Yes Yes RST = Low ERROR: Power removed Normal Operation 1. VQ = VA/2. 2. Aout bias = VA/2. 3. Audio signal generated per register settings. PDN bit set to '1'b ERROR: MCLK/LRCK ratio change ERROR: MCLK removed Analog Output Mute 1. VQ = VA/2. 2. Aout bias = VA/2. 3. No audio signal generated. Analog Output Freeze 1. VQ = VA/2. 2. Aout bias = VA/2 + last audio sample. 3. No audio signal generated. Figure 11. Audio Output Initialization Flow Chart 32 CS42438 5.0 V 4.125 V VA AOUTx+ 2.5 V 0.875 V 4.125 V AOUTx- 2.5 V 0.875 V Full-Scale Differential Output Level = (AOUTx+) - (AOUTx-) = 6.5 VPP = 2.3 VRMS Figure 12. Full-Scale Output 6.3.3 Digital Volume Control Hardware Mode DAC Volume Control and Mute are not accessible in Hardware Mode. Software Mode Each DAC's output level is controlled via the Volume Control registers operating over the range of 0 to -127.5 dB attenuation with 0.5 dB resolution. See "AOUTX Volume Control (addresses 08h- 0Fh)" on page 48. Volume control changes are programmable to ramp in increments of 0.125 dB at the rate controlled by the SZC[1:0] bits in the Digital Volume Control register. See "Transition Control (address 06h)" on page 46. Each output can be independently muted via mute control bits in the register "DAC Channel Mute (address 07h)" on page 48. When enabled, each AOUTx_MUTE bit attenuates the corresponding DAC to its maximum value (-127.5 dB). When the AOUTx_MUTE bit is disabled, the corresponding DAC returns to the attenuation level set in the Volume Control register. The attenuation is ramped up and down at the rate specified by the SZC[1:0] bits. 6.4 System Clocking The CODEC serial audio interface ports operate as a slave and accept externally generated clocks. The CODEC requires external generation of the master clock (MCLK). The frequency of this clock must be an integer multiple of, and synchronous with, the system sample rate, Fs. Hardware Mode The allowable ratios include 256Fs and 512Fs in Single-Speed Mode and 256Fs in Double-Speed Mode. The frequency of MCLK must be specified using the MFREQ (pin 3). See Table 5 below for the required frequency range. MFREQ 0 1 Description 1.5360 MHz to 12.8000 MHz 2.0480 MHz to 25.6000 MHz Ratio (xFs) SSM DSM QSM 256 N/A N/A 512 256 N/A Table 5. MCLK Frequency Settings 33 CS42438 Software Mode The frequency range of MCLK must be specified using the MFREQ bits in register "MCLK Frequency (MFreq[2:0])" on page 44. 6.5 CODEC Digital Interface The ADC and DAC serial ports operate as a slave and support the TDM digital interface formats with varying bit depths from 16 to 32 as shown in Figure 13. Data is clocked out of the ADC on the falling edge of SCLK and clocked into the DAC on the rising edge. TDM is the only mode supported in hardware and software mode. 6.5.1 TDM Data is received most significant bit first on the first SCLK after an FS transition and is valid on the rising edge of SCLK. SCLK must operate at 256Fs. FS identifies the start of a new frame and is equal to the sample rate, Fs. FS is sampled as valid on the rising SCLK edge preceding the most significant bit of the first data sample and must be held valid for at least 1 SCLK period. Each time slot is 32 bits wide, with the valid data sample left justified within the time slot. Valid data lengths are 16, 18, 20, or 24. 256 clks Bit or Word Wide FS SCLK ADC_SDOUT/ DAC_SDIN LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB AIN1/AOUT1 AIN2/AOUT2 AIN3/AOUT3 AIN4/AOUT4 AIN5/AOUT5 AIN6/AOUT6 AUX1/AOUT7 AUX2/AOUT8 32 clks 32 clks 32 clks 32 clks 32 clks 32 clks 32 clks 32 clks Figure 13. TDM Serial Audio Format 6.5.2 I/O Channel Allocation Digital Input/Output DAC_SDIN ADC_SDOUT Interface Format TDM TDM Analog Output/Input Channel Allocation from/to Digital I/O AOUT 1,2,3,4,5,6,7,8 AIN 1,2,3,4,5,6; (2 additional channels from AUX_SDIN) Table 6. Serial Audio Interface Channel Allocations 6.6 AUX Port Digital Interface Formats These serial data lines are used when supporting the TDM Mode of operation with an external ADC or S/PDIF receiver attached. The AUX serial port operates only as a clock master. The AUX_SCLK will operate at 64xFs, where Fs is equal to the ADC sample rate (FS on the TDM interface). If the AUX_SDIN signal is not being used, it should be tied to AGND via a pull-down resistor. Hardware Mode The AUX port will only operate in the Left Justified digital interface format and supports bit depths ranging from 16 to 24 bits (see figure 15 on page 35 for timing relationship between AUX_LRCK and AUX_SCLK). Software Mode The AUX port will operate in either the Left Justified or IS digital interface format with bit depths ranging from 16 to 24 bits. Settings for the AUX port are made through the register "Interface Formats (address 04h)" on page 44. 34 CS42438 6.6.1 IS AUX_LRCK L eft C h a n n el R ig ht C h a n n el AUX_SCLK AUX_SDIN MSB M SB LS B MSB LS B AUX2 AUX1 Figure 14. AUX IS Format 6.6.2 Left Justified AUX_LRCK L e ft C h a n n el R ig ht C h a n n el AUX_SCLK AUX_SDIN MSB LS B M SB LS B MSB AUX2 AUX1 Figure 15. AUX Left Justified Format 35 CS42438 6.7 Control Port Description and Timing The control port is used to access the registers, in software mode, allowing the CS42438 to be configured for the desired operational modes and formats. The operation of the control port may be completely asynchronous with respect to the audio sample rates. However, to avoid potential interference problems, the control port pins should remain static if no operation is required. The control port has 2 modes: SPI and IC, with the CS42438 acting as a slave device. SPI mode is selected if there is a high to low transition on the AD0/CS pin, after the RST pin has been brought high. IC mode is selected by connecting the AD0/CS pin through a resistor to VLC or DGND, thereby permanently selecting the desired AD0 bit address state. 6.7.1 SPI Mode In SPI mode, CS is the CS42438 chip select signal, CCLK is the control port bit clock (input into the CS42438 from the microcontroller), CDIN is the input data line from the microcontroller, CDOUT is the output data line to the microcontroller. Data is clocked in on the rising edge of CCLK and out on the falling edge. Figure 16 shows the operation of the control port in SPI mode. To write to a register, bring CS low. The first seven bits on CDIN form the chip address and must be 1001111. The eighth bit is a read/write indicator (R/W), which should be low to write. The next eight bits form the Memory Address Pointer (MAP), which is set to the address of the register that is to be updated. The next eight bits are the data which will be placed into the register designated by the MAP. During writes, the CDOUT output stays in the Hi-Z state. It may be externally pulled high or low with a 47 k resistor, if desired. There is a MAP auto increment capability, enabled by the INCR bit in the MAP register. If INCR is a zero, the MAP will stay constant for successive read or writes. If INCR is set to a 1, the MAP will autoincrement after each byte is read or written, allowing block reads or writes of successive registers. To read a register, the MAP has to be set to the correct address by executing a partial write cycle which finishes (CS high) immediately after the MAP byte. The MAP auto increment bit (INCR) may be set or not, as desired. To begin a read, bring CS low, send out the chip address and set the read/write bit (R/W) high. The next falling edge of CCLK will clock out the MSB of the adCS CC LK C H IP ADDRESS C D IN 1001111 MAP MSB R/W C H IP ADDRESS DATA b y te 1 High Impedance CDOUT LSB 1001111 R/W b y te n MSB MAP = Memory Address Pointer, 8 bits, MSB first Figure 16. Control Port Timing in SPI Mode 36 LSB MSB LSB CS42438 dressed register (CDOUT will leave the high impedance state). If the MAP auto increment bit is set to 1, the data for successive registers will appear consecutively. 6.7.2 IC Mode In IC mode, SDA is a bidirectional data line. Data is clocked into and out of the part by the clock, SCL. There is no CS pin. Pins AD0 and AD1 form the two least significant bits of the chip address and should be connected through a resistor to VLC or DGND as desired. The state of the pins is sensed while the CS42438 is being reset. The signal timings for a read and write cycle are shown in Figure 17 and Figure 18. A Start condition is defined as a falling transition of SDA while the clock is high. A Stop condition is a rising transition while the clock is high. All other transitions of SDA occur while the clock is low. The first byte sent to the CS42438 after a Start condition consists of a 7 bit chip address field and a R/W bit (high for a read, low for a write). The upper 5 bits of the 7-bit address field are fixed at 10011. To communicate with a CS42438, the chip address field, which is the first byte sent to the CS42438, should match 10011 followed by the settings of the AD1 and AD0. The eighth bit of the address is the R/W bit. If the operation is a write, the next byte is the Memory Address Pointer (MAP) which selects the register to be read or written. If the operation is a read, the contents of the register pointed to by the MAP will be output. Setting the auto increment bit in MAP allows successive reads or writes of consecutive registers. Each byte is separated by an acknowledge bit. The ACK bit is output from the CS42438 after each input byte is read, and is input to the CS42438 from the microcontroller after each transmitted byte. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 24 25 26 27 28 SCL CHIP ADDRESS (WRITE) 1 SDA 0 0 1 MAP BYTE 1 AD1 AD0 0 INCR 6 5 4 3 DATA +1 DATA 2 1 0 ACK 7 6 ACK 1 0 7 6 1 DATA +n 0 7 6 1 0 ACK ACK STOP START Figure 17. Control Port Timing, IC Write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 SCL CHIP ADDRESS (WRITE) SDA 1 0 0 1 STOP MAP BYTE 1 AD1 AD0 0 INCR 6 ACK START 5 4 3 2 1 CHIP ADDRESS (READ) 1 0 0 0 ACK 1 DATA 1 AD1 AD0 1 7 ACK START DATA +1 0 7 ACK 0 DATA + n 7 0 NO ACK STOP Figure 18. Control Port Timing, IC Read Since the read operation can not set the MAP, an aborted write operation is used as a preamble. As shown in Figure 18, the write operation is aborted after the acknowledge for the MAP byte by sending a stop condition. The following pseudocode illustrates an aborted write operation followed by a read operation. Send start condition. Send 10011xx0 (chip address & write operation). Receive acknowledge bit. 37 CS42438 Send MAP byte, auto increment off. Receive acknowledge bit. Send stop condition, aborting write. Send start condition. Send 10011xx1(chip address & read operation). Receive acknowledge bit. Receive byte, contents of selected register. Send acknowledge bit. Send stop condition. Setting the auto-increment bit in the MAP allows successive reads or writes of consecutive registers. Each byte is separated by an acknowledge bit. 6.8 Recommended Power-up Sequence 6.8.1 Hardware Mode 1) Hold RST low until the power supply and hardware control pins are stable. In this state, the control port is reset to its default settings and VQ will remain low. 2) Bring RST high. The device will initially be in a low power state with VQ low. 3) Start MCLK to the appropriate frequency, as discussed in section 6.4 on page 33. 4) The device will initiate the hardware mode power up sequence. All features will default to the hardware mode defaults as listed in Table 2 on page 27 according to the hardware mode control pins. VQ will quick-charge to approximately VA/2 and the analog output bias will clamp to VQ. 5) Apply LRCK, SCLK and SDIN. Following approximately 2000 sample periods, the device is initialized and ready for normal operation. NOTE: During the H/W mode power up sequence, there must be no transitions on any of the hardware control pins. 6.8.2 Software Mode 1) Hold RST low until the power supply is stable. In this state, the control port is reset to its default settings and VQ will remain low. 2) Bring RST high. The device will initially be in a low power state with VQ low. All features will default as described in the "Register Quick Reference" on page 40. 3) Perform a write operation to the Power Control register ("Power Control (address 02h)" on page 43) to set bit 0 to a `1'b. This will place the device in a power down state. 4) Load the desired register settings while keeping the PDN bit set to `1'b. 5) Start MCLK to the appropriate frequency, as discussed in section 6.4 on page 33. The device will initiate the software mode power up sequence. 6) Set the PDN bit in the power control register to `0'b. 7) Apply LRCK, SCLK and SDIN. Following approximately 2000 sample periods, the device is initialized and ready for normal operation. 6.9 Reset and Power-up It is recommended that reset be activated if the analog or digital supplies drop below the recommended operating condition to prevent power glitch related issues. 38 CS42438 The Delta-Sigma modulators settle in a matter of microseconds after the analog section is powered, either through the application of power or by setting the RST pin high. However, the voltage reference will take much longer to reach a final value due to the presence of external capacitance on the FILT+ pin. A time delay of approximately 400 ms is required after applying power to the device or after exiting a reset state. During this voltage reference ramp delay, all serial ports and DAC outputs will be automatically muted. 6.10 Power Supply, Grounding, and PCB layout As with any high resolution converter, the CS42438 requires careful attention to power supply and grounding arrangements if its potential performance is to be realized. Figures 1 to 2 show the recommended power arrangements, with VA connected to clean supplies. VD, which powers the digital circuitry, may be run from the system logic supply. Extensive use of power and ground planes, ground plane fill in unused areas and surface mount decoupling capacitors are recommended. Decoupling capacitors should be as near to the pins of the CS42438 as possible. The low value ceramic capacitor should be the nearest to the pin and should be mounted on the same side of the board as the CS42438 to minimize inductance effects. All signals, especially clocks, should be kept away from the FILT+, VQ pins in order to avoid unwanted coupling into the modulators. The FILT+ and VQ decoupling capacitors, particularly the 0.1 F, must be positioned to minimize the electrical path from FILT+ and AGND. The CDB42438 evaluation board demonstrates the optimum layout and power supply arrangements. For optimal heat dissipation from the package, it is recommended that the area directly under the part be filled with copper and tied to the ground plane. The use of vias connecting the topside ground to the backside ground is also recommended. 39 CS42438 7 REGISTER QUICK REFERENCE Software Mode register defaults are as shown. Addr Function 01h ID p 42 02h Power Control p 43 03h default Functional Mode p 44 04h default default Misc Control p 44 default 7 6 5 4 3 2 1 0 Chip_ID3 Chip_ID2 Chip_ID1 Chip_ID0 Rev_ID3 Rev_ID2 Rev_ID1 Rev_ID0 1 0 1 1 0 0 0 1 PDN_ADC3 PDN_ADC2 PDN_ADC1 PDN_DAC4 PDN_DAC3 0 0 0 0 0 0 0 0 Reserved Reserved Reserved Reserved MFreq2 MFreq1 MFreq0 Reserved 1 1 1 1 0 0 0 0 FREEZE AUX_DIF Reserved Reserved Reserved Reserved Reserved Reserved 0 0 1 1 0 1 1 0 DAC_DEM ADC1 SINGLE ADC2 SINGLE ADC3 SINGLE AIN5_MUX AIN6_MUX PDN_DAC2 PDN_DAC1 PDN 05h ADC Control ADC1-2_HPF FREEZE (w/DAC_DEM) p 45 default 0 ADC3_HPF FREEZE 0 0 0 0 0 0 0 06h Transition Control p 46 default DAC_SZC1 DAC_SZC0 AMUTE MUTE ADC_SP ADC_SNG VOL ADC_SZC1 ADC_SZC0 07h Channel Mute 0 0 0 0 0 0 0 0 AOUT8 MUTE AOUT7 MUTE AOUT6 MUTE AOUT5 MUTE AOUT4 MUTE AOUT3 MUTE AOUT2 MUTE AOUT1 MUTE 0 0 0 0 0 0 0 0 08h Vol. Control AOUT1 p 48 default AOUT1 VOL7 AOUT1 VOL6 AOUT1 VOL5 AOUT1 VOL4 AOUT1 VOL3 AOUT1 VOL2 AOUT1 VOL1 AOUT1 VOL0 0 0 0 0 0 0 0 0 09h Vol. Control AOUT2 p 48 default AOUT2 VOL7 AOUT2 VOL6 AOUT2 VOL5 AOUT2 VOL4 AOUT2 VOL3 AOUT2 VOL2 AOUT2 VOL1 AOUT2 VOL0 0 0 0 0 0 0 0 0 0Ah Vol. Control AOUT3 p 48 default AOUT3 VOL7 AOUT3 VOL6 AOUT3 VOL5 AOUT3 VOL4 AOUT3 VOL3 AOUT3 VOL2 AOUT3 VOL1 AOUT3 VOL0 0 0 0 0 0 0 0 0 0Bh Vol. Control AOUT4 p 48 default AOUT4 VOL7 AOUT4 VOL6 AOUT4 VOL5 AOUT4 VOL4 AOUT4 VOL3 AOUT4 VOL2 AOUT4 VOL1 AOUT4 VOL0 0 0 0 0 0 0 0 0 0Ch Vol. Control AOUT5 p 48 default AOUT5 VOL7 AOUT5 VOL6 AOUT5 VOL5 AOUT5 VOL4 AOUT5 VOL3 AOUT5 VOL2 AOUT5 VOL1 AOUT5 VOL0 0 0 0 0 0 0 0 0 0Dh Vol. Control AOUT6 p 48 default AOUT6 VOL7 AOUT6 VOL6 AOUT6 VOL5 AOUT6 VOL4 AOUT6 VOL3 AOUT6 VOL2 AOUT6 VOL1 AOUT6 VOL0 0 0 0 0 0 0 0 0 0Eh Vol. Control AOUT7 p 48 default AOUT7 VOL7 AOUT7 VOL6 AOUT7 VOL5 AOUT7 VOL4 AOUT7 VOL3 AOUT7 VOL2 AOUT7 VOL1 AOUT7 VOL0 0 0 0 0 0 0 0 0 0Fh Vol. Control AOUT8 p 48 default AOUT8 VOL7 AOUT8 VOL6 AOUT8 VOL5 AOUT8 VOL4 AOUT8 VOL3 AOUT8 VOL2 AOUT8 VOL1 AOUT8 VOL0 0 0 0 0 0 10h DAC Chan- INV_AOUT8 nel Invert p 49 default 0 p 48 40 default DAC_SNG VOL 0 0 INV_AOUT7 0 INV_AOUT6 INV_AOUT5 INV_AOUT4 INV_AOUT3 INV_AOUT2 0 0 0 0 0 0 INV_AOUT1 0 CS42438 Addr Function 7 6 5 4 3 2 1 0 11h Vol. Control AIN1 p 48 default AIN1 VOL7 AIN1 VOL6 AIN1 VOL5 AIN1 VOL4 AIN1 VOL3 AIN1 VOL2 AIN1 VOL1 AIN1 VOL0 0 0 0 0 0 0 0 0 12h Vol. Control AIN2 p 49 default AIN2 VOL7 AIN2 VOL6 AIN2 VOL5 AIN2 VOL4 AIN2 VOL3 AIN2 VOL2 AIN2 VOL1 AIN2 VOL0 0 0 0 0 0 0 0 0 13h Vol. Control AIN3 p 48 default AIN3 VOL7 AIN3 VOL6 AIN3 VOL5 AIN3 VOL4 AIN3 VOL3 AIN3 VOL2 AIN3 VOL1 AIN3 VOL0 0 0 0 0 0 0 0 0 14h Vol. Control AIN4 p 49 default AIN4 VOL7 AIN4 VOL6 AIN4 VOL5 AIN4 VOL4 AIN4 VOL3 AIN4 VOL2 AIN4 VOL1 AIN4 VOL0 0 0 0 0 0 0 0 0 15h Vol. Control AIN5 p 48 default AIN5 VOL7 AIN5 VOL6 AIN5 VOL5 AIN5 VOL4 AIN5 VOL3 AIN5 VOL2 AIN5 VOL1 AIN5 VOL0 0 0 0 0 0 0 0 0 16h Vol. Control AIN6 p 49 default AIN6 VOL7 AIN6 VOL6 AIN6 VOL5 AIN6 VOL4 AIN6 VOL3 AIN6 VOL2 AIN6 VOL1 AIN6 VOL0 0 0 0 0 0 0 0 0 17h ADC Channel Invert p 49 default Reserved Reserved INV_A6 INV_A5 INV_A4 INV_A3 INV_A2 INV_A1 0 0 0 0 0 0 0 0 18h Status Control p 50 default Reserved Reserved Reserved Reserved Reserved Reserved MODE1 MODE0 0 0 0 0 0 0 0 0 19h Status Reserved Reserved Reserved Reserved CLK Error ADC3 OVFL ADC2 OVFL ADC1 OVFL 1Ah Status Mask p 50 p 51 default default 0 0 0 X X X X X Reserved Reserved Reserved Reserved CLK Error_M ADC3 OVFL_M ADC2 OVFL_M ADC1 OVFL_M 0 0 0 0 0 0 0 0 41 CS42438 8 REGISTER DESCRIPTION All registers are read/write except for the I.D. and Revision Register and Interrupt Status Register which are read only. See the following bit definition tables for bit assignment information. The default state of each bit after a power-up sequence or reset is listed in each bit description. 8.1 MEMORY ADDRESS POINTER (MAP) Not a register 7 6 5 4 3 2 1 0 INCR MAP6 MAP5 MAP4 MAP3 MAP2 MAP1 MAP0 8.1.1 INCREMENT(INCR) Default = 1 Function: Memory address pointer auto increment control 0 - MAP is not incremented automatically. 1 - Internal MAP is automatically incremented after each read or write. 8.1.2 MEMORY ADDRESS POINTER (MAP[6:0]) Default = 0000001 Function: Memory address pointer (MAP). Sets the register address that will be read or written by the control port. 8.2 CHIP I.D. AND REVISION REGISTER (ADDRESS 01H) (READ ONLY) 7 Chip_ID3 6 Chip_ID2 8.2.1 5 Chip_ID1 4 Chip_ID0 3 Rev_ID3 CHIP I.D. (CHIP_ID[3:0]) Default = 0000 Function: I.D. code for the CS42438. Permanently set to 0000. 8.2.2 CHIP REVISION (REV_ID[3:0]) Default = 0001 Function: CS42438 revision level. Revision A is coded as 0001. 42 2 Rev_ID2 1 Rev_ID1 0 Rev_ID0 CS42438 8.3 POWER CONTROL (ADDRESS 02H) 7 6 5 4 3 2 1 0 PDN_ADC3 PDN_ADC2 PDN_ADC1 PDN_DAC4 PDN_DAC3 PDN_DAC2 PDN_DAC1 PDN 8.3.1 POWER DOWN ADC PAIRS(PDN_ADCX) Default = 0 0 - Disable 1 - Enable Function: When enabled, the respective ADC channel pair (ADC1 - AIN1/AIN2; ADC2 - AIN3/AIN4; and ADC3 - AIN5/AIN6) will remain in a reset state. 8.3.2 POWER DOWN DAC PAIRS (PDN_DACX) Default = 0 0 - Disable 1 - Enable Function: When enabled, the respective DAC channel pair (DAC1 - AOUT1/AOUT2; DAC2 - AOUT3/AOUT4; DAC3 - AOUT5/AOUT6; and DAC4 - AOUT7/AOUT8) will remain in a reset state. It is advised that any change of these bits be made while the DACs are muted or the power down bit (PDN) is enabled to eliminate the possibility of audible artifacts. 8.3.3 POWER DOWN (PDN) Default = 0 0 - Disable 1 - Enable Function: The entire device will enter a low-power state when this function is enabled. The contents of the control registers are retained in this mode. 43 CS42438 8.4 FUNCTIONAL MODE (ADDRESS 03H) 7 6 5 4 3 2 1 0 Reserved Reserved Reserved Reserved MFreq2 MFreq1 MFreq0 Reserved 8.4.1 MCLK FREQUENCY (MFREQ[2:0]) Default = 000 Function: Sets the appropriate frequency for the supplied MCLK. For TDM operation, SCLK must equal 256Fs. MCLK can be equal to or greater than SCLK. MFreq2 MFreq1 MFreq0 0 0 0 0 1 0 0 1 1 X 0 1 0 1 X Description 1.0290 MHz to 12.8000 MHz 1.5360 MHz to 19.2000 MHz 2.0480 MHz to 25.6000 MHz 3.0720 MHz to 38.4000 MHz 4.0960 MHz to 51.2000 MHz SSM 256 384 512 768 1024 Ratio (xFs) DSM QSM N/A N/A N/A N/A 256 N/A 384 N/A 512 256 Table 7. MCLK Frequency Settings 8.5 INTERFACE FORMATS (ADDRESS 04H) 7 6 5 4 3 2 1 0 FREEZE AUX_DIF Reserved Reserved Reserved Reserved Reserved Reserved 8.5.1 FREEZE CONTROLS (FREEZE) Default = 0 Function: This function will freeze the previous settings of, and allow modifications to be made to the channel mutes, the DAC and ADC Volume Control/Channel Invert registers without the changes taking effect until the FREEZE is disabled. To have multiple changes in these control port registers take effect simultaneously, enable the FREEZE bit, make all register changes, then disable the FREEZE bit. 8.5.2 AUXILIARY DIGITAL INTERFACE FORMAT (AUX_DIF) Default = 0 0 - Left Justified 1 - IS Function: This bit selects the digital interface format used for the AUX Serial Port. The required relationship between the Left/Right clock, serial clock and serial data is defined by the Digital Interface Format and the options are detailed in Figures 14-15. 44 CS42438 8.6 MISC CONTROL (ADDRESS 05H) 7 6 5 4 3 2 1 0 ADC1-2_HPF FREEZE ADC3_HPF FREEZE DAC_DEM ADC1 SINGLE ADC2 SINGLE ADC3 SINGLE AIN5_MUX AIN6_MUX 8.6.1 ADC1-2 HIGH PASS FILTER FREEZE (ADC1-2_HPF FREEZE) Default = 0 Function: When this bit is set, the internal high-pass filter will be disabled for ADC1 and ADC2.The current DC offset value will be frozen and continue to be subtracted from the conversion result. See "ADC Digital Filter Characteristics" on page 16. 8.6.2 ADC3 HIGH PASS FILTER FREEZE (ADC3_HPF FREEZE) Default = 0 Function: When this bit is set, the internal high-pass filter will be disabled for ADC3.The current DC offset value will be frozen and continue to be subtracted from the conversion result. See "ADC Digital Filter Characteristics" on page 16. 8.6.3 DAC DE-EMPHASIS CONTROL (DAC_DEM) Default = 0 0 - No De-Emphasis 1 - De-Emphasis Enabled (Auto-Detect Fs) Function: Enables the digital filter to maintain the standard 15s/50s digital de-emphasis filter response at the auto-detected sample rate of either 32, 44.1, or 48 kHz. De-emphasis will not be enabled, regardless of this register setting, at any other sample rate. 8.6.4 ADC1 SINGLE-ENDED MODE (ADC1 SINGLE) Default = 0 0 - Disabled; Differential input to ADC1 1 - Enabled; Single-Ended input to ADC1 Function: When enabled, this bit allows the user to apply a single-ended input to the positive terminal of ADC1. +6 dB digital gain is automatically applied to the serial audio data of ADC1. The negative leg must be driven to the common mode of the ADC. See Figure 20 on page 56 for a graphical description. 8.6.5 ADC2 SINGLE-ENDED MODE (ADC2 SINGLE) Default = 0 0 - Disabled; Differential input to ADC2 1 - Enabled; Single-Ended input to ADC2 45 CS42438 Function: When enabled, this bit allows the user to apply a single-ended input to the positive terminal of ADC2. +6 dB digital gain is automatically applied to the serial audio data of ADC2. The negative leg must be driven to the common mode of the ADC. See Figure 20 on page 56 for a graphical description. 8.6.6 ADC3 SINGLE-ENDED MODE (ADC3 SINGLE) Default = 0 0 - Disabled; Differential input to ADC 1 - Enabled; Single-Ended input to ADC Function: When disabled, this bit removes the 4:2 multiplexer from the signal path of ADC3 allowing a differential input. When enabled, this bit allows the user to choose between 4 single-ended inputs to ADC3, using the AIN5_MUX and AIN6_MUX bits. See Figure 10 on page 29 and Figure 20 on page 56 for graphical descriptions. 8.6.7 ANALOG INPUT CH. 5 MULTIPLEXER (AIN5_MUX) Default = 0 0 - Single-Ended Input AIN5A 1 - Single-Ended Input AIN5B Function: ADC3 can accept single-ended input signals when the ADC3 SINGLE bit is enabled. The AIN5_MUX bit selects between two input channels (AIN5A or AIN5B) to be sent to ADC3 in single-ended mode. This bit is ignored when the ADC3_SINGLE bit is disabled. See Figure 10 on page 29 for a graphical description. 8.6.8 ANALOG INPUT CH. 6 MULTIPLEXER (AIN6_MUX) Default = 0 0 - Single-Ended Input AIN6A 1 - Single-Ended Input AIN6B Function: ADC3 can accept a single-ended input signal when the ADC3 SINGLE bit is enabled. The AIN6_MUX bit selects between two input channels (AIN6A or AIN6B) to be sent to ADC3 in single-ended mode. This bit is ignored when the ADC3_SINGLE bit is disabled. See Figure 10 on page 29 for a graphical description. 8.7 TRANSITION CONTROL (ADDRESS 06H) 7 6 5 4 DAC_SNGVOL DAC_SZC1 DAC_SZC0 AMUTE 8.7.1 2 SINGLE VOLUME CONTROL (DAC_SNGVOL, ADC_SNGVOL) Default = 0 46 3 MUTE ADC_SP ADC_SNGVOL 1 0 ADC_SZC1 ADC_SZC0 CS42438 Function: The individual channel volume levels are independently controlled by their respective Volume Control registers when this function is disabled. When enabled, the volume on all channels is determined by the AOUT1 and AIN1 Volume Control register and the other Volume Control registers are ignored. 8.7.2 SOFT RAMP AND ZERO CROSS CONTROL (ADC_SZC[1:0], DAC_SZC[1:0]) Default = 00 00 - Immediate Change 01 - Zero Cross 10 - Soft Ramp 11 - Soft Ramp on Zero Crossings Function: Immediate Change When Immediate Change is selected all volume level changes will take effect immediately in one step. Zero Cross Zero Cross Enable dictates that signal level changes, either by gain changes, attenuation changes or muting, will occur on a signal zero crossing to minimize audible artifacts. The requested level change will occur after a timeout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample rate) if the signal does not encounter a zero crossing. The zero cross function is independently monitored and implemented for each channel. Soft Ramp Soft Ramp allows level changes, either by gain changes, attenuation changes or muting, to be implemented by incrementally ramping, in 1/8 dB steps, from the current level to the new level at a rate of 1 dB per 8 left/right clock periods. Soft Ramp on Zero Crossing Soft Ramp and Zero Cross Enable dictates that signal level changes, either by gain changes, attenuation changes or muting, will occur in 1/8 dB steps and be implemented on a signal zero crossing. The 1/8 dB level change will occur after a timeout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample rate) if the signal does not encounter a zero crossing. The zero cross function is independently monitored and implemented for each channel. 8.7.3 AUTO-MUTE (AMUTE) Default = 1 0 - Disabled 1 - Enabled Function: The Digital-to-Analog converters of the CS42438 will mute the output following the reception of 8192 consecutive audio samples of static 0 or -1. A single sample of non-static data will release the mute. Detection and muting is done independently for each channel. The quiescent voltage on the output will be retained during the mute period. The muting function is affected, similar to volume control changes, by the Soft and Zero Cross bits (SZC[1:0]). 47 CS42438 8.7.4 MUTE ADC SERIAL PORT (MUTE ADC_SP) Default = 0 0 - Disabled 1 - Enabled Function: When enabled, the ADC Serial Port will be muted. 8.8 DAC CHANNEL MUTE (ADDRESS 07H) 7 6 5 4 3 2 1 0 AOUT8_MUTE AOUT7_MUTE AOUT6_MUTE AOUT5_MUTE AOUT4_MUTE AOUT3_MUTE AOUT2_MUTE AOUT1_MUTE 8.8.1 INDEPENDENT CHANNEL MUTE (AOUTX_MUTE) Default = 0 0 - Disabled 1 - Enabled Function: The respective Digital-to-Analog converter outputs of the CS42438 will mute when enabled. The quiescent voltage on the outputs will be retained. The muting function is affected by the DAC Soft and Zero Cross bits (DAC_SZC[1:0]). 8.9 AOUTX VOLUME CONTROL (ADDRESSES 08H- 0FH) 7 6 5 4 3 2 1 0 AOUTx_VOL7 AOUTx_VOL6 AOUTx_VOL5 AOUTx_VOL4 AOUTx_VOL3 AOUTx_VOL2 AOUTx_VOL1 AOUTx_VOL0 8.9.1 VOLUME CONTROL (AOUTX_VOL[7:0]) Default = 00h Function: The AOUTx Volume Control registers allow independent setting of the signal levels in 0.5 dB increments from 0 dB to -127.5 dB. Volume settings are decoded as shown in Table 8. The volume changes are implemented as dictated by the Soft and Zero Cross bits (DAC_SZC[1:0]). All volume settings less than -127.5 dB are equivalent to enabling the AOUTx_MUTE bit for the given channel. Binary Code Volume Setting 00000000 00101000 01010000 01111000 10110100 0 dB -20 dB -40 dB -60 dB -90 dB Table 8. Example AOUT Volume Settings 48 CS42438 8.10 DAC CHANNEL INVERT (ADDRESS 10H) 7 6 5 4 3 2 1 0 INV_AOUT8 INV_AOUT7 INV_AOUT6 INV_AOUT5 INV_AOUT4 INV_AOUT3 INV_AOUT2 INV_AOUT1 8.10.1 INVERT SIGNAL POLARITY (INV_AOUTX) Default = 0 0 - Disabled 1 - Enabled Function: When enabled, these bits will invert the signal polarity of their respective channels. 8.11 AINX VOLUME CONTROL (ADDRESS 11H - 16H) 7 6 5 4 3 2 1 0 AINx_VOL7 AINx_VOL6 AINx_VOL5 AINx_VOL4 AINx_VOL3 AINx_VOL2 AINx_VOL1 AINx_VOL0 8.11.1 AINX VOLUME CONTROL (AINX_VOL[7:0]) Default = 00h Function: The level of AIN1 - AIN6 can be adjusted in 0.5 dB increments as dictated by the ADC Soft and Zero Cross bits (ADC_SZC[1:0]) from +12 to -115.5 dB. Levels are decoded in two's complement, as shown in Table 9. Binary Code Volume Setting 0001 1000 0001 0100 0000 1010 0000 0000 1111 1111 1111 1110 0001 1010 +12 dB +10 dB +5 dB 0 dB -0.5 dB -1 dB -115 dB Table 9. Example AIN Volume Settings 8.12 ADC CHANNEL INVERT (ADDRESS 17H) 7 6 5 4 3 2 1 0 Reserved Reserved INV_AIN6 INV_AIN5 INV_AIN4 INV_AIN3 INV_AIN2 INV_AIN1 8.12.1 INVERT SIGNAL POLARITY (INV_AINX) Default = 0 0 - Disabled 1 - Enabled 49 CS42438 Function: When enabled, these bits will invert the signal polarity of their respective channels. 8.13 STATUS CONTROL (ADDRESS 18H) 7 6 5 4 3 2 1 0 Reserved Reserved Reserved Reserved Reserved Reserved MODE1 MODE0 8.13.1 ERROR MODE (MODE[1:0]) Default = 00 00 - Rising edge active 01 - Falling edge active 10 - Level active 11 - Reserved Function: There are three ways to set the Status flags active in accordance with the error condition. In the Rising edge active mode, the Status flags become active on the arrival of the error condition. In the Falling edge active mode, the Status flags become active on the removal of the error condition. In Level active mode, the Status flags become active during the error condition. 8.14 STATUS (ADDRESS 19H) (READ ONLY) 7 6 5 4 3 2 1 0 Reserved Reserved Reserved Reserved CLK Error ADC3_OVFL ADC2_OVFL ADC1_OVFL For all bits in this register, a "1" means the associated error condition has occurred at least once since the register was last read. A"0" means the associated error condition has NOT occurred since the last reading of the register. Reading the register resets all bits to 0. Status bits that are masked off in the associated mask register will always be "0" in this register. 8.14.1 CLOCK ERROR (ADC_CLK ERROR) Default = x Function: Indicates an invalid MCLK to FS ratio. See "System Clocking" on page 33 for valid clock ratios. 8.14.2 ADC OVERFLOW (ADCX_OVFL) Default = x Function: Indicates that there is an over-range condition anywhere in the CS42438 ADC signal path of each of the associated ADC's. 50 CS42438 8.15 STATUS MASK (ADDRESS 1AH) 7 6 5 4 3 Reserved Reserved Reserved Reserved CLK Error_M 2 1 0 ADC3_OVFL_M ADC2_OVFL_M ADC1_OVFL_M Default = 0000 Function: The bits of this register serve as a mask for the error sources found in the register "Status (address 19h) (Read Only)" on page 50. If a mask bit is set to 1, the error is unmasked, meaning that its occurrence will affect the status register. If a mask bit is set to 0, the error is masked, meaning that its occurrence will not affect status register. The bit positions align with the corresponding bits in the Status register. 51 CS42438 9 PARAMETER DEFINITIONS Dynamic Range The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. Dynamic Range is a signal-to-noise ratio measurement over the specified band width made with a -60 dBFS signal. 60 dB is added to resulting measurement to refer the measurement to full-scale. This technique ensures that the distortion components are below the noise level and do not affect the measurement. This measurement technique has been accepted by the Audio Engineering Society, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307. Expressed in decibels. Total Harmonic Distortion + Noise The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified band width (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels. Measured at -1 and -20 dBFS as suggested in AES17-1991 Annex A. Frequency Response A measure of the amplitude response variation from 10 Hz to 20 kHz relative to the amplitude response at 1 kHz. Units in decibels. Interchannel Isolation A measure of crosstalk between the left and right channel pairs. Measured for each channel at the converter's output with no signal to the input under test and a full-scale signal applied to the other channel. Units in decibels. Interchannel Gain Mismatch The gain difference between left and right channel pairs. Units in decibels. Gain Error The deviation from the nominal full-scale analog output for a full-scale digital input. Gain Drift The change in gain value with temperature. Units in ppm/C. Offset Error The deviation of the mid-scale transition (111...111 to 000...000) from the ideal. Units in mV. 52 CS42438 10 REFERENCES 1) Cirrus Logic, Audio Quality Measurement Specification, Version 1.0, 1997. http://www.cirrus.com/products/papers/meas/meas.html 2) Cirrus Logic, AN18: Layout and Design Rules for Data Converters and Other Mixed Signal Devices, Version 6.0, February 1998. 3) Cirrus Logic, Techniques to Measure and Maximize the Performance of a 120 dB, 96 kHz A/D Converter Integrated Circuit, by Steven Harris, Steven Green and Ka Leung. Presented at the 103rd Convention of the Audio Engineering Society, September 1997. 4) Cirrus Logic, A Stereo 16-bit Delta-Sigma A/D Converter for Digital Audio, by D.R. Welland, B.P. Del Signore, E.J. Swanson, T. Tanaka, K. Hamashita, S. Hara, K. Takasuka. Paper presented at the 85th Convention of the Audio Engineering Society, November 1988. 5) Cirrus Logic, The Effects of Sampling Clock Jitter on Nyquist Sampling Analog-to-Digital Converters, and on Oversampling Delta Sigma ADC's, by Steven Harris. Paper presented at the 87th Convention of the Audio Engineering Society, October 1989. 6) Cirrus Logic, An 18-Bit Dual-Channel Oversampling Delta-Sigma A/D Converter, with 19-Bit Mono Application Example, by Clif Sanchez. Paper presented at the 87th Convention of the Audio Engineering Society, October 1989. 7) Cirrus Logic, How to Achieve Optimum Performance from Delta-Sigma A/D and D/A Converters,by Steven Harris. Presented at the 93rd Convention of the Audio Engineering Society, October 1992. 8) Cirrus Logic, A Fifth-Order Delta-Sigma Modulator with 110 dB Audio Dynamic Range, by I. Fujimori, K. Hamashita and E.J. Swanson. Paper presented at the 93rd Convention of the Audio Engineering Society, October 1992. 9) Philips Semiconductor, The IC-Bus Specification: Version 2.1, January 2000. http://www.semiconductors.philips.com 53 CS42438 11 PACKAGE DIMENSIONS 52L MQFP PACKAGE DRAWING E E1 D D1 1 e B A A1 L DIM A A1 B D D1 E E1 e* L MIN --0.000 0.009 ----------0.029 0.00 * Nominal pin pitch is 0.65 mm Controlling dimension is mm. JEDEC Designation: MS022 54 INCHES NOM ------0.519 0.394 0.519 0.394 0.026 0.035 4 MAX 0.096 0.010 0.016 ----------0.041 7.00 MIN --0.00 0.22 ----------0.73 0.00 MILLIMETERS NOM ------13.20 BSC 10.00 BSC 13.20 BSC 10.00 BSC 0.65 BSC 0.88 4 MAX 2.45 0.25 0.40 ----------1.03 7.00 CS42438 THERMAL CHARACTERISTICS Parameter Junction to Ambient Thermal Impedance 2 Layer Board 4 Layer Board Symbol Min Typ Max Units JA JA - 47 38 - C/Watt C/Watt 55 CS42438 12 APPENDIX A: EXTERNAL FILTERS 12.1 ADC Input Filter The analog modulator samples the input at 6.144 MHz (internal MCLK=12.288 MHz). The digital filter will reject signals within the stopband of the filter. However, there is no rejection for input signals which are multiples of the digital passband frequency (n x 6.144 MHz), where n=0,1,2,... Refer to Figures 19 and 20 for a recommended analog input filter that will attenuate any noise energy at 6.144 MHz, in addition to providing the optimum source impedance for the modulators. Refer to Figures 21 and 22 for low cost, low component count passive input filters. The use of capacitors which have a large voltage coefficient (such as general purpose ceramics) must be avoided since these can degrade signal linearity. 634 470 pF C0G ADC1-3 91 - 4.7 F AINx+ + 100 k 634 634 VA 2700 pF C0G 470 pF C0G 10 k 100 k 91 - AINx- + 0.1 F 100 k 100 F 332 Figure 19. Single to Differential Active Input Filter 634 VA 100 k 470 pF - 4.7 F C0G ADC1-2 91 AIN1+,2+,3+,4+ + 100 k 2700 pF C0G 100 k VA 100 k 4.7 F AIN1-,2-,3-,4100 k 634 VA 100 k 470 pF - 4.7 F C0G ADC3 91 AIN5A,6A + 100 k 2700 pF C0G 100 k 634 VA 100 k 470 pF - 4.7 F C0G 91 AIN5B,6B + 100 k 100 k 2700 pF C0G Figure 20. Single-Ended Active Input Filter 56 CS42438 12.1.1 Passive Input Filter The passive filter implementation shown in Figure 21 will attenuate any noise energy at 6.144 MHz but will not provide optimum source impedance for the ADC modulators. Full analog performance will therefore not be realized using a passive filter. Figure 21 illustrates the unity gain, passive input filter solution. In this topology the distortion performance is affected, but the dynamic range performance is not limited. 150 ADC1-2 10 F AIN1+,2+,3+,4+ 100 k 2700 pF C0G VA 100 k AIN1-,2-,3-,44.7 F 150 100 k ADC3 10 F AIN5A,6A 100 k 2700 pF C0G 150 10 F AIN5B,6B 100 k 2700 pF C0G Figure 21. Passive Input Filter 12.1.2 Passive Input Filter w/Attenuation Some applications may require signal attenuation prior to the ADC. The full-scale input voltage will scale with the analog power supply voltage. For VA = 5.0 V, the full-scale input voltage is approximately 2.8 Vpp, or 1 Vrms (most consumer audio line level outputs range from 1.5 to 2 Vrms). Figure 22 shows a passive input filter with 6 dB of signal attenuation. Due to the relatively high input impedance on the analog inputs, the full distortion performance cannot be realized. Also, the resistor divider circuit will determine the input impedance into the input filter. In the circuit shown in Figure 22, the input impedance is approximately 5 k. By doubling the resistor values, the input impedance will increase to 10 k. However, in this case the distortion performance will drop due to the increase in series resistance on the analog inputs. 57 CS42438 10 F ADC1-2 2.5 k AIN1+,2+,3+,4+ 2.5 k 100 k 2700 pF C0G VA 100 k AIN1-,2-,3-,44.7 F 10 F 100 k ADC3 2.5 k AIN5A,6A 2.5 k 100 k 2700 pF C0G 10 F 2.5 k AIN5B,6B 100 k 2.5 k 2700 pF C0G Figure 22. Passive Input Filter w/Attenuation 58 CS42438 12.2 DAC Output Filter The CS42438 is a linear phase design and does not include phase or amplitude compensation for an external filter. Therefore, the DAC system phase and amplitude response will be dependent on the external analog circuitry. Shown below is the recommended active and passive output filters. 1800 pF DAC1-4 4.75 k 390 pF C0G AOUTx - 5.49 k 2.94 k 1.65 k 887 AOUTx + C0G + 562 47.5 k 1200 pF 5600 pF C0G 22 F C0G 1.87 k 22 F Figure 23. Active Analog Output Filter DAC1-4 3.3 F AOUTx+ 560 + 10 k C C= R ext Rext+ 560 4 FSRext560 Figure 24. Passive Analog Output Filter 59 CS42438 0 0 -10 -10 -20 -20 -30 -30 -40 -40 Amplitude (dB) Amplitude (dB) 13 APPENDIX B: ADC FILTER PLOTS -50 -60 -70 -80 -90 -100 -50 -60 -70 -80 -90 -100 -110 -110 -120 -120 -130 -130 -140 0.40 -140 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0.42 0 0.10 -1 0.08 -2 0.06 -3 0.04 -4 -5 -6 -7 0.50 0.52 0.54 0.56 0.58 0.60 0.00 -0.02 -0.04 -8 -0.06 -9 -0.08 -0.10 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.55 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 Frequency (normalized to Fs) Figure 27. Single Speed Mode Transition Band (Detail) Figure 28. Single Speed Mode Passband Ripple 0 0 -10 -10 -20 -20 -30 -30 -40 -40 Amplitude (dB) Amplitude (dB) 0.48 0.02 Frequency (normalized to Fs) -50 -60 -70 -80 -90 -100 -50 -60 -70 -80 -90 -100 -110 -110 -120 -120 -130 -130 -140 -140 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Frequency (normalized to Fs) Figure 29. Double Speed Mode Stopband Rejection 60 0.46 Figure 26. Single Speed Mode Transition Band Amplitude (dB) Amplitude (dB) Figure 25. Single Speed Mode Stopband Rejection -10 0.45 0.44 Frequency (normalized to Fs) Frequency (normalized to Fs) 0.40 0.42 0.44 0.46 0.48 0.50 0.52 0.54 0.56 0.58 0.60 Frequency (normalized to Fs) Figure 30. Double Speed Mode Transition Band CS42438 ` 0 0 .10 -1 0 .0 8 0 .0 6 Amplitude (dB) Amplitude (dB) -2 -3 -4 -5 -6 -7 0 .0 4 0 .0 2 0 .0 0 -0 .0 2 -0 .0 4 -0 .0 6 -8 -0 .0 8 -9 -10 0.46 -0 .10 0 .0 0 0.47 0.48 0.49 0.50 0.51 0.52 0 .15 0 .2 0 0 .2 5 0 .3 0 0 .3 5 0 .4 0 0 .4 5 0 .50 Figure 32. Double Speed Mode Passband Ripple 0 0 -10 -2 0 -3 0 -4 0 -10 -2 0 -3 0 Amplitude (dB) Amplitude (dB) 0 .10 Fr e que ncy (norm alize d to Fs ) Frequency (normalized to Fs) Figure 31. Double Speed Mode Transition Band (Detail) 0 .0 5 -50 -6 0 -70 -8 0 -9 0 -10 0 -110 -4 0 -50 -6 0 -70 -8 0 -9 0 -10 0 -110 -12 0 -13 0 -14 0 -12 0 -13 0 -14 0 0 .0 0 .1 0 .2 0 .3 0 .4 0 .5 0 .6 0 .7 0 .8 0 .9 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.60 0.65 0.70 0.75 0.80 0.85 1.0 Fre que ncy (norm alize d to Fs ) Fre que ncy (norm alize d to Fs ) Figure 33. Quad Speed Mode Stopband Rejection Figure 34. Quad Speed Mode Transition Band 0 .10 -2 0 .0 8 -3 0 .0 6 Amplitude (dB) Amplitude (dB) 0 -1 -4 -5 -6 -7 -8 0 .0 4 0 .0 2 0 .0 0 -0 .0 2 -0 .0 4 -0 .0 6 -9 -0 .0 8 -10 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 Frequency (normalized to Fs) -0 .10 0 .0 0 0 .0 3 0 .0 5 0 .0 8 0 .10 0 .13 0 .15 0 .18 0 .2 0 0 .2 3 0 .2 5 0 .2 8 Fr e que ncy (norm alize d to Fs ) tail) Figure 35. Quad Speed Mode Transition Band (De- Figure 36. Quad Speed Mode Passband Ripple 61 CS42438 14 APPENDIX C: DAC FILTER PLOTS Figure 37. Single Speed Stopband Rejection Figure 38. Single Speed Transition Band Figure 39. Single Speed Transition Band (detail) Figure 40. Single Speed Passband Ripple Figure 41. Double Speed Stopband Rejection Figure 42. Double Speed Transition Band 62 CS42438 Figure 43. Double Speed Transition Band (detail) Figure 44. Double Speed Passband Ripple 0 0 -10 -10 -20 -30 -20 Amplitude (dB) Amplitude (dB) -40 -50 -60 -30 -40 -70 -50 -80 -90 -60 -100 0 0.1 0.2 0.3 0.4 0.5 0.6 Frequency(normalized to Fs) 0.7 0.8 0.9 1 Figure 45. Quad Speed Stopband Rejection 0.35 0.4 0.45 0.5 0.55 0.6 Frequency(normalized to Fs) 0.65 0.7 0.75 Figure 46. Quad Speed Transition Band 0 0.2 -5 0.15 -10 0.1 0.05 -20 Amplitude (dB) Amplitude (dB) -15 -25 -30 0 -0.05 -35 -0.1 -40 -0.15 -45 -0.2 -50 0.4 0.45 0.5 0.55 0.6 Frequency(normalized to Fs) 0.65 0.7 Figure 47. Quad Speed Transition Band (detail) 0.05 0.1 0.15 0.2 0.25 0.3 Frequency(normalized to Fs) 0.35 0.4 0.45 Figure 48. Quad Speed Passband Ripple 63 CS42438 15 REVISION HISTORY Revision A1 Date July 2004 Changes Initial Release Table 10. Revision History Contacting Cirrus Logic Support For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find one nearest you go to http://www.cirrus.com/ IMPORTANT NOTICE "Advance" product information describes products that are in development and subject to development changes. Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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