CS42438-DM - Cirrus Logic, Inc.

Advance Product Information This document contains information for a new product.

Cirrus Logic reserves the right to modify this product without notice.

Cirrus Logic, Inc.

http://www.cirrus.com

Features

zSix 24-bit A/D, Eight 24-bit D/A Converters

zADC Dynamic Range

–105 dB Differential

–102 dB Single-Ended

zDAC Dynamic Range

–108 dB Differential

–105 dB Single-Ended

zADC/DAC THD+N

–-98 dB Differential

–-95 dB Single-Ended

zCompatible with industry standard Time

Division Multiplexed (TDM) Serial Interface

zSystem Sampling Rates up to 192 kHz

zProgrammable ADC High Pass Filter for DC

Offset Calibration

zLogarithmic Digital Volume Control

zHardware Mode or Software I²C/SPI

zSupports logic levels between 5 V and 1.8 V

General Description

The CS42438 CODEC provides six multi-bit analog-to-digi-

tal and eight multi-bit digital-to-analog Delta-Sigma

converters. The CODEC is capable of operation with either

differential or single-ended inputs and outputs, in a 52-pin

MQFP package.

Six fully differential or single-ended inputs are available on

stereo ADC1, ADC2 and ADC3. When operating in Single-

Ended Mode, an internal MUX before ADC3 allows selec-

tion from up to four single-ended inputs. Digital volume

control is provided for each ADC channel, with selectable

overflow detection.

All eight DAC channels provide digital volume control and

can operate with differential or single-ended outputs.

An auxiliary serial input is available for an additional two

channels of PCM data.

The CS42438 is ideal for audio systems requiring wide dy-

namic range, negligible distortion and low noise, such as

A/V receivers, DVD receivers and automotive audio

systems.

ORDERING INFORMATION

CS42438-CMZ -10° to 70° C 52-pin MQFP

CS42438-DMZ -40° to 85° C 52-pin MQFP

CS42438-DM -40° to 85° C 52-pin MQFP

CDB42438 Evaluation Board

Control Port & Serial

Audio Port Supply =

1.8 V to 5 V

Configuration Internal Voltage

Reference

Reset

TDM Ser ia l

Interface

Level TranslatorLevel Translator

TDM Seri a l Audio

Input

Digital Supply =

3.3 V

Hardware Mode or

I2C/SPI Software Mode

Control Data

Analog Supply =

3.3 V to 5 V

Differential or

Single-Ended

Outputs

Input Master

Clock

TDM Seri a l Audio

Output

Multibit

Oversampling

ADC1&2

High Pass

Filter Differential or

Single-Ended

Analog Inputs

Digital

Filters 4

tional MUX allows sel ection fr om u

to 4 sin

le-ended in

uts.

Multibit

Oversampling

ADC3

High Pass

Filter 2

Digital

Filters 2

4:2*

Auxil liary Serial

Audio Input

Volume

Controls Digital

Filters

Multibit

DAC1-4 and

Analog Filters

∆Σ

Modulators

CS42438

JUL ‘04

DS646A1

108 dB, 192 kHz 6-in, 8-out TDM CODEC

CS42438
2
TABLE OF CONTENTS
1  DIGITAL I/O PIN CHARACTERISTICS .....................................................................................6
2  PIN DESCRIPTION - SOFTWARE MODE   ........................... ... .................... ... ................... ... .....7
3  PIN DESCRIPTIONS - HARDWARE MODE  ............................................................................9
4  TYPICAL CONNECTION DIAGRAMS  ....................................................................................11
5  CHARACTERISTICS AND SPECIFICATIONS .......................................................................13
SPECIFIED OPERATING CONDITIONS...............................................................................13
ABSOLUTE MAXIMUM RATINGS .........................................................................................13
ANALOG INPUT CHARACTERISTICS (CS42438-CM).........................................................14
ANALOG INPUT CHARACTERISTICS (CS42438-DM).........................................................15
ADC DIGITAL FILTER CHARACTERISTICS.........................................................................16
ANALOG OUTPUT CHARACTERISTICS (CS42438-CM).....................................................17
ANALOG OUTPUT CHARACTERISTICS (CS42438-DM).....................................................19
COMBINED DAC INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE................21
SWITCHING SPECIFICATIONS - ADC/DAC PORT..............................................................22
SWITCHING CHARACTERISTICS - AUX PORT...................................................................23
SWITCHING SPECIFICATIONS - CONTROL PORT - I²C MODE.........................................24
SWITCHING SPECIFICATIONS - CONTROL PORT - SPI FORMAT ...................................25
DC ELECTRICAL CHARA CTERISTIC S........... ... ... ... .... ... ... ... .... ... ... ... ... .................... ... ... ......26
DIGITAL INTERFACE SPECIFICATIONS & CHARACTERISTICS.......................................26
6  APPLICATIONS .......................................................... .... ... ... ... .... ... ... ... ...................................27
6.1 Overview ................ ... ................................................. ... ... .... ... ... ... ... .... ............................27
6.2 Analog Inputs ... ... ... ... .... ... ................................................................................. ... ... .........28
6.2.1 Line Level Inputs . ... ... .... ................................ ... ... .... ... ... ... ... .... ............................28
6.2.2 ADC3 Analog Input  .............................................................................................29
6.2.3 High Pass Filter and DC Offset Calibration .........................................................30
6.3 Analog Outputs ................................................................................ .... ... ... ... .... ... ... ... ......31
6.3.1 Initialization  ............... .... ... ................................................ ... .... ... ... ... .... ... ... .........31
6.3.2 Line Level Outputs and Filtering  .........................................................................31
6.3.3 Digital Volume Control  .............. .... ... ...................................................................33
6.4 System Clocking ....... .... ... ... ... .... ... ................................................ ... .... ... ... ... .... ... ............33
6.5 CODEC Digital Interface ............ ... ... ... ... .... ... ... .................... ... ................... ... ...................34
6.5.1 TDM  ............. .... ... ... ... .... ... ................ ... ... .... ... ... ................ ... .... ... ... ... .... ...............34
6.5.2 I/O Channel Allocation  ........................................................................................34
6.6 AUX Port Digital Interface Formats ..................................................................................34
6.6.1 I²S ........... ... ... .... ................ ... ... ... .... ... ................ ... .... ... ... ... ................ .... ... ... ... ......35
6.6.2 Left Justified . .... ... ................ ... ... .... ... ... ... .... ... ................................................ ... ...35
6.7 Control Port Description and Timing ................................................................................36
6.7.1 SPI Mode  ...................................................................................... ... .... ... ... ... ... ...36
6.7.2 I²C Mode  ... ... .... ... ... ... .... ... ................................................ ... .... ... ... ... .... ... ... .........37
6.8 Recommended Power-up Sequence ..... .... ... ...................................................................38
6.8.1 Hardware Mode ... ... ................... .................... ................... ...................................38
6.8.2 Software Mode . ... ... ................ ... .... ... ... ... .... ... ... ...................................................38
6.9  Reset and Power-up .......................................................................................................38
6.10 Power Supply, Grounding, and PCB layout ...................................................................39
7  REGISTER QUICK REFERENCE  ...........................................................................................40
8  REGISTER DESCRIPTION  ..................................................................................................... 42
8.1 Memory Address Pointer (MAP).......... ... .... ... ... ... .... ... ... ... .... ... ... ... ... .... ................... ... ... ...42
8.2 Chip I.D. and Revision Register (address 01h) (Read Only)...... ... ... .... ................... ... ... ...42
8.3 Power Control (address 02h)............................................................................................43
8.4 Functional Mode (address 03h)........................................................................................44
8.5 Interface Formats (address 04h).......................................................................................44

3
CS42438
6 Misc Control (address 05h) ........ ... ... ... ... .... ... ... .................... ... ................... ... ................... 45
7 Transition Control (address 06h)...................................................................................... 46
8 DAC Channel Mute (address 07h) ................................................................................... 48
9 AOUTX Volume Control (addresses 08h- 0Fh)    ............................................................ 48
10 DAC Channel Invert (address 10h) ................................................................................ 49
11 AINX Volume Control (address 11h - 16h)..................................................................... 49
12 ADC Channel Invert (address 17h) ................................................................................ 49
13 Status Control (address 18h).......................................................................................... 50
14  Status (address 19h) (Read Only)................................................................................. 50
15 Status Mask (address 1Ah)............................................................................................ 51
PARAMETER DEFINITIONS ................................................................................................... 52
REFERENCES ....................................................................................................................... 53
PACKAGE DIMENSIONS  ..................................................................................................... 54
THERMAL CHARACTERISTICS ........................................................................................... 55
APPENDIX A: EXTERNAL FILTERS .................................................................................... 56
1 ADC Input Filter ............................................................................................................. 56
1.1 Passive Input Filt er  ........ ... ... ... .... ... ................ ... .... ... ... ... ... .... ... ......................... 57
1.2 Passive Input Filt er w/Attenuation  .. ... ... .... ... ... ... .... ... ... ................... .... ............... 57
2 DAC Output Filter .......................................................................................................... 59
APPENDIX B: ADC FILTER PLOTS ..................................................................................... 60
APPENDIX C: DAC FILTER PLOTS ..................................................................................... 62
REVISION HISTORY ............................................................................................................. 64

CS42438
4
LIST OF FIGURES
Figure 1. Typical Connection Diagram (Software Mode) ..............................................................11
Figure 2. Typical Connection Diagram (Hardware Mode)....................... ... ... .... ... ... ... .... ...............12
Figure 3. Output Test Load ...........................................................................................................20
Figure 4. Maximum Loading..........................................................................................................20
Figure 5. TDM Serial Audio Interface Timing ................................................................................22
Figure 6. Serial Audio Interface Slave Mode Timing.....................................................................23
Figure 7. Control Port Timing - I²C Format....................................................................................24
Figure 8. Control Port Timing - SPI Format...................................................................................25
Figure 9. Full-Scale Input..............................................................................................................29
Figure 10. ADC3 Input Topology...................................................................................................29
Figure 11. Audio Output Initialization Flow Chart..........................................................................32
Figure 12. Full-Scale Output .........................................................................................................33
Figure 13. TDM Serial Audio Format.............................................................................................34
Figure 14. AUX I²S Format............................................................................................................35
Figure 15. AUX Left Justified Format ............................................................................................35
Figure 16. Control Port Timing in SPI Mode..................................................................................36
Figure 17. Control Port Timing, I²C Write......................................................................................37
Figure 18. Control Port Timing, I²C Read......................................................................................37
Figure 19. Single to Differential Active Input Filter........................................................................56
Figure 20. Single-Ended Active Input Filter...................................................................................56
Figure 21. Passive Input Filter.......................................................................................................57
Figure 22. Passive Input Filter w/Attenuation................................................................................58
Figure 23. Active Analog Output Filter ..........................................................................................59
Figure 24. Passive Analog Output Filter........................................................................................59
Figure 25. Single Speed Mode Stopband Rejection ............ ... ... ... .... ... ... ... ...................................60
Figure 26. Single Speed Mode Transition Band......... ... ... .... ... ... ... .... ... ... ... ... .... ................... ... ......60
Figure 27. Single Speed Mode Transition Band (Detail)......... ... ... .... ... ... ... ... .... ... ... ................... ...60
Figure 28. Single Speed Mode Passband Ripple..........................................................................60
Figure 29. Double Speed Mode Stopband Rejection....................................................................60
Figure 30. Double Speed Mode Transition Band ..........................................................................60
Figure 31. Double Speed Mode Transition Band (Detail)........................... ... .... ................... ... ......61
Figure 32. Double Speed Mode Passband Ripple........................................................................61
Figure 33. Quad Speed Mode Stopband Rejection.......................................................................61
Figure 34. Quad Speed Mode Transition Band.............................................................................61
Figure 35. Quad Speed Mode Transition Band (Detail)................................................................61
Figure 36. Quad Speed Mode Passband Ripple...........................................................................61
Figure 37. Single Speed Stopband Rejection ............... ... .... ... ... ... .... ............................................62
Figure 38. Single Speed Transition Band......................................................................................62
Figure 39. Single Speed Transition Band (detail)..........................................................................62
Figure 40. Single Speed Passband Ripple....................................................................................62
Figure 41. Double Speed Stopband Rejection..............................................................................62
Figure 42. Double Speed Transition Band....................................................................................62
Figure 43. Double Speed Transition Band (detail).. ... ... ... .... ... ................... .................... ...............63
Figure 44. Double Speed Passband Ripple..................................................................................63
Figure 45. Quad Speed Stopband Rejection.................................................................................63
Figure 46. Quad Speed Transition Band.......................................................................................63
Figure 47. Quad Speed Transition Band (detail)...........................................................................63
Figure 48. Quad Speed Passband Ripple.....................................................................................63

CS42438

LIST OF TABLES

Table 1. I/O Power Rails........................................................................................................................ 6

Table 2. Hardware Configurable Settings............................................................................................ 27

Table 3. AIN5 Analog Input Selection.................................................................................................. 30

Table 4. AIN6 Analog Input Selection.................................................................................................. 30

Table 5. MCLK Frequency Settings..................................................................................................... 33

Table 6. Serial Audio Interface Channel Allocations ........................................................................... 34

Table 7. MCLK Frequency Settings..................................................................................................... 44

Table 8. Example AOUT Volume Settings .......................................................................................... 48

Table 9. Example AIN Volume Settings .............................................................................................. 49

Table 10. Revision History......... ... .... ... ... ... .... ... ... ... ... .... ................... ... .................... ... ... ...................... 64

CS42438

1 DIGITAL I/O PIN CHARACTERISTICS

Various pins on the CS42438 are powered from separate power supply rails. The logic level for each input

should adhere to the corresponding power rail and should not exceed the maximum ratings.

Power

Rail Pin Name I/O Driver Receiver

VLC RST Input - 1.8 V - 2.5 V and 3.3/5.0 V TTL Comp atible

SCL/CCLK Input - 1.8 V - 2.5 V and 3.3/5.0 V TTL Compatible, with Hysteresis

SDA/CDOUT Input/

Output 1.8 V - 5.0 V,

CMOS/Open Drain 1.8 V - 2.5 V and 3.3/5.0 V TTL Compatible, with Hysteresis

AD0/CS Input - 1.8 V - 2.5 V and 3.3/5.0 V TTL Compatible

AD1/CDIN Input - 1.8 V - 2.5 V and 3.3/5.0 V TTL Compatible

VLS MCLK Input - 1.8 V - 2.5 V and 3.3/5.0 V TTL Compatible

LRCK Input/

Output 1.8 V - 5.0 V,

CMOS 1.8 V - 2.5 V and 3.3/5.0 V TTL Compatible

SCLK Input/

Output 1.8 V - 5.0 V,

CMOS 1.8 V - 2.5 V and 3.3/5.0 V TTL Compatible

ADC_SDOUT Output 1.8 V - 5.0 V,

CMOS -

DAC_SDIN Input - 1.8 V - 2.5 V and 3.3/5.0 V TTL Compatib le

AUX_LRCK Output 1.8 V - 5.0 V,

CMOS -

AUX_SCLK Output 1.8 V - 5.0 V,

CMOS -

AUX_SDIN Input - 1.8 V - 2.5 V and 3.3/5.0 V TTL Comp atible

VA MUTEC Output 1.8 V - 5.0 V,

CMOS -

Table 1. I/O Power Rails

CS42438

2 PIN DESCRIPTION - SOFTWARE MODE

Pin Name #Pin Description

SCL/CCLK 1Serial Control Port Clock (Input) - Serial clock for the control port interface.

SDA/CDOUT 2Serial Control Data I/O (Input/Output) - Input/Output for I2C data. Output for SPI data.

AD0/CS 3Address Bit [0]/ Chip Select (Input) - Chip address bit in I2C Mode. Control signal used to select

the chip in SPI mode.

AD1/CDIN 4Address Bit [1]/ SPI Data Input (Input) - Chip address bit in I2C Mode. Input for SPI data.

RST 5Reset (Input) - The device enters a low power mode and all internal registers are reset to their

default settings when low.

VLC 6Control Port Power (Input) - Determines the required signal level for the RST, MFREQ pins.

FS 7Frame Sync (Input) - Signals the start of a new TD M frame in the TDM digital interfa c e fo rma t.

VD 8Digita l Power (Input) - Positive power supply for the digital section.

DGND 9,18 Digital Ground (Input) -

VLS 10 Serial Port Interface Power (Input) - Dete rmines the required signal level for the serial port inter-

faces.

SCLK 11 Serial Clock (Input) - Serial clock for the serial audio interface. Input frequency must be 256xFs.

MCLK 12 Master Clock (Input) - Clock source for the delta-sigma modulato r s and digital filters.

ADC_SDOUT 13 Serial Au dio Data Output (Output) - TDM output for two’s complement serial audio data.

DAC_SDIN 14 DAC Serial Audio Data Input (Input) - TDM Input for two’s complement serial audio data.

AUX_LRCK 15 Auxiliary Left/Right Clock (Output) - Determines which channel, Left or Right, is currently active

on the Auxiliary serial audio data line.

AUX_SCLK 16 Auxiliary Serial Clock (Output) - Serial clock for the Auxiliary serial audio interface.

SCL/CCLK

14 15 16 17 18 19 20 21 22 23 24 25

52 51 50 49 48 47 46 45 44 43 42 41

VLS

MCLK

VLC

AD1/CDIN

AOUT7-

AOUT5+

AOUT3+

AGND

AUX_SDIN

DAC_SDIN

ADC_SDOUT

AUX_SCLK

AUX_LRCK

AD0/CS

AOUT4+

RST

AOUT6+

AOUT3-

AOUT2+

AOUT2-

AOUT1-

AOUT1+

DGND

SCLK

DGND

AOUT6-

AOUT4-

SDA/CDOUT

AOUT5-

AOUT7+

AOUT8+

AOUT8-

FILT+

AGND

AIN6+/AIN6A

AIN6-/AIN6B

AIN3+

AIN4-

AIN4+

AIN5-/AIN5B

AIN3-

AIN5+/AIN5A

AIN2-

AIN2+

AIN1+

AIN1-

CS42438

AUX_SDIN 17 Auxiliary Serial Input (Input) - The CS42438 provides an additional serial input fo r two’s comple-

ment serial audi o da ta.

AOUT1 +,-

AOUT2 +,-

AOUT3 +,-

AOUT4 +,-

AOUT5 +,-

AOUT6 +,-

20,19

21,22

24,23

25,26

28,27

29,30

Differential Analog Output (Output) - The full-scale differential analog output level is specified in

the Analog Characteristics specification table. Each positive leg of the differential outputs may also

be used single-ended.

AGND 35,48 Analog Ground (Input) -

VQ 36 Quiescent Voltage (Output) - Filter connection for internal quiescent reference voltage.

VA 37,46 Analog Power (Input) - Positive power supply for the analog section.

AIN1 +,-

AIN2 +,-

AIN3 +,-

AIN4 +,-

AIN5 +,-

AIN6 +,-

39,38

41,40

43,42

45,44

50,49

52,51

Differential Analog Input (Input) - Signals are presented differentially to the delta-sigma modula-

tors. The full-scale input level is specified in the Analog Characteristics specification table. Single-

ended inputs may be applied to the positive terminals when the ADCx SINGLE bit is enabled.

Once in Single-Ended Mode, the negative terminal of AIN1-AIN4 must be externally driven to com-

mon mode. See below for a description of AIN5-AIN6 in Single-Ended Mode.

AIN5 A,B

AIN6 A,B 50,49

52,51 Single-Ended Analog Input (Input) - In Single-Ended Mode, an internal analog mux allows selec-

tion between 2 channels for both analog inputs AIN5 and AIN6 (see section 8.6. 6-8.6.8 for de tails).

The unused leg of each input is internally connected to common mode. The full-scale input level is

specified in the Analog Cha r acteristics specificati on table.

FILT+ 47 Positive Voltage Reference (Output) - Positive reference voltage for the interna l sampling cir-

cuits.

CS42438

3 PIN DESCRIPTIONS - HARDWARE MODE

Pin Name #Pin Description

AIN5_MUX

AIN6_MUX 1

2Analog Input Multiplexer (Input) - Allows selection between the A and B single-ended inputs of

ADC3. See sections 8.6.7 and 8.6.8 for details.

MFREQ 3MCLK Frequency (Input) - Sets the required frequency range of the input Master Clock. See sec-

tion 6.4 for the appropriate settings.

ADC3_HPF 4ADC3 High-Pass Filter Fre eze (Input) - When this pin is driven high, the internal high-p ass filter

will be disabled for ADC3.The current DC offset value will be frozen and continue to be subtracted

from the conversion result. See “ADC Digital Filter Characteristics” on page 16.

RST 5Reset (Input) - The device enters a low power mode and all internal registers are reset to their

default settings when low.

VLC 6Control Port Power (Input) - Determines the required signal level for the RST, MFREQ pins.

FS 7Frame Sync (Input) - Signals the start of a new TD M frame in the TDM digital interfa c e fo rma t.

VD 8Digita l Power (Input) - Positive power supply for the digital section.

VLS 10 Serial Port Interface Power (Input) - Dete rmines the required signal level for the serial port inter-

faces.

SCLK 11 Serial Clock (Input) - Serial clock for the serial audio interface. Input frequency must be 256xFs.

ADC_SDOUT/

ADC3_SINGLE 13 Serial Audio Data Output (Out put) - TDM output for two’s complement serial audio data. St art-up

Option for Hardware Mode: Pull-up to VLS enables Single-Ended Mode for AIN5-AIN6.

DAC_SDIN 14 DAC Serial Audio Data Input (Input) - Input for two’s complement serial audio data.

AUX_LRCK 15 Auxiliary Left/Right Clock (Output) - Determines which channel, Left or Right, is currently active

on the Auxiliary serial audio data line.

AUX_SCLK 16 Auxiliary Serial Clock (Output) - Serial clock for the Auxiliary serial audio interface.

AIN5_MUX

14 15 16 17 18 19 20 21 22 23 24 25

52 51 50 49 48 47 46 45 44 43 42 41

VLS

MCLK

VLC

ADC3_HPF

FILT+

AOUT7-

AOUT5+

AOUT3+

AGND

AUX_SDIN

DAC_SDIN

ADC_SDOUT/

ADC3_SINGLE

AUX_SCLK

AUX_LRCK

MFREQ

AOUT4+

RST

AOUT6+

AOUT3-

AGND

AOUT2+

AOUT2-

AOUT1-

AOUT1+

DGND

SCLK

DGND

AIN6+/AIN6A

AIN6-/AIN6B

AOUT6-

AOUT4-

AIN6_MUX

AOUT5-

AOUT7+

AOUT8+

AOUT8-

AIN3+

AIN4-

AIN4+

AIN5-/AIN5B

AIN3-

AIN5+/AIN5A

AIN1+

AIN2-

AIN2+

AIN1-

CS42438

AUX_SDIN 17 Auxiliary Serial Input (Input) - The CS42438 provides an additional serial input fo r two’s comple-

ment serial audi o da ta.

AOUT1 +,-

AOUT2 +,-

AOUT3 +,-

AOUT4 +,-

AOUT5 +,-

AOUT6 +,-

20,19

21,22

24,23

25,26

28,27

29,30

Differential Analog Output (Output) - The full-scale differential analog output level is specified in

the Analog Characteristics specification table. Each positive leg of the differential outputs may also

be used single-ended.

AGND 35,48 Analog Ground (Input) -

VQ 36 Quiescent Voltage (Output) - Filter connection for internal quiescent reference voltage.

VA 37,46 Analog Power (Input) - Positive power supply for the analog section.

AIN1 +,-

AIN2 +,-

AIN3 +,-

AIN4 +,-

AIN5 +,-

AIN6 +,-

39,38

41,40

43,42

45,44

50,49

52,51

Differential Analog Input (Input) - Signals are presented differentially to the delta-sigma modula-

tors. The full-scale input level is specified in the Analog Characteristics specification table. Single-

ended inputs may be applied to the positive terminals when the ADCx SINGLE pin is enabled.

Once in Single-Ended Mode, the negative terminal of AIN1-AIN4 must be externally driven to com-

mon mode. See below for a description of AIN5-AIN6 in Single-Ended Mode.

AIN5 A,B

AIN6 A,B 50,49

52,51 Single-Ended Analog Input (Input) - In Single-Ended Mode, an internal analog mux allows selec-

tion between 2 channels for both analog inputs AIN5 and AIN6 (see section 8.6. 6-8.6.8 for de tails).

The unused leg of each input is internally connected to common mode. The full-scale input level is

specified in the Analog Cha r acteristics specificati on table.

FILT+ 47 Positive Voltage Reference (Output) - Positive reference voltage for the interna l sampling cir-

cuits.

CS42438

4 TYPICAL CONNECTION DIAGRAMS

VLS

100 µF 0.1 µF

FILT+

0.1 µF 4.7 µF

0.01 µF

DGND

MCLK

Digital A udio

Processor

AUX_SDIN

CS5341

A/D

Converter

VAVD

AGNDAGND

AIN1+

AIN1-

Connect DGND and AGND at Codec

DAC_SDIN

SCLK

0.01 µF

+10 µF

0.01 µF

+3.3 V +

10 µF 0.01 µF

+1.8 V

to +5.0 V

Analog Input 1

Input

Filter 1

1. See the ADC Input Filter section in the Appendix.

2. See the DAC Output Filter section in the Appendix.

AUX_SCLK

AUX_LRCK

ADC_SDOUT

Analog Input 2

Analog Input 3

Analog Input 4

AIN5+/AIN5A

+3.3 V to +5 V

DGND

AIN2+

AIN2-

AIN3+

AIN3-

AIN4+

AIN4-

AIN5-/AIN5B

AIN6+/AIN6A

AIN6-/AIN6B

Analog Input 5

Analog Input 6

Analog Input 5A

Analog Input 5B

Analog Input 6A

Analog Input 6B

Input

Filter 1

AOUT1+

AOUT1-

AOUT2+

AOUT2-

AOUT3+

AOUT3-

AOUT4+

AOUT4-

Analog Output F i l ter 2

AOUT5+

AOUT5-

AOUT6+

AOUT6-

AOUT7+

AOUT7-

AOUT8+

AOUT8-

Analog Output F i l ter 2

Input

Filter 1

Input

Filter 1

Input

Filter 1

Input

Filter 1

Input

Filter 1

Input

Filter 1

Input

Filter 1

Input

Filter 1

VLC

0.1 µF

+1.8 V

to +5 V

SCL/CCLK

RST

AD0/CS

Micro-

Controller

2 kΩ2 kΩ

** **

** Resistors are required for

I2C control port operation

SDA/CDOUT

AD1/CDIN

Figure 1. Typical Connection Diagram (Software Mode)

CS42438

VLS

100 µF 0.1 µF

FILT+

0.1 µF 4.7 µF

0.01 µF

DGND

VLC

0.1 µF

AIN6_MUX

AIN5_MUX

ADC3_HPF

RST

MCLK

MFREQ

Digital Audio

Processor

AUX_SDIN

CS5341

A/D

Converter

VAVD

AGND

AIN1+

AIN1-

Connect DGND a nd AGND at Codec

DAC_SDIN

SCLK

0.01 µF

+10 µF

0.01 µF

+3.3 V +

10 µF 0.01 µF

+1.8 V

to +5.0 V

Analog Input 1

Input

Filter 1

1. See the ADC Input Filter section in the Appendix.

2. See the DAC Output Filter section in the Appendix.

AUX_SCLK

AUX_LRCK

ADC_SDOUT/

ADC3_SINGLE

Analog Input 2

Analog Input 3

Analog Input 4

AIN5+/AIN5A

+3.3 V to +5 V

DGND

AIN2+

AIN2-

AIN3+

AIN3-

AIN4+

AIN4-

AIN5-/AIN5B

AIN6+/AIN6A

AIN6-/AIN6B

Analog Input 5

Analog Input 6

Analog Input 5A

Analog Input 5B

Analog Input 6A

Analog Input 6B

VLS

* MUX configuration settings for AIN5-AIN6. See

the ADC Input MUX section.

Input

Filter 1

AOUT1+

AOUT1-

AOUT2+

AOUT2-

AOUT3+

AOUT3-

AOUT4+

AOUT4-

Analog Output Filter 2

AOUT5+

AOUT5-

AOUT6+

AOUT6-

AOUT7+

AOUT7-

AOUT8+

AOUT8-

Analog Output Filter 2

Input

Filter 1

Input

Filter 1

Input

Filter 1

Input

Filter 1

Input

Filter 1

Input

Filter 1

Input

Filter 1

Input

Filter 1

Figure 2. Typical Connection Diagram (Hardware Mode)

CS42438

5 CHARACTERISTICS AND SPECIFICATIONS

(All Min/Max characteristics and specifications are guaranteed over the Specified Oper ating Conditions. Typical per-

formance char acteristics an d specificat ions are deri ved from measurements taken at nominal supply voltages and

TA = 25° C.)

SPECIFIED OPERATING CONDITIONS (AGND=DGND=0 V, all voltages with respect to

ground.)

ABSOLUTE MAXIMUM RATINGS (AGND = DGND = 0 V; all voltages with respect to ground.)

WARNING: Operation at or beyond these limits may result in perm anent damage to the device. Normal opera tion is

not guaranteed at these extremes.

Notes: 1. Analog input/output performance will slightly degrade at VA = 3.3 V.

2. Any pin except supplies. Transient currents of up to ±100 mA on the analog input pins will not cause SCR

latch-up.

3. The maximum over/und er voltage is limited by the input current.

Parameters Symbol Min Typ Max Units

DC Power Supply

Analog 3.3 V

(Note 1) 5.0 V VA 3.14

4.75 3.3

53.47

5.25 V

Digital 3.3 V VD 3.14 3.3 3.47 V

Serial Audio Interface 1.8 V

2.5 V

3.3 V

5.0 V

VLS 1.71

2.37

3.14

4.75

1.8

2.5

3.3

1.89

2.63

3.47

5.25

Control Port Interface 1.8 V

2.5 V

3.3 V

5.0 V

VLC 1.71

2.37

3.14

4.75

1.8

2.5

3.3

1.89

2.63

3.47

5.25

Ambient Temperature

Commercial -CM

Automotive -DM TA-10

-40 -

-+70

+85 °C

°C

Parameters Symbol Min Max Units

DC Power Supply Analog

Digital

Serial Port Interface

Control Port Interface

VLS

VLC

-0.3

6.0

Input Current (Note 2) Iin -±10mA

Analog Input Voltage (Note 3) VIN AGND-0.7 VA+0.7 V

Digital Input Voltage Serial Port Interface

(Note 3) Control Port Interface VIND-S

VIND-C

-0.3

-0.3 VLS+ 0.4

VLC+ 0.4 V

Ambient Operating Temperature CS42438-CM

(power applied) CS42438-DM TA

-20

-50 +85

+95 °C

°C

St orage Temperature Tstg -65 +150 °C

CS42438

ANALOG INPUT CHARACTERISTICS (CS42438-CM) (Test Conditions (unle ss ot he rwise

specified): VLS = VLC = VD = 3.3 V, VA = 5 V; Full scale input sine wave: 1 kHz through the active input filter on

page 56; Measurement Bandwidth is 10 Hz to 20 kHz unless otherwise specified.)

Differential Single-Ended

Parameter Min Typ Max Min Typ Max Unit

Single Speed Mode Fs=48 kHz

Dynamic Range A-weighted

unweighted 99

96 105

102 -

-96

93 102

99 -

-dB

Total Harmonic Distortion + Noise -1 dB

(Note 4) -20 dB

-60 dB

-98

-82

-42

-92

-95

-79

-39

-89

Double Speed Mode Fs=96 kHz

Dynamic Range A-weighted

unweighted

40 kHz bandwidth unweighted

105

102

93 102

Total Harmonic Distortion + Noise -1 dB

(Note 4) -20 dB

-60 dB

40 kHz bandwidth -1 dB

-98

-82

-42

-90

-92

-95

-79

-39

-90

-89

Quad Speed Mode Fs=192 kHz

Dynamic Range A-weighted

unweighted

40 kHz bandwidth unweighted

105

102

93 102

-dB

Total Harmonic Distortion + Noise -1 dB

(Note 4) -20 dB

-60 dB

40 kHz bandwidth -1 dB

-98

-82

-42

-87

-92

-95

-79

-39

-87

-89

All Speed Modes

Interchannel Isolation - 90 - - 90 - dB

DC Accuracy

Interchannel Gain Mismatch - 0.1 - - 0.1 - dB

Gain Drift - ±100 - - ±100 - ppm/°C

Analog Input

Full-scale Input Voltage 1.06*VA 1.12*VA 1.18*VA 0. 53 *VA 0.56*VA 0.59*VA Vpp

Differential Input Impedance (Note 5) 37 - - - - - kΩ

Single-Ended Input Impedance (Note 6) ---18--kΩ

Common Mode Rejection Ratio (CMRR) - 82 - - - - dB

CS42438

ANALOG INPUT CHARACTERISTICS (CS42438-DM) (Test Conditions (unle ss ot he rwise

specified):VLS = VLC = VD = 3.3 V, VA = 5 V; Full scale input sine wave: 1 kHz through the active input filter on

page 56; Measurement Bandwidth is 10 Hz to 20 kHz unless otherwise specified.)

Notes: 4. Referred to the typical full-scale voltage.

5. Measured between AINx+ and AINx-.

6. Measured between AINxx and AGND.

Differential Single-Ended

Parameter Min Typ Max Min Typ Max Unit

Single Speed Mode Fs=48 kHz

Dynamic Range A-weighted

unweighted 97

94 105

102 -

-94

91 102

99 -

-dB

Total Harmonic Distortion + Noise -1 dB

(Note 4) -20 dB

-60 dB

-98

-82

-42

-90

-95

-79

-39

-87

Double Speed Mode Fs=96 kHz

Dynamic Range A-weighted

unweighted

40 kHz bandwidth unweighted

105

102

Total Harmonic Distortion + Noise -1 dB

(Note 4) -20 dB

-60 dB

40 kHz bandwidth -1 dB

-98

-82

-42

-87

-90

-95

-79

-39

-87

Quad Speed Mode Fs=192 kHz

Dynamic Range A-weighted

unweighted

40 kHz bandwidth unweighted

105

102

Total Harmonic Distortion + Noise -1 dB

(Note 4) -20 dB

-60 dB

40 kHz bandwidth -1 dB

-98

-82

-42

-87

-90

-95

-79

-39

-87

All Speed Modes

Interchannel Isolation - 90 - - 90 - dB

DC Accuracy

Interchannel Gain Mismatch - 0.1 - - 0.1 - dB

Gain Drift - ±100 - - ±100 - ppm/°C

Analog Input

Full-scale Input Voltage 1.04*VA 1.12*VA 1.20*VA 0. 52 *VA 0.56*VA 0.60*VA Vpp

Differential Input Impedance (Note 5) 37 - - - - - kΩ

Single-Ended Input Impedance (Note 6) ---18--kΩ

Common Mode Rejection Ratio (CMRR) - 82 - - - - dB

CS42438

ADC DIGITAL FILTER CHARACTERISTICS

Notes: 7. Filter response is guaranteed by design.

8. Response is clock dependent and will scale with Fs. Note that the response plots (Figures 25 to 36) have

been normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs.

Parameter (Note 7, 8) Min Typ Max Unit

Single Speed Mode (Note 8)

Passband (Frequency Response) to -0.1 dB corner 0 - 0.4896 Fs

Passband Ripple - - 0.035 dB

Stopband 0.5688 - - Fs

St opband Attenuation 70 - - dB

Total Group Delay - 12/Fs - s

Double Speed Mode (Note 8)

Passband (Frequency Response) to -0.1 dB corner 0 - 0.4896 Fs

Passband Ripple - - 0.025 dB

Stopband 0.5604 - - Fs

St opband Attenuation 69 - - dB

Total Group Delay - 9/Fs - s

Quad S p eed Mode (Note 8)

Passband (Frequency Response) to -0.1 dB corner 0 - 0.2604 Fs

Passband Ripple - - 0.025 dB

Stopband 0.5000 - - Fs

St opband Attenuation 60 - - dB

Total Group Delay - 5/Fs - s

High Pass Filter Characteristics

Frequency Response -3.0 dB

-0.13 dB -1

20 -

-Hz

Phase Deviation @ 20 Hz - 10 - Deg

Passband Ripple - - 0 dB

Filter Settling Time - 105/Fs 0 s

CS42438

ANALOG OUTPUT CHARACTERISTICS (CS42438-CM) (Test Conditions (unless other-

wise specified):VLS = VLC = VD = 3.3 V, VA = 5 V; Measurement Bandwidth is 10 Hz to 20 kHz unless otherwise

specified; Full scale 997 Hz output sine wave (see Note 10); Single-ended test load: RL = 3 kΩ, CL = 10 pF.)

Parameter Differential

Min Typ Max Single-Ended

Min Typ Max Unit

Single-Speed Mode Fs = 48 kHz

Dynamic Range

18 to 24-Bit A-weighted

unweighted

16-Bit A-weighted

unweighted

102

108

105

102

Total Harmonic Distortion + Noise

18 to 24-Bit 0 dB

-20 dB

-60 dB

16-Bit 0 dB

-20 dB

-60 dB

-98

-85

-45

-93

-76

-36

-92

-95

-82

-42

-90

-73

-33

-89

Double-Speed Mode Fs = 96 kHz

Dynamic Range

18 to 24-Bit A-weighted

unweighted

16-Bit A-weighted

unweighted

102

108

105

102

Total Harmonic Distortion + Noise

18 to 24-Bit 0 dB

-20 dB

-60 dB

16-Bit 0 dB

-20 dB

-60 dB

-98

-85

-45

-93

-76

-36

-92

-95

-82

-42

-90

-73

-33

-89

Quad-Speed Mode Fs = 192 kHz

Dynamic Range

18 to 24-Bit A-weighted

unweighted

16-Bit A-weighted

unweighted

102

108

105

102

Total Harmonic Distortion + Noise

18 to 24-Bit 0 dB

-20 dB

-60 dB

16-Bit 0 dB

-20 dB

-60 dB

-98

-85

-45

-93

-76

-36

-92

-95

-82

-42

-90

-73

-33

-89

CS42438

All Speed Modes

Interchannel Isolation (1 kHz) - 100 - - 100 - dB

Analog Output

Full Scale Output 1.235•VA 1.300•VA 1.365•VA 0.618•VA 0.650•VA 0.683•VA Vpp

Interchannel Gain Mismatch - 0.1 0.25 - 0.1 0.25 dB

Gain Drift - ±100 - - ±100 - ppm/°C

Output Impedance - 100 - - 100 - Ω

DC Current draw from an AOUT pin

(Note 9) --10--10µA

AC-Load Resistance (RL)(Note 11) 3--3--kΩ

Load Capacitance (CL)(Note 11) - - 100 - - 100 pF

CS42438

ANALOG OUTPUT CHARACTERISTICS (CS42438-DM) (Test Conditions (unless other-

wise specified): VLS = VLC = VD = 3.3 V,VA = 5 V; Measurement Bandwidth is 10 Hz to 20 kHz unless otherwise

specified; Full scale 997 Hz output sine wave (see Note 10); Single-ended test load: RL = 3 kΩ, CL = 10 pF.)

Parameter Differential

Min Typ Max Single-Ended

Min Typ Max Unit

Single-Speed Mode Fs = 48 kHz

Dynamic Range

18 to 24-Bit A-weighted

unweighted

16-Bit A-weighted

unweighted

100

108

105

102

Total Harmonic Distortion + Noise

18 to 24-Bit 0 dB

-20 dB

-60 dB

16-Bit 0 dB

-20 dB

-60 dB

-98

-85

-45

-93

-76

-36

-90

-95

-82

-42

-90

-73

-33

-87

Double-Speed Mode Fs = 96 kHz

Dynamic Range

18 to 24-Bit A-weighted

unweighted

16-Bit A-weighted

unweighted

100

108

105

102

Total Harmonic Distortion + Noise

18 to 24-Bit 0 dB

-20 dB

-60 dB

16-Bit 0 dB

-20 dB

-60 dB

-98

-85

-45

-93

-76

-36

-90

-95

-82

-42

-90

-73

-33

-87

Quad-Speed Mode Fs = 192 kHz

Dynamic Range

18 to 24-Bit A-weighted

unweighted

16-Bit A-weighted

unweighted

100

108

105

102

Total Harmonic Distortion + Noise

18 to 24-Bit 0 dB

-20 dB

-60 dB

16-Bit 0 dB

-20 dB

-60 dB

-98

-85

-45

-93

-76

-36

-90

-95

-82

-42

-90

-73

-33

-87

CS42438

Notes: 9. Guaranteed by design. The DC current draw represents the allowed current draw from the AOUT pin

due to typical leakage through the electrolytic DC blocking capacitors.

10. One-half LSB of triangular PDF dither is added to data.

11. Guaranteed by design. See Figure 3. RL and CL reflect the recommended min imum resistance and

maximum capacitance required for the internal op-amp's stability and signal integrity. In this circuit

topology, CL will effectively move the dominant pole of the two-pole amp in the output stage. Increasing

this value beyond the recommended 100 pf can cause the internal op-amp to become unstable. See

Appendix A for a recomm e nd e d outp ut filt er.

All Speed Modes

Interchannel Isolation (1 kHz) - 100 - - 100 - dB

Analog Output

Full Scale Output 1.210•VA 1.300•VA 1.392•VA 0.605•VA 0.650•VA 0.696•VA Vpp

Interchannel Gain Mismatch - 0.1 0.25 - 0.1 0.25 dB

Gain Drift - ±100 - - ±100 - ppm/°C

Output Impedance - 100 - - 100 - Ω

DC Current draw from an AOUT pin

(Note 9) --10--10µA

AC-Load Resistance (RL)(Note 11) 3--3--kΩ

Load Capacitance (CL)(Note 11) - - 100 - - 100 pF

100

2.5

51015

Safe Operating

Region

Capacitive Load -- C (pF)

Resistive Load -- R (k

Ω

)

125

320

AOUTxx

3.3 µF

Analog

Output

DAC1-4

AGND

Figure 3. Output Test Load Figure 4. Maximum Loading

CS42438

COMBINED DAC INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE

Notes: 12. Response is clock dependent and will scale with Fs. Note that the response plots (Figures 37 to 48) have

been normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs.

13. Single and Double Spee d Mode Measurement Bandwidth is from Stopband to 3 Fs.

Quad Speed Mode Measurement Bandwidth is from Stopband to 1.34 Fs.

14. De-emphasis is only availabl e in Single Speed Mode.

Parameter (Note 7, 12) Min Typ Max Unit

Single Speed Mode

Passband (Frequency Respo nse) to -0.05 dB corner

to -3 dB corner 0

-0.4780

0.4996 Fs

Frequency Resp onse 10 Hz to 20 kHz -.01 - +0.08 dB

StopBand 0.5465 - - Fs

StopBand Attenuation (Note 13) 50 - - dB

Group Delay - 10/Fs - s

De-emphasis Error (Note 14) Fs = 32 kHz

Fs = 44.1 kHz

Fs = 48 kHz

+1.5/+0

+0.05/-0.25

-0.2/-0.4

Double Speed Mode

Passband (Frequency Response) to -0.1 dB corner

to -3 dB corner 0

-0.4650

0.4982 Fs

Frequency Resp onse 10 Hz to 20 kHz -0.05 - +.2 dB

StopBand 0.5770 - - Fs

StopBand Attenuation (Note 13) 55 - - dB

Group Delay - 5/Fs - s

Quad S p eed Mode

Passband (Frequency Response) to -0.1 dB corner

to -3 dB corner 0

-0.397

0.476 Fs

Frequency Response 10 Hz to 20 kHz 0 - +0.00004 dB

StopBand 0.7 - - Fs

StopBand Attenuation (Note 13) 51 - - dB

Group Delay - 2.5/Fs - s

CS42438

SWITCHING SPECIFICATIONS - ADC/DAC PORT (Inputs: Logic 0 = DGND, Logic 1 = VLS,

ADC_SDOUT CLOAD = 15 pF.)

Notes: 15. After powering up the CS42438, RST should be held low after the power supplies and clocks are settled.

16. See Table 7 on page 44 for suggested MCLK frequencies.

Parameters Symbol Min Max Units

Slave Mode

RST pin Low Pulse Width (Note 15) 1-ms

MCLK Frequency 0.512 50 MHz

MCLK Duty Cycle (Note 16) 45 55 %

Input Sample Rate (FS pin) Single-Speed Mode

Double-Speed Mode

Quad-Speed Mode

100

200

kHz

SCLK Duty Cycle 45 55 %

SCLK High Time tsckh 8-ns

SCLK Low Time tsckl 8-ns

FS Rising Edge to SCLK Rising Edge tfss 5-ns

SCLK Rising Edge to FS Falling Edge tfsh 16 - ns

SCLK Falling Edge to ADC_SDOUT Output Valid tdpd -5ns

DAC_SDIN Setup Time Before SCLK Rising Edge tds 3-ns

DAC_SDIN Hold Time After SCLK Rising Edge tdh 5-ns

DAC_SDIN Hold Time After SCLK Rising Edge tdh1 5-ns

ADC_SDOUT Hold Time After SCLK Rising Edge tdh2 10 - ns

ADC_SDOUT Valid Before SCLK Rising Edge tdval 15 - ns

ADC_SDOUT

DAC_SDIN

tds

SCLK

(input)

MSB

tdh1

tsckh tsckl

tdval

MSB-1

MSB MSB-1

tfsh

tfss

tdh2

Figure 5. TDM Serial Audio Interface Timing

CS42438

SWITCHING CHARACTERISTICS - AUX PORT (Inputs: Logic 0 = DGND, Logic 1 = VLS.)

Parameters Symbol Min Max Units

Master Mode

Output Sample Rate (AUX_LRCK) All Speed Modes Fs- LRCK kHz

AUX_SCLK Frequency - 64·LRCK kHz

AUX_SCLK Duty Cycle 45 55 %

AUX_LRCK Edge to SCLK Rising Edge tlcks -5ns

AUX_SCLK Falling Edge to ADC_SDOUT Output Valid tdpd -5ns

AUX_SDIN Setup Time Before SCLK Rising Edge tds 3-ns

AUX_SDIN Hold Time After SCLK Rising Edge tdh 5-ns

AUX_SDIN

AUX_SCLK

AUX_LRCK

tsckh tsckl

tlcks

tds

MSB

tdh

MSB-1

Figure 6. Serial Audio Interface Slave Mode Timing

CS42438

SWITCHING SPECIFICATIONS - CONTROL PORT - I²C MODE (VLC = 1.8 V - 5.0 V,

VLS = VD = 3.3 V, VA = 5.0 V; Inputs: Logic 0 = DGND, Logic 1 = VLC, SDA CL=30pF)

Notes: 17. Data must be held for sufficient time to bridge the transition time, tfc, of SCL.

18. Guaranteed by design.

Parameter Symbol Min Max Unit

SCL Clock Frequency fscl - 100 kHz

RST Rising Edge to Start tirs 500 - ns

Bus Free Time Between Transmissions tbuf 4.7 - µs

Start Condition Hold Time (prior to first clock pulse) thdst 4.0 - µs

Clock Low time tlow 4.7 - µs

Clock High Time thigh 4.0 - µs

Setup Time for Repeated S tart Condition tsust 4.7 - µs

SDA Hold Time from SCL Falling (Note 17) thdd 0-µs

SDA Setup time to SCL Rising tsud 250 - ns

Rise Time of SCL and SDA (Note 18) trc -1µs

Fall Time SCL and SDA (Note 18) tfc -300ns

Setup Time for Stop Condition tsusp 4.7 - µs

Acknowledge Delay from SCL Falling tack 300 1000 ns

tbuf thdst

tlow thdd

thigh

tsud

Stop Start

SDA

SCL

tirs

RST

thdst

trc

tfc

tsust

tsus

Start Stop

Repeated

trd tfd

tack

Figure 7. Control Port Timing - I²C Format

CS42438

SWITCHING SPECIFICATIONS - CONTROL PORT - SPI FORMAT

(VLC = 1.8 V - 5.0 V, VLS = VD = 3.3 V, VA = 5.0 V; Inputs: Logic 0 = DGND, Logic 1 = VLC, CDOUT CL=30pF)

Notes: 19. Data must be held for sufficient time to bridge the transitio n tim e of CC LK.

20. For fsck <1 MHz.

Parameter Symbol Min Max Units

CCLK Clock Frequency fsck 06.0MHz

RST Rising Edge to CS Falling tsrs 20 - ns

CS Falling to CCLK Edge tcss 20 - ns

CS High Time Between Transmissions tcsh 1.0 - µs

CCLK Low Time tscl 66 - ns

CCLK High Time tsch 66 - ns

CDIN to CCLK Rising Setup Time tdsu 40 - ns

CCLK Rising to DATA Hold Time (Note 19) tdh 15 - ns

CCLK Falling to CDOUT Stable tpd -50ns

Rise Time of CDOUT tr1 -25ns

Fall Time of CDOUT tf1 -25ns

Rise Time of CCLK and CDIN (Note 20) tr2 - 100 ns

Fall Time of CCLK and CDIN (Note 20) tf2 - 100 ns

CCLK

CDIN

CDOUT

RST tsrs

tscl

tsch

tcss tr2

tf2

tcsh

tdsu tdh

MSB

tpd

Figure 8. Control Port Timing - SPI Format

CS42438

DC ELECTRICAL CHARACTERISTICS (AGND = 0 V; all voltages with respect to ground.)

Notes: 21. Nor mal operation is defined as RST = HI with a 997 Hz, 0 dBFS input to the DAC and AUX port, and a

1 kHz, -1 dB analog input to the ADC port sampled at the highest Fs for each speed mode . DAC outputs

are open, unless otherwise specified.

22. IDT measured with no external loading on pin 2 (SDA).

23. Valid with the recommended capacitor values on FILT+ and VQ. Increasing the capacitance will also

increase the PSRR.

24. Power Down Mode is defined as RST = LO with all clocks and data lines held static and no analog input.

25. Guaranteed by design . The DC current draw re presen ts the allowed current dr aw from the VQ p in due

to typical leakage through the electrolytic de-coupling capacitors.

DIGITAL INTERFACE SPECIFICATIONS & CHARACTERISTICS

Notes: 26. See “Digital I/O Pin Characteristics” on page 6 for serial and control port power rails.

27. Control Port signals in software mode include: SCL/CCLK, SDA/CDOUT, AD0/CS, AD1/CDIN, and

RST. Control Port signals in hardware mode include: AIN5_MUX, AIN6_MUX, MFREQ, and RST.

Parameters Symbol Min Typ Max Units

Normal Operation (Note 21)

Power Supply Current VA = 5.0 V

VLS = VLC = VD = 3.3 V

(Note 22)

IDT

60.6

Power Dissipation VLS = VLC = VD = 3.3 V, VA = 5 V - 600 850 mW

Power Supply Rejection Ratio (Note 23) 1 kHz

60 Hz PSRR -

-60

40 -

-dB

Power-down Mode (Note 24)

Power Dissipation VLS = VLC = VD = 3.3 V, VA = 5 V - 1.25 - mW

VQ Characteristics

Nominal Voltage

Output Impedance

DC current source/sink (Note 25)

0.5•VA

kΩ

µA

FILT+ Nominal Voltage - VA - V

Parameters (Note 26) Symbol Min Typ Max Units

High-Level Output Voltage at Io=2 mA Serial Port

Control Port VOH VLS-1.0

VLC-1.0 -

-V

Low-Level Output Voltage at Io=2 mA Serial Port

Control Port VOL -

-0.4

0.4 V

High-Level Input Voltage Serial Port

Control Port VIH

0.7xVLS

0.7xVLC -

-V

Low-Level Input Voltage Serial Port

Control Port VIL

-0.2xVLS

0.2xVLC V

Input Leakage Current Iin --±10µA

Input Capacitance (Note 18) - - 10 pF

27
CS42438
6 APPLICATIONS
6.1 Overview
The CS42438 is a highly integrated mixed signal 24-bit audio CODEC comprised of 6 analog-to-digital
converters (ADC), implemented using multi-bit Delta-Sigma techniques, and 8 digital-to-analog convert-
ers (DAC) also implemented using multi-bit Delta-Sigma techniques. 
Other functions integrated within the CODEC include independent digital volume controls for each DAC,
digital de-emphasis filters for the DAC, digital vo lume control with gain on ea ch ADC channel, ADC hig h-
pass filters, and an on-chip voltage reference. 
All serial data is transmitted through two independent serial ports: the DAC serial port and the ADC seria l
port. Each serial port can be configured independently to  operate at different samp le and clock ra tes, but
both must run synchronous to each other. 
The serial audio interface p orts allow up  to 8  DAC channels and 8 ADC channels in a Time-Division Mul-
tiplexed (TDM) interface format. The CS42438 features an Auxiliary Port used to accommodate an addi-
tional two channels of PCM data on the SDOUT data line in the TDM digital interface format. See “AUX
Port Digital Interface Formats” on page 34 for details.
The CS42438 operates in one of three oversampling modes based  on the input sample rate. Mode selec-
tion is determined automatically based on the MCLK frequency setting. Single-Speed mode (SSM) sup-
ports input sample rates up to 50 kHz and uses a 128x oversampling ratio. Double-Speed mode (DSM)
supports input sample rates up to 100 kHz and uses an oversampling ratio of 64x. Quad-Speed mode
(QSM) supports input sample rates up to 200 kHz and uses an oversampling ratio  of 32x. NOTE: QSM  is
only available in software mode (see section 6.4 on page 33 for details).
All functions can be configured through software via a serial control port operable in SPI mode or in I²C
mode. A hardware, stand-alone mode is also available, allowing configuration of the codec on  a more lim-
ited basis. See Table 2 for the default configuration in Hardware Mode. 
Figure 1 on page 11 and Figure 2 on page 12 show the recommended connections for the CS42438  in
software and hardware mode, respectively. See section 8 on page 42 for the defa ult register settings and
options in Software Mode.
 
Hardware Mode Feature Summary
Function Default Configuration Hardware Control Note
Power Down ADC All ADC’s are enabled - -
Power Down DAC All DAC’s are enabled - -
Power Down Device Device is powered up - -
MCLK Frequency Select Selectab le between 256Fs 
and 512Fs “MFREQ” pin 3 see section 
6.4
Freeze Control N/A - -
AUX Serial Port Interface Format Left-Justified - -
ADC1/ADC2 High Pass Filter Freeze High Pass Filter is always 
enabled --
ADC3 High Pass Filter Freeze High Pass Filter can be 
enabled/disabled “ADC3_HPF” pin 4 see section 
6.2.3
DAC De-Emphasis No De-Emphasis applied - -
ADC1/ADC2 Single-Ended Mode Disabled - -
Table 2. Hardware Configurable Settings

CS42438
28
6.2 Analog Inputs
6.2.1 Line Level Inputs 
AINx+ and AINx- are the line level differential analog inputs internally biased to VQ, approxi-
mately VA/2. Figure 9 on page 29 shows the full-scale analog input levels. The CS42438 also
accommodates single-ended signals on all inputs, AIN1-AIN6. See “ADC Input Filter” on
page 56 for the recommended input filters.
Hardware Mode
AIN Volume Control and ADC Overflow status are not accessible in Hardware Mode. Single-
ended operation is only supported for ADC3. See section 6.2.2 below. 
Software Mode
For single-ended operation on ADC1-ADC3 (AIN1 to AIN6), the ADCx_SINGLE bit in the regis-
ter “Misc Control (address 05h)” on page 45 must be set appropriately (see Figure 20 on page
56 for required external components).  
The gain/attenuation of the signal can be adjusted for each AINx independently through the
“AINX Volume Control (address 11h - 16h)” on page 49. The ADC output d ata is in 2’s co mple-
ment binary format. For inputs above positive full sc ale or below negative full scale, the ADC will
output 7FFFFFH or 800000H,  respectively an d cause  the ADC Overflow bit in the register  “Sta-
tus (address 19h) (Read Only)” on page 50 to be set to a ‘1’.
ADC3 Single-Ended Mode Selectable between Differ-
ential and Single-Ended “ADC_SDOUT/
ADC3_SINGLE” pin 13 see section 
6.2.2
AIN5 Multiplexer Selects between AIN5A and 
AIN5B when ADC3 in Sin-
gle-Ended Mode
“AIN5_MUX” pin 1 see section 
6.2.2
AIN6 Multiplexer Selects between AIN6A and 
AIN6B when ADC3 in Sin-
gle-Ended Mode
“AIN6_MUX” pin 2 see section 
6.2.2
DAC Volume Control/Mute/Invert All DAC Volume = 0 dB, un-
muted, not invert ed --
ADC Volume Control All ADC Volume = 0 dB - -
DAC Soft Ramp/Zero Cross All DAC’s Soft Ramp on 
Zero Cross --
ADC Soft Ramp/Zero Cross All ADC’s Soft Ramp on 
Zero Cross --
DAC Auto-Mute Enabled - -
Status Interrupt N/A - -
Hardware Mode Feature Summary
Function Default Configuration Hardware Control Note
Table 2. Hardware Configurable Settings

CS42438

6.2.2 ADC3 Analog Input

ADC3 accommodates differential as well as single-ended inputs. In Single-Ended mode, an in-

ternal MUX selects from up to 4 single-ended inputs.

Hardware Mode

Single-Ended mode is selected using a pull-up on the ADC_SDOUT/ADC3_SINGLE pin during

startup. Analog input selection is then made via the AINx_MUX pins. See Tables 3-4 below for

ADC3 setup options. Refer to Figure 10 on page 29 for the internal ADC3 analog input topology.

Full-Scale Differential Input Level =

(AINx+) - (AINx-) = 5.6 VPP = 1.98 VRMS

AINx+

AINx-

3.9 V

2.5 V

1.1 V

5.0 V

3.9 V

2.5 V

1.1 V

Figure 9. Full-Scale Input

AIN5

AIN5_MUX

AIN6_MUX

ADC3

Single-Ended Input Filter

Differential

Input Filter

ADC3 SINGLE

Differential

Input Filter

AIN5A

AIN5B

AIN5+/-

AIN6+/-

AIN6A

AIN6B

AIN6

Figure 10. ADC3 Input Topology

CS42438

Software Mode

Single-Ended mode is selected using the ADC3_SINGLE bit. Analog input selection is then

made via the AINx_MUX bits. See register “Misc Control (address 05h)” on page 45 for all bit

selections. Refer to Figure 10 on page 29 for the internal ADC3 analog input topology.

6.2.3 High Pass Filter and DC Offset Calibration

The high pass filter continuously subtracts a measure of the DC offset from the output of the dec-

imation filter. If the high pass filter is disabled during normal operation, the current value of the

DC offset for the corresponding channel is frozen and this DC offset will continue to be subtract-

ed from the conversion resu lt. This feature makes it possible to perform a syste m DC offset cal-

ibration by:

1) Running the CS42438 with the high pass filter enabled until the filter settles. See the Digital

Filter Characteristics for filter settling time.

2) Disabling the high pass filter and freezing the stored DC offset.

Hardware Mode

The high pass filters for ADC1 and ADC2 are permanently enabled in Hardware Mode. The high

pass filter for ADC3 is enabled by driving the ADC3_HPF (pin 4) high.

Software Mode

The high pass filter for ADC1/ADC2 ca n be enabled and disable d. The high pass filter for ADC3

can be independently enabled and disabled. The high pass filters are controlled using the

HPF_FREEZE bit in the register “Misc Control (address 05h)” on page 45.

Configurat io n Set ti n g

AIN5 Input Selection

ADC_SDOUT

(pin 13) AIN5_MUX

(pin 1)

47 kΩ Pull-d own X Differential Input (pins 50 & 49)

47 kΩ Pull-up Low AIN5A Input (pin 50)

47 kΩ Pull-up High AIN5B Input (pin 49)

Table 3. AIN5 Analog Input Selection

Configurat io n Set ti n g

AIN6 Input Selection

ADC_SDOUT

(pin 13) AIN6_MUX

(pin 2)

47 kΩ Pull-d own X Differential Input (pins 52 & 51)

47 kΩ Pull-up Low AIN5A Input (pin 52)

47 kΩ Pull-up High AIN5B Input (pin 51)

Table 4. AIN6 Analog Input Selection

CS42438

6.3 Analog Outputs

6.3.1 Initialization

The initialization and Power-Down sequence flow chart is shown in Figure 11 on page 32. The

CS42438 enters a Power-Down state upon initial power-up. The interpolation & decimation fil-

ters, Delta-Sigma modulators and control port registers are reset. The internal voltage refer-

ence, multi-bit digital-to-analog and analog-to-digital converters and switched-capacitor low-

pass filters are powered down.

The device will remain in the Power-Down state until the RST pin is brought high. The control

port is accessible once RST is high and the desired register settings can be loaded per the in-

terface descriptions in the “Con trol Port Desc ription and Timing” on page 36. In hardware mode

operation, the hardware mode pins must be setup before RST is brought high. All features will

default to the hardware mode defaults as listed in Table 2.

Once MCLK is valid, VQ will quickly charge to VA/2, and the internal voltage reference, FILT+,

will begin powering up to normal operation. Po wer is applied to the D/A converters and switched-

capacitor filters, and the analog outputs are clamped to the quiescent voltage, VQ. Once LRCK is

valid, MCLK occurrences are counted over one LRCK period to determine the MCLK/LRCK fre-

quency ratio. After an approximate 2000 sample period delay, normal operation begins.

6.3.2 Line Level Outputs and Filtering

The CS42438 contains on-chip buffer amplifiers capable of producing line level differential as

well as single-ended outputs on AOUT1-AOUT8 . These amplifiers are biased to a quiescent DC

level of approximately VQ.

The Delta-Sigma conversion process produces high frequency noise beyond the audio pass-

band, most of which is removed by the on-chip analog filters. The remaining out-of-band noise

can be attenuated using an off-chip low pass filter.

See “DAC Output Filter” on page 59 for recommended output filter. The active filter configuration

accounts for the normally differing AC loads on the AOUTx+ and AOUTx- differential output pins.

Also shown is a passive filter configuration which minimizes costs and the number of compo-

nents.

Figure 12 shows the full-scale analog output levels. All outputs are internally biased to VQ, ap-

proximately VA/2.

CS42438

No Power

1. VQ = ?

2. Aout bias = ?

3. No audio signa l

generated.

Control Port

Accessed

Control P ort

Access Detected?

Valid MCLK

Applied? V a lid MCLK

Applied?

PDN bit = '1'b?

Sub-Clocks Applied

1. LRCK va li d.

2. SCLK va lid.

3. Audio samples

processed.

Valid

MCLK/LRCK

Ratio?

YesYes

YesNo

Yes

Normal Operat io n

1. VQ = VA/2.

2. Aout bias = VA/2.

3. Audio signa l ge nerated per register s e ttings.

Analog Output Freeze

1. VQ = VA/2.

2. Ao ut bias = VA/2 + l ast audio sample.

3. No audio signa l ge nerated.

Analog Output Mute

1. VQ = VA/2.

2. Aou t bias = VA/2.

3. No audio signal generated.

ERROR: MCLK/LRCK ratio change ERROR: MCLK removed

RST = Lo w

ERROR: Power removed

PDN bit set

to '1'b

Softw ar e Mode

Regist ers setup to

desired settings.

Hardware Mode

H/W pins setup to

desired settings.

RST = Lo w?

2000 LRCK delay

Power-Up

1. VQ = VA/2.

2. Aout bias = VQ.

Power-Down

1. VQ discharge to 0 V.

2. Aout bias = Hi-Z.

3. No audio signal generated.

4. Control Port Registers retain

settings.

Power-Down (Power Applied)

1. VQ = 0 V.

2. Aout = Hi-Z.

3. No au dio signal generate d.

4. Control Port Registers re s et

to default.

Figure 11. Audio Output Initialization Flow Chart

CS42438

6.3.3 Digital Volume Control

Hardware Mode

DAC Volume Control and Mute are not accessible in Hardware Mode.

Software Mode

Each DAC’s output level is controlled via the Volume Control registers operating over the rang e

of 0 to -127.5 dB attenuation with 0.5 dB resolution. See “AOUTX Volume Control (addresses

08h- 0Fh)” on page 48. Volume control changes are programmable to ramp in increments of

0.125 dB at the rate controlled by the SZC[1:0] bits in the Digital Volume Control register. See

“Transition Control (address 06h)” on page 46.

Each output can be independently muted via mute control bits in the register “DAC Channel

Mute (address 07h)” on page 48. When enabled, each AOUTx_MUTE bit attenuates the corre-

sponding DAC to its maximum value (-127.5 dB). When the AOUTx_MUTE bit is disabled, the

corresponding DAC returns to the attenuation level set in the Volume Control register. The at-

tenuation is ramped up and down at the rate specified by the SZC[1:0] bits.

6.4 System Clocking

The CODEC serial audio interface ports operate as a slave and accept externally generated clocks.

The CODEC requires external generation of the master clock (MCLK). The frequency of this clock must

be an integer multiple of, and synchronous with, the system sample rate, Fs.

Hardware Mode

The allowable ratios include 256F s and 512Fs in Single-Speed Mo de and 256Fs in Double-Speed Mode.

The frequency of MCLK must be specified using the MFREQ (pin 3). See Table 5 below for the required

frequency range.

Ratio (xFs)

MFREQ Description SSM DSM QSM

01.5360 MHz to 12.8 000 MHz 256 N/A N/A

12.0480 MHz to 25.6000 MHz 512 256 N/A

Table 5. MCLK Frequency Settings

AOUTx+

AOUTx-

Full-Scale Differential Output Level =

(AOUTx+) - (AOUTx-) = 6.5 VPP = 2.3 VRMS

4.125 V

2.5 V

0.875 V

5.0 V

4.125 V

2.5 V

0.875 V

Figure 12. Full-Scale Output

CS42438

Software Mode

The frequency range of MCLK must be specified using the MFREQ bits in register “MCLK Frequency

(MFreq[2:0])” on page 44.

6.5 CODEC Digital Interface

The ADC and DAC serial ports operate as a slave and support the TDM digital interface formats with vary-

ing bit depths from 16 to 32 as shown in Figure 13. Data is clocked out of the ADC on the falling edge of

SCLK and clocked into the DAC on the rising edge. TDM is the only mode supported in hardware and

software mode.

6.5.1 TDM

Data is received most significant bit first on the first SCLK after an FS transition and is valid on

the rising edge of SCLK. SCLK must operate at 256Fs. FS identifies the start of a new frame

and is equal to the sample rate, Fs. FS is sampled as valid on the rising SCLK edge preceding

the most significant bit of the first data sample and must be held valid for at least 1 SCLK period.

Each time slot is 32 bits wide, with the valid data sample left justified within the time slot. Valid

data lengths are 16, 18, 20, or 24.

6.5.2 I/O Channel Allocation

6.6 AUX Port Digital Interface Formats

These serial data lines are used when supporting the TDM Mode of operation with an external ADC or

S/PDIF receiver attached. The AUX serial port operates only as a clock master. The AUX_SCLK will op-

erate at 64xFs, where Fs is equal to the ADC sample rate (FS on the TDM interface). If the AUX_SDIN

signal is not being used, it should be tied to AGND via a pull-down resistor.

Hardware Mode

The AUX port will only operate in the Left Justified digital interface format and supports bit dept hs ranging

from 16 to 24 bits (see figure 15 on page 35 for timing relationship between AUX_LRCK and AUX_SCLK).

Software Mode

The AUX port will operate in either the Left Justified or I²S digital interface format with bit depths ranging

from 16 to 24 bits. Settings for the AUX port are made through the register “Interface Formats (address

04h)” on page 44.

Digital

Input/Output Interface

Format Analog Output/Input Channe l Allocation

from/to Digital I/O

DAC_SDIN TDM AOUT 1,2,3,4,5,6,7,8

ADC_SDOUT TDM AIN 1,2,3,4,5,6; (2 additional channels from AUX_SDIN)

Table 6. Serial Audio Interface Ch annel Allocations

AIN6/AOUT6

SCLK

LSBMSB LSBMSB LSBMSB LSBMSB LSBMSB LSBMSB

ADC_SDOUT/

DAC_SDIN AIN1/AOUT1 AIN4/AOUT4AIN2/AOUT2 AIN5/AOUT5AIN3/AOUT3

32 clks 32 clks 32 clks 32 cl ks 32 clk s 32 cl ks

AUX2/AOUT8

LSBMSB LSBMSB

AUX1/AOUT7

32 clks 32 clks

FS 256 clks

MSB

Bit or Word Wide

LSB

Figure 13. TDM Serial Audio Format

CS42438

6.6.1 I²S

6.6.2 Left Justified

AUX_LRCK

AUX_SCLK

MSB LSB MSB LSB

AUX1

Left Channel Right Channel

AUX_SDIN

AUX2

MSB

Figure 14. AUX I²S Format

AUX_LRCK

AUX_SCLK

MSB LSB MSB LSB

AUX1

Left Channel Right Channel

AUX_SDIN

AUX2

MSB

Figure 15. AUX Left Justified Format

CS42438

6.7 Control Port Description and Timing

The control port is used to access the registers, in software mode, allowing the CS42438 to be configured

for the desired operational modes and formats. The operation of the control port may be comp letely asyn-

chronous with respect to the audio sample rates. However, to avoid potential interference problems, the

control port pins should remain static if no operation is required.

The control port has 2 modes: SPI and I²C, with the CS42438 acting as a slave device. SPI mode is se-

lected if there is a high to low transition on the AD0/CS pin, after the RST pin has been brought high. I²C

mode is selected by connecting the AD0/CS pin through a resistor to VLC or DGND, thereby permanently

selecting the desired AD0 bit address state.

6.7.1 SPI Mode

In SPI mode, CS is the CS4 2438 chip select signal, CCL K is the control po rt bit clock (input into

the CS42438 from the microcontroller), CDIN is the input data line from the microcontroller, CD-

OUT is the output data line to t he microcontroller. Data is clocke d in on the rising edge of CCLK

and out on the falling edge.

Figure 16 shows the operation of the control port in SPI mode. To write to a register, bring CS

low. The first seven bits on CDIN fo rm the chip address a nd must be 1001111 . The eighth bit is

a read/write indicator (R/W), which should be low to write. The next eight bits form the Memory

Address Pointer (MAP), which is set to the address of the register that is to be updated. The next

eight bits are the data which will be placed into the register designated by the MAP. During

writes, the CDOUT output stays in the Hi-Z state. It may be externally pulled high or low with a

47 kΩ resistor, if desired.

There is a MAP auto increment capability, enabled by the INCR bit in the MAP register. If INCR

is a zero, the MAP will stay constant for succe ssive read or writes. If INCR is set to a 1, the MAP

will autoincrement after each byte is read or written, allowing block reads or writes of successive

registers.

To read a register, the MAP has to be set to the correct address by executing a partial write cycle

which finishes (CS high) immediately after the MAP byte. The MAP auto increment bit (INCR)

may be set or not, as desired. To begin a read, bring CS low, send out the chip address and set

the read/write bit (R/W) high. The next falling edge of CCLK will clock out the MSB of the ad-

MAP

MSB LSB

DATA

byte 1 byte n

R/W R/W

ADDRESS

CHIP

ADDRESS

CHIP

CDIN

CCLK

CDOUT MSB LSB MSB LSB

1001111

MAP = Memory Address Pointer, 8 bits, MSB first

High Impedance

Figure 16. Control Port Timing in SPI Mode

CS42438

dressed register (CDOUT will leave the high impedance state). If the MAP auto increment bit is

set to 1, the data for successive registers will appear consecutively.

6.7.2 I²C Mode

In I²C mode, SDA is a bidirectional data line. Data is clocked into and out o f the part by the clock,

SCL. There is no CS pin. Pins AD0 and AD1 form the two least significant bits of the chip ad-

dress and should b e connected through a re sistor to VLC or DGND as desired. The state of the

pins is sensed while the CS42438 is being reset.

The signal timings for a read and write cycle are shown in Figure 17 and Figure 18. A Start con-

dition is defined as a falling transition of SDA wh ile the clock is high. A Stop condition is a rising

transition while the clock is high. All other transitions of SDA occur while the clock is low. The

first byte sent to the CS42438 after a Start condition consists of a 7 bit chip address field and a

R/W bit (high for a read, low for a write). The upper 5 bits of the 7-bit address field are fixed at

10011. To communicate with a CS42438, the chip address field, which is the first byte sent to

the CS42438, should match 10011 followed by the settings of the AD1 and AD0 . The eighth bit

of the address is the R/W bit. If the operation is a write, the next byte is the Memory Address

Pointer (MAP) which selects the register to be read or written. If the operation is a read, the con-

tents of the register pointed to by the MAP will be output. Setting the au to increme nt bit in MAP

allows successive reads or writes of consecutive registers. Each byte is separated by an ac-

knowledge bit. The ACK bit is output from the CS42438 after each input byte is read, and is input

to the CS42438 from the microcontroller after each transmitted byte.

Since the read operation can not set the MAP, an aborted write operation is used as a preamble.

As shown in Figure 18, the write operation is aborted after the acknowledge for the MAP byte

by sending a stop condition. The following p seudocode illustrates an aborted write operation fol-

lowed by a read operation.

Send start condition.

Send 10011xx0 (chip address & write operation).

Receive acknowledge bit.

4 5 6 7 24 25

SCL

CHIP ADDRESS (WRITE) MAP BYTE DATA DATA +1

START

ACK STOP

ACKACKACK

1 0 0 1 1 AD1 AD0 0

SDA INCR 6 5 4 3 2 1 0 7 6 1 0 7 6 1 0 7 6 1 0

0 1 2 3 8 9 12 16 17 18 1910 11 13 14 15 27 28

DATA +n

Figure 17. Control Port Timing, I²C Write

SCL

CHIP ADDRESS (WRITE) MAP BYTE DATA DATA +1

START ACK

STOP

ACK

1 0 0 1 1 AD1 AD0 0

SDA 1 0 0 1 1 AD1 AD0 1

CHIP ADDRESS (READ)

START

INCR 6 5 4 3 2 1 0 7 0 7 0 7 0

168 9 12 13 14 154 5 6 7 0 1 20 21 22 23 24 26 27 28

2 3 10 11 17 18 19 25

ACK

DATA + n

STOP

Figure 18. Control Port Timing, I²C Read

CS42438

Send MAP byte, auto increment off.

Receive acknowledge bit.

Send stop condition, aborting write.

Send start condition.

Send 10011xx1(chip address & read operation).

Receive acknowledge bit.

Receive byte, contents of selected register.

Send acknowledge bit.

Send stop condition.

Setting the auto-increment bit in the MAP allows successive reads or writes of consecutive reg-

isters. Each byte is separated by an acknowledge bit.

6.8 Recommended Power-up Sequence

6.8.1 Hardware Mode

1) Hold RST low until the power supply and hardware control pins are stable. In this state, the

control port is reset to its default settings and VQ will remain low.

2) Bring RST high. The device will initially be in a low power state with VQ low.

3) Start MCLK to the appropriate frequency, as discussed in section 6.4 on page 33.

4) The device will initiate the hardware mode power up sequence. All features will default to the

hardware mode defaults as listed in Table 2 on page 27 according to the hardware mode control

pins. VQ will quick-charge to approximately VA/2 and the analog output bias will clamp to VQ.

5) Apply LRCK, SCLK and SDIN. Following approximately 2000 sample periods, the device is

initialized and ready for normal operation.

NOTE: During the H/W mode power up sequence, there must be no transitions on any of the

hardware control pins.

6.8.2 Software Mode

1) Hold RST low until the power supply is stable. In this state, the control port is reset to its de-

fault settings and VQ will remain low.

2) Bring RST high. The device will initially be in a low power state with VQ low. All features will

default as described in the “Register Quick Reference” on page 40.

3) Perform a write operation to the Power Control register (“Power Control (address 02h)” on

page 43) to set bit 0 to a ‘1’b. This will place the device in a power down state.

4) Load the desired register settings while keeping the PDN bit set to ‘1’b.

5) Start MCLK to the appropriate frequency, as discussed in section 6.4 on page 33. The device

will initiate the software mode power up sequence.

6) Set the PDN bit in the power control register to ‘0’b.

7) Apply LRCK, SCLK and SDIN. Following approximately 2000 sample periods, the device is

initialized and ready for normal operation.

6.9

Reset and Power-up

It is recommended that reset be activated if the analog or digital supplies drop below the recommended

operating condition to prevent power glitch related issues.

CS42438

The Delta-Sigma modulators settle in a matter of microseconds after the analog section is powered, either

through the application of power or by setting the RST pin high. However, the voltage reference will take

much longer to reach a final value due to the presence of external capacitance on the FILT+ pin. A time

delay of approximately 400 ms is required after applying power to the device or after e xiting a reset state.

During this voltage reference ramp delay, all serial ports and DAC outputs will be automatically muted.

6.10 Power Supply, Grounding, and PCB layout

As with any high resolution converter, the CS42438 requires careful attention to power supply and ground-

ing arrangements if its potential performance is to be realized. Figures 1 to 2 show the recommended

power arrangements, with VA connected to clean supplies. VD, which powers the digital circuitry, may be

run from the system logic supply.

Extensive use of power and ground planes, ground plane fill in unused areas and surface mount decou-

pling capacitors are recommended. Decoupling capacitors should be as near to the pins of the CS42438

as possible. The low value ceramic capacitor should be the nea rest to the pin and should be mou nted on

the same side of the board as the CS42438 to min imize inductance effects. All signals, especially clocks,

should be kept away from the FILT+, VQ pins in order to avoid unwanted coupling into the modulators.

The FILT+ and VQ decoupling capacitors, particularly the 0.1 µF, must be positioned to minimize the elec-

trical path from FILT+ and AGND. The CDB42438 evaluation board demonstrates the optimum layout and

power supply arrangements.

For optimal heat dissipation from the package, it is recommended that the area directly under the pa rt be

filled with copper and tied t o the ground plane. The use of vias connecting the topside ground to the back-

side ground is also recommended.

CS42438
40
7 REGISTER QUICK REFERENCE 
Software Mode register defaults are as shown.
Addr Function 7 6 5 4 3 2 1 0
01h ID Chip_ID3 Chip_ID2 Chip_ID1 Chip_ID0 Rev_ID3 Rev_ID2 Rev_ID1 Rev_ID0
p42  default 10110001
02h Power Con-
trol PDN_ADC3 PDN_ADC2 PDN_ADC1 PDN_DAC4 PDN_DAC3 PDN_DAC2 PDN_DAC1 PDN
p43 default 0 0 0 0 0 0 0 0
03h Functional 
Mode Reserved Reserved Reserved Reserved MFreq2 MFreq1 MFreq0 Reserved
p44 default 1 1 1 1 0 0 0 0
04h Misc Control FREEZE AUX_DIF Reserved Reserved Reserved Reserved Reserved Reserved
p44 default 00110110
05h ADC Control
(w/DAC_DEM) ADC1-2_HPF 
FREEZE ADC3_HPF 
FREEZE DAC_DEM ADC1
SINGLE ADC2
SINGLE ADC3
SINGLE AIN5_MUX AIN6_MUX
p45 default 00000000
06h Transition 
Control DAC_SNG
VOL DAC_SZC1 DAC_SZC0 AMUTE MUTE 
ADC_SP ADC_SNG
VOL ADC_SZC1 ADC_SZC0
p46 default 00000000
07h Channel 
Mute AOUT8 
MUTE AOUT7 
MUTE AOUT6 
MUTE AOUT5 
MUTE AOUT4 
MUTE AOUT3 
MUTE AOUT2 
MUTE AOUT1 
MUTE
p48 default 0 0 0 0 0 0 0 0
08h Vol. Control 
AOUT1 AOUT1
 VOL7 AOUT1 
VOL6 AOUT1 
VOL5 AOUT1 
VOL4 AOUT1 
VOL3 AOUT1 
VOL2 AOUT1 
VOL1 AOUT1 
VOL0
p48 default 00000000
09h Vol. Control 
AOUT2 AOUT2 
VOL7 AOUT2 
VOL6 AOUT2 
VOL5 AOUT2 
VOL4 AOUT2 
VOL3 AOUT2
VOL2 AOUT2 
VOL1 AOUT2 
VOL0
p48 default 00000000
0Ah Vol. Control 
AOUT3 AOUT3 
VOL7 AOUT3 
VOL6 AOUT3 
VOL5 AOUT3 
VOL4 AOUT3 
VOL3 AOUT3 
VOL2 AOUT3 
VOL1 AOUT3 
VOL0
p48 default 00000000
0Bh Vol. Control 
AOUT4 AOUT4 
VOL7 AOUT4 
VOL6 AOUT4 
VOL5 AOUT4 
VOL4 AOUT4 
VOL3 AOUT4 
VOL2 AOUT4 
VOL1 AOUT4 
VOL0
p48 default 00000000
0Ch Vol. Control 
AOUT5 AOUT5 
VOL7 AOUT5 
VOL6 AOUT5 
VOL5 AOUT5 
VOL4 AOUT5 
VOL3 AOUT5 
VOL2 AOUT5 
VOL1 AOUT5 
VOL0
p48 default 00000000
0Dh Vol. Control 
AOUT6 AOUT6 
VOL7 AOUT6 
VOL6 AOUT6 
VOL5 AOUT6 
VOL4 AOUT6 
VOL3 AOUT6 
VOL2 AOUT6 
VOL1 AOUT6 
VOL0
p48 default 00000000
0Eh Vol. Control 
AOUT7 AOUT7 
VOL7 AOUT7 
VOL6 AOUT7 
VOL5 AOUT7 
VOL4 AOUT7 
VOL3 AOUT7 
VOL2 AOUT7 
VOL1 AOUT7 
VOL0
p48 default 00000000
0Fh Vol. Control 
AOUT8 AOUT8 
VOL7 AOUT8 
VOL6 AOUT8 
VOL5 AOUT8 
VOL4 AOUT8 
VOL3 AOUT8 
VOL2 AOUT8 
VOL1 AOUT8 
VOL0
p48 default 00000000
10h DAC Chan-
nel Invert INV_AOUT8 INV_AOUT7 INV_AOUT6 INV_AOUT5 INV_AOUT4 INV_AOUT3 INV_AOUT2 INV_AOUT1
p49 default 00000000

41
CS42438
11h Vol. Control
AIN1  AIN1
VOL7 AIN1
VOL6 AIN1
VOL5 AIN1
VOL4 AIN1
VOL3 AIN1
VOL2 AIN1
VOL1 AIN1
VOL0
p48 default 00000000
12h Vol. Control
AIN2  AIN2
VOL7 AIN2
VOL6 AIN2
VOL5 AIN2
VOL4 AIN2
VOL3 AIN2
VOL2 AIN2
VOL1 AIN2
VOL0
p49 default 00000000
13h Vol. Control
AIN3  AIN3
VOL7 AIN3
VOL6 AIN3
VOL5 AIN3
VOL4 AIN3
VOL3 AIN3
VOL2 AIN3
VOL1 AIN3
VOL0
p48 default 00000000
14h Vol. Control
AIN4  AIN4
VOL7 AIN4
VOL6 AIN4
VOL5 AIN4
VOL4 AIN4
VOL3 AIN4
VOL2 AIN4
VOL1 AIN4
VOL0
p49 default 00000000
15h Vol. Control
AIN5  AIN5
VOL7 AIN5
VOL6 AIN5
VOL5 AIN5
VOL4 AIN5
VOL3 AIN5
VOL2 AIN5
VOL1 AIN5
VOL0
p48 default 00000000
16h Vol. Control
AIN6  AIN6
VOL7 AIN6
VOL6 AIN6
VOL5 AIN6
VOL4 AIN6
VOL3 AIN6
VOL2 AIN6
VOL1 AIN6
VOL0
p49 default 00000000
17h ADC Chan-
nel Invert Reserved Reserved INV_A6 INV_A5 INV_A4 INV_A3 INV_A2 INV_A1
p49 default 00000000
18h Status Con-
trol Reserved Reserved Reserved Reserved Reserved Reserved MODE1 MODE0
p50 default 00000000
19h Status Reserved Reserved Reserved Reserved CLK
Error ADC3
OVFL ADC2
OVFL ADC1
OVFL
p50 default 000XXXXX
1Ah Status Mask Reserved Reserved Reserved Reserved CLK
Error_M ADC3 
OVFL_M ADC2 
OVFL_M ADC1 
OVFL_M
p51 default 00000000
Addr Function 7 6 5 4 3 2 1 0

CS42438

8 REGISTER DESCRIPTION

All registers are read/write except for the I.D. and Revision Register and Interr upt Status Register which

are read only. See the following bit definition tables for bit assignment information. The default state of

each bit after a power-up sequence or reset is listed in each bit description.

8.1 MEMORY ADDRESS POINTER (MAP)

Not a register

8.1.1 INCREMENT(INCR)

Default = 1

Function:

Memory address pointer auto increment control

0 - MAP is not incremented automatically.

1 - Internal MAP is automatically incremented afte r each read or write.

8.1.2 MEMORY ADDRESS POINTER (MAP[6:0])

Default = 0000001

Function:

Memory address pointer (MAP). Sets the register address that will be read or written by the control

port.

8.2 CHIP I.D. AND REVISION REGISTER (ADDRESS 01H) (READ ONLY)

8.2.1 CHIP I.D. (CHIP_ID[3:0])

Default = 0000

Function:

I.D. code for the CS42438. Permanently set to 0000.

8.2.2 CHIP REVISIO N (REV_ ID[3:0])

Default = 0001

Function:

CS42438 revision level. Revision A is coded as 0001.

76543210

INCR MAP6 MAP5 MAP4 MAP3 MAP2 MAP1 MAP0

76543210

Chip_ID3 Chip_ID2 Chip_ID1 Chip_ID0 Rev_ID3 Rev_ID2 Rev_ID1 Rev_ID0

CS42438

8.3 POWER CONTROL (ADDRESS 02H)

8.3.1 POWER DOWN ADC PAIRS(PDN_ADCX)

Default = 0

0 - Disable

1 - Enable

Function:

When enabled, the resp ective ADC channel pair ( ADC1 - AIN1/AIN2; ADC2 - AIN3/AIN4; and ADC3

- AIN5/AIN6) will remain in a reset state.

8.3.2 POWER DOWN DAC PAIRS (PDN_DACX)

Default = 0

0 - Disable

1 - Enable

Function:

When enabled, the respective DAC channel pair (DAC1 - AOUT1/AOUT2; DAC2 - AOUT3/AOUT4;

DAC3 - AOUT5/AOUT6; and DAC4 - AOUT7/AOUT8) will remain in a reset state. It is advised that

any change of these bits be made wh ile the DACs are muted or the power down bit (PDN) is enabled

to eliminate the possibility of audible artifacts.

8.3.3 POWER DOWN (PDN)

Default = 0

0 - Disable

1 - Enable

Function:

The entire device will enter a low-power state when this function is enabled. The contents of the con-

trol registers ar e re ta ine d in th is mo de .

76543210

PDN_ADC3 PDN_ADC2 PDN_ADC1 PDN_DAC4 PDN_DAC3 PDN_DAC2 PDN_DAC1 PDN

CS42438

8.4 FUNCTIONAL MODE (ADDRESS 03H)

8.4.1 MCLK FREQUENCY (MFREQ[2:0])

Default = 000

Function:

Sets the appropriate fr equency for the suppli ed MCLK. For TDM operation, SCLK must equal 256Fs.

MCLK can be equal to or greater than SCLK.

8.5 INTERFACE FORMATS (ADDRESS 04H)

8.5.1 FREEZE CONTROLS (FREEZE)

Default = 0

Function:

This function will freeze the previous settings of, and allow modifications to be made to the channel

mutes, the DAC and ADC Volume Control/Channel Invert registers wit hout the changes taking effect

until the FREEZE is disabled . To hav e multiple changes in these control port registers take effect si-

multaneously, enable the FREEZE bit, make all register changes, then disable the FREEZE bit.

8.5.2 AUXILIARY DIGITAL INTERFACE FORMAT (AUX_DIF)

Default = 0

0 - Left Justified

1 - I²S

Function:

This bit selects the digital interface format use d for the AUX Serial Port. The re quired relationship be-

tween the Left/Right clock, serial clock and serial data is defined by the Digital Interface Format and

the options are detailed in Figures 14-15.

76543210

Reserved Reserved Reserved Reserved MFreq2 MFreq1 MFreq0 Reserved

Ratio (xFs)

MFreq2 MFreq1 MFreq0 Description SSM DSM QSM

000

1.0290 MHz to 12.8000 MHz 256 N/A N/A

001

1.5360 MHz to 19.2000 MHz 384 N/A N/A

010

2.0480 MHz to 25.6000 MHz 512 256 N/A

011

3.0720 MHz to 38.4000 MHz 768 384 N/A

1XX

4.0960 MHz to 51.2000 MHz 1024 512 256

Table 7. MCLK Frequency Settings

76543210

FREEZE AUX_DIF Reserved Reserved Reserved Reserved Reserved Reserved

CS42438

8.6 MISC CONTROL (ADDRESS 05H)

8.6.1 ADC1-2 HIGH PASS FILTER FREEZE (ADC1-2_HPF FREEZE)

Default = 0

Function:

When this bit is set, the internal high-pass filter will be disabled for ADC1 and ADC2.The current DC

offset value will be frozen and continue to be subtracted from the conversion result. See “ADC Digital

Filter Characteristics” on page 16.

8.6.2 ADC3 HIGH PASS FILTER FREEZE (ADC3_HPF FREEZE)

Default = 0

Function:

When this bit is set, the internal high-pass filter will be disabled for ADC3.The current DC offset value

will be frozen and continue to be subtracted from the conversion result. See “ADC Digital Filter Char-

acteristics” on page 16.

8.6.3 DAC DE-EMPHASIS CONTROL (DAC_DEM)

Default = 0

0 - No De-Emphasis

1 - De-Emphasis Enabled (Auto-De tect Fs)

Function:

Enables the digital filter to maintain the standard 15µs/50µs digital de-empha sis filter response at the

auto-detected sample rate of either 32, 44.1, or 48 kHz. De-emphasis will not be enabled, regardless

of this register sett ing , at any other sample rate.

8.6.4 ADC1 SINGLE-EN DED MODE (AD C1 SINGLE)

Default = 0

0 - Disabled; Differential input to ADC1

1 - Enabled; Single-Ended input to ADC1

Function:

When enabled, this bit allows the user to apply a single- ended input to the positive terminal of ADC1.

+6 dB digital gain is automatically applied to the serial audio data of ADC1. The negative leg must be

driven to the common mode of the ADC. See Figure 20 on pag e 56 for a graphical description.

8.6.5 ADC2 SINGLE-EN DED MODE (AD C2 SINGLE)

Default = 0

0 - Disabled; Differential input to ADC2

1 - Enabled; Single-Ended input to ADC2

76543210

ADC1-2_HPF

FREEZE ADC3_HPF

FREEZE DAC_DEM ADC1

SINGLE ADC2

SINGLE ADC3

SINGLE AIN5_MUX AIN6_MUX

CS42438

Function:

When enabled, this bit allows the user to apply a single- ended input to the positive terminal of ADC2.

+6 dB digital gain is automatically applied to the serial audio data of ADC2. The negative leg must be

driven to the common mode of the ADC. See Figure 20 on page 56 for a graphical description.

8.6.6 ADC3 SINGLE-EN DED MODE (AD C3 SINGLE)

Default = 0

0 - Disabled; Differential input to ADC

1 - Enabled; Single-Ended input to ADC

Function:

When disabled, this bit re moves the 4:2 multip lexer from the signal path of ADC3 allowin g a differen-

tial input. When enabled, this bit allows the user to choose between 4 single-ended inputs to ADC3,

using the AIN5_MUX and AIN6_MUX bits. See Figure 10 on page 29 and Figure 20 on page 56 for

graphical descriptions.

8.6.7 ANALOG INPUT CH. 5 MULTIPLEXER (AIN5_MUX)

Default = 0

0 - Single-Ended Input AIN5 A

1 - Single-Ended Input AIN5 B

Function:

ADC3 can accept single-ended input signals when the ADC3 SINGLE bit is enabled. The AIN5_MUX

bit selects between two inp ut channels (AIN5A or AIN5B) to be sent to ADC3 in sin gle-ende d mode.

This bit is ignored when the ADC3 _SINGLE bit is disabled. See Figure 10 on page 29 for a gr aphical

description.

8.6.8 ANALOG INPUT CH. 6 MULTIPLEXER (AIN6_MUX)

Default = 0

0 - Single-Ended Input AIN6 A

1 - Single-Ended Input AIN6 B

Function:

ADC3 can accept a single-ended input signal when the ADC3 SINGLE bit is enabled. The AIN6_MUX

bit selects between two inp ut channels (AIN6A or AIN6B) to be sent to ADC3 in sin gle-ende d mode.

This bit is ignored when the ADC3 _SINGLE bit is disabled. See Figure 10 on page 29 for a gr aphical

description.

8.7 TRANSITION CONTROL (ADDRESS 06H)

8.7.1 SINGLE VOLUME CONTROL (DAC_SNGVOL, ADC_SNGVOL)

Default = 0

76543210

DAC_SNGVOL DAC_SZC1 DAC_SZC0 AMUTE MUTE ADC_SP ADC_SNGVOL ADC_SZC1 ADC_SZC0

CS42438

Function:

The individual channel volume levels are independently controlled by their respective Volume Control

registers when this function is disabled. When enabled, the volume on all channels is determined by

the AOUT1 and AIN1 Volume Control register and the other Volume Control registers are ignored.

8.7.2 SOFT RAMP AND ZERO CROSS CONTROL (ADC_SZC[1:0], DAC_SZC[1:0])

Default = 00

00 - Immediate Change

01 - Zero Cross

10 - Soft Ramp

11 - Soft Ramp on Zero Crossings

Function:

Immediate Ch an ge

When Immediate Change is selected all volume level changes will take effect immediately in one step.

Zero Cross

Zero Cross Enable dictates that signal level changes, e ither by gain changes, attenuation changes or

muting, will occur on a signal zero crossing to minimize audible artifacts. The requested level change

will occur after a timeout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz

sample rate) if the signal d oes not encounter a zero crossing. T he zero cross function is independen t-

ly monitored and implemented for each channel.

Soft Ramp

Soft Ramp allows level changes, either by gain changes, attenuation changes or muting, to be imple-

mented by incrementally ramping, in 1/8 dB steps, from the current level to the new level at a rate of

1 dB per 8 left/r igh t cloc k pe rio ds .

Soft Ramp on Zero Crossing

Soft Ramp and Zero Cross Enable dictates that signal level changes, either by gain changes, atten-

uation changes or muting, will occur in 1/8 dB steps and be implemented on a signal zero crossing.

The 1/8 dB level change will occur after a timeout period between 512 and 1024 sample periods (10.7

ms to 21.3 ms at 48 kHz sample rate) if the signal does not encounter a zero crossing. The zero cross

function is independently monitored and implemented for each channel.

8.7.3 AUTO-MUTE (AMUTE)

Default = 1

0 - Disabled

1 - Enabled

Function:

The Digital-to-Analog converters of the CS42438 will mute the output following the reception of 8192

consecutive audio samples of static 0 or -1. A single sample of non-static data will release the mute.

Detection and muting is done independently for each channel. The quiescent voltage on the output

will be retained during the mute period. The muting function is affected, similar to volume control

changes, by the Soft and Zero Cross bits (SZC[1:0]).

CS42438

8.7.4 MUTE ADC SERIAL PORT (MUTE ADC_SP)

Default = 0

0 - Disabled

1 - Enabled

Function:

When enabled, the ADC Serial Port will be muted.

8.8 DAC CHANNEL MUTE (ADDRESS 07H)

8.8.1 INDEPENDENT CHANNEL MUTE (AOUTX_MUTE)

Default = 0

0 - Disabled

1 - Enabled

Function:

The respective Digital-to-Analog converter outputs of the CS42438 will mute when enabled. The qui-

escent voltage on the outputs will be retained. The muting function is affected by the DAC Soft and

Zero Cross bits (DAC_SZC[1:0]).

8.9 AOUTX VOLUME CONTROL (ADDRESSES 08H- 0FH)

8.9.1 VOLUME CONTROL (AOUTX_VOL[7:0])

Default = 00h

Function:

The AOUTx Volume Control registers allow independent setting of the signal levels in 0.5 dB incre-

ments from 0 dB to -127.5 dB. Volume settings are decoded as shown in Ta ble 8. The volume chang-

es are implemented as dictated by the Soft and Zero Cross bits (DAC_SZC[1:0]). All volume settings

less than -127.5 dB are equivalent to enabling the AOUTx_MUTE bit for the gi ven channel.

76543210

AOUT8_MUTE AOUT7_MUTE AOUT6_MUTE AOUT5_MUTE AOUT4_MUTE AOUT3_MUTE AOUT2_MUTE AOUT1_MUTE

76543210

AOUTx_VOL7 AOUTx_VOL6 AOUTx_VOL5 AOUTx_VOL4 AOUTx_VOL3 AOUTx_VOL2 AOUTx_VOL1 AOUTx_VOL0

Binary Code Volume Setting

00000000 0 dB

00101000 -20 dB

01010000 -40 dB

01111000 -60 dB

1011010 0 -90 dB

Table 8. Example AOUT Volume Settings

CS42438

8.10 DAC CHANNEL INVERT (ADDRESS 10H)

8.10.1 INVERT SIGNAL POLARITY (INV_AOUTX)

Default = 0

0 - Disabled

1 - Enabled

Function:

When enabled, these bits will invert the signal polarity of their respective channels.

8.11 AINX VOLUME CONTROL (ADDRESS 11H - 16H)

8.11.1 AINX VOLUME CONTROL (AINX_VOL[7:0])

Default = 00h

Function:

The level of AIN1 - AIN6 can be adjusted in 0.5 dB increments as dictated by the ADC Soft and Zero

Cross bits (ADC_SZC[1:0]) from +12 to -115.5 dB. Levels are decoded in two’s complement, as

shown in Table 9.

8.12 ADC CHANNEL INVERT (ADDRESS 17H)

8.12.1 INVERT SIGNAL POLARITY (INV_AINX)

Default = 0

0 - Disabled

1 - Enabled

76543210

INV_AOUT8 INV_AOUT7 INV_AOUT6 INV_AOUT5 INV_AOUT4 INV_AOUT3 INV_AOUT2 INV_AOUT1

76543210

AINx_VOL7 AINx_VOL6 AINx_VOL5 AINx_VOL4 AINx_VOL3 AINx_VOL2 AINx_VOL1 AINx_VOL0

Binary Code Volume Setting

0001 1000 +12 dB

0001 0100 +10 dB

0000 1010 +5 dB

0000 0000 0 dB

1111 1111 -0.5 dB

1111 1110 -1 dB

0001 1010 -115 dB

Table 9. Example AIN Volume Settings

76543210

Reserved Reserved INV_AIN6 INV_AIN5 INV_AIN4 INV_AIN3 INV_AIN2 INV_AIN1

CS42438

Function:

When enabled, these bits will invert the signal polarity of their respective channels.

8.13 STATUS CONTROL (ADDRESS 18H)

8.13.1 ERROR MODE (MODE[1:0])

Default = 00

00 - Rising edge active

01 - Falling edge active

10 - Level active

11 - Reserved

Function:

There are three ways to set the Status flags active in accordance with the error condition. In the Rising

edge active mode, the Status flags become active on the arrival of the error condition. In the Falling

edge active mode, the Status fla gs become active on the removal of the error condition. In Level ac-

tive mode, the Status flags become active during the error condition.

8.14 STATUS (ADDRESS 19H) (READ ONLY)

For all bits in this register, a “1” means the associated error condition has occurred at least once since the register

was last read. A”0” means the associated error condition has NOT occurred since the last reading of the register.

Reading the register resets all bits to 0. Status bits that are masked off in the associated mask register will always

be “0” in this register.

8.14.1 CLOCK ERROR (ADC_CLK ERROR)

Default = x

Function:

Indicates an invalid MCLK to FS ratio. See “System Clocking” on page 33 for valid clock ratios.

8.14.2 ADC OVERFLOW (ADCX_OVFL)

Default = x

Function:

Indicates that there is an over- range conditio n anywhere in the CS42438 ADC signal path of each of

the associated ADC’s.

76543210

Reserved Reserved Reserved Reserved Reserved Reserved MODE1 MODE0

76543210

Reserved Reserved Reserved Reserved CLK Error ADC3_OVFL ADC2_OVFL ADC1_OVFL

CS42438

8.15 STATUS MASK (ADDRESS 1AH)

Default = 0000

Function:

The bits of this register serve as a mask for the error sources found in the register “Status (address

19h) (Read On ly)” on page 50. If a mask bit is set to 1, the error is u nmasked, meanin g that its occur-

rence will affect the status register. If a mask bit is set to 0, the error is masked, meaning that its oc-

currence will not affect status register. The bit positions align with the corresponding bits in the Status

76543210

Reserved Reserved Reserved Reserved CLK Error_M ADC3_OVFL_M ADC2_OVFL_M ADC1_OVFL_M

CS42438

9 PARAMETER DEFINITIONS

Dynamic Range

The ratio of the rms valu e of the signal to the rms sum of all other spectral components o ver the specified

bandwidth. Dynamic Range is a signal-to-noise ratio measurement over the specified band width made

with a -60 dBFS signal. 60 dB is added to r esulting me asur ement to refe r the measurem ent to full-scale .

This technique ensures that th e distortion components are below the noise level and do not affect the

measurement. This measurement technique has been accepted by the Audio Engineering Society,

AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307. Expressed in decibels.

Total Harmonic Distortion + Noise

The ratio of the rms valu e of the signal to the rms sum of all other spectral components o ver the specified

band width (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels. Measured

at -1 and -20 dBFS as suggested in AES17-1991 Annex A.

Frequency Response

A measure of the amplitude response variation from 10 Hz to 20 kHz relative to the amplitude response

at 1 kHz. Units in decibels.

Interchannel Isolation

A measure of crosstalk between the left and right channel pairs. Measured for each channel at the con-

verter's output with no signal to the input under test and a full-scale signal applied to the other channel.

Units in decibels.

Interchannel Gain Mismatch

The gain difference between left and right channel pairs. Units in decibels.

Gain Error

The deviation from the nominal full-scale analog output for a full-scale digital input.

Gain Drift

The change in gain value with temperature. Units in ppm/°C.

Offset Error

The deviation of the mid- scale transition (111...111 to 000...000) from the ideal. Units in mV.

CS42438

10 REFERENCES

1) Cirrus Logic, Audio Quality Measurement Specification, Version 1 .0, 1997.

http://www.cirrus.com/products/papers/meas/meas.html

2) Cirrus Logic, AN18: Layout and Design Rules for Data Converters and Other Mixed Signal Devices,

Version 6.0, February 1998.

3) Cirrus Logic, Techniques to Measure and Maximize the Performance of a 120 dB, 96 kHz A/D Convert-

er Integrated Circuit, by Steven Harris, Steven Green and Ka Leung. Presen ted at the 103rd Convention

of the Audio Engineering Society, September 1997.

4) Cirrus Logic, A Stereo 16-bit Delta-Sigma A/D Converter for Digital Audio, by D.R. Welland, B.P. Del

Signore, E.J. Swanson, T. Tanaka, K. Hamashita, S. Hara, K. Takasuka. Paper presented at the 85th

Convention of the Audio Engineering Society, November 1988.

5) Cirrus Logic, The Effects of Sampling Clock Jitter on Nyquist Sampling Analog-to-Digital Converters,

and on Oversampling Delta Sigma ADC's, by Steven Harris. Paper presented at the 87th Convention of

the Audio Engineering Society, October 1989.

6) Cirrus Logic, An 18-Bit Dual-Channel Oversampling Delta-Sigma A/D Converter, with 19-Bit Mono Ap-

plication Example, by Clif Sanchez. Paper presented at the 87th Convention of the Audio Engineering So-

ciety, October 1989.

7) Cirrus Logic, How to Achieve Optimum Performance from Delta-Sigma A/D and D/A Converters,by

Steven Harris. Presented at the 93rd Convention of the Audio Engineering Society, October 1992.

8) Cirrus Logic, A Fifth-Order Delta-Sigma Modulator with 110 dB Audio Dynamic Range, by I. Fujimori,

K. Hamashita and E.J. Swanson. Paper presented at the 93rd Convention of the Audio Engineering So-

ciety, October 1992.

9) Philips Semiconductor, The I²C-Bus Specification: Version 2.1, January 2000. http://www.semiconduc-

tors.philips.com

CS42438

11 PACKAGE DIMENSIONS

INCHES MILLIMETERS

DIM MIN NOM MAX MIN NOM MAX

A --- --- 0.096 --- --- 2.45

A1 0.000 --- 0.010 0.00 --- 0.25

B 0.009 --- 0.016 0.22 --- 0.40

D --- 0.519 --- --- 13.20 BSC ---

D1 --- 0.394 --- --- 10.00 BSC ---

E --- 0.519 --- --- 13.20 BSC ---

E1 --- 0.394 --- --- 10.00 BSC ---

e* --- 0.026 --- --- 0.65 BSC ---

L 0.029 0.035 0.041 0.73 0.88 1.03

∝0.00° 4° 7.00° 0.00° 4° 7.00°

* Nominal pin pitch is 0.65 mm

Controlling dimension is mm.

JEDEC Designation: MS022

∝

52L MQFP PACKAGE DRAWING

CS42438

THERMAL CHARACTERISTICS

Parameter Symbol Min Typ Max Units

Junction to Ambient Thermal Impedance 2 Layer Board

4 Layer Board θJA

θJA

-47

38 -

-°C/Watt

°C/Watt

CS42438

12 APPENDIX A: EXTERNAL FILTERS

12.1 ADC Input Filter

The analog modula tor samples the input at 6. 144 MHz (internal MCLK=12.288 MHz). The digita l filter will

reject signals within the stopband of the filter. However, there is no rejection for input signals which are

multiples of the digital passband frequency (n ×6.144 MHz), where n=0,1,2,... Refer to Figures 19 and 20

for a recommended analog input filter that will attenuate any noise energy at 6.144 MHz, in addition to

providing the optimum source imped ance for the modulators. Refer to Figures 21 and 22 for low cost, low

component count passive input filters. The use o f capacitors wh ich have a large voltage coe fficient (such

as general purpose ceramics) must be avoided since these can degrade signal linearity.

4.7 µF

100 kΩ10 kΩ

100 kΩ

0.1 µF 100 µF

470 pF

C0G

634 Ω

91 Ω

2700 pF

C0G

332 Ω

AINx+

AINx-

ADC1-3

Figure 19. Single to Differential Active Input Filter

470 pF

C0G

634 Ω

91 Ω

2700 pF

C0G

4.7 µF

100 kΩ

4.7 µF

AIN1+,2+,3+,4+

AIN1-,2-,3-,4-

ADC1-2

ADC3

470 pF

C0G

634 Ω

91 Ω

2700 pF

C0G

4.7 µF

100 kΩ

AIN5A,6A

470 pF

C0G

634 Ω

91 Ω

2700 pF

C0G

4.7 µF

100 kΩ

AIN5B,6B

Figure 20. Single-Ended Active Input Filter

CS42438

12.1.1 Passive Input Filter

The passive filter implementation shown in Figure 21 will attenuate any noise energy at

6.144 MHz but will not provide op timum source impedance for th e ADC modulators. Full analog

performance will therefore not be realized using a passive filter. Figure 21 illustrates the unity

gain, passive input filter solution. In this topology the distortion performance is affected, but the

dynamic range performance is not limited.

12.1.2 Passive Input Filter w/Attenuation

Some applications may require signal attenuation prior to the ADC. The full-scale inp ut voltage

will scale with the analog power supply voltage. For VA = 5.0 V, the full-scale input voltage is

approximately 2.8 Vpp, or 1 Vrms (most consumer audio line level outputs range from 1.5 to

2Vrms).

Figure 22 shows a passive input filter with 6 dB of signal attenuation. Due to th e re latively h igh

input impedance on the analog inputs, the full d ist ortion performance ca nnot be realized . Also,

the resistor divider circuit will determine the input impedance into the input filter. In the circuit

shown in Figure 22, the input impedance is approximately 5 kΩ. By doubling the resistor values,

the input impedance will increase to 10 kΩ. However , in this case the distortion performance will

drop due to the increase in series resistance on the analog inputs.

2700 pF

C0G

10 µF

100 kΩ

150 ΩAIN1+,2+,3+,4+

AIN1-,2-,3-,4-

ADC1-2

100 kΩ

4.7 µF

AIN5A,6A

AIN5B,6B

ADC3

2700 pF

C0G

10 µF

100 kΩ

150 Ω

2700 pF

C0G

10 µF

100 kΩ

150 Ω

Figure 21. Passive Input Filter

CS42438

2700 pF

C0G

10 µF

2.5 kΩ

100 kΩ

2.5 kΩAIN1+,2+,3+,4+

AIN1-,2-,3-,4-

ADC1-2

100 kΩ

4.7 µF

2700 pF

C0G

10 µF

2.5 kΩ

100 kΩ

2.5 kΩAIN5A,6A

AIN5B,6B

ADC3

2700 pF

C0G

10 µF

2.5 kΩ

100 kΩ

2.5 kΩ

Figure 22. Passive Input Filter w/Attenuation

CS42438

12.2 DAC Output Filter

The CS42438 is a linear phase design and does n ot include phase or amp litude compensa tion for an ex-

ternal filter. Therefore, the DAC system phase and amplitude response will be depende nt on the external

analog circuitry. Shown below is the recommended active and passive output filters.

AOUTx +

AOUTx - -

390 pF

C0G 562Ω

22 µF

4.75 k Ω

1800 pF

C0G

887 Ω

2.94 kΩ

5.49 kΩ

1.65 kΩ

1.87 kΩ22 µF

1200 pF

C0G

5600 pF

C0G

47.5 k Ω

DAC1-4

Figure 23. Active Analog Output Filter

AOUTx+

3.3 µF

560 Ω

10 kΩRext

Rext

+ 560

C= 4πFSRext

560

DAC1-4

Figure 24. Passive Analog Output Filter

CS42438

13 APPENDIX B: ADC FILTER PLOTS

-140

-130

-120

-110

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

0.00.10.20.30.40.50.60.70.80.91.0

Frequency (normalized to Fs)

Amp litud e (d B )

-140

-130

-120

-110

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

0.40 0.42 0.44 0.46 0.48 0.50 0.52 0.54 0.56 0.58 0.60

Frequency (normalized to Fs)

Amplitude ( dB

)

Figure 25. Single Speed Mode Stopband Rejec-

tion Figure 26. Single Speed Mode Transition Band

-10

-9

-8

-7

-6

-5

-4

-3

-2

-1

0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.55

Freque nc y (normalized to Fs)

Amplitude (dB)

-0.10

-0.08

-0.06

-0.04

-0.02

0.00

0.02

0.04

0.06

0.08

0.10

0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5

Frequency (normalized to Fs)

Amplitude (dB)

Figure 27. Single Speed Mode Transition Band (De-

tail) Figure 28. Single Speed Mode Passband Ripple

-140

-130

-120

-110

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

Frequency (normalized to Fs )

Amplitude (dB

)

-140

-130

-120

-110

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

0.40 0.42 0.44 0.46 0.48 0.50 0.52 0.54 0.56 0.58 0.60

Frequency (normalized to Fs)

Am pli tu d e (dB)

Figure 29. Double Speed Mode Stopband Rejection Figure 30. Double Speed Mode Transition Band

CS42438

‘

-0.10

-0.08

-0.06

-0.04

-0.02

0.00

0.02

0.04

0.06

0.08

0.10

0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50

Frequency (normalized to Fs )

Amplitude (dB)

-10

-9

-8

-7

-6

-5

-4

-3

-2

-1

0.46 0.47 0.48 0.49 0.50 0.51 0.52

Frequency (normalized to Fs)

Amplitude (dB

)

Figure 31. Double Speed Mode Transition Band

(Detail) Figure 32. Double Speed Mode Passband Ripple

-140

-130

-120

-110

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

Fr equency (normalize d to Fs )

Amplitude ( dB)

-140

-130

-120

-110

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.60 0.65 0.70 0.75 0.80 0.85

Fr equency (normalize d to Fs)

Amplitud e (dB)

Figure 33. Quad Speed Mode Stopband Rejection Figure 34. Quad Speed Mode Transition Band

-0.10

-0.08

-0.06

-0.04

-0.02

0.00

0.02

0.04

0.06

0.08

0.10

0.00 0.03 0.05 0.08 0.10 0.13 0.15 0.18 0.20 0.23 0.25 0.28

Frequency (normalized to Fs)

Amplitude (dB)

Figure 35. Quad Speed Mode Transition Band (De- tail)

Figure 36. Quad Speed Mode Passband Ripple

-10

-9

-8

-7

-6

-5

-4

-3

-2

-1

0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50

Frequency (normalized to Fs)

Am p li tu d e (d B)

CS42438

14 APPENDIX C: DAC FILTER PLOTS

Figure 37. Single Speed Stopband Rejection Figure 38. Single Speed Transition Band

Figure 39. Single Speed Transition Band (detail) Figure 40. Single Speed Passband Ripple

Figure 41. Double Speed Stopband Rejection Figure 42. Double Speed Transition Band

CS42438

Figure 43. Double Speed Transition Band (detail) Figure 44. Double Speed Passband Ripple

0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75

-60

-50

-40

-30

-20

-10

Amplitude (dB)

Frequency(normalized to Fs)

Figure 45. Quad Speed Stopband Rejection Figure 46. Quad Speed Transition Band

00.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

Amplitude (dB)

Frequency(normalized to Fs)

0.4 0.45 0.5 0.55 0.6 0.65 0.7

-50

-45

-40

-35

-30

-25

-20

-15

-10

-5

Amplitude (dB)

Frequency(normalized to Fs)

0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45

-0.2

-0.15

-0.1

-0.05

0.05

0.1

0.15

0.2

Amplitude (dB)

Frequency(normalized to Fs)

Figure 47. Quad Speed Transition Band (detail) Figure 48. Quad Speed Passband Ripple

CS42438
64
15 REVISION HISTORY
        
        
Revision Date Changes
A1 July 2004 Initial Release
Table 10. Revision History
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