DS1644/DS1644LPM DALLAS DS1644/DS1644LPM SEMICONDUCTOR Nonvolatile Timekeeping RAM FEATURES PIN ASSIGNMENT Upward compatible with the 0$1643 Timekeeping vec RAM WE Integrated NV SRAM, real time clock, crystal, power ANS fail control circuit and lithium energy source AB Optional low profile socketable module a9 Fits into a standard 68-pin PLCC surface AN mountable socket OE 255 mil package height Ato Standard JEDEC bytewide 32K x 8 static RAM pinout ce pQ7 Clock registers are accessed identical to the static pas RAM. These registers are resident in the eight top pas RAM locations. pa4 @ Totally nonvolatile with over 10 years of operation in pas the absence of power 28-Pin Encapsulated Package Access time of 120 ns and 150 ns (720 Mil Extended) Quartz accuracy +1 minute a month @ 25C, factory NC 1 94 NC calibrated NC 2 33 NC _NC 3 32 At4 BCD coded year, month, date, day, hours, minutes, PFO 4 3t A13 voc 5 30 Al2 and seconds we 6 29 Ati E Power fail write protection allows for +10% Voc power CE 3 a Ag. supply tolerance DQ7 9 26 AB Das 10 25 AT DQ5s " 24 AS ORDERING INFORMATION pa4 12 23 AS DS1644-XX = (28-pin DIP module) DQ3 13 22 A4 pa2 14 21 A3 ~12 120 ns access oat 1s 20 A2 paQ0 16 419 AY -15 150 ns access GND 17 18 AO DS1644L-XX (Low Profile Module) 34-Pin Low Profile Module Ly 12 120ns access PIN DESCRIPTION -15 150 ns access A0-A14 ~ Address Input CE Chip Enable OE Output Enable WE Write Enable Voc +5 Volts GND Ground DQ0-DQ7 Data Input/Output NC ~ No Connection PFO Power Fail Output (0S1644LPM only) 090895 1/11 a geet 1985 by Dakss Semiconductor Corporation. . regarding 50 and other intelectual , 6 na aneDESCRIPTION The DS1644LPM is a low profile module that fits into a standard 68pin PLCC surface mountable socket and is functionally equivalent to the DS1644. The DS 1644 is a 32K x 8 nonvolatile static RAM with a full function real time clock which are both accessible in a bytewide for- mat. The nonvolatile timekeeping RAM is pin and func- tion equivaient to any JEDEC standard 32K x 8 SRAM. The device can also be easily substituted in ROM, EPROM and EEPROM sockets providing read/write nonvoiatility and the addition of the real time clock func- tion. The real time clock information resides in the eight uppermost RAM locations. The RTC registers contain year, month, date, day, hours, minutes, and seconds data in 24 hour BCD format. Corrections for the day of the month and leap year are made automatically. The RTC clock registers are double buffered to avoid access of incorrect data that can occur during clock update cycles. The double buffered system also prevents time loss as the timekeeping countdown continues unabated by access to time register data. The DS1644 also con- tains its own power fail circuitry which deselects the de- vice when the Vcc supply is in an out-of-tolerance condition. This feature prevents loss of data from un- DS1644 BLOCK DIAGRAM Figure 1 DS1644/0S1644LPM predictable system operation brought on by low Vcc as errant access and update cycles are avoided. CLOCK OPERATIONS - READING THE CLOCK While the double buffered register structure reduces the chance of reading incorrect data, internal updates to the 0S1644 clock registers should be halted before clock data is read to prevent reading of data in transition. However, halting the internal clock register updating process does not affect clock accuracy. Updating is halted when a 1 is written into the read bit, the seventh most significant bit in the control register. As iong as a 1 remains in that position, updating is halted. After a halt is issued, the registers reflect the count, that is day, date, and time that was current at the moment the hait command was issued. However, the internal clock reg- isters of the double buffered system continue to update so that the clock accuracy is not affected by the access of data. All of the DS1644 registers are updated simul- taneously after the clock status is reset. Updating is within a second after the read bit is written to zero. CLOCK OSCILLATOR AND REGISTERS 32.768 KHz CLOCK COUNTDOWN K > TI CHAIN CE | WE 32K XB __ NV SRAM OE PFO <_ POWER MONITOR, POWER GOOD K A0-A14 + SWITCHING, AND Vpat WRITE PROTECTION ; . Vec = 561 090895 2/110S1644/DS1644LPM DS1644 TRUTH TABLE Table 1 Vee ce | OF | WE MODE ba POWER Vin x x DESELECT HIGH Z STANDBY x x xX DESELECT HIGH Z STANDBY 5 VOLTS + 10% Vit x Vit WRITE DATA IN ACTIVE Ve | Ve | Vi READ DATA OUT ACTIVE Vi | Vin | Vie READ HIGH Z ACTIVE <4.5 VOLTS x x x DESELECT HIGH Z CMOS STANDBY >Veat DATA RETENTION <Vpat x x x DESELECT HIGH Z MODE SETTING THE CLOCK running, the LSB of the seconds register will toggle at The eighth bit of the control register is the write bit. Set- ting the write bit to a 1, like the read bit, haits updates to the DS1644 registers. The user can then load them with the correct day, date and time data in 24 hour BCD for- mat. Resetting the write bit to a 0 then transfers those values to the actual clock counters and allows normal operation to resume. Note that both the read bit and write bit perform similar functions and setting both bits during the same access cycle will prevent the clock reg- isters from updating. STOPPING AND STARTING THE CLOCK OSCILLATOR The clock oscillator may be stopped at any time. To in- crease the sheif life, the oscillator can be turned off to minimize current drain from the battery. The OSC bit is the MSB for the seconds registers. Setting ittoa 1 stops the oscillator. FREQUENCY TEST BIT Bit 6 of the day byte is the frequency test bit. When the frequency test bit is set to logic 1 and the oscillator is 512 Hz. When the seconds register is being read, the DQ line will toggle at the 512 Hz frequency as long as conditions for access remain valid (i.e., CE low, OE low, and address for seconds register remain valid and stable). CLOCK ACCURACY The DS1644 is guaranteed to keep time accuracy to within +1 minute per month at 25C. The clock is cali- brated at the factory by Dallas Semiconductor using special calibration nonvolatile tuning elements. The DS1644 does not require additional calibration, and temperature deviations will have a negligible effect in most applications. For this reason, methods of field clock calibration are not available and not necessary. Attempts to calibrate the clock that may be used with similar device types (MK48T08 family) will not have any effect even though the DS1644 appears to accept cal- ibration data. 090895 3/11 5520S1644/DS1644LPM DS1644 REGISTER MAP - BANK1 Table 2 ADDRESS PATA FUNCTION B; Be Bs By By By B, Bo 7FFF . - - . - . . - YEAR 00-99 7FFE X x X - - . - . MONTH 01-12 7FFD x x - - - - . - DATE 01-31 7FFC x FT X X x - - . DAY 01-07 7FFB x X - . . - - - HOUR 00-23 7FFA X - - - . - - - | MINUTES 00-59 7FFg | OSC; - - - - . - | SECONDS 00-59 7FF8 w R - . - - - - | CONTROL A OSC = STOP BIT R = READBIT FT = FREQUENCY TEST W = WRITEBIT X = UNUSED NOTES: X bits are unused but must be set to zero during write cycle to insure proper clock operation. Bits 0 through 5 of control register A are not dedicated to any particular function and can be used as normal RAM bits. RETRIEVING DATA FROM RAM OR CLOCK The DS1644 is in the read mode whenever WE (write enabie) is high, and CE (chip enable) is low. The device architecture allows ripple-through access to any of the address locations in the NV SRAM. Valid data will be available at the DQ pins within ta, after the last address input is stable, providing that the CE and OE access times are satisfied. if CE or OE access times are not met, valid data will be available at the latter of chip en- able access (tcg,) or at output enable access time (toga). The state of the data input/output pins (DQ) is controlled by CE and OE. if the outputs are activated before ta,, the data lines are driven to an intermediate state until taa. If the address inputs are changed while CE and OE remain valid, output data will remain valid for output data hold time (to}4) but will then go indeterminate until the next address access. WRITING DATA TO RAM OR CLOCK The DS1644 is in the write mode whenever WE and CE are in their active state. The start of a write is referenced to the latter occurring high to low transition of WE or CE. The addresses must be held valid throughout the cycle. CE or WE must retum inactive for a minimum of twa prior to the initiation of another read or write cycle. Data in must be valid tps prior to the end of write and remain valid for tpy afterward. In a typical application, the OE signal will be high during a write cycle. However, OE can be active provided that care is taken with the data bus to avoid bus contention. If OE is low prior to WE transitioning low the data bus can become active with read data defined by the address inputs. A low transi- tion on WE will then disable the outputs twez after WE goes active. 553 090895 4/11DS1644/0S1644LPM DATA RETENTION MODE When Vcc is within nominal limits (Vcc > 4.5 volts) the DS1644 can be accessed as described above with read or write cycles. However, when Vcc is below the power fail point Vpr (point at which write protection occurs) the internal clock registers and RAM are blocked from ac- cess. This is accomplished internally by inhibiting ac- cess via the CE signal. At this time the power fail output signal (PFO) will be driven active low and will remain active until Voc returns to nominal levels. When Voc falls below the level of the internal battery supply, power input is switched from the Vcc pin to the internal battery and clock activity, RAM, and clock data are maintained from the battery until Vcc is returned to nominal level. INTERNAL BATTERY LONGEVITY The DS 1644 has a self contained lithium power source that is designed to provide energy for clock activity, and clock and RAM data retention when the Voc supply is not present. The capability of this internal power supply is sufficient to power the DS1644 continuously for the life of the equipment in which it is installed. For specifi- cation purposes, the life expectancy is 10 years at 25C with the internal clock oscillator running in the absence of Vcc power. The DS1644 is shipped from Dallas Semiconductor with the clock oscillator turned off, so the expected life should be considered to start from the time the clock oscillator is first turned on. Actual life ex- pectancy of the DS1644 will be much longer than 10 years since no internal lithium battery energy is con- sumed when Vcc is present. In fact, in most applica- tions, the life expectancy of the DS1644 will be approxi- mately equal to the shelf life (expected useful life of the lithium battery with no ioad attached) of the lithium bat- tery which may prove to be as long as 20 years. 0908095 5/11 5540S1644/DS1644LPM ABSOLUTE MAXIMUM RATINGS* Voltage on Any Pin Relative to Ground -0.3V to +7.0V Operating Temperature 0C to 70C Storage Temperature -20C to +70C Soldering Temperature 260C for 10 seconds * This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absoiute maximum rating conditions for extended periods of time may affect reliability. RECOMMENDED DC OPERATING CONDITIONS (0C to 70C) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Supply Voltage Vcc 4.5 5.0 5.5 v 1 Logic 1 Voltage All Inputs Vin 2.2 Voct0.3 Vv Logic 0 Voltage All Inputs Vit -0.3 0.8 Vv DC ELECTRICAL CHARACTERISTICS (OC <ta < 70C; Vec=5.0V + 10%) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Average Vcc Power Supply Cur- lec1 60 mA 3 rent TTL Standby Current (CE = V\y) loc2 6 mA 3 CMOS Standby Current loc3 4.0 mA (CE=Vec-0.2V) Input Leakage Current (any input) hit -1 +1 pA Output Leakage Current lot -1 +1 pA Output Logic 1 Voltage Vou 2.4 Vv (lout = -1.0 mA) Output Logic 0 Voltage VoL 0.4 Vv (lout = +2.1 MA) Write Protection Voltage Vpr 4.0 4.25 4.5 v 090895 6/11 555DS1644/D81644LPM AC ELECTRICAL CHARACTERISTICS (0C to 70C; Vog = 5.0V + 10%) PARAMETER SYMBOL osieat2 psi UNITS NOTES MIN MAX MIN MAX Read Cycle Time tac 120 150 ns Address Access Time tan 120 150 ns CE Access Time tcea 120 150 ns CE Data Off Time tcez 40 50 ns Output Enable Access Time toga 100 120 ns Output Enable Data Off Time toez 40 50 ns Output Enable to DQ Low-Z toeL 5 5 ns CE to DQ Low-Z toeEL 5 5 ns Output Hold from Address tou 5 ns Write Cycle Time two 120 150 ns Address Setup Time tas 0 0 ns CE Pulse Width tcew 100 120 ns Address Hold from End of Write tay 15 20 ns Write Pulse Width twew 120 150 ns WE Data Off Time twez 40 50 ns WE or CE Inactive Time twr 10 15 ns Data Setup Time tos 85 110 ns Data Hoid Time High tou 16 20 ns AC TEST CONDITIONS Input Levels: OV to 3V Transition Times: 5ns CAPACITANCE (ta = 25C) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Capacitance on all pins Cc; 7 pF (except DQ) Capacitance on DQ pins Coa 10 pF 090895 7/11 556DS1644/0S1644LPM AC ELECTRICAL CHARACTERISTICS (POWER-UP/DOWN TIMING) (0C to 70C) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES CE or WE at Vi before Power tpp 0 us Down Vpr (Max) to Vpp (Min) Vcc Fall te 300 ps Time Ver (Min) to Vso Voc Fail Time tea 10 us Vgo0 to Vpr (Min) Voc Rise Time tre 1 ys Vpg (Min) to Vpe (Max) Vcc Rise tr 0 ps Time Power Up trec 15 25 35 ms Expected Data Retention Time tor 10 years 4 (Oscillator On) DS1644 READ CYCLE TIMING READ READ WRITE tre *__ tae a e.__ two +e AO-A14 W X K le tan _ tay ry t tas tceA ] CE toe OE aw toes > twr _ {+ twew r WE toe Fr ton le toez DQ0-Da7 Yo q K X { ___ a VALID OUT VALID OUT, VALID IN 7 kK 557 080895 8/11DS1644/DS1644LPM DS1644 WRITE CYCLE TIMING WRITE p___. two WRITE two _-_#} REAI 0 ww te | y 3 2 A0-A14 i XM K 3 Fk tas twr ~ ta rv + em it tan > GE ] as tcew 1 | \ f[* toca OE / twr | 'wew WE r D ton tcez ' ton os wez Ds pao- VALID ) VALID I }4 par OUT L ALID IN { VALID IN 4 VALID OUT POWER DOWN/POWER UP TIMING Voc Vpr (MAX) te Vso \ ) 7 {po -_ Y 7 7 + cE \ / Vpe (MIN) ir trp m rec 7 x ff YN rt \TA ee DATA RETENTION ton | 090895 9/11 558DS1644/DS1644LPM NOTES: OUTPUT LOAD 1. All voltages are referenced to ground. +5 VOLTS . Typical values are at 25C and nominal supplies. 2 3. Outputs are open. 4 1.8KQ . Data retention time is at 25C and is calculated from the date code on the device package. The date code XXYY is the year followed by the week D.U.T. of the year in which the device was manufactured. For example, 9225, would mean the 25th week of 1992 KQ 100 pF DS1644 28PIN PACKAGE PKG 28-PIN DIM MIN MAX A IN. | 1.470 1.490 MM 37.34 37.85 :@ BIN. | 0.715 0.740 1 MM 18.16 18.80 s A >| Cc IN. | 0.335 | 0.365 MM 8.51 9.27 D IN. | 0.075 0.105 MM 1.91 2.67 E IN, | 0.015 0.030 r MM 0.38 0.78 c F IN. | 0.140 0.180 MM 3.56 4.57 FE G IN. | 0.090 0.110 MM 2.29 2.79 Le D alle K lobe H IN. | 0.590 0.630 MM 14.99 16.00 JIN. | 0.010 0.018 MM 0.25 0.45 K IN. J 0.015 0.025 MM 0.38 0.64 090895 10/11 559DS1644/DS1644LPM DS1644LPM 34-PIN LOW PROFILE MODULE Poa meta id 4 m 7 UBL ik 4 i ; | | | PKG INCHES Dim MIN MAX A 0,955 0.980 B 0.840 0.855 Cc 0.230 0.250 D 0.975 0.995 E 0,047 0.053 F 0.015 0.025 NOTE: The recommended 68-pin PLCC surface mountable socket to be used with this 34pin module is: McKenzie P/N# 34P-SMT-3. The McKenzie socket plus the DS1644LPM has the following approximate dimen- sions: length, width = 1.22, height = 0.255. 090895 11/11 560