ANALOG DEVICES > LC2M0s 8-Bit pxP-Compatible 12-Bit DAC AD7548 FEATURES 8-Bit Bus Compatible 12-Bit DAC All Grades 12-Bit Monotonic Over Full Temperature Ranges Operation Specified at +5V, +12V or +15V Power Supply Low Gain Drift of 5apm/C Maximum Full 4 Quadrant Multiplication Skinny DIP and Surface Mount Packages APPLICATIONS 8-Bit Microprocessor Based Control Systems Programmable Amplifiers Function Generation Servo Control GENERAL DESCRIPTION The AD7548 is a 12-bit monolithic CMOS D/A converter for use with 8-bit bus microprocessors. Data is loaded in two bytes to input holding registers as shown in the block diagram opposite. The AD7548 can be configured to accept either left- or right-jus- tified data, least significant byte or most significant byte first, . using standard TTL compatible control inputs. A separate load DAC control input allows the user the choice of updating the analog output coincident with loading new data to the DAC input register or at any time after the data loading event. This feature is especially important in multi-DAC systems where simultaneous update of all DACs is required. The new Linear Compatible CMOS (LC? MOS) process used in the manufacture of the AD7548 allows precision thin-film linear circuitry and high-speed low-power CMOS logic to be integrated on the same small chip. The high-speed logic allows direct interfacing to most of the popular 8-bit microprocessors. Rev.A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks arethe property of their respective owners. AD7548 FUNCTIONAL BLOCK DIAGRAM Voo (18> AY A07548 Vee o4 R-2R LAODER DATA OVERRIDE LOGK aa DAC REGISTER INPUT REGISTERS DATA STEERING Locic i 087-DB0 PRODUCT HIGHLIGHTS 1, wa Microprocessor Compatibility High speed input control (TTL/SV CMOS compatible) allow direct interfacing to most of the popular 8-bit - microprocessors. . Guaranteed Monotonicity The AD7548 is guaranteed monotonic to 12-bits over the full temperature range for all grades and at all specified supply voltages. . Selectable Data Input Format Left- or right-justified data, least significant or most significant byte first. This allows the AD7548 to be interfaced with microprocessors using either Motorola or Intel-type data formatting. . Monolithic Construction For increased reliability and reduced package size 0.3 20-pin DIP and 20-terminal surface mount packages. . Single Supply Operation See Figure 8. . Low Gain Error and Gain Error T.C. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 2005 Analog Devices, Inc. All rights reserved.SPECIFICATIONS! = +51 e-=-+10gg= K-07 A pees: axes tev gc j,A K,B Parameter Versi _ Versi SV TV Units Test Conditions/C: ts ACCURACY Resolution 12 12 12 12 Bits Relative Accuracy #1 +12 +1 +12 LSB max Differential Nonlinearity +1 2 +1 +12 LSB max All grades guaranteed monotonic to 12-bits over temperature, Full Scale Error " #6 23 +6 *3 LSB max Measured using internal Rr and includes effects of leakage current and gain TC. Full Seale Error can be trimmed to zero. Gain Temperature Coefficient; AGain/A Temperature - 5 25 +5 =5 ppmC max Typical value is 2ppm/C Output Leakage Current Tour (Pin 1) + 25C +5 $ +5 5 nA max All digital inputs = 0V Tinin tO Tynax +25 ~ 225 +150 +150 nA max REFERENCE INPUT Input Resistance, Pin 19 7 7 7 7 kO min Typical Input Resistance = 11k0. 20 20 20 20 kN max DIGITALINPUTS Vins (Input High Voltage) 2.4 2.4 2.4 2.4 V min Vir (Input Low Voltage) 0.8 0.8 0.8 0.8 Vmax Tyn (Input Current) / + 25C +1 +1 1 1 pA max Vi = OV or Von Tin tO Tinax +10 +10 +10 +10 pA max Cr input CapacitanceY 7 7 7 pF max POWER SUPPLY Vyp Range 4.75/5.25 4.75/5.25 4.75/5.25 4.75/5.25 Vmin/V max Specifications guaranteed over this range Ipp 2 2 2 2 mA max All digital inputs Vj, or Vin 300 300 300 300 pA max All digital inputs OV or Vpp. SPECIFICATIONS? ioctcatos to 12, oes cterace secre JA K,B Parameter Versions Versions SVersion TVersion Units Test Conditionas/Comments ACCURACY Resolution 12 12 12 12 Bits Relative Accuracy +1 +2 +) +2 LSB max Differential Nonlinearity +1 +212 tl +12 LSB max All grades guaranteed monotonic to 12-bits over temperature, Full Scale Error +6 +3 +6 +3 LSB max . Measured using internal Rr end includes oO effects of leakage current and gain TC. . - Full Scale Error can be trimmed to zero. Gain Temperature Coefficient; AGain/S Temperature +5 +5 +5 +5 ppm/C max Typical value is 2ppm/C Output Leakage Current Tour (Pin 1) + 25C +5 +5 +5 +5 nA max Ali digital inputs = 0V Tinin tO Tmax +25 +25 +150 + 150 nA max REFERENCE INPUT Input Resistance, Pin 19 7 7 7 7 kN min Typical Input Resistance = 11kN 20 20 20 20 kN max DIGITAL INPUTS Vin (Input High Voltage) 2.4 24 2.4 2.4 Vin Vit (Input Low Voltage) 0.8 0.8 0.8 0.8 Vmax Tp (Input Current) + 25C +1 1 1 +1 A max Vin = OV or Vpp Tin tO Tmax +10 +10 +10 +10 pA max Cry (input Capacitance 7 7 7 pF max POWER SUPPLY Vpp Range 1L.4/15.75 11.4/E5.75 L4.4/15.75 11.4/15.75 Vmin/Vmax Specifications guaranteed over this range Ipp 3 3 3 3 mA max All digital inputs Vir or Vin 1 1 1 1 mA max All digitalinputs OV or Vpp NOTES Temperature range as follows: J, K Versions; 0 to +70C A, B Versions; 40C to + 85C S, T Versions; 55C to + 125C 2Guaranteed by design but not production tested. Specifications subject to change without notice. REV. ATIMING CHARACTERISTICS' (Yop = +5V, Veer = + 10V, logy = AGNO = OV unless otherwise stated) Limit? at Limit? at Limit at Ta=0to +70C Ta= -55C Parameter T,=25C ~40C to + 85C to + 125C Units Test Conditions/Comments tos 240 240 290 ns min Data Valid Setup Time tow 50 50 70 ns min Data ValidHoldTime _ tows 30 40 50 ns min CSMSB or CSLSB to WR Setup Time lowH 15 20 25 ns min CSMSB or CSLSB to WR Hold Time trws 30 49 50 ns min LDAC to WR Serup Time tlwH 15 20 25 ns min LDAC to WR Hold Time twr 250 280 320 ns min Write Pulse Width TIMING CHARACTERISTICS? p= 12vto +157 vap=-+10 lan -=AEND-=OV unos otervise state) Limit? at Limit? at Limit at Ta=0to +70C Ta= -55C Parameter T,=25C ~40C to + 85C to + 125C Units Test Conditions/Comments tos 160 190 230 ns min Data Valid Setup Time tox 30 30 50 ns min Data Valid Hold Time tows .30 40 50 ns min CSMSB or CSLSB to WR Setup Time town 45 20 25 ns min CSMSB or CSLSB to WR Hold Time trws 30 40 50 ns min LDAC to WR Setup Time tLwH 15 20 25 ns min LDAC to WR Hold Time twR 170 200 240 ns min Write Pulse Width AC PERFORMANCE CHARACTERISTICS Thase characteristics are included for Design Guidance only and are not subject to test. (Veer = + 10V; louy = AGND = GV, Output Amplifier is AD544 except where stated) Vpp = +5V Vpp= +12Vto + 1SV Parameter Version | T,= +25C 4 Ta=Tyuns Tmax | Ta +25C | TaTxan, Tmax | Units Test Conditions/Comments Outpur Current Settling Time 1.5 ~ 1 - #STYp To0.01% of full scale range. lout load = 1002, Cry = 13pF, DAC register alternately loaded with all }s and all 0s Digital to Analog Glitch Measured with Vapr = OV, Impulse . 400 ~ 330 - nV-sec typ Tout load = 1002, Crys = 13pF. DAC register alternately loaded with all 1s and all 0s Muldplying Feedthrough Error? 3 5 3 5 mV p-ptyp | Vaer= +5V, lOkHzsine wave DAC register loaded with all 0s. Total Harmonic Distortion ~35 - -85 - dBtyp Veer = 6V rms @ 1kHz. DAC register loaded with all 1s. Power Supply Rejection AGAIN/A Vpp + 0.015 +0.03 +0.01 0.02 % per% max | AVop= +5% Output Capacitance lout (Pin 1) 200 200 200 200 pF max DAC register loaded with all !s. 100 100 100 100 pF max DAC register loaded with all 0s. Output Noise Voltage Density (10Hz-100kHz) 15 - 15 - nV/VHiz ryp | Measured between Rep and lout NOTES "Guaranteed by design but not production tested. *Tenspersiure range as follows: J, K Versions; 010 + 70C. A.B Versions; - 40C co 65C 5, T Versions; - 55Ct0 + 123C , ugh can be further dby ing the metal lid on Uy ic package (Suffix D)1o DGND. Specifications subject to change without notice. REV.AABSOLUTE MAXIMUM RATINGS* (T, = +25C unless otherwise noted) Vpp (Pin 18) to DGND Vrer (Pin 19) to Vars (Pin 20) to Digital Input Voltage (Pins 4-17) to DGND . Vem 1 to DGND AGND to DGND Power Dissipation (Any Package) To +75C CAUTION: AGND AGND Cr ee) CC ee ee ee ww ee we Operating Temperature Range Commercial (J, K Versions) .... 2.0.05... 0 to +70C Industrial (A, B Versions) ......... 40C to + 85C Extended (S, T Versions). ........ 55C to + 125C Storage Temperature .....0.....43 65C to + 150C Lead Temperature (Soldering, l0secs) ........ + 300C *Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD (Electro-Static-Discharge) sensitive device. The digital control inputs are Zener protect- ed; however, permanent damage may occur on unconnected devices subject to high energy electrostatic fields. Unused devices must be stored in conductive foam or shunts. The foam should be discharged to the destination socket before devices are removed. WARNING! Ss ESO SENSITIVE DEVICE PIN CONFIGURATIONS DIP LCCcc banaell Q ow O i] me e852: acno [2] [38] Vnee azi 20 1" pono [3 | [18] Yoo ZSMSE te ADysas 7] WR tSMsB. 4 18 Voo room CE] tet is] come orm "i crm fe he] iat CTRL 6 16 CELSE DB7(MSB) 7 15 WAC pB7 (mse) [7 | [14] Deo use) oss te fy on Das 8 14 DBO(LSB) pas [9 | 2] vez 9 10 11 12 13 ov [i a] os ga82% ORDERING INFORMATION! Relati Full-Scal: Accuracy Error care Temperature Range and Package Options Tein Tmax Taint. Oto +70C -25Cto +85C | 55Cto +125C Plastic DIP(N-20) | Hermetic (Q-20) Hermetic (Q-20) + 1LSB +6LSB AD7548JIN AD7548AQ AD7548SQ + V2LSB +3LSB AD7548KN AD7548BQ AD7548TQ PLCC (P-20A) LCCC (E-20A) +1LSB +6LSB AD7548JP AD7548SE + V/2LSB +3LSB AD7548KP AD7548TE NOTES _'To order MIL-STD-883, Class B processed parts, add/883B to part number. Contact your locaf sales office for military data sheet. Analog Devices reserves the right to ship ceramic (package outline D-20) packages in lieu of cerdip (package outline Q-20) packages. 3See Section 13 for package outline information. PLCC: Plastic Leaded Chip Carrier. 3LCCC: Leadiess Ceramic Chip Carrier. REV.APIN FUNCTION DESCRIPTION PIN awh re 10 n 12 13 14 15 16 18 19 20 MNEMONIC Tour AGND DGND CSMSB DF/DOR- CTRL DB7 DB6 DBS DB4 DB3 DB2 DBI DBO LDAC CSLSB Von Vase Res CONTROL INPUT INFORMATION Figure la shows the data load timing diagram for the AD7548. DESCRIPTION DAC current OUT bus. Normally terminated at virtua! ground of output amplifier. Analog Ground. Digital Ground. __ Chip Select Most Significant (MS) Byte. Active Low Input. Used in combination with WR to load external data into the input register or in combination with WR and LDAC to load external data into both input and DAC registers. Data Format/Data Override. When this input is LOW, data in the DAC register is forced to one of two override codes selected by CTRL. When the override signal is removed, the DAC output returns to reflect the valuc in the DAC register. With DF/DOR HIGH, CTRL selects either a left or right justified input data format. For normal operation, DF/DOR is held HIGH. DE/GOR| CTRL | FUNCTION 0 0 DAC register contents overridden by all 0s Q 1 DAC register contents overriden by all 1's 1 0 Left-justified input data selected 1 1 Right-justified input data selected Control Input. See pin description, |MOST SIGNIFICANT BYTE~#}<LEAST SIGNIFICANT BYTE #| A xj{_ xX {X CTRL=0" CTRL=1" X= Dont care states. Data Bir 7. Mast Significant Bit (MSB). Data Bit 6. Dat Bit 5. Data Bit 4. Data Bit 3. Data Bit 2. Data Bit 1. Data Bit 0. Least Significant Bit (LSB). Load DAC Input, active LOW. This signal, in combination with others, is used to load the DAC register from either the input registeror the external data bus. Chip Select Least Significant (LS) Byte. Active LOW input. Used in combination with WR to load external data into the input register or in combination with WR and LDAC to load external data into both input and DAC registers. WRITE Input. This active tow signal, in combination with others is used in loading external data into the AD7548 input register and in transferring data from the input register to the DAC register. WR CSMSE CSESS CBAC! FUNCTION 0 1 0 1 Load LS Byte to Input Register. 0 1 0 0 Load LS Byte to Input Register and DAC Register. 0 0 ! 1 Load MS Byte to Input Register. 0 0 I 0 Load MS Byte to Input Register and DAC Register. 0 1 1 0 Load Input Register to DAC Register. 1 x xX x No Data Transfer +$5V to + 15V Supply Input. Reference Voltage Input. Feedback Resistor. Used for normal D/A conversion. Figure Ib shows the simplified input control structure of the AD7548. town -T SV essa t cs | tows town 1 1 bet aa ov _L__ ca Oo_--__ Sse i \ I sv Onan . DATA OVERRIDE ov oe p pe i i p53 io = o> wa twa f sv 7 tow! Iton! av " tos jton | | tog I ton wv cSise T > y Y os (INPUT REGISTERS DATA tSMs6 0-4 TS ev ' T> NOTES 1, ALL INPUT SIGNAL RISE AND FALL THMES MEASURED FROM 10% TO 90% OF +5V. WR Onmworerernnt! 1,2% = 20ns, DATA STEERING 2. TIMING MEASUREMENT REFERENCE LEVEL IS Yat Ms LoGic - Figure 1a. AD7548 Timing Diagram . CSMSB (PIN 4) AND CSLSB (PIN 16) MAY BE INTERCHANGED. FOR LEFT. JUSTIFIED DATA CTRL = + 0V WITH DFIOOA = +5V. FOR RIGHT- JUSTIFIED DATA CTRL = +5V WITH DFIDOR= +5v. Figure 1b. Simplified AD7548 Input Control Structure REV.AGENERAL CIRCUIT INFORMATION The simplified D/A circuit is shown in Figure 2. An inverted R-2R ladder structure is used, which stecrs binarily weighted currents between Inu and AGND, thus maintaining a constant current in each ladder leg independent of the switch state. The input resistance at Vy: is constant and equal to the value R in Figure 2. Since the input resistance is constant, the reference terminal can be driven by a reference voltage or a reference current, ac or dc, of positive or negative polarity. (If a current source is used, a low temperature cocfficient external Reg is recommended to define scale factor). Vice WA 8 rw" lour -O AGND < eT --F2, i ! I ' i DATA LATCHES AND SWITCH DRIVERS Figure 2. AD7548 Simplified Functional Diagram EQUIVALENT CIRCUIT ANALYSIS Figure 3 shows an equivalent circuit for the analog section of the AD7548 D/A converter. The current source ILgaxace i8 composed of surface and junction leakages. The resistor Ro, denotes the equivalent output resistance of the DAC which varies with input code (excluding all 0s code) from 0.8R to 2R, where R is typically 11k. Cour is the capacitance due to the current steering switches and varies from about SOpF to 120pF (typical values) depending upon the digital input. g(Vrer, N) is the Thevenin equivalent voltage generator due to the reference input voltage, Varr, and the transfer function of R-2R ladder, N. For further information on CMOS multiplying D/A converters. refer to Application Guide to CMOS Multiplying D/A Conver- ters available from Analog Devices, Publication Number G479- 15-8/78. th, oY nes N) AGND Figure 3. AD7548 Equivalent Analog Output Circuit DATA LOADING The AD7548 accepts incoming data in either left-justified format or right-justified format depending on the control inputs DF/DOR and CTRL. (See pin description of DF/DOR and CTRL on preceding page). Two operating modes are possible for controlling the transfer of data from the input register to the DAC register, the automatic transfer mode and the strobed transfer mode. AUTOMATIC TRANSFER MODE This is the simplest and fastest method of transferring data to the DAC register. It is facilitated by connecting LDAC to either CSMSB, as shown in Figure 10, or CSLSB Figure 4 shows the timing diagram for automatic transfer of 8 +4-bit data to the DAC register. The first write cycle loads the first byte of data to the input register. The second write cycle loads the second byte of data to the input register and automatically transfers both bytes to the DAC register. Updating a single byte (High or Low) in the DAC register can be achieved in one write cycle using the automatic transfer mode. DATA Csise cemse Wy 1 ad . ~ | LOAD BYTE LINTO LOAD BYTE 2 INTO INPUT AECISTER. ANALOG OUTPUT PDATED. Figure 4. Automatic-Transfer Mode STROBED TRANSFER MODE Figure 5 shows the timing-diagram for the strobed transfer of 8 +4-bit data to the DAC. register. Three write cycles are required for this transfer mode. The first two. write cycles sequentially load bytes 1 and 2 into the input register. The third write cycle transfers data from the input register to the DAC register. The strobed transfer mode allows the DAC registers of several AD7548s to be updated simultaneously, as shown in Figure 13, by means of a master strobe signal connected to the LDAC of each device. A single byte of data High or Low) can be transferred to the DAC register in two write cyeles using the strobed transfer LOAD BYTE TINTO INPUT REGISTER LOAD BYTE 2 INTO TRANSFER DATA INPUT REGISTER FROM INPUT REGISTER TO DAC REGISTER. ANALOG OUTPUT UPDATED. Figure:5. Strobed Transfer Mode DATA OVERRIDE The contents of the DAC register can be overridden by pulling DF/DOR (pin 5) LOW.:-The: CTRL (pin 6) input then determines whether the DAC register data is overidden by all 0s (CTRL LOW) or all ls (CTRE-HIGH). This feature allows the user to _calibrate the AD7548.ia:citcuits such as Figure 6 without calling on the microprocessor.toload calibration data. REV.AApplying the AD7548 UNIPOLAR BINARY OPERATION (2-QUADRANT MULTIPLICATION) Figure 6 shows the analog circuit connections required for unipolar binary operation. With a dc input voltage or current (positive or negative polarity) applied at pin 19, the circuit is a unipolar D/A converter. With an ac input voltage the circuit provides 2- quadrant multiplication (digitally controlled attenuation). Table I shows the code relationship for the circuit of Figure 6. For full scale trimming the DAC register is loaded with 1111 HAI 1111, This is most easily accomplished by using the data override function. R1 is then adjusted for Vour= Vin (4095/ 4096). Alternatively full scale can be adjusted by omitting R1 and R2 and trimming the reference voltage magnitude. Capacitor Cl provides phase compensation and helps prevent overshoot and ringing when using high speed op amps. NOTES 1. CONTROL INPUTS OMITTED FOR CLARITY. 2. Ry, #10082, Ry=33{ FOR ALL GRADES. 3. SEE APPLICATION HINTS. Figure 6. Unipolar Binary Operation Binary Number in DAC Register Analog Output, Vout MSB LSB lid) 4211 1101 ~ Vin (Zose) 1000 0000 0000 Van (2038 ) = - 12Vin 0000 0000 0001 Vin (gpg } 0000 0000 0000 |ov Table {.. Unipolar Binary Code Table for Circuit of Figure 6 - BIPOLAR OPERATION (4-QUADRANT MULTIPLICATION) Figure 7 and Table II illustrate the recommended circuit and code relationship for bipolar operation. The circuit uses offset binary input coding. However, 2s complement coding can be accommodated if the MSB is inverted (done in software) before data is loaded inta the DAC. With the DAC register loaded to 1000 0000 0000, adjust RI for Vour = OV (alternatively one can omit Rl and R2 and adjust the ratio of R3 and R4 for Vour=0V). Full scale trimming can be accomplished by adjusting the amplitude of Vpx or by varying the valuc of RS. R3, R4 and R5 must be selected to match within 0.01% and they should be the same type of resistor (preferably metal film) so that their temperature coefficients match. Mismatch of R3 to R4 causes both offset and full scale error. Mismatch of R5 to R4 and R3 causes full scale error. $ i) > R22 ct > 20% 12 20 33pF Voo Rew a3 Re 45) v, four (4 10k nee At AA = v, Vn Ri a hed our AD7548 AGND(2 a2 - OGNO apssa? 6 + 7 ) 3 Sk ADS44) 10% INPUT DIGITAL. ANALOG OATA GROUND COMMON NOTES 3. CONTROL INPUTS OMITTED FOR CLARITY, 2. Ry = 10011, R.= 3342 FOR ALL GRAD! ES. 3. SEE APPLICATION HINTS. Figure 7. Bipolar Operation (Offset Binary Coding) Binary Number in DAC Register Analog Output, Vour MSB _LSB 2047 Plike2d2123 2121 + Vi (3082) 10000000 0001 + Vin (sa4a) 1000 0000 0000 {ov 0111 1111 1111 - Viv (sah) 0000 0000 0000 Vyy (3048) Table I!. Bipolar Code Table for Offset Binary Circuit of Figure 7 REV.ASINGLE SUPPLY OPERATION Figure 8 shows the AD7548 connected in a voltage switching mode. The input voltage is connected to Ioyr. The D/A converter output voltage is taken from the Vrer pin and has a constant impedance equal to R. Rpg is not used in this circuit. The input voltage Vin must always be positive with respect to AGND in order to prevent an internal diode from turning on. To maintain linearity the input voltage should remain within 2.5V of AGND with Vpp from +12V to + 15V. The output voltage Vour of Figure 8 is expressed as R, +R Vout = (Vim) (Dy( at Where D is a fractional representation of the digital input word (0SD=4095/4096). +15V WPeUT DATA Figure 8. Single Supply Operation Using Voltage Switching Mode APPLICATION HINTS - Output Offset: CMOS D/A converters in circuits such as Figures 6 and 7 exhibit a code dependent output resistance which in turn cause a code dependent amplifier noise gain. The effect is a code dependent differential nonlinearity term at the amplifier output which, depends on Vos where Vos is the amplifier input offset voltage. To maintain monotonic operation it is recommended that Vos be no greater than (25 x 10)(Vrer) over the temperature range of operation. Suitable op amps are AD5S17L and ADS44L. The ADS17L is best suited for fixed reference applications with low bandwidth requirements: it has extremely low offset (S0u.V) and in most applications will not require an offset trim. The AD544L has a much wider bandwidth and higher slew rate and is recommended for multiplying and other applications requiring fast settling. An offset trim on the AD544L may be necessary in some circuits. General Ground Management: AC or transient voltages between AGND and DGND can cause noise injection into the analog output. The simplest method of ensuring that voltages at AGND and DGND are equal is to tie AGND and DGND together at the AD7548. In more complex systems where the AGND and DGND intertie is on the backplane, it is recommended that two diodes be connected in inverse parallel between the AD7548 AGND and DGND pins (1N914 or equivalent). Temperature Coefficients: The gain temperature coefficient of the AD7548 has a maximum value of 5ppm/C and typical value of 2ppm/C. This corresponds to worst case gain shifts of 2LSBs and 0.8LSBs respectively over a 100C temperature range. When trim resistors R1 and R2 are used to adjust full scale range, the temperature coefficient of Rl and R2 should also be taken into account. The reader is referred to Analog Devices Application Note Gain Error and Gain Temperature Coefficient of CMOS Multiplying DACs, Publication Number E630-10-6/81. High Frequency Considerations: AD7548 output capacitance works in conjunction with the amplifier feedback resistance to add a pole to the open loop response. This can cause ringing or oscillation. Stability can be restored by adding a phase compen- sation capacitor in parallel with the feedback resistor. Feedthrough: The dynamic performance of the AD7548 will depend upon the gain and phase stability of the output amplifier, together with the optimum choice of PC board layout and de- coupling components. A suggested printed circuit layout for Figure 6 is shown in Figure 9 which minimizes feedthrough from Vpgr to the output in multiplying applications. PIN 1 ouTeuT C1 LOCATION NOTE INPUT GUARD EDUCE FEEDTHROUGH INPUTS 0000000 LAYOUT SHOWS COPPER SIDE (i.., BOTTOM VIEW) GAIN TRIM RESISTORS 81 ANO R2 OF FIGURE 6 ARE NOT INCLUDED. Figure 9. Suggested Layout for AD7548 and Op Amp For additional information on multiplying DACs refer to Ap- plication Guide to CMOS Multiplying D/A Converters, Publi- cation Number G479-15-8/78, available from Analog Devices. REV.AMICROPROCESSOR INTERFACING AD7548 - MC6800 INTERFACE A typical 6800 configuration using the automatic transfer mode of the AD7548 is shown in Figure 10. Table ITI gives a sample loading routine written in re-entrant form. Data load and store instructions use extended addressing. The 12-bit data to be passed to the subroutine is stored in locations XXYY and XXYY + 1. The data is considered right-justified with the four most significant bits occupying the lower half of XXYY + 1. The AD7548 is assigned a base address of PPQQ. This address selects the low byte register of the AD7548. Address PPQQ + 1 selects both the high byte register and the LDAC control input. AO-A1B ADDRESS BUS 5 ao ni =n : v oD ADDRESS > csise _ VvMA . EN DF/DOR { CTRL Mcs800 esse tBAC 2 pa wa AD7548 280-087 po-b? DATA BUS S *LINEAR CIRCUITRY OMITTED FOR CLAAITY Figure 10. AD7548 - MC6800 interface (Automatic Transfer Mode} JSR WWZZ Jump to AD7548 subroutine WWZZ PSHA Push A onto stack TPA PSHA Push CCR onto stack LDAA $XXYY STAA $PPQQ Load low byte to AD7548 LDAA $XXYY+1 STAA $PPQQ+1 Load high byte toAD7548 and update analog output PULA TAP Pull CCR from stack PULA Pull A from stack RTS Return to main program Table Ill. Sample Routine for AD7548 MC6800 Interface AD7548 - 8085A INTERFACE Figure 1] shows a typical AD7548 to 8085A microprocessor interface configured for automatic transfer of 8 + 4-bit right-jus- tified data. Table IV gives a sample loading routine written in re-entrant form. The 12-bit data to be passed to the subroutine is stored in locations XXYY and XXYY + 1. The four most significant data bits occupy the lower half of XXYY + 1. As before, addresses PPQQ and PPQQ + 1 select the CSLSB and CSMSB/LDAC control inputs respectively. Since only two in- structions (LHLD, SHLD) are required to both fetch and load the 12-bit data word to the AD7548, it may be more efficient to insert these instructions as required in the main program rather than use a subroutine such as illustrated here. ABais AOORESS BUS oP ADDRESS DECODE ALE Voo oF DOR CTRL 98085A AD7548* DG0-DR7 ae AD0-A0?7 ADDROATA BUS 5 *LINEAR CIACUITRY OMITTED FOR CLARITY Figure 11. AD7548 - 8085A Interface (Automatic Transfer Mode} CALL 7548 7548. PUSH: PSW Push register contents onto stack PUSH H LHLD XXYY Fetch 12-bit data SHLD PPQQ Load 12-bit data POP H Pop register contents from stack POP PSW RET Return to main program Table IV. Sample Routine for AD7548-8085A Interface REV.AAD7548 MC6809 INTERFACE The AD7548 can be interfaced to the MC6809 microprocessor as shown in Figure 12 for automatic transfer of 8 + 4-bit data. Similar to the 8085A instructions LHLD and SHLD, the 6809 has two instructions to fetch and store 12-bit (16-bit) data to the AD7548, LDD and STD. However, in the 6809, the high byte of data is moved first, then the low byte (this is the opposite of the 8085A). This means that if the 12-bit data is assumed to reside at addresses XXYY and XXYY+1 then XXYY must contain the high byte. It also means that the address decoding logic of Figure 11 must be slightly changed so that the even-order AD7548 address, PPQQ from before, selects the CSMSB input . to load the high byte first. In this automatic transfer configuration LDAC is tied to the CSLSB input. The AD7548 analog output can thus be updated using only two instructions as follows: LDD $XXYY STD SPPQQ The strobed transfer configuration is shown in Figure 13 with a de- dicated decoder output assigned to each chip select input. The com- mon LDAC signal allows simultaneous update of both AD7548 DAC registers. AO-AI5 ADDRESS BUS G | | rx) aw ENT - cEMSE Vow ADDRESS DECODE oF DGR 4 al ena CTRL MC6809 else pac . wi AD7548* 00-07 DATA BUS 6 *LINEAR CIRCUITRY OMITTED FOR CLARITY Figure 12. AD7548 - MC6809 Interface (Automatic Transfer Mode) A0-A15 [avoress MCes09 DECODE za 2 ADDRESS BUS csise couse (pac OFDOR 4 CTH 0 1 ge 3 4 y AD7S48 Q Ka bs & O80 -DB7 DO-D?7 OATA BUS csise Vpe OFDGR 4 CTRL AD?548 DBO-DB? ay < Wr Figure 13. AD7548- MC6809 Interface (Strobed Transfer Mode} REV.AAD7548 6502 INTERFACE Figure 14 shows a typical AD7548 to 6502 microprocessor interface configured for automatic transfer of right-justified data. As a -. programming example, Figure 15 shows a flow chart for producing a 12-bit (4095-step-max) voltage ramp under 6502 control. Index registers X and Y of the 6502 form a 12-bit counter with the X- register holding the low byte of data and the Y-register the high byte. Table V shows the program listing. The X-register is compared with FF, and the Y-register with 10}, to determine when the ramp voltage has reached its maximum value (FFF},). By changing the comparison data in the program the maximum ramp output voltage can be varied from levels corresponding to FFF; down to 000;;. In the program listing of Table V the AD7548 has been assigned contiguous addresses 0400 (low byte) and 0401 (high byte and DAC register). A086 ADDRESS BUS G | ao ADDRESS DECODE <5 Voo | CSL: Rw EN DFDOR CTRL 6502 | SMse LoaAC o2 o>] iw h AD7548* DBO-D87 00-07 DATA BUS S *LINEAR CIRCUITRY OMITTED FOR CLARITY Figure 14. AD7548 6502 interface (Automatic Transfer Mode) ENTER CLEAR Y CLEAR X INCREMENT X tt STORE X (LOW BYTE) TO AD7548 ! STORE Y (HIGH BYTE) TO AD?7648 & LOAD DAC REGISTER INCREMENT Y Figure 15. Flow Chart for Voltage Ramp Generation ADDRESS OP-CODE MNEMONIC | OPERAND 0000 AO LDY # 00 01 090 02 A2 LDX # 00 03 00 04 4c JMP 0008 05 08 06 00 07 E8 INX 08 8E STX 0400 09 00 0A 04 0B 8C STY 0401 0c ol oD 04 OE E0 CPX # FF OF FF 10 DO BNE 0007 \l F5 12 C8 INY 13 CO CPY + 10 14 10 15 DO BNE 0002 16 EB 17 FO BEQ 0000 0018 E7 Table V. Program Listing for Figure 15 REV.AAD7548 - Z80 INTERFACE Figure 16 shows a typical AD7548 to Z80 microprocessor interface configured for automatic transfer of right-justified data. Similar to the 8085A and 6809 cases, 16-bit load instructions are available .in the Z80 which can fetch and load 12-bit data to the AD7548. Since the low byte of data is moved first and assuming the 12- bit data resides at addresses XXYY and XXYY + 1, address XXYY must contain the low byte. As before, addresses PPQQ and PPQQ + | select the AD7548 CSLSB and CSMSB/LDAC control inputs respectively. Choosing the Z80 register pair BC to hold the 12-bit data, the two instructions required to update the AD7548 analog output are as follows: LD BC, (XXYY) LD (PPQQ), BC AG-A15 ADDRESS BUS DECODE Voo n 780 WR ap7sas* 080-087 q 0-D7 DATA BUS 5 *LINEAR CINGUITAY OMITTED FOR CLARITY Figure 16. AD7548- Z80 interface (Automatic Transfer Mode} 0.005 (0.13) MIN 0.080 (2.03) MAX ke- tl be. = = 0.180 (4.57) [| [ss (7.62) 0.048 (1.21) 0.165 (4.19) PIN 1 0.280 (7.11) 0.042 (1.07) 0.056 (1.42 a om we on oD Sas tton a Pele 0.20 (0.51) 0.020 (0.50) . ela R 40.021 40021(083 Ff 53) 0.048 (1.21) Bef 3 ok 060 (28.92) 0.320 (8.13) TOAD (1 oT} *Y F 0.050 goats) f 0.013 (0.33) a [*~ 0.990 (88.18) 0.060 (1.52) 0.300 (7.62) qd topview bf (1.27) 0.330 (8.38) BOTTOM u 5013 (0.38) (rns pow) =F BSC = 0.032 (0.81) 0.290 (7.37) (PINS UP) 0.200 (5.08) q 0.026 (0.66) Os 149 Ff MAX 0.150 0.200 (5.08) G. Bt) 0.020 |A_ 9 13 ele (0.50) 4 0.125 (3.18) MIN 01356 (9.04) >i [sm f+ 0.028 0.64 MIN (3.18) eile oh bee R =i 0,015 (0.38) 0-350 (8.89) 0.023 (0.58) 0.100 vine 78) wn 0120 a earrieaey (254) BESeRSR 0.008 (0.0) 0.014 (0.36) 2.54 0.030 (0.76) P 0,395 (10.02). 1090 (2.29) 0385 (76) CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN 20-Lead Plastic Dual In-Line Package [PDIP] (N-20) Dimensions shown in inches and (millimeters) COMPLIANT TO JEDEC STANDARDS MO-047AA CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN Figure 40. 20-Lead Plastic Leaded Chip Carrier [PLCC] (P-20A) Dimensions shown in inches and (mm) 0.985 (25.02) le 0.965 (24.51) a |_ 0.200 (5.08) 0,965 (24.51) 0.075 (1.91) 0.295 (7.49 REF 0.945 (24.00) Beers 0.100 (2.54) 0.100 (2.54) REF En En El ln Eg ln, Ee 2B 0.064 (1.63) 0.095 (2.41) 36 =r 0.275 (6.99) ae wy, 9.015 (0.38) : = 0.325 (8.26) F noes 2 s" . . Le 0.310 (7.87) 0.358 (9.09) 0.358 0.011 (0.28) toe e a 0.180(4.57) _ 0,015 (0:38) MIN 5.300 (7.62) ali 63) 0.150 (3.81) 0.342 (8.69) (9.09) aooT OTe) Pel BOTTOM o 022 (0.56) MAX] 015 (0. 0.138 (3.43) @. ai sQ sQ ~RTYP Lg" 0.050 (1.27) (3.05) 0.075 (1.91) F ese 4 YARRA ARR TE | REF PULLILAS . vp RETR ht cera, fF gustan] degadi . : elke 0.054 (1.37 , . eps 0100 0.060 (1.52) SEATING 0.015 (0.38) (1.37) 0.045 (1.14) BSC .110 (2.79) 0,022 (0.56) 4) 5.050 (4.37) PLANE 0.010 (0.25) 0.018 (0.46 0.050 (1.27) 50141036) . = BSC 0.045 (7.14) 9.008 (0.20) CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 24, 20-Terminal Ceramic Leadless Chip Carrier [LCC] (E-20) Dimensions shown in inches and (millimeters) 022106-A COMPLIANT TO JEDEC STANDARDS MO-095-AE CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN A I I I 0.28 (7.11) O24 (61) 4 0.32 (8.128 rrr rye 0.97 (2464) 0.29 (7.366 6.938 (23.75) t J 0.20 15.0 0.18 (4.57) | 0.15 (3.8) f 0.011 (0.28 ao) UU | ey t on 07 (1.78) 0.02 ios 5) 7, 2.79) 15. G05 127) 6.016 (0.41) 0.05 (2.28 0 20-Lead Cerdip (Q-20) REV.A