Copyright ANPEC Electronics Corp.
Rev. A.2 - Apr., 2010 www.anpec.com.tw1
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and
advise customers to obtain the latest version of relevant information to verify before placing orders.
3W Mono Fully Differential Audio Power Amplifier
APA0714
The APA0714 is a Mono, fully differential Class-AB audio
amplifier which can operate with supply voltage from 2.4V
to 5V and is available in MSOP8, MSOP8P, or TDFN3x3-8
package.
The built-in feedback resistors can minimize the external
component count and save the PCB space. High PSRR
and fully differential architecture increase immunity to
noise and RF rectification. In addition to these features, a
short startup time and small package size make the
APA0714 an ideal choice for Mobil Phones and Portable
Devices.
The APA0714 also integrates the de-pop circuitry that re-
duces the pops and click noises during power on/off and
shutdown mode operation. Both Thermal and over-cur-
rent protections are integrated to avoid the IC to be de-
stroyed by over temperature and short-circuit.
The APA0714 is capable of driving 3W at 5V into 3Ω
speaker.
FeaturesGeneral Description
Applications
•Mobil Phones
•Portable Devices
•Operating Voltage: 2.4V~5.5V
•Fully Differential Class-AB Amplifier
•High PSRR and Excellent RF Rectification
Immunity
•Low Crosstalk
•3W Output Power into 3Ω Load at VDD=5V
•Thermal and Over-Current Protections
•Built-in Feedback Resistors Eliminate
External Components Counts
•Space Saving Package
- MSOP-8
- MSOP-8P
- TDFN3x3-8
•Lead Free and Green Devices Available
(RoHS Compliant)
Simplified Application Circuit
APA0714
Input Speaker
LINN
LINP
LOUTP
LOUTN
Pin Configuration
BYPASS 27 GND
INP 3
INN 4
6 VDD
5 OUTP
8 OUTN
SD 1
MSOP-8
Top View
BYPASS 27 GND
INP 3
INN 4
6 VDD
5 OUTP
8 OUTN
SD 1
MSOP-8P
Top View
BYPASS 2
INP 3
INN 4
SD 1
7 GND
6 VDD
5 OUTP
8 OUTN
TDFN3x3-8
TOP View
=Thermal Pad (connected the Thermal Pad to
GND plane for better heat dissipation)
Copyright ANPEC Electronics Corp.
Rev. A.2 - Apr., 2010 www.anpec.com.tw2
APA0714
Symbol
Parameter Rating Unit
VDD Supply Voltage -0.3 to 6 V
Input Voltage (INN, INP, SD to GND) -0.3 to 6
VIN Input Voltage (OUTN, OUTP to GND) -0.3 to VDD +0.3 V
TJ Maximum Junction Temperature 150 οC
TSTG Storage Temperature Range -65 to +150 οC
TSDR Maximum Soldering Temperature Range, 10 Seconds 260 οC
PD Power Dissipation Internally Limited W
Ordering and Marking Information
Absolute Maximum Ratings (Note 1)
Note : ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which
are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for
MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen
free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by
weight).
Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Thermal Characteristics
Symbol Parameter Typical Value Unit
θJA
Thermal Resistance -Junction to Ambient (Note 2) MSOP-
8
MSOP-
8P
TDFN3x3-
8
200
50
52
οC/W
θJC Thermal Resistance -Junction to Case (Note 3) MSOP-
8P
TDFN3x3-
8
10
11
οC/W
Note 2: Please refer to “ Layout Recommendation”, the Thermal Pad on the bottom of the IC should soldered directly to the PCB’s
ThermalPad area that with several thermal vias connect to the ground plan, and the PCB is a 2-layer, 5-inch square area with 2oz
copper thickness.
Note 3: The case temperature is measured at the center of the Thermal Pad on the underside of the MSOP-8P and TDFN3x3-8
package.
APA0714
Handling Code
Temperature Range
Package Code
XXXXX - Date Code
Assembly Material
APA0714 X :
APA0714 XA :
APA0714 QB :
XXXXX - Date Code
XXXXX - Date Code
APA
0714
XXXXX
A0714
XXX
XX
Package Code
X : MSOP-8 XA : MSOP-8P QB : TDFN3x3-8
Operating Ambient Temperature Range
I : -40 to 85 oC
Handling Code
TR : Tape & Reel
Assembly Material
G : Halogen and Lead Free Device
A0714
XXX
XX
Copyright ANPEC Electronics Corp.
Rev. A.2 - Apr., 2010 www.anpec.com.tw3
APA0714
Symbol Parameter Rating Unit
VDD Supply Voltage 2.4
~
5.5 V
VIH High Level Threshold Voltage
SD 1.8
~
VDD V
VIL Low Level Threshold Voltage
SD 0
~
0.35 V
VIC Common Mode Input Voltage 0.5
~
VDD-0.5 V
Operating Ambient Temperature Range -40
~
85 οC
Operating Junction Temperature Range -40
~
125 οC
Speaker Resistance 3
~
Ω
Recommended Operating Conditions
APA0714
Symbol
Parameter Test Conditions Min.
Typ. Max.
Unit
IDD Supply Current - 3 6 mA
ISD Shutdown Current LSD=RSD=0V - - 5 µA
II Input Current LSD, RSD - 0.1 - µA
Gain RL=4Ω 36kΩ
Ri 40kΩ
Ri 44kΩ
Ri V/V
TSTART-UP Start-Up Time from End of
Shutdown Cb=0.22µF - 65 - ms
RSD Resistance from Shutdown to GND
90 100 110 kΩ
VDD=5V, TA=25°C
RL=3Ω - 2.4 -
RL=4Ω - 2.1 -
THD+N=1%
RL=8Ω 1 1.3 -
RL=3Ω - 3 -
RL=4Ω - 2.6 -
PO Output Power
THD+N=10%
fin=1kHz RL=8Ω - 1.6 -
W
RL=4Ω
PO=1.5W - 0.05 -
THD+N
Total Harmonic Distortion Pulse
Noise fin=1kHz RL=8Ω
PO=0.9W - 0.035
- %
PSRR Power Supply Rejection Ratio Cb=0.22µF, RL=8Ω, VRR=0.2VPP,
fin=217Hz - 80 - dB
CMRR Common-Mode Rejection Ratio Cb=0.22µF, RL=8Ω, VIC=0.2VPP,
fin=217Hz - 60 - dB
S/N Signal to Noise Ratio With A-weighted Filter,
PO=1.3W, RL=8Ω - 105 - dB
VOS Output Offset Voltage RL=8Ω - 5 20 mV
Vn Noise Output Voltage Cb=0.22µF, With A-weighting Filter - 15 - µV
(rms)
Electrical Characteristics
VDD=5V, GND=0V, TA= 25oC (unless otherwise noted)
Copyright ANPEC Electronics Corp.
Rev. A.2 - Apr., 2010 www.anpec.com.tw4
APA0714
Electrical Characteristics (Cont.)
VDD=5V, GND=0V, TA= 25oC (unless otherwise noted)
APA0714
Symbol
Parameter Test Conditions Min.
Typ. Max. Unit
VDD=3.6V, TA=25°C
RL=3Ω - 1.2 -
RL=4Ω - 1 - THD+N=1%
RL=8Ω - 0.65 -
RL=3Ω - 1.5 -
RL=4Ω - 1.3 -
PO Output Power
THD+N=10%
fin=1kHz RL=8Ω - 0.8 -
W
RL=4Ω
PO=0.7W - 0.07 -
THD+N
Total Harmonic Distortion
Pulse Noise fin=1kHz RL=8Ω
PO=0.45W - 0.05 - %
PSRR Power Supply Rejection Ratio Cb=0.22µF, RL=8Ω, VRR=0.2VPP,
fin=217Hz - 78 -
CMRR Common-Mode Rejection
Ratio Cb=0.22µF, RL=8Ω, VIC=0.2VPP,
fin=217Hz - 60 -
S/N Signal to Noise Ratio With A-weighting Filter,
PO=0.65W, RL=8Ω - 103 -
dB
VOS Output Offset Voltage RL=8Ω - 5 20 mV
Vn Noise Output Voltage Cb=0.22µF, With A-weighting Filter - 15 - µV
(rms)
VDD=2.4V, TA=25°C
RL=3Ω - 0. 5 -
RL=4Ω - 0.45 -
THD+N=1%
RL=8Ω - 0.3 -
RL=3Ω - 0.7 -
RL=4Ω - 0.6 -
PO Output Power
THD+N=10%
fin=1kHz RL=8Ω - 0.35 -
W
PO=0.3W,
RL=4Ω - 0.1 -
THD+N
Total Harmonic Distortion
Pulse Noise fin = 1kHz PO=0.2W,
RL=8Ω - 0.08 - %
PSRR Power Supply Rejection Ratio Cb=0.22µF, RL=8Ω, VRR=0.2VPP,
fin=217Hz - 75 -
CMRR Common-Mode Rejection
Ratio Cb=0.22µF, RL=8Ω, VIC=0.2VPP,
fin=217Hz - 60 -
S/N Signal to Noise Ratio With A-weighting Filter,
PO=0.3W, RL=8Ω - 100 -
dB
VOS Output Offset Voltage RL=8Ω - 5 20 mV
Vn Noise Output Voltage Cb=0.22µF, With A-weighting Filter - 15 - µV
(rms)
Copyright ANPEC Electronics Corp.
Rev. A.2 - Apr., 2010 www.anpec.com.tw5
APA0714
Typical Operating Characteristics
0.01
10
0.1
1
10m 5100m 1
THD+N (%)
Output Power (W)
THD+N vs. Output Power
VDD=2.4V
VDD=3.6V VDD=5.0V
RL=3Ω
fin=1kHz
Ci=0.22µF
AV=12dB
BW<80kHz
0.01
10
0.1
1
10m 5100m 1
THD+N (%)
Output Power (W)
THD+N vs. Output Power
VDD=2.4V
VDD=3.6V VDD=5.0V
RL=4Ω
fin=1kHz
Ci=0.22µF
AV=12dB
BW<80kHz
0.01
10
0.1
1
10m 3100m 1
THD+N (%)
Output Power (W)
THD+N vs. Output Power
VDD=2.4V
VDD=3.6V VDD=5.0V
RL=8Ω
fin=1kHz
Ci=0.22µF
AV=12dB
BW<80kHz
0.01
10
0.1
1
20 20k100 1k 10k
THD+N vs. Frequency
Frequency (Hz)
VDD=5.0V
RL=3Ω
Ci=0.22µF
AV=12dB
BW<80kHz
THD+N (%)
PO=1.7W
PO=1W
0.01
10
0.1
1
20 20k100 1k 10k
THD+N vs. Frequency
Frequency (Hz)
VDD=5.0V
RL=4Ω
Ci=0.22µF
AV=12dB
BW<80kHz
THD+N (%)
PO=1.5W
PO=1W
0.01
10
0.1
1
20 20k100 1k 10k
THD+N vs. Frequency
Frequency (Hz)
THD+N (%)
PO=0.9W
PO=0.5W
VDD=5.0V
RL=8Ω
Ci=0.22µF
AV=12dB
BW<80kHz
Copyright ANPEC Electronics Corp.
Rev. A.2 - Apr., 2010 www.anpec.com.tw6
APA0714
Typical Operating Characteristics (Cont.)
0.01
10
0.1
1
20 20k100 1k 10k
THD+N vs. Frequency
Frequency (Hz)
THD+N (%)
PO=0.1W
PO=0.7W
PO=0.5W
VDD=3.6V
RL=4Ω
Ci=0.22µF
AV=12dB
BW<80kHz
0.01
10
0.1
1
20 20k100 1k 10k
THD+N vs. Frequency
Frequency (Hz)
THD+N (%)
PO=0.1W
PO=0.45W
PO=0.25W
VDD=3.6V
RL=8Ω
Ci=0.22µF
AV=12dB
BW<80kHz
0.01
10
0.1
1
20 20k100 1k 10k
THD+N vs. Frequency
Frequency (Hz)
THD+N (%)
PO=0.3W
PO=0.1W
VDD=2.4V
RL=4Ω
Ci=0.22µF
AV=12dB
BW<80kHz
0.01
10
0.1
1
20 20k100 1k 10k
THD+N vs. Frequency
Frequency (Hz)
THD+N (%)
PO=0.2W
PO=0.1W
VDD=2.4V
RL=8Ω
Ci=0.22µF
AV=12dB
BW<80kHz
RL=8Ω,THD+N=10%
RL=3Ω,THD+N=1%
RL=4Ω,THD+N=10%
RL=3Ω,THD+N=10%
RL=8Ω,THD+N=1%
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
2.4 3.0 3.5 4.0 4.5 5.0
Output Power (W)
Supply Volume (V)
Output Power vs. Supply Voltage
fin=1kHz
AV=12dB
RL=4Ω,THD+N=1%
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
3 8 13 18 23 28 32
Output Power vs. Load Resistance
Output Power (W)
Load Resistance (Ω)
fin=1kHz
AV=12dB
VDD=2.4V,THD+N=10%
VDD=2.4V,THD+N=1%
VDD=3.6V,THD+N=1%
VDD=3.6V,THD+N=10%
VDD=5V,THD+N=1%
VDD=5V,THD+N=10%
Copyright ANPEC Electronics Corp.
Rev. A.2 - Apr., 2010 www.anpec.com.tw7
APA0714
Typical Operating Characteristics (Cont.)
0.0
0.2
0.4
0.6
0.8
1.0
0.0 0.5 1.0 1.5 2.0 2.5 3.0
VDD=5V
fin=1kHz
AV=12dB
RL=8Ω
RL=4Ω
RL=3Ω
Supply Current vs. Output Power
Supply Current (A)
Output Power (W)
Power Dissipation vs. Output Power
Output Power (W)
Power Dissipation (W)
0.0
0.5
1.0
1.5
2.0
0.0 0.5 1.0 1.5 2.0 2.5 3.0
VDD=5V
fin=1kHz
AV=12dB
RL=3Ω
RL=4Ω
RL=8Ω
0.0
0.2
0.4
0.6
0.8
1.0
0.0 0.3 0.6 0.9 1.2 1.5 1.8
Power Dissipation vs. Output Power
VDD=3.6V
fin=1kHz
AV=12dB
RL=3Ω
RL=4Ω
RL=8Ω
Output Power (W)
Power Dissipation (W)
0.2
0.4
0.6
0.8
0.0 0.3 0.6 0.9 1.2 1.5 1.8
RL=8Ω
RL=4Ω
RL=3Ω
Supply Current vs. Output Power
Supply Current (A)
Output Power (W)
0.0
VDD=3.6V
fin=1kHz
AV=12dB
1u
50u
2u
3u
4u
5u
7u
10u
20u
30u
40u
20 20k50 100 200 500 1k 2k 5k 10k
Output Noise Voltage vs. Frequency
Output Noise Voltage (Vrms)
Frequency (Hz)
VDD=3.6V
RL=8Ω
AV=12dB
Ci=0.22µF
A-Weighting
1u
50u
2u
3u
4u
5u
7u
10u
20u
30u
40u
20 20k
50 100 200 500 1k 2k 5k 10k
Output Noise Voltage vs. Frequency
Output Noise Voltage (Vrms)
Frequency (Hz)
VDD=5.0V
RL=8Ω
AV=12dB
Ci=0.22µF
A-Weighting
Copyright ANPEC Electronics Corp.
Rev. A.2 - Apr., 2010 www.anpec.com.tw8
APA0714
Typical Operating Characteristics (Cont.)
+60
+260
+100
+140
+180
+220
+4
+14
+6
+8
+10
+12
10 200k100 1k 10k
Frequency Response
Frequency (Hz)
Gain (dB)
Phase (deg)
VDD=5.0V
AV=12dB
RL=8Ω
Ci=0.22µF
Gain
Phase
-100
+0
-90
-80
-70
-60
-50
-40
-30
-20
-10
20 20k100 1k 10k
Frequency (Hz)
PSRR vs. Frequency
Power Supply Rejection Ratio (dB)
VDD=3.6V
RL=8Ω
AV=12dB
Ci=0.22µF
Vrr=0.2Vrms
Cb=0.1µF
Cb=0.01µF
Cb=1µF
Cb=0.47µF
-80
+0
-70
-60
-50
-40
-30
-20
-10
20 20k100 1k 10k
CMRR vs. Frequency
Common Mode Rejection Ratio (dB)
Frequency (Hz)
RL=8Ω
AV=12dB
Vin=0.2VPP
Ci=0.22µF
VDD=2.4V
VDD=3.6V VDD=5.0V
1u
50u
2u
3u
4u
5u
7u
10u
20u
30u
40u
20 20k100 1k 10k
Output Noise Voltage vs. Frequency
Output Noise Voltage (Vrms)
Frequency (Hz)
VDD=2.4V
RL=8Ω
AV=12dB
Ci=0.22µF
A-Weighting
-100
+0
-90
-80
-70
-60
-50
-40
-30
-20
-10
1 52 3 4
CMRR vs. Common Mode Input Voltage
Common Mode Rejection Ratio (dB)
Common Mode Input Voltage (Vrms)
RL=8Ω
AV=12dB
fin=1kHz
Ci=0.22µF
VDD=2.4V
VDD=3.6V VDD=5.0V
-100
+0
-90
-80
-70
-60
-50
-40
-30
-20
-10
20 20k100 1k 10k
Frequency (Hz)
PSRR vs. Frequency
Power Supply Rejection Ratio (dB)
RL=8Ω
AV=12dB
Cb=0.22µF
Ci=0.22µF
Vrr=0.2Vrms
VDD=2.4V
VDD=3.6V VDD=5.0V
Copyright ANPEC Electronics Corp.
Rev. A.2 - Apr., 2010 www.anpec.com.tw9
APA0714
Typical Operating Characteristics (Cont.)
0
50
100
150
200
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
Bypass Capacitor (µF)
Start-up Time (ms)
Start-up Time vs. Bypass Capacitor
VDD=5.0V
Av=12dB
No Load
+60
+260
+100
+140
+180
+220
+4
+14
+6
+8
+10
+12
10 200k100 1k 10k
Frequency Response
Frequency (Hz)
Gain (dB)
Phase (deg)
Gain
Phase
VDD=3.6V
AV=12dB
RL=8Ω
Ci=0.22µF
+60
+260
+100
+140
+180
+220
+4
+14
+6
+8
+10
+12
10 200k100 1k 10k
Frequency Response
Frequency (Hz)
Gain (dB)
Phase (deg)
Gain
Phase
VDD=2.4V
AV=12dB
RL=8Ω
Ci=0.22µF
-160
+0
-120
-80
-40
02k
400 800 1.2k 1.6k
-160
+0
-120
-80
-40
Supply Voltage (dBV)
Output Voltage (dBV)
Frequency (Hz)
GSM Power Supply Rejection vs.
Frequency
1
2
3
4
5
02.4 3.0 3.5 4.0 4.5 5.0 5.5
Supply Voltage (V)
Supply Current (mA)
Av=12dB
No Load
Supply Current vs. Supply Voltage
Copyright ANPEC Electronics Corp.
Rev. A.2 - Apr., 2010 www.anpec.com.tw10
APA0714
Operating Waveforms
1
2
CH1: VDD, 100mV/Div, DC
CH2: VOUT, 20mV/Div, DC
Vottage Offset = 5.0V
VDD
VOUT
TIME: 2ms/Div
GSM Power Supply Rejection vs. Time
1
2
VDD
CH1: VDD, 2V/Div, DC
CH2: VOUT, 50mV/Div, DC
TIME: 20ms/Div
VOUT
Power On
1
2
CH1: VDD, 2V/Div, DC
CH2: VOUT, 50mV/Div, DC
TIME: 50ms/Div
VOUT
VDD
Power Off
1
2
CH1: VSD, 2V/Div, DC
CH2: VOUTN, 2V/Div, DC
TIME: 20ms/Div
VOUTN
VSD
Shutdown Release
Copyright ANPEC Electronics Corp.
Rev. A.2 - Apr., 2010 www.anpec.com.tw11
APA0714
Operating Waveforms (Cont.)
1
2
CH1: VSD, 2V/Div, DC
CH2: VOUTN, 2V/Div, DC
TIME: 20ms/Div
VOUTN
VSD
Shutdown
Pin Description
PIN
NO. NAME I/O/P
FUNCTION
1 SD I Shutdown mode control signal input, place left channel speaker amplifier in shutdown mode
when held low.
2 BYPASS P Bypass voltage input pin
3 INP I The non-inverting input of amplifier. INP is via a capacitor to Gnd for single-end (SE) input
signal.
4 INN I The inverting input of amplifier. INN is used as audio input terminal, typically.
5 ROUTP O The positive output terminal of speaker amplifier.
6 VDD P Supply voltage input pin
7 GND P Ground connection for circuitry.
8 LOUTN O The negative output terminal of speaker amplifier.
Copyright ANPEC Electronics Corp.
Rev. A.2 - Apr., 2010 www.anpec.com.tw12
APA0714
Block Diagram
OUTP
LINP
LINN
BYPASS
Bias and Control Circuitrys
SD
OUTN
Copyright ANPEC Electronics Corp.
Rev. A.2 - Apr., 2010 www.anpec.com.tw13
APA0714
Typical Application Circuits
Single-ended input mode
Input 0.22µF
0.22µF
SHUTDOWN
Control
4Ω
VDD
0.1µF10µF
Ci1
Ci2
5 OUTP
INP 3
INN 4
8 OUTN
Bias and Control
Circuitrys2 BYPASS
SD 1
6 VDD
7 GND
Rf1
Rf2
Ri1
Ri2
40kΩ
40kΩ
10kΩ
10kΩ
Cb
0.22µF
Cs1
Cs2
RSD
100kΩ
Copyright ANPEC Electronics Corp.
Rev. A.2 - Apr., 2010 www.anpec.com.tw14
APA0714
Typical Application Circuits (Cont.)
Differential input mode
Input 0.22µF
0.22µF
SHUTDOWN
Control
4Ω
VDD
0.1µF10µF
Ci1
Ci2
5 OUTP
INP 3
INN 4
8 OUTN
Bias and Control
Circuitrys2 BYPASS
SD 1
6 VDD
7 GND
Rf1
Rf2
Ri1
Ri2
40kΩ
40kΩ
10kΩ
10kΩ
Cb
0.22µF
Cs1
Cs2
RSD
100kΩ
Copyright ANPEC Electronics Corp.
Rev. A.2 - Apr., 2010 www.anpec.com.tw15
APA0714
Function Description
Fully Differential Amplifier
The power amplifiers are fully differential amplifiers with
differential inputs and outputs. The fully differential ampli-
fier has some advantages versus traditional amplifiers.
First, don’t need the input coupling capacitors because
the common-mode feedback compensates the input bias.
The inputs can be biased from 0.5V~VDD-0.5V, and the
outputs are still biased at mid-supply of the power
amplifier. If the inputs are biased at out of the input range,
the coupling capacitors are required. Second, the fully
differential amplifier has outstanding immunity against
supply voltage ripple (217Hz) cuased by the GSM RF trans-
mitters signal which is better than the typical audio
amplifier.
Shutdown Function
The over-temperature circuit limits the junction tempera-
ture of the APA0714. When the junction temperature ex-
ceeds TJ=+150oC, a thermal sensor turns off the
amplifiers, allowing the device to cool. The thermal sen-
sor allows the amplifiers to start-up after the junction tem-
perature cools down to about 125 oC. The thermal protec-
tion is designed with a 25 oC hysteresis to lower the aver-
age TJ during continuous thermal overload conditions,
increasing lifetime of the IC.
Thermal Protection
Over-Current Protection
The APA0714 monitors the output buffers current. When
the over current occurs, the output buffers current will be
reduced and limited to a fold-back current level.
The power amplifier will go back to normal operation until
the over-current current situation has been removed. In
addition, if the over-current period is long enough and the
IC’s junction temperature reaches the thermal protection
threshold, the IC enters thermal protection mode.
In order to reduce power consumption while not in use,
the APA0714 contains a shutdown function to externally
turn off the amplifier bias circuitry. This shutdown feature
turns the amplifier off when logic low is placed on the SD
pin for APA0714. The trigger point between a logic high
and logic low level is typically 1.8V. It is best to switch
between ground and the supply voltage VDD to provide
maximum device performance. By switching the SD pin
to low level, the amplifier enters a low-consumption-cur-
rent state, IDD for APA0714 is in shutdown mode. Under
normal operating, APA0714’s SD pin should pull to high
level to keep the IC out of the shutdown mode. The SD
pin should be tied to a definite voltage to avoid unwanted
state change.
Copyright ANPEC Electronics Corp.
Rev. A.2 - Apr., 2010 www.anpec.com.tw16
APA0714
Effective Bypass Capacitor (CBYPASS)
The BYPASS pin sets the VDD/2 for internal reference by
voltage divider. Adding capacitors at this pin to filter the
noise and regulator the mid-supply rail will increase the
PSRR and noise performance.
The capacitors should be as close to the device as
possible. The effect of a larger bypass capacitor will im-
prove PSRR due to increased supply stability.
The bypass capacitance also affects to the start time. The
large capacitors will increase the start time when device
in shutdown.
Optimizing Depop Circuitry
Circuitry has been included in the APA0714 to minimize
the amount of popping noise at power-up and when com-
ing out of shutdown mode. Popping occurs whenever a
voltage step is applied to the speaker. In order to elimi-
nate clicks and pops, all capacitors must be fully dis-
charged before turn-on. Rapid on/off switching of the de-
vice or the shutdown function will cause the click and pop
circuitry.
The value of Ci will also affect turn-on pops. The bypass
voltage ramp up should be slower than input bias voltage.
Although the BYPASS pin current source cannot be
modified, the size of CBYPASS can be changed to alter the
device turn-on time and the amount of clicks and pops.
By increasing the value of CBYPASS, turn-on pop can be
reduced. However, the tradeoff for using a larger bypass
capacitor is to increase the turn-on time for this device.
There is a linear relationship between the size of CBYPASS
and the turn-on time.
A high gain amplifier intensifies the problem as the small
delta in voltage is multiplied by the gain. Hence, it is ad-
vantageous to use low-gain configurations.
Power Supply Decoupling Capacitor (Cs)
The APA0714 is a high-performance CMOS audio ampli-
fier that requires adequate power supply decoupling to
ensure the output total harmonic distortion (THD+N) is
as low as possible. Power supply decoupling also pre-
This leakage current creates a DC offset voltage at the
input of the amplifier. The offset reduces useful
headroom, especially in high gain applications. For this
reason, a low-leakage tantalum or ceramic capacitor is
the best choice. When polarized capacitors are used, the
positive side of the capacitor should face the amplifier
input in most applications because the DC level of the
Application Information
Input Resistance (Ri)
The gain for the APA0714 is set by the external input re-
sistors (Ri) and internal feedback resistors (Rf).
i
f
VR
R
A=(1)
The internal feedback resistors are 40kΩ typical. For the
performance of a fully differential amplifier, it’s better to
select matching input resistors Ri1 and Ri2. Therefore,
1% tolerance resistors are recommended. If the input
resistors are not matched, the CMRR and PSRR perfor-
mance are worse than using matching devices.
Input Capacitor (Ci)
When the APA0714 is driven by a differential input source,
the input capacitor may not be required.
In the single-ended input application, an input capacitor,
Ci, is required to allow the amplifier to bias the input sig-
nal to the proper DC level for optimum operation. In this
case, Ci and the input resistance Ri form a high-pass filter
with the corner frequency determined in the following
equation:
ii
)C(highpass CR21
Fπ
=(2)
The value of Ci must be considered carefully because it
directly affects the low frequency performance of the circuit.
Consider the example where Ri is 10kΩ and the specifi-
cation that calls for a flat bass response down to 100Hz.
The equation is reconfigured below:
ci
iFR21
Cπ
=(3)
When the input resistance variation is considered, the Ci
is 0.16µF. So a value in the range of 0.22µF to 0.47µF
would be chosen. A further consideration for this capaci-
tor is the leakage path from the input source through the
input network (Ri + Rf, Ci) to the load.
amplifiers’ inputs are held at VDD/2. Please note that it is
important to confirm the capacitor polarity in the application.
Copyright ANPEC Electronics Corp.
Rev. A.2 - Apr., 2010 www.anpec.com.tw17
APA0714
RL (Ω)
PO (W)
Efficiency
(%) IDD(A)
PD (W)
PSUP (W)
0.25 30.1 0.17 0.58 0.83
0.50 43.1 0.23 0.66 1.16
1 61.5 0.33 0.63 1.63
8
1.6 77.7 0.43 0.46 2.06
0.4 27.5 0.29 1.06 1.46
1.2 48.1 0.51 1.30 2.50
2 62.4 0.66 1.21 3.21
4
2.6 74.1 0.70 0.91 3.51
0.5 27.5 0.37 1.32 1.82
1 38.7 0.52 1.58 2.58
2 55.1 0.74 1.63 3.63
3
3 66.8 0.92 1.49 4.49
Application Information (Cont.)
Layout Recommendation
1. All components should be placed close to the APA0714.
For example, the input capacitor (Ci) should be close to
APA0714’s input pins to avoid causing noise coupling to
APA0714’s high impedance inputs; the decoupling ca-
pacitor (Cs) should be placed by the APA0714’s power pin
to decouple the power rail noise.
2. The output traces should be short, wide ( >50mil), and
symmetric.
3. The input trace should be short and symmetric.
4. The power trace width should greater than 50mil.
5. The MSOP-8P and DFN3x3-8 Thermal PAD should be
soldered on PCB, and the ground plane needs soldered
mask (to avoid short circuit) except the Thermal PAD area.
A final point to remember about linear amplifiers (either
SE or Differential) is how to manipulate the terms in the
efficiency equation to an utmost advantage when possible.
Note that in equation, VDD is in the denominator. This indi-
cates that as VDD goes down, efficiency goes up. In other
words, use the efficiency analysis to choose the correct
supply voltage and speaker impedance for the application.
Table 1 calculates efficiencies for four different output
power levels. Note that the efficiency of the amplifier is
quite low for lower power levels and rises sharply as
power to the load is increased resulting in nearly flat in-
ternal power dissipation over the normal operating range.
Note that the internal dissipation at full output power is
The optimum decoupling is achieved by using two differ-
ent types of capacitors that target on different types of
noises on the power supply leads. For higher frequency
transients, spikes, or digital hash on the line, a good low
equivalent-series- resistance (ESR) ceramic capacitor,
typically 0.1µF, is placed as close as possible to the de-
vice VDD lead works best. For filtering lower frequency
noise signals, a large aluminum electrolytic capacitor of
10µF or greater placed near the audio power amplifier is
recommended.
Fully Differential Amplifier Efficiency
The traditional class AB power amplifier efficiency can be
calculated starts out as being equal to the ratio of power
from the power supply to the power delivered to the load.
The following equations are the basis for calculating the
amplifier efficiency.
where:
So the Efficiency (η) is:
Power Supply Decoupling Capacitor (Cs) (Cont.)
SUP
O
P
P
)( Efficiency =η
L
2
P
L
2
Orms
OR2
V
R
V
P==
2
V
VP
Orms =
L
PPDD
AVGDDDDSUP RV2V
XIV Pπ
=＝
）（
L
P
AVG)DD R
2V
Iπ
=
（
DD
LO
DD
P4V R2P
4V
V
)( Efficiency π
π
=η＝
(4)
(5)
(6)
less than the dissipation in the half power range. Calcu-
lating the efficiency for a specific system is the key to
proper power supply design. For a Mono 1W audio sys-
tem with 8Ω loads and a 5V supply, the maximum draw
on the power supply is almost 1.63W.
Table 1: Efficiency vs. Output Power in 5-V Differential
Amplifier Syetems
vents the oscillations caused by long lead length between
the amplifier and the speaker.
Copyright ANPEC Electronics Corp.
Rev. A.2 - Apr., 2010 www.anpec.com.tw18
APA0714
Application Information (Cont.)
Layout Recommendation (Cont.)
Figure 1: TDFN3X3-8 Land Pattern Recommendation
1.4mm
1.85mm
0.38mm
3.3mm
0.65mm
0.7mm
Ground plane
for Thermal
PAD
Solder Mask
to Prevent
Short Circuit
ThermalVia
diameter
0.3mm X 5
1.95mm
Copyright ANPEC Electronics Corp.
Rev. A.2 - Apr., 2010 www.anpec.com.tw19
APA0714
Package Information
MSOP-8
A
0
L
VIEW A
0.25
GAUGE PLANE
SEATING PLANE
A1
D
e
SEE VIEW A
E1
E
A2
bc
S
Y
M
B
O
LMIN. MAX.
1.10
0.00
0.22 0.38
0.08 0.23
0.15
A
A1
b
c
D
E
E1
e
L
MILLIMETERS
A2 0.75 0.95
0.65 BSC
MSOP-8
0.40 0.80 0.026 BSC
MIN. MAX.
INCHES
0.043
0.000
0.030 0.037
0.009 0.015
0.003 0.009
0.016 0.031
0
0.006
0
°
8
°
0
°
8
°
4.70 5.10
2.90 3.10
2.90 3.10 0.114 0.122
0.185 0.201
0.114 0.122
Note: 1. Follow JEDEC MO-187 AA.
2. Dimension“D”does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion or gate burrs shall not exceed 6 mil
per side.
3. Dimension“E1”does not include inter-lead flash or protrusions.
Inter-lead flash and protrusions shall not exceed 5 mil per side.
Copyright ANPEC Electronics Corp.
Rev. A.2 - Apr., 2010 www.anpec.com.tw20
APA0714
Package Information (Cont.)
MSOP-8P
A
0
L
VIEW A
0.25
SEATING PLANE
GAUGE PLANE
A1
D
e
SEE VIEW A
E1
E
A2
bc
D1
E2
EXPOSED
PAD
S
Y
M
B
O
LMIN. MAX.
1.10
0.00
0.22 0.38
0.08 0.23
0.15
A
A1
b
c
D
E
E1
e
L
MILLIMETERS
A2 0.75 0.95
0.65 BSC
MSOP-8P
0.40 0.80 0.026 BSC
MIN. MAX.
INCHES
0.043
0.000
0.030 0.037
0.009 0.015
0.003 0.009
0.016 0.031
0
0.006
D1
E2
1.50 2.50 0.059 0.098
1.50 2.50 0.059 0.098
0
°
8
°
0
°
8
°
2.90 3.10
2.90 3.10
4.70 5.10
0.114 0.122
0.185 0.201
0.114 0.122
Note: 1. Follow JEDEC MO-187 AA-T
2. Dimension “D”does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion or gate burrs shall not flash or protrusions.
3. Dimension “E1” does not include inter-lead flash or protrusions.
Inter-lead flash and protrusions shall not exceed 6 mil per side.
Copyright ANPEC Electronics Corp.
Rev. A.2 - Apr., 2010 www.anpec.com.tw21
APA0714
Package Information (Cont.)
TDFN3x3-8
D
E
Pin 1
A
b
A1
A3
S
Y
M
B
O
LMIN. MAX.
0.80
0.00
0.25 0.35
1.90 2.40
0.05
1.40
A
A1
b
D
D2
E
E2
e
L
MILLIMETERS
A3 0.20 REF
TDFN3x3-8
0.30 0.50
1.75
0.008 REF
MIN. MAX.
INCHES
0.031
0.000
0.010 0.014
0.075 0.094
0.055
0.012 0.020
0.70
0.069
0.028
0.002
0.65 BSC 0.026 BSC
0.20 0.008
K
2.90 3.10 0.114 0.122
2.90 3.10 0.114 0.122
Pin 1 Corner
D2
e
E2K
L
Copyright ANPEC Electronics Corp.
Rev. A.2 - Apr., 2010 www.anpec.com.tw22
APA0714
Application
A H T1 C d D W E1 F
330.0±
2.00
50 MIN.
12.4+2.00
-
0.00
13.0+0.50
-0.20
1.5 MIN.
20.2 MIN.
12.0±
0.30
1.75±
0.10
5.5±
0.05
P0 P1 P2 D0 D1 T A0 B0 K0
MSOP-8
4.00±
0.10
8.00±
0.10
2.00±
0.05
1.5+0.10
-0.00
1.5 MIN.
0.6+0.00
-0.40
5.30±
0.20
3.30±
0.20
1.40±
0.20
Application
A H T1 C d D W E1 F
330.0±
2.00
50 MIN.
12.4+2.00
-
0.00
13.0+0.50
-0.20
1.5 MIN.
20.2 MIN.
12.0±
0.30
1.75±
0.10
5.5±
0.05
P0 P1 P2 D0 D1 T A0 B0 K0
MSOP-8P
4.00±
0.10
8.00±
0.10
2.00±
0.05
1.5+0.10
-0.00
1.5 MIN.
0.6+0.00
-0.40
5.30±
0.20
3.30±
0.20
1.40±
0.20
Application
A H T1 C d D W E1 F
178.0±
2.00
50 MIN.
12.4+2.00
-0.00
13.0+0.50
-0.20
1.5 MIN.
20.2 MIN.
12.0±
0.30
1.75±
0.10
5.5±
0.05
P0 P1 P2 D0 D1 T A0 B0 K0
TDFN3x3-8
4.0±
0.10
8.0±
0.10
2.0±
0.05
1.5+0.10
-0.00
1.5 MIN.
0.6+0.00
-0.40
3.30±
0.20
3.30±
0.20
1.30±
0.20
(mm)
Carrier Tape & Reel Dimensions
A
E1
A
B
W
F
T
P0
OD0
BA0
P2
K0
B0
SECTION B-B
SECTION A-A
OD1
P1
H
T1
A
d
Copyright ANPEC Electronics Corp.
Rev. A.2 - Apr., 2010 www.anpec.com.tw23
APA0714
Package Type Unit Quantity
MOSP-8 Tape & Reel 3000
MOSP-8P Tape & Reel 3000
TDFN3x3-8 Tape & Reel 3000
Devices Per Unit
Taping Dircetion Information
MSOP-8(P)
TDFN3x3-8
USER DIRECTION OF FEED
USER DIRECTION OF FEED
Copyright ANPEC Electronics Corp.
Rev. A.2 - Apr., 2010 www.anpec.com.tw24
APA0714
Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly
Preheat & Soak
Temperature min (Tsmin)
Temperature max (Tsmax)
Time (Tsmin to Tsmax) (ts)
100 °C
150 °C
60-120 seconds
150 °C
200 °C
60-120 seconds
Average ramp-up rate
(Tsmax to TP) 3 °C/second max. 3°C/second max.
Liquidous temperature (TL)
Time at liquidous (tL) 183 °C
60-150 seconds 217 °C
60-150 seconds
Peak package body Temperature
(Tp)* See Classification Temp in table 1 See Classification Temp in table 2
Time (tP)** within 5°C of the specified
classification temperature (Tc) 20** seconds 30** seconds
Average ramp-down rate (Tp to Tsmax)
6 °C/second max. 6 °C/second max.
Time 25°C to peak temperature 6 minutes max. 8 minutes max.
* Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum.
** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum.
Classification Reflow Profiles
Classification Profile
Copyright ANPEC Electronics Corp.
Rev. A.2 - Apr., 2010 www.anpec.com.tw25
APA0714
Customer Service
Anpec Electronics Corp.
Head Office :
No.6, Dusing 1st Road, SBIP,
Hsin-Chu, Taiwan
Tel : 886-3-5642000
Fax : 886-3-5642050
Taipei Branch :
2F, No. 11, Lane 218, Sec 2 Jhongsing Rd.,
Sindian City, Taipei County 23146, Taiwan
Tel : 886-2-2910-3838
Fax : 886-2-2917-3838
Classification Reflow Profiles (Cont.)
Table 1. SnPb Eutectic Process – Classification Temperatures (Tc)
Package
Thickness Volume mm3
<350 Volume mm3
≥350
<2.5 mm 235 °C 220 °C
≥2.5 mm 220 °C 220 °C
Table 2. Pb-free Process – Classification Temperatures (Tc)
Package
Thickness Volume mm3
<350 Volume mm3
350-2000 Volume mm3
>2000
<1.6 mm 260 °C 260 °C 260 °C
1.6 mm – 2.5 mm 260 °C 250 °C 245 °C
≥2.5 mm 250 °C 245 °C 245 °C
Reliability Test Program
Test item Method Description
SOLDERABILITY JESD-22, B102 5 Sec, 245°C
HOLT JESD-22, A108 1000 Hrs, Bias @ Tj=125°C
PCT JESD-22, A102 168 Hrs, 100%RH, 2atm, 121°C
TCT JESD-22, A104 500 Cycles, -65°C~150°C
HBM MIL-STD-883-3015.7 VHBM≧2KV
MM JESD-22, A115 VMM≧200V
Latch-Up JESD 78 10ms, 1tr≧100mA
