SN75ALS171, SN75ALS171A
TRIPLE DIFFERENTIAL BUS TRANSCEIVERS
SLLS056D – AUGUST 1987 – REVISED SEPTEMBER 1995
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Three Bidirectional Transceivers
D
Driver Meets or Exceeds the Requirements
of ANSI EIA/TIA-422-B and RS-485 and ITU
Recommendation V.11
D
Two Skew Limits Available
D
Designed to Operate Up to 20 Million Data
Transfers per Second (FAST-20 SCSI)
D
High-Speed Advanced Low-Power Schottky
Circuitry
D
Low Pulse Skew...5 ns Max
D
Designed for Multipoint Transmission on
Long Bus Lines in Noisy Environments
D
Features Independent Driver Enables and
Combined Receiver Enables
D
Wide Positive and Negative Input/Output
Bus Voltages Ranges
D
Driver Output Capacity...±60 mA
D
Thermal Shutdown Protection
D
Driver Positive- and Negative-Current
Limiting
D
Receiver Input Impedances...12 kΩ Min
D
Receiver Input Sensitivity...±300 mV Max
D
Receiver Input Hysteresis...60 mV Typ
D
Operates From a Single 5-V Supply
D
Glitch-Free Power-Up and Power-Down
Protection
description
The SN75ALS171 and the SN75ALS171A triple differential bus transceivers are monolithic integrated circuits
designed for bidirectional data communication on multipoint bus transmission lines. They are designed for
balanced transmission lines, and each driver meets ANSI Standards EIA/TIA-422-B and RS-485 and both the
drivers and receivers meet ITU Recommendation V .11. The SN75ALS171A is designed for F AST -20 SCSI and
can transmit or receive data pulses as short as 30 ns with a maximum skew of 5 ns.
The SN75ALS171 and the SN75ALS171A operate from a single 5-V power supply. The drivers and receivers
have individual active-high and active-low enables, respectively, which can be externally connected together
to function as a direction control. The driver differential output and the receiver differential input pairs are
connected internally to form differential input/output (I/O) bus ports that are designed to of fer minimum loading
to the bus when the driver is disabled or VCC is at 0 V. These ports feature wide positive and negative
common-mode voltage ranges making the device suitable for party-line applications.
The SN75ALS171 and the SN75ALS171A are characterized for operation from 0°C to 70°C.
Copyright 1995, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
DW OR J PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
1R
1DE
1D
GND
GND
2R
2DE
2D
3R
3DE
1B
1A
RE
CDE
VCC
2B
2A
3B
3A
3D
SN75ALS171, SN75ALS171A
TRIPLE DIFFERENTIAL BUS TRANSCEIVERS
SLLS056D – AUGUST 1987 – REVISED SEPTEMBER 1995
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Function Tables
EACH DRIVER
INPUT ENABLES OUTPUTS
DDE CDE A B
H H H H L
L H HLH
XLXZZ
XXLZZ
EACH RECEIVER
DIFFERENTIAL INPUTS ENABLE OUTPUT
A–B RE R
VID ≥ 0.3 V L H
–0.3 V < VID < 0.3 V L ?
VID ≤ –0.3 V L L
X H Z
Open L H
H = high level, L = low level, ? = indeterminate, X = irrelevant,
Z = high impedance (off)
AVAILABLE OPTIONS
SKEW LIMIT PART NUMBER
10 ns SN75ALS171DW SN75ALS171J
5 ns SN75ALS171ADW
SN75ALS171, SN75ALS171A
TRIPLE DIFFERENTIAL BUS TRANSCEIVERS
SLLS056D – AUGUST 1987 – REVISED SEPTEMBER 1995
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic symbol†
EN4
5EN3
5EN2
5EN1
G5
9
11
6
8
1
3
18
10
7
2
17
3R
2R
1R
RE
3DE
2DE
1DE
CDE
1
1
1
3D
2D
1D
3B
3A
2B
2A
1B
1A
13
12
15
14
20
19
1
1
2
2
3
3
4
4
4
†This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
logic diagram (positive logic)
1B
1A
20
19
2B
2A
15
14
3B
3A
13
12
17
2
3
18
1
7
8
6
10
11
9
Bus
Bus
Bus
CDE
1DE
1D
RE
1R
2DE
2D
3DE
2R
3D
3R
schematics of inputs and outputs
EQUIVALENT OF EACH INPUT
Driver Input: R(eq) = 12 kΩ NOM
Enable Inputs: R(eq) = 8 kΩ NOM
R(eq) = equivalent resistor
TYPICAL OF A AND B I/O PORTS TYPICAL OF RECEIVER OUTPUT
85 Ω
NOM
Output
VCC
1.1 kΩ
NOM
3 kΩ
NOM
18 kΩ
NOM
A or B
180 kΩ
NOM
Connected
on A Port
VCC
R(eq)
VCC
Input
180 kΩ
NOM
Connected
on B Port
SN75ALS171, SN75ALS171A
TRIPLE DIFFERENTIAL BUS TRANSCEIVERS
SLLS056D – AUGUST 1987 – REVISED SEPTEMBER 1995
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VCC (see Note 1) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range at any bus terminal –7 V to 12 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Enable input voltage, VI 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous total power dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, TA 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: DW package 260°C. . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: J package 300°C. . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may af fect device reliability.
NOTE 1: All voltage values, except differential I/O bus voltage, are with respect to network ground terminal.
DISSIPATION RATING TABLE
PACKAGE TA ≤ 25°C
POWER RATING DERATING FACTOR
ABOVE TA = 25°CTA = 70°C
POWER RATING
DW 1125 mW 9.0 mW/°C 720 mW
J1025 mW 8.2 mW/°C 656 mW
recommended operating conditions
MIN NOM MAX UNIT
Supply voltage, VCC 4.75 5 5.25 V
Voltage at any bus terminal (separately or common mode), VI or VIC –7 12 V
High-level input voltage, VIH D, CDE, DE, and RE 2 V
Low-level input voltage, VIL D, CDE, DE, and RE 0.8 V
Differential input voltage, VID (see Note 2) ±12 V
High level out
p
ut current IOH
Driver –60 mA
High
-
le
v
el
o
u
tp
u
t
c
u
rrent
,
I
OH Receiver –400 µA
Low level out
p
ut current IOL
Driver 60
mA
Lo
w-
le
v
el
o
u
tp
u
t
c
u
rrent
,
I
OL Receiver 8
mA
Operating free-air temperature, TA0 70 °C
NOTE 2: Differential-input/output bus voltage is measured at the noninverting terminal A with respect to the inverting terminal B.
SN75ALS171, SN75ALS171A
TRIPLE DIFFERENTIAL BUS TRANSCEIVERS
SLLS056D – AUGUST 1987 – REVISED SEPTEMBER 1995
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DRIVER SECTION
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS†MIN TYP‡MAX UNIT
VIK Input clamp voltage II = –18 mA –1.5 V
VOOutput voltage IO = 0 0 6 V
VOH High-level output voltage VCC = 4.75 V,
VIL = 0.8 V, VIH = 2 V,
IOH = –55 mA 2.7 V
VOL Low-level output voltage VCC = 4.75 V,
VIL = 0.8 V, VIH = 2 V,
IOL = 55 mA 1.7 V
|VOD1|Differential output voltage IO = 0 1.5 6 V
|VOD2|Differential output voltage RL = 100 Ω,See Figure 1 1/2VOD1
or 2§2.5 5 V
OD2
g
RL = 54 Ω,See Figure 1 1.5 2.5 5
VOD3 Differential output voltage Vtest = –7 V to 12 V, See Figure 2 1.5 5 V
∆|VOD|Change in magnitude of differential
output voltage¶±0.2 V
VOC
Common mode out
p
ut voltage
RL=54Ωor 100 Ω
See Figure 1
3
V
V
OC
Common
-
mode
o
u
tp
u
t
v
oltage
R
L =
54
Ω
or
100
Ω
,
See
Fig
u
re
1
–1
V
∆|VOC|Change in magnitude of common-mode
output voltage¶±0.2 V
IO
Out
p
ut current
Output disabled, VO = 12 V 1
mA
I
O
O
u
tp
u
t
c
u
rrent
,
See Note 3 VO = –7 V –0.8
mA
IIH
High level enable in
p
ut current
D and DE
VIH =27V
20
I
IH
High
-
le
v
el
enable
-
inp
u
t
c
u
rrent
CDE
V
IH =
2
.
7
V
60
µA
IIL
Low level enable in
p
ut current
D and DE
VIL =04V
–100 µ
A
I
IL
Lo
w-
le
v
el
enable
-
inp
u
t
c
u
rrent
CDE
V
IL =
0
.
4
V
–900
VO = –6 V –250
IOS
Short circuit output current
VO = 0 –150
mA
I
OS
Sh
or
t
-c
i
rcu
it
ou
t
pu
t
curren
t
VO = VCC 250
mA
VO = 8 V 250
ICC
Su
pp
ly current
No load
Outputs enabled 69 90
mA
I
CC
S
u
ppl
y
c
u
rrent
No
load
Outputs disabled 57 78
mA
†The power-off measurement in ANSI Standard EIA/TIA-422-B applies to disabled outputs only and is not applied to combined inputs and outputs.
‡All typical values are at VCC = 5 V and TA = 25°C.
§The minimum VOD2 with 100-W load is either 1/2 VOD2 or 2 V, whichever is greater.
¶∆|VOD| and ∆|VOC| are the changes in magnitude of VOD and VOC, respectively , that occur when the input is changed from a high level to a
low level.
NOTE 3: This applies for both power on and off; refer to EIA Standard RS-485 for exact conditions. The EIA/TIA-422-B limit does not apply for
a combined driver and receiver terminal.
SN75ALS171, SN75ALS171A
TRIPLE DIFFERENTIAL BUS TRANSCEIVERS
SLLS056D – AUGUST 1987 – REVISED SEPTEMBER 1995
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
ALS171 R
L
= 54 Ω,See Figure 3, 3 13
ALS171A
L,
CL = 50 pF
g,
611
td(OD) Differential output delay time ALS171 RL1 = RL3 = 165 Ω,
CL=60
p
F
VTERM = 5 V,
See Figure 6
313 ns
ALS171A
C
L =
60
pF
,
RL2 = 75 Ω,
See
Figure
6
611
tk( )
Pulse skew‡
RL = 54 Ω,
See Figure 3 CL = 50 pF, 1 5 ns
t
sk(p)
P
u
l
se s
k
ew
‡
RL1 = RL3 = 165 Ω,
CL = 60 pF, RL2 = 75 Ω,
See Figure 6 1 5 ns
§
ALS171 R
L
= 54 Ω, C
L
= 50 pF, 10
tk(li )
Skew limit§
ALS171A
L,
See Figure 3
L,
5
ns
t
sk(lim)
Sk
ew
li
m
it§
ALS171 R
L1
= R
L3
= 165 Ω, R
L2
= 75 Ω,10
ns
ALS171A
L1 L3 ,
CL = 60 pF,
L2 ,
See Figure 6 5
RL = 54 Ω,
See Figure 3 CL = 50 pF, 3 8 13
tt(OD) Differential-output transition time RL1 = RL3 = 165 Ω,
CL = 60 pF,
See Figure 6
RL2 = 75 Ω,
VTERM = 5 V, 3 8 13 ns
tPZH Output enable time to high level RL = 110 Ω,See Figure 4 30 50 ns
tPZL Output enable time to low level RL = 110 Ω,See Figure 5 30 50 ns
tPHZ Output disable time from high level RL = 110 Ω,See Figure 4 3 8 13 ns
tPLZ Output disable time from low level RL = 110 Ω,See Figure 5 3 8 13 ns
tPDE Differential-output enable time RL1 = RL3 = 165 Ω, RL2 = 75 Ω,830 45 ns
tPDZ Differential-output disable time
L1 L3
CL = 60 pF,
L2
See Figure 7 5 10 45 ns
†All typical values are at VCC = 5 V and TA = 25°C.
‡Pulse skew is defined as the |td(ODH) – td(ODL)| of each channel.
§Skew limit is the maximum difference in propagation delay times between any two channels of one device and between any two devices. This
parameter is applicable at one VCC and operating temperature within the recommended operating conditions.
SYMBOL EQUIVALENTS
DATA-SHEET PARAMETER EIA/TIA-422-B RS-485
VOVoa, Vob Voa, Vob
|VOD1| VoVo
|VOD2| Vt (RL = 100 Ω) Vt (RL = 54 Ω)
|VOD3|Vt (Test Termination
Measurement 2)
Vtest Vtst
∆|VOD|||Vt|–|Vt|| ||Vt|–|Vt||
VOC |Vos||Vos|
∆|VOC||Vos –Vos||Vos –Vos|
IOS |Isa|, |Isb|
IO|Ixa|, |Ixb| Iia, Iib
SN75ALS171, SN75ALS171A
TRIPLE DIFFERENTIAL BUS TRANSCEIVERS
SLLS056D – AUGUST 1987 – REVISED SEPTEMBER 1995
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
RECEIVER SECTION
electrical characteristics over recommended ranges of common-mode input voltage, supply
voltage, and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
VIT+ Positive-going input threshold voltage VO = 2.7 V, IO = –0.4 mA 0.3 V
VIT– Negative-going input threshold voltage VO = 0.5 V, IO = 8 mA –0.3‡V
Vhys Hysteresis voltage (VIT+ – VIT–)60 mV
VIK Enable-input clamp voltage II = –18 mA –1.5 V
VOH High-level output voltage VID = 300 mV,
See Figure 8 IOH = –400 µA, 2.7 V
VOL Low-level output voltage VID = –300 mV,
See Figure 8 IOL = 8 mA, 0.45 V
IOZ High-impedance-state output current VO = 0.4 V to 2.4 V ±20 µA
II
Line in
p
ut current
Other input = 0 V, VI = 12 V 1
mA
I
I
Line
inp
u
t
c
u
rrent
,
See Note 4 VI = –7 V –0.8
mA
IIH High-level enable-input current VIH = 2.7 V 60 µA
IIL Low-level enable-input current VIL = 0.4 V –300 µA
riInput resistance 12 kΩ
IOS Short-circuit output current VID = 300 mV, VO = 0 –15 –85 mA
ICC
Su
pp
ly current
No load
Outputs enabled 69 90
mA
I
CC
S
u
ppl
y
c
u
rrent
No
load
Outputs disabled 57 78
mA
†All typical values are at VCC = 5 V and TA = 25°C.
‡The algebraic convention, in which the less positive (more negative) limit is designated minimum, is used in this data sheet for common-mode
input voltage and threshold voltage levels only.
NOTE 4: This applies for both power on and off; refer to EIA Standard RS-485 for exact conditions.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature range
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
tPLH
Pro
p
agation delay time low to high level out
p
ut
ALS171
VID =
–
15Vto15V
9 19
ns
t
PLH
Propagation
dela
y
time
,
lo
w-
to
high
-
le
v
el
o
u
tp
u
t
ALS171A
VID
=
–1
.
5
V
to
1
.
5
V
,
CL = 15 pF, 11 16
ns
tPHL
Pro
p
agation delay time high to low level out
p
ut
ALS171
L,
TA = 25°C,
SFi 9
9 19
ns
t
PHL
Propagation
dela
y
time
,
high
-
to
lo
w-
le
v
el
o
u
tp
u
t
ALS171A See Figure 9 11 16
ns
tsk(p) Pulse skew§V
ID
= –1.5 V to 1.5 V
,
2 5 ns
tk(li )
Ske limit¶
ALS171
VID
1.5
V
to
1.5
V,
C
L
= 15 pF, 10
ns
t
sk(lim)
Sk
ew
li
m
i
t
¶
ALS171A See Figure 9 5
ns
tPZH Output enable time to high level C
L
= 15 pF, 7 14 ns
tPZL Output enable time to low level
L,
See Figure 10 7 14 ns
tPHZ Output disable time from high level CL = 15 pF, 20 35 ns
tPLZ Output disable time from low level
L
See Figure 10 8 17 ns
†All typical values are at VCC = 5 V and TA = 25°C.
§Pulse skew is defined as the |tPLH–tPHL| of each channel.
¶Skew limit is the maximum difference in propagation delay times between any two channels of one device and between any two devices. This
parameter is applicable at one VCC and operating temperature within the recommended operating conditions.
SN75ALS171, SN75ALS171A
TRIPLE DIFFERENTIAL BUS TRANSCEIVERS
SLLS056D – AUGUST 1987 – REVISED SEPTEMBER 1995
8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
VOC
2
RL
VOD2
2
RL
Figure 1. Driver VOD and VOC
375 Ω
375 Ω
60 Ω
Vtest
VOD3
Figure 2. Driver VOD3
TEST CIRCUIT VOLTAGE WAVEFORMS
3 V
0 V
≈ – 2.5 V
50%
10%
tt(OD) tt(OD)
td(ODL)
1.5 V
50%
10%
90%90%
1.5 V
td(ODH)
Output
Input
CL= 50 pF
(see Note B)
Output
3 V
50 Ω
Generator
(see Note A)
RL = 54 Ω
≈ 2.5 V
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns,
ZO = 50 Ω.
B. CL includes probe and jig capacitance.
Figure 3. Driver Test Circuit and Voltage Waveforms
SN75ALS171, SN75ALS171A
TRIPLE DIFFERENTIAL BUS TRANSCEIVERS
SLLS056D – AUGUST 1987 – REVISED SEPTEMBER 1995
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
TEST CIRCUIT VOLTAGE WAVEFORMS
1.5 V
VOH
tPHZ
tPZH
0 V
3 V
1.5 V
2.3V
Output
Input
Output
S1
0 V or 3 V
CL = 50 pF
(see Note B) RL = 110 Ω
50 Ω
Generator
(see Note A)
Voff ≈ 0 V
0.5 V
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns,
ZO = 50 Ω.
B. CL includes probe and jig capacitance.
Figure 4. Driver Test Circuit and Voltage Waveforms
TEST CIRCUIT VOLTAGE WAVEFORMS
VOL
tPLZ
tPZL
5 V
0.5 V
2.3 V
0 V
3 V
1.5 V1.5 V
5 V
Output
Input
Output
S1
0 V or 3 V
CL = 50 pF
(see Note B)
50 Ω
Generator
(see Note A)
RL = 110 Ω
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns,
ZO = 50 Ω.
B. CL includes probe and jig capacitance.
Figure 5. Driver Test Circuit and Voltage Waveforms
SN75ALS171, SN75ALS171A
TRIPLE DIFFERENTIAL BUS TRANSCEIVERS
SLLS056D – AUGUST 1987 – REVISED SEPTEMBER 1995
10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
TEST CIRCUIT
VOLTAGE WAVEFORMSVOLTAGE WAVEFORMS
Output
RL2 = 75 Ω
RL1 = 165 Ω
5 V
0 V
S1
CL = 60 pF
(see Note B)
3 V
S2
0 V
5 V
RL3 = 165 Ω
50 Ω
Generator
(see Note A)
S2 to 0 V
S1 to 5 V
≈ 2.9 V
0 V
3 V
10%
0 V
90%90%
10%
0 V
tt(OD)
td(ODL)
tt(OD)
td(ODH)
1.5 V
Output
Input 1.5 V
≈ – 2.9 V
CL = 60 pF
(see Note B)
S2 to 5 V
S1 to 0 V
≈ 2.3 V
0 V
3 V
10%
0 V
90%90%
10%
0 V
tt(OD)
td(ODL)
tt(OD)
td(ODH)
1.5 V
Output
Input 1.5 V
≈ – 2.9 V
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns,
ZO = 50 Ω.
B. CL includes probe and jig capacitance.
Figure 6. Driver Test Circuit and Voltage Waveforms
With Double-Differential-SCSI Termination for the Load
SN75ALS171, SN75ALS171A
TRIPLE DIFFERENTIAL BUS TRANSCEIVERS
SLLS056D – AUGUST 1987 – REVISED SEPTEMBER 1995
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
S3 to 0 V
0 V0 V
S3 to 5 V
0 V
Input
Output
tPZL tPZH
S1 to 0 V
S2 to 5 V
S2 to 0 V
S1 to 3 V
0 V
3 V
0 V
tPZL
tPZH
1.5 V
Output
Input 1.5 V
≈ 2.3 V
≈ –1 V ≈ – 2.3 V
≈ 1 V
Output
RL2 = 75 Ω
RL1 = 165 Ω
5 V
0 V
S2
CL = 60 pF
(see Note B)
3 V
S3
0 V
5 V
RL3 = 165 Ω
50 Ω
Generator
(see Note A)
CL = 60 pF
(see Note B)
1.5 V1.5 V 0 V
3 V
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns,
ZO = 50 Ω.
B. CL includes probe and jig capacitance.
Figure 7. Driver Differential-Enable and Disable Times With a Double-SCSI Termination
SN75ALS171, SN75ALS171A
TRIPLE DIFFERENTIAL BUS TRANSCEIVERS
SLLS056D – AUGUST 1987 – REVISED SEPTEMBER 1995
12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
–I
OH
VOH
+I
OL
VOL
VID
Figure 8. Receiver VOH and VOL
TEST CIRCUIT VOLTAGE WAVEFORMS
VOL
VOH
3 V
0 V
tPHL
tPLH
Output
Input 1.5 V1.5 V
1.3 V
51 Ω
CL = 15 pF
(see Note B)
Output
0 V
1.5 V
Generator
(see Note A)
1.3 V
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns,
tf ≤ 6 ns, ZO = 50 Ω.
B. CL includes probe and jig capacitance.
Figure 9. Receiver Test Circuit and Voltage Waveforms
SN75ALS171, SN75ALS171A
TRIPLE DIFFERENTIAL BUS TRANSCEIVERS
SLLS056D – AUGUST 1987 – REVISED SEPTEMBER 1995
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
TEST CIRCUIT
VOLTAGE WAVEFORMS
2 kΩS2
5 V
S3
1N916 or Equivalent5 kΩ
CL = 15 pF
(see Note B)
50 Ω
S1
1.5 V
– 1.5 V
Generator
(see Note A)
tPZL
1.5 V
1.5 V
3 V
0 V
VOL
S1 to – 1.5 V
S2 Closed
S3 Open
tPZH
1.5 V
1.5 V S1 to 1.5 V
S2 Open
S3 Closed
Input
0 V
3 V
Output
0 V
VOH
VOL
0.5 V
1.5 V
0 V
3 V
S1 to – 1.5 V
S2 Closed
S3 Closed
tPLZ
VOH
tPHZ
S1 to 1.5 V
S2 Closed
S3 Closed
3 V
0 V
1.5 V
0.5 V
Input
Output ≈ 1.3 V
Input
Output
Input
Output
≈ 4.5 V
≈ 1.3 V
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns,
tf ≤ 6 ns, ZO = 50 Ω.
B. CL includes probe and jig capacitance.
Figure 10. Receiver Test Circuit and Voltage Waveforms
SN75ALS171, SN75ALS171A
TRIPLE DIFFERENTIAL BUS TRANSCEIVERS
SLLS056D – AUGUST 1987 – REVISED SEPTEMBER 1995
14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 11
2.5
1.5
1
00 – 20 – 40 – 60
– High-Level Output Voltage – V
3.5
4
DRIVER
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
5
– 80 – 100 – 120
VOH
IOH – High-Level Output Current – mA
4.5
3
2
0.5
VCC = 5 V
TA = 25°C
Figure 12
2.5
1.5
1
00204060
– Low-Level Output Voltage – V
3.5
4
DRIVER
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
5
80 100 120
VOL
IOL – Low-Level Output Current – mA
4.5
3
2
0.5
VCC = 5 V
TA = 25°C
2
1.5
0.5
00102030405060
– Differential Output Voltage – V
2.5
3.5
DRIVER
DIFFERENTIAL OUTPUT VOLTAGE
vs
OUTPUT CURRENT
4
70 80 90 100
1
3
VCC = 5 V
TA = 25°C
VOD
IO – Output Current – mA
Figure 13
SN75ALS171, SN75ALS171A
TRIPLE DIFFERENTIAL BUS TRANSCEIVERS
SLLS056D – AUGUST 1987 – REVISED SEPTEMBER 1995
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 14
2
1
00 –10 – 20 – 30
– High-Level Output Voltage – V
3
4
RECEIVER
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
5
– 40 – 50
VCC = 5.25 V
VCC = 5 V
VCC = 4.75 V
IOH – High-Level Output Current – mA
VOH
VID = 0.3 V
TA = 25°C
4.5
3.5
2.5
1.5
0.5
Figure 15
2
0
– 40 – 20 0 20 40 60 80
RECEIVER
HIGH-LEVEL OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
5
100 120
4
3
1
– High-Level Output Voltage – V
VOH
TA – Free-Air Temperature – °C
VCC = 5 V
VID = 300 mV
IOH = – 440 µA
4.5
3.5
2.5
1.5
0.5
Figure 16
0.3
0.2
0.1
00510
– Low-Level Output Voltage – V
0.4
0.5
RECEIVER
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
0.6
15 20 25 30
IOL – Low-Level Output Current – mA
VOL
VCC = 5 V
TA = 25°C
VID = – 300 mV
Figure 17
0.3
0.2
0.1
0
– 40 – 20 0 20 40 60
0.4
0.5
RECEIVER
LOW-LEVEL OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
0.6
80 100 120
– Low-Level Output Voltage – VV OL
TA – Free-Air Temperature – °C
VCC = 5 V
VID = – 300 mA
IOL = 8 mA
SN75ALS171, SN75ALS171A
TRIPLE DIFFERENTIAL BUS TRANSCEIVERS
SLLS056D – AUGUST 1987 – REVISED SEPTEMBER 1995
16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 18
2
1
00 0.5 1 1.5
– Output Voltage – V
3
4
RECEIVER
OUTPUT VOLTAGE
vs
ENABLE VOLTAGE
5
2 2.5 3
VCC = 5 V
VCC = 4.75 V
VID = 0.3 V
Load = 8 kΩ to GND
TA = 25°C
VI – Enable Voltage – V
VO
VCC = 5.25 V
4.5
3.5
2.5
1.5
0.5
Figure 19
3
2
1
00 0.5 1
4
5
RECEIVER
OUTPUT VOLTAGE
vs
ENABLE VOLTAGE
6
1.5 2 2.5 3
VID = 0.3 V
Load = 1 kΩ to VCC
TA = 25°C
VCC = 5.25 V
VCC = 5 V
VCC = 4.75 V
VI – Enable Voltage – V
– Output Voltage – V
VO
SN75ALS171, SN75ALS171A
TRIPLE DIFFERENTIAL BUS TRANSCEIVERS
SLLS056D – AUGUST 1987 – REVISED SEPTEMBER 1995
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
Transceivers
Up to 32
1/3 SN75ALS170
See Note A
1/3 SN75ALS170
•••
NOTE A: The line should be terminated at both ends in its characteristic impedance. Stub lengths off the main line should be kept as short
as possible.
Figure 20. Typical Application Circuit
330 Ω
150 Ω
330 Ω
4 V to 5.25 V
Transceivers
Up to 16
4 V to 5.25 V
330 Ω
150 Ω
330 Ω
•••
Figure 21. Typical Differential SCSI Application CIrcuit
SN75ALS171, SN75ALS171A
TRIPLE DIFFERENTIAL BUS TRANSCEIVERS
SLLS056D – AUGUST 1987 – REVISED SEPTEMBER 1995
18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
To Reset Logic 9
11
6
8
1
VCC
3
EN4
18 5EN3
10 5EN2
75EN1
2
17 G5
To SCSI Bus
Controller
20
19
1
1
14
15
BSY
–BSY
–SEL
SEL
1
13
12 –RST
RST
SN75ALS171
ARB
SELIN
BSYIN
SBEN
SELOUT
SN75ALS170
REQ
–REQ
8
9
1
EN
EN
7
6
I/O
–I/O
–C/D
C/D
11
10
EN
EN 1
4
5
2
1
1
EN
EN 13
14
BSYOUT
REQ
I/O
MSG
C/D
TARGET
ATN
ACK
INIT
SB7
SB6
SB5
SB4
SB3
SB2
SB1
SB0
SBP
14
13
EN
EN 1
1
2
5
4
1
EN
EN 10
11
ACK
–ACK
–ATN
ATN
6
7EN
EN 1
9
8–MSG
MSG
SN75ALS170
SN74LS04
1
12
3 4
5 6
98
11 10
1213
SN75ALS170
DB(P)
–DB(P)
8
9
1
EN
EN
7
6
DB(0)
–DB(0)
–DB(1)
DB(1)
11
10
EN
EN 1
4
5
2
1
1
EN
EN 13
14
14
13
EN
EN 1
1
2
5
4
1
EN
EN 10
11
DB(4)
–DB(4)
–DB(3)
DB(3)
6
7EN
EN 1
9
8–DB(2)
DB(2)
SN75ALS170
SN75ALS170
DB(5)
–DB(5)
8
9
1
EN
EN
7
6
DB(6)
–DB(6)
–DB(7)
DB(7)
11
10
EN
EN 1
4
5
2
1
1
EN
EN 13
14
ID2
ID1
ID0
SN74LS00
&
12
13
10
9
5
4
2
1
11
8
6
3
3
6
8
11
1
2
4
5
9
10
13
12
SN74LS00
&
BIN/OCT 15
14
13
12
11
10
9
1
2
3
7
&
6
4
5
SN74LS138
CC
V
Figure 22. Typical Differential SCSI Bus Interface Implementation
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
SN75ALS171ADW ACTIVE SOIC DW 20 25 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN75ALS171ADWE4 ACTIVE SOIC DW 20 25 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN75ALS171ADWG4 ACTIVE SOIC DW 20 25 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN75ALS171ADWR ACTIVE SOIC DW 20 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN75ALS171ADWRE4 ACTIVE SOIC DW 20 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN75ALS171ADWRG4 ACTIVE SOIC DW 20 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN75ALS171DW ACTIVE SOIC DW 20 25 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN75ALS171DWE4 ACTIVE SOIC DW 20 25 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN75ALS171DWG4 ACTIVE SOIC DW 20 25 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN75ALS171DWR ACTIVE SOIC DW 20 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN75ALS171DWRE4 ACTIVE SOIC DW 20 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN75ALS171DWRG4 ACTIVE SOIC DW 20 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN75ALS171J OBSOLETE CDIP J 20 TBD Call TI Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
PACKAGE OPTION ADDENDUM
www.ti.com 10-May-2007
Addendum-Page 1
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 10-May-2007
Addendum-Page 2
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN75ALS171ADWR SOIC DW 20 2000 330.0 24.4 10.8 13.1 2.65 12.0 24.0 Q1
SN75ALS171DWR SOIC DW 20 2000 330.0 24.4 10.8 13.1 2.65 12.0 24.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN75ALS171ADWR SOIC DW 20 2000 367.0 367.0 45.0
SN75ALS171DWR SOIC DW 20 2000 367.0 367.0 45.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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