T2080
QorIQ T2080 Data Sheet
Features
• 4 e6500 cores built on Power Architecture®
technology sharing a 2 MB L2 cache
• 512 KB CoreNet platform cache (CPC)
• Hierarchical interconnect fabric
– CoreNet fabric supporting coherent and non-
coherent transactions with prioritization and
bandwidth allocation amongst CoreNet end-points
– Queue Manager (QMan) fabric supporting packet-
level queue management and quality of service
scheduling
• One 32-/64-bit DDR3 SDRAM memory controller
– DDR3 and DDR3L with ECC and interleaving
support
– Memory pre-fetch engine
• Data Path Acceleration Architecture (DPAA)
incorporating acceleration for the following functions:
– Packet parsing, classification, and distribution
(Frame Manager 1.1)
– Queue management for scheduling, packet
sequencing, and congestion management (Queue
Manager 1.1)
– Hardware buffer management for buffer allocation
and de-allocation (Buffer Manager 1.1)
– Cryptography Acceleration (SEC 5.2)
– RegEx Pattern Matching Acceleration (PME 2.1)
– Decompression/Compression Acceleration (DCE
1.0)
– DPAA chip-to-chip interconnect via RapidIO
Message Manager (RMan 1.0)
• 16 SerDes lanes at up to 10 GBaud
• 8 Ethernet interfaces, supporting combinations of:
– Up to four 10 Gbps Ethernet MACs
– Up to eight 1 Gbps Ethernet MACs
– Up to four 2.5Gbps Ethernet MACs
– IEEE Std 1588™ support
• High-speed peripheral interfaces
– Four PCI Express controllers (two support PCIe 2.0
and two support PCIe 3.0)
– Two Serial RapidIO 2.0 controllers running at up to
5 GBaud with Type 11 messaging and Type 9 data
streaming support
• Additional peripheral interfaces
– Two Serial ATA (SATA 2.0) controllers
– Two high-speed USB 2.0 controllers with integrated
PHY
– Enhanced secure digital host controller (SD/MMC/
eMMC)
– Enhanced Serial peripheral interface (eSPI)
– Four I2C controllers
– Four 2-pin UARTs or two 4-pin UARTs
– Integrated flash controller supporting NAND and
NOR flash
• Three 8-channel DMA engines
• 896 FC-PBGA package, 25 mm x 25 mm, 0.8mm pitch
NXP Semiconductors Document Number T2080
Data Sheet: Technical Data Rev. 3, 03/2018
NXP reserves the right to change the production detail specifications as may be
required to permit improvements in the design of its products.
Table of Contents
1 Overview.............................................................................................. 3
2 Pin assignments....................................................................................3
2.1 896 ball layout diagrams........................................................... 4
2.2 Pinout list...................................................................................10
3 Electrical characteristics.......................................................................43
3.1 Overall DC electrical characteristics.........................................43
3.2 Power sequencing......................................................................49
3.3 Power-down requirements.........................................................51
3.4 Power characteristics.................................................................51
3.5 Power-on ramp rate................................................................... 56
3.6 Input clocks............................................................................... 57
3.7 RESET initialization..................................................................61
3.8 DDR3 and DDR3L SDRAM controller.................................... 62
3.9 eSPI interface.............................................................................68
3.10 DUART interface...................................................................... 71
3.11 Ethernet interface, Ethernet management interface 1 and 2,
IEEE Std 1588...........................................................................72
3.12 USB interface............................................................................ 80
3.13 Integrated flash controller..........................................................82
3.14 Enhanced secure digital host controller (eSDHC).....................85
3.15 Multicore programmable interrupt controller (MPIC).............. 89
3.16 JTAG controller.........................................................................89
3.17 I2C interface.............................................................................. 92
3.18 GPIO interface...........................................................................95
3.19 High-speed serial interfaces (HSSI).......................................... 97
4 Hardware design considerations...........................................................149
4.1 System clocking........................................................................ 149
4.2 Power supply design..................................................................154
4.3 Decoupling recommendations...................................................163
4.4 SerDes block power supply decoupling recommendations.......163
4.5 Connection recommendations................................................... 164
4.6 Thermal......................................................................................175
4.7 Recommended thermal model...................................................176
4.8 Thermal management information............................................ 176
5 Package information.............................................................................178
5.1 Package parameters for the FC-PBGA......................................178
5.2 Mechanical dimensions of the FC-PBGA.................................178
6 Security fuse processor.........................................................................180
7 Ordering information............................................................................180
7.1 Part numbering nomenclature....................................................180
7.2 Orderable part numbers addressed by this document................181
8 Revision history....................................................................................183
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
2 NXP Semiconductors
1 Overview
The T2080 QorIQ integrated multicore communications processor combines 4 dual-
threaded cores built on Power Architecture® technology with high-performance data path
acceleration and network and peripheral bus interfaces required for networking, telecom/
datacom, wireless infrastructure, and military/aerospace applications.
This chip can be used for combined control, data path, and application layer processing in
routers, switches, gateways, and general-purpose embedded computing systems. Its high
level of integration offers significant performance benefits compared to multiple discrete
devices, while also simplifying board design.
This figure shows the block diagram of the chip.
Power Architecture
e6500
Power Architecture
e6500
Power Architecture
e6500
Power Architecture
e6500
32 KB
D-Cache
32 KB
I-Cache
32 KB
D-Cache
32 KB
I-Cache
32 KB
D-Cache
32 KB
I-Cache
32 KB
D-Cache
32 KB
I-Cache
2 MB Banked L2
(peripheral access management unit)
CoreNet TM
Coherency Fabric
MPIC
PreBoot Loader
Security Monitor
Internal BootROM
Power mgmt
SDXC/eMMC
eSPI
2x DUART
IFC
Clocks/Reset
GPIO
CCSR
512 KB
Plat Cache
64-bit DDR3/3L
with ECC
PAMU PAMU
PAMU
SEC
PME
QMan
BMan
RMan
DCE
FMan
Parse, classify,
distribute
Buffer
4x 1/2.5/10G
3x DMA
PCIe
SATA 2.0
PCle
PCle
PCle
SRIO
SRIO
SATA 2.0
Real-time
debug
Watch point
cross-
trigger
Perf
Monitor
Aurora
Trace
8 lanes up to 10 GHz SerDes
2x USB2.0 w/PHY
4x I2C
8 lanes up to 8 GHz SerDes
1GE 1GE
1GE 1GE
Pre-Fetch
DCB
HiGig
Figure 1. Block diagram
2Pin assignments
Overview
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
NXP Semiconductors 3
2.1 896 ball layout diagrams
This figure shows the complete view of the T2080 ball map diagram. Figure 3, Figure 4,
Figure 5, and Figure 6 show quadrant views.
Pin assignments
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
4 NXP Semiconductors
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
AG
AH
AJ
AK
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
AG
AH
AJ
AK
DDR Interface 1 IFC DUART I2C eSPI
eSDXC MPIC LP Trust Trust System Control
ASLEEP SYSCLK DDR Clocking RTC Debug
DFT JTAG Analog Signals Serdes 1 Serdes 2
USB PHY 1 and 2 IEEE1588 Ethernet MI 1 Ethernet MI 2 Ethernet Cont. 1
Ethernet Cont. 2 DMA Power Ground No Connects
SEE DETAIL A SEE DETAIL B
SEE DETAIL C SEE DETAIL D
Figure 2. Complete BGA Map for the T2080
Pin assignments
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
NXP Semiconductors 5
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
IFC_
AD00
IFC_
AD01
IFC_
AD02
IFC_
AD03
IFC_
AD04
IFC_
AD05
IFC_
AD06
IFC_
AD07
IFC_
AD08
IFC_
AD09
IFC_
AD10
IFC_
AD11
IFC_
AD12
IFC_
AD13
IFC_
AD14
IFC_
AD15
IFC_
A16
IFC_
A17
IFC_
A18
IFC_
A19
IFC_
A21
IFC_
A22
UART1_
SOUT
UART2_
SOUT
UART1_
SIN
UART2_
SIN
UART1_
RTS_B
UART2_
RTS_B
UART1_
CTS_B
UART2_
CTS_B
IIC1_
SCL
IIC1_
SDA
IIC2_
SCL
IIC2_
SDA
SPI_
MOSI SPI_
MISO
SPI_
CLK
SPI_
CS0_B
SPI_
CS1_B
SPI_
CS2_B
SPI_
CS3_B
SDHC_
CMD
SDHC_
DAT0 SDHC_
DAT1
SDHC_
DAT2
SDHC_
DAT3
SDHC_
CLK
IRQ00
IRQ01
IRQ02
IRQ03
IRQ04
IRQ05
IRQ06
IRQ07 IRQ08IRQ09
IRQ10
IRQ11
IRQ_
OUT_B
LP_
TMP_
DETECT_B
PORESET_
BHRESET_
B
RESET_
REQ_B
ASLEEPSYSCLK EVT0_B
EVT1_B
EVT2_B
EVT3_B
EVT4_B
CLK_
OUT
SCAN_
MODE_B
TEST_
SEL_B
USB1_
UDP
USB1_
UDM
USB1_
VBUS
CLMP
USB1_
UID
USB1_
DRV
VBUS
USB1_
PWR
FAULT
USB2_
UDP
USB2_
UDM
USB2_
VBUS
CLMP
USB2_
UID
USB2_
DRV
VBUS
USB2_
PWR
FAULT
USB_
IBIAS_
REXT
EMI1_
MDIO
EMI2_
MDC
EMI2_
MDIO
EC1_
TXD3
EC1_
TXD2
EC1_
TXD1
EC1_
TX_
CTL
EC1_
GTX_
CLK
EC1_
GTX_
CLK125
EC1_
RXD3
EC1_
RXD2
EC1_
RXD1
EC1_
RXD0
EC1_
RX_
CTL
EC1_
RX_
CLK
EC2_
TX_
CTL
EC2_
RXD3
EC2_
RXD0
USBCLK
IIC3_
SCL
IIC3_
SDA
IIC4_
SCL
IIC4_
SDA
DMA1_
DREQ0_
B
DMA1_
DACK0_
B
DMA1_
DDONE0_
B
DMA2_
DREQ0_
B
DMA2_
DACK0_
B
DMA2_
DDONE0_
B
SDHC_
CD_B
SDHC_
WP TH_
TPA
DDR Interface 1 IFC DUART I2C eSPI
eSDXC MPIC LP Trust Trust System Control
ASLEEP SYSCLK DDR Clocking RTC Debug
DFT JTAG Analog Signals Serdes 1 Serdes 2
USB PHY 1 and 2 IEEE1588 Ethernet MI 1 Ethernet MI 2 Ethernet Cont. 1
Ethernet Cont. 2 DMA
GND074GND075GND076GND077
GND083GND084GND085GND086GND087GND088
GND094GND095GND096GND097GND098
GND104GND105GND106GND107GND108GND109
GND115GND116GND117GND118GND119
GND122GND123GND124GND125
GND131GND132GND133GND134
GND138GND139GND140GND141
GND146GND147GND148
GND152
GND158GND159GND160
GND163GND164
GND168
GND173GND174GND175GND176
GND179GND180
USB_
AGND01
USB_
AGND02
USB_
AGND03
USB_
AGND04
USB_
AGND05
USB_
AGND06
USB_
AGND07
USB_
AGND08
USB_
AGND09
USB_
AGND10
OVDD01
OVDD07OVDD08OVDD09OVDD10OVDD11
DVDD1
DVDD2
CVDD1CVDD2
PROG_
MTR PROG_
SFP
TH_
VDD
VDD31VDD32VDD33VDD34
VDD38VDD39VDD40
VDD44VDD45VDD46VDD47
VDD51VDD52VDD53
VDD57VDD58VDD59VDD60
VDD_
LP
AVDD_
CGA1
AVDD_
CGA2
AVDD_
PLAT
USB_
HVDD1
USB_
HVDD2
USB_
OVDD1
USB_
OVDD2
USB_
SVDD1
USB_
SVDD2
Power Ground No Connects
Figure 3. Detail A
Pin assignments
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
6 NXP Semiconductors
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
D1_
MDQ00
D1_
MDQ01
D1_
MDQ02
D1_
MDQ03 D1_
MDQ04
D1_
MDQ05
D1_
MDQ06
D1_
MDQ07
D1_
MDQ08
D1_
MDQ09
D1_
MDQ10 D1_
MDQ11
D1_
MDQ12 D1_
MDQ13
D1_
MDQ14
D1_
MDQ15
D1_
MDQ16
D1_
MDQ17 D1_
MDQ18
D1_
MDQ19
D1_
MDQ20 D1_
MDQ21
D1_
MDQ22
D1_
MDQ23
D1_
MDQ24
D1_
MDQ25
D1_
MDQ26 D1_
MDQ27
D1_
MDQ28
D1_
MDQ29
D1_
MDQ30 D1_
MDQ31
D1_
MDQ36
D1_
MECC0
D1_
MECC1 D1_
MECC2 D1_
MECC3
D1_
MECC4
D1_
MECC5
D1_
MECC6
D1_
MECC7
D1_
MAPAR_
ERR_B
D1_
MDM0
D1_
MDM1
D1_
MDM2
D1_
MDM3
D1_
MDM8
D1_
MDQS0
D1_
MDQS1
D1_
MDQS2
D1_
MDQS3
D1_
MDQS8
D1_
MDQS0_B
D1_
MDQS1_B
D1_
MDQS2_B
D1_
MDQS3_B
D1_
MDQS8_B
D1_
MBA2
D1_
MA02
D1_
MA03
D1_
MA04
D1_
MA05
D1_
MA06
D1_
MA07
D1_
MA08
D1_
MA09
D1_
MA11
D1_
MA12
D1_
MA14
D1_
MA15
D1_
MCKE0
D1_
MCKE1
D1_
MCKE2
D1_
MCKE3
D1_
MCK0
D1_
MCK1
D1_
MCK0_B
D1_
MCK1_B
D1_
MDIC0
D1_
MDIC1
IFC_
A20
IFC_
A23
IFC_
A24
IFC_
A25
IFC_
A26
IFC_
A27
IFC_
A28
IFC_
A29
IFC_
A30
IFC_
A31
IFC_
PAR0
IFC_
PAR1
IFC_
CS0_B
IFC_
CS1_B
IFC_
CS2_B
IFC_
CS3_B
IFC_
WE0_B
IFC_BCTL
IFC_
TE
IFC_
NDDQS
IFC_
AVD
IFC_
CLE
IFC_
OE_B
IFC_
WP0_B
IFC_
RB0_B
IFC_
RB1_B
IFC_
PERR_B
IFC_
CLK0
IFC_
CLK1
IFC_
NDDDR_
CLK
IFC_
CS4_B
IFC_
CS5_B
IFC_
CS6_B
IFC_
CS7_B
TMP_
DETECT_
B
DDRCLK
RTC
CKSTP_
OUT_B
TCK
TDI
TDO
TMS
TRST_B
D1_
TPA
D1_
MVREF
TD1_
ANODE
TD1_
CATHODE
FA_
ANALOG_
PIN
FA_
ANALOG_
G_V
DDR Interface 1 IFC DUART I2C eSPI
eSDXC MPIC LP Trust Trust System Control
ASLEEP SYSCLK DDR Clocking RTC Debug
DFT JTAG Analog Signals Serdes 1 Serdes 2
USB PHY 1 and 2 IEEE1588 Ethernet MI 1 Ethernet MI 2 Ethernet Cont. 1
Ethernet Cont. 2 DMA
GND069GND070GND071GND072GND073
GND078GND079GND080GND081GND082
GND089GND090GND091GND092GND093
GND099GND100GND101GND102GND103
GND110GND111GND112GND113GND114
GND120GND121
GND126GND127GND128GND129GND130
GND135GND136GND137
GND142GND143GND144GND145
GND149GND150GND151
GND153GND154GND155GND156GND157
GND161GND162
GND165GND166GND167
GND169GND170GND171GND172
GND177GND178
SENSE
GND
OVDD02OVDD03OVDD04OVDD05OVDD06
G1VDD13
G1VDD14G1VDD15
G1VDD16
G1VDD17G1VDD18
G1VDD19
G1VDD20
G1VDD21
G1VDD22
G1VDD23
G1VDD24
G1VDD25
FA_
VL
VDD28VDD29VDD30
VDD35VDD36VDD37
VDD41VDD42VDD43
VDD48VDD49VDD50
VDD54VDD55VDD56
AVDD_
D1
SENSE
VDD
Power Ground No Connects
Figure 4. Detail B
Pin assignments
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
NXP Semiconductors 7
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
AG
AH
AJ
AK
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
AG
AH
AJ
AK
SD1_
TX0_
P
SD1_
TX0_
N
SD1_
RX0_
P
SD1_
RX1_
P
SD1_
RX0_
N
SD1_
RX1_
N
SD1_
REF_
CLK1_P
SD1_
REF_
CLK1_N
SD1_
IMP_
CAL_RX
SD1_
PLL1_
TPA
SD1_
PLL1_
TPD
SD2_
TX0_
P
SD2_
TX1_
P
SD2_
TX2_
P
SD2_
TX3_
P
SD2_
TX4_
P
SD2_
TX5_
P
SD2_
TX6_
P
SD2_
TX7_
P
SD2_
TX0_
N
SD2_
TX1_
N
SD2_
TX2_
N
SD2_
TX3_
N
SD2_
TX4_
N
SD2_
TX5_
N
SD2_
TX6_
N
SD2_
TX7_
N
SD2_
RX0_
P
SD2_
RX1_
P
SD2_
RX2_
P
SD2_
RX3_
P
SD2_
RX4_
P
SD2_
RX5_
P
SD2_
RX6_
P
SD2_
RX7_
P
SD2_
RX0_
N
SD2_
RX1_
N
SD2_
RX2_
N
SD2_
RX3_
N
SD2_
RX4_
N
SD2_
RX5_
N
SD2_
RX6_
N
SD2_
RX7_
N
SD2_
REF_
CLK1_P
SD2_
REF_
CLK1_N
SD2_
REF_
CLK2_P
SD2_
REF_
CLK2_N
SD2_
IMP_
CAL_TX
SD2_
IMP_
CAL_RX
SD2_
PLL1_
TPA
SD2_
PLL2_
TPA
SD2_
PLL1_
TPD
SD2_
PLL2_
TPD
TSEC_
CLK_
IN
TSEC_
TRIG_IN
1
TSEC_
TRIG_IN
2
TSEC_
ALARM_OUT
1
TSEC_
ALARM_OUT
2
TSEC_
CLK_
OUT
TSEC_
PULSE_OUT
1
TSEC_
PULSE_OUT
2
EMI1_
MDC EC1_
TXD0
EC2_
TXD3
EC2_
TXD2 EC2_
TXD1
EC2_
TXD0
EC2_
GTX_
CLK
EC2_
GTX_
CLK125
EC2_
RXD2
EC2_
RXD1
EC2_
RX_
CTL
EC2_
RX_
CLK
NC_
AB15
NC_
AC15
NC_
AD12 NC_
AD13 NC_
AD14
NC_
AD9
NC_
AE12 NC_
AE13
NC_
AF13
DDR Interface 1 IFC DUART I2C eSPI
eSDXC MPIC LP Trust Trust System Control
ASLEEP SYSCLK DDR Clocking RTC Debug
DFT JTAG Analog Signals Serdes 1 Serdes 2
USB PHY 1 and 2 IEEE1588 Ethernet MI 1 Ethernet MI 2 Ethernet Cont. 1
Ethernet Cont. 2 DMA
GND018
GND019GND020GND021GND022GND023GND024
GND031GND032GND033GND034GND035GND036GND037
GND043GND044GND045GND046GND047
GND053GND054GND055GND056GND057
GND063GND064GND065GND066GND067GND068
X1GND05
X1GND11X1GND12
S1GND08S1GND09
S1GND17S1GND18
S1GND23S1GND24
X2GND01X2GND02
X2GND03X2GND04X2GND05X2GND06X2GND07X2GND08
X2GND09X2GND10X2GND11X2GND12X2GND13
X2GND14X2GND15X2GND16X2GND17
X2GND18X2GND19
X2GND20X2GND21X2GND22X2GND23X2GND24
X2GND25X2GND26
S2GND01S2GND02S2GND03S2GND04
S2GND05S2GND06S2GND07
S2GND08S2GND09S2GND10S2GND11S2GND12S2GND13
S2GND14S2GND15S2GND16S2GND17
S2GND18S2GND19S2GND20S2GND21S2GND22
S2GND23S2GND24S2GND25S2GND26S2GND27S2GND28S2GND29S2GND30S2GND31S2GND32
S2GND33S2GND34S2GND35S2GND36S2GND37S2GND38
S2GND40S2GND41S2GND42S2GND43S2GND44
AGND_
SD2_PLL
1
AGND_
SD2_PLL
2
LVDD1
LVDD2
LVDD3
S2VDD1
S2VDD2S2VDD3S2VDD4S2VDD5S2VDD6
X2VDD1X2VDD2X2VDD3
X2VDD4
X2VDD5X2VDD6
VDD01
VDD05VDD06VDD07VDD08
VDD12VDD13VDD14
VDD18VDD19VDD20VDD21
VDD25VDD26VDD27
AVDD_
SD2_
PLL1
AVDD_
SD2_
PLL2
Power Ground No Connects
Figure 5. Detail C
Pin assignments
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
8 NXP Semiconductors
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
AG
AH
AJ
AK
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
AG
AH
AJ
AK
D1_
MDQ32
D1_
MDQ33
D1_
MDQ34 D1_
MDQ35
D1_
MDQ37
D1_
MDQ38
D1_
MDQ39
D1_
MDQ40
D1_
MDQ41
D1_
MDQ42
D1_
MDQ43
D1_
MDQ44
D1_
MDQ45
D1_
MDQ46
D1_
MDQ47
D1_
MDQ48
D1_
MDQ49
D1_
MDQ50
D1_
MDQ51
D1_
MDQ52
D1_
MDQ53
D1_
MDQ54 D1_
MDQ55
D1_
MDQ56
D1_
MDQ57
D1_
MDQ58
D1_
MDQ59
D1_
MDQ60
D1_
MDQ61
D1_
MDQ62
D1_
MDQ63
D1_
MAPAR_
OUT
D1_
MDM4
D1_
MDM5
D1_
MDM6
D1_
MDM7
D1_
MDQS4
D1_
MDQS5
D1_
MDQS6
D1_
MDQS7
D1_
MDQS4_B
D1_
MDQS5_B
D1_
MDQS6_B
D1_
MDQS7_B
D1_
MBA0
D1_
MBA1
D1_
MA00
D1_
MA01
D1_
MA10
D1_
MA13
D1_
MWE_B
D1_
MRAS_B
D1_
MCAS_B
D1_
MCS0_B
D1_
MCS1_B
D1_
MCS2_B
D1_
MCS3_B
D1_
MCK2
D1_
MCK3
D1_
MCK2_B
D1_
MCK3_B
D1_
MODT0
D1_
MODT1
D1_
MODT2
D1_
MODT3
SD1_
TX1_
P
SD1_
TX2_
P
SD1_
TX3_
P
SD1_
TX4_
P
SD1_
TX5_
P
SD1_
TX6_
P
SD1_
TX7_
P
SD1_
TX1_
N
SD1_
TX2_
N
SD1_
TX3_
N
SD1_
TX4_
N
SD1_
TX5_
N
SD1_
TX6_
N
SD1_
TX7_
N
SD1_
RX2_
P
SD1_
RX3_
P
SD1_
RX4_
P
SD1_
RX5_
P
SD1_
RX6_
P
SD1_
RX7_
P
SD1_
RX2_
N
SD1_
RX3_
N
SD1_
RX4_
N
SD1_
RX5_
N
SD1_
RX6_
N
SD1_
RX7_
N
SD1_
REF_
CLK2_P
SD1_
REF_
CLK2_N
SD1_
IMP_
CAL_TX
SD1_
PLL2_
TPA
SD1_
PLL2_
TPD
DDR Interface 1 IFC DUART I2C eSPI
eSDXC MPIC LP Trust Trust System Control
ASLEEP SYSCLK DDR Clocking RTC Debug
DFT JTAG Analog Signals Serdes 1 Serdes 2
USB PHY 1 and 2 IEEE1588 Ethernet MI 1 Ethernet MI 2 Ethernet Cont. 1
Ethernet Cont. 2 DMA
GND001
GND002
GND003GND004
GND005
GND006GND007
GND008GND009
GND010GND011
GND012
GND013GND014GND015
GND016GND017
GND025GND026GND027GND028GND029GND030
GND038GND039GND040GND041GND042
GND048GND049GND050GND051GND052
GND058GND059GND060GND061GND062
X1GND01
X1GND02X1GND03X1GND04
X1GND06X1GND07X1GND08X1GND09X1GND10
X1GND13X1GND14X1GND15X1GND16X1GND17
X1GND18X1GND19
X1GND20X1GND21
X1GND22
S1GND01S1GND02S1GND03S1GND04S1GND05S1GND06S1GND07
S1GND10S1GND11S1GND12S1GND13S1GND14S1GND15S1GND16
S1GND19S1GND20S1GND21S1GND22
S1GND25S1GND26S1GND27S1GND28S1GND29
S1GND30
S1GND31S1GND32S1GND33S1GND34S1GND35S2GND39
AGND_
SD1_PLL
1
AGND_
SD1_PLL
2
G1VDD01
G1VDD02
G1VDD03
G1VDD04
G1VDD05
G1VDD06
G1VDD07G1VDD08
G1VDD09
G1VDD10G1VDD11G1VDD12
S1VDD1S1VDD2S1VDD3S1VDD4S1VDD5S1VDD6
X1VDD1X1VDD2X1VDD3X1VDD4X1VDD5
X1VDD6
X1VDD7
VDD02VDD03VDD04
VDD09VDD10VDD11
VDD15VDD16VDD17
VDD22VDD23VDD24
AVDD_
SD1_
PLL1
AVDD_
SD1_
PLL2
Power Ground No Connects
Figure 6. Detail D
Pin assignments
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
NXP Semiconductors 9
2.2 Pinout list
This table provides the pinout listing for the T2080 by bus. Primary functions are bolded
in the table.
Table 1. Pinout list by bus
Signal Signal description Package
pin
number
Pin
type
Power supply Notes
DDR SDRAM Memory Interface 1
D1_MA00 Address Y30 O G1VDD ---
D1_MA01 Address W29 O G1VDD ---
D1_MA02 Address M30 O G1VDD ---
D1_MA03 Address L30 O G1VDD ---
D1_MA04 Address L29 O G1VDD ---
D1_MA05 Address J30 O G1VDD ---
D1_MA06 Address J29 O G1VDD ---
D1_MA07 Address G29 O G1VDD ---
D1_MA08 Address H30 O G1VDD ---
D1_MA09 Address F30 O G1VDD ---
D1_MA10 Address AB30 O G1VDD ---
D1_MA11 Address G30 O G1VDD ---
D1_MA12 Address E29 O G1VDD ---
D1_MA13 Address AG29 O G1VDD ---
D1_MA14 Address D30 O G1VDD ---
D1_MA15 Address C29 O G1VDD ---
D1_MAPAR_ERR_B Address Parity Error E30 I G1VDD 1, 6
D1_MAPAR_OUT Address Parity Out AA30 O G1VDD ---
D1_MBA0 Bank Select AC30 O G1VDD ---
D1_MBA1 Bank Select AA29 O G1VDD ---
D1_MBA2 Bank Select D28 O G1VDD ---
D1_MCAS_B Column Address Strobe AE29 O G1VDD ---
D1_MCK0 Clock P30 O G1VDD ---
D1_MCK0_B Clock Complement N30 O G1VDD ---
D1_MCK1 Clock R30 O G1VDD ---
D1_MCK1_B Clock Complement R29 O G1VDD ---
D1_MCK2 Clock U29 O G1VDD ---
D1_MCK2_B Clock Complement U30 O G1VDD ---
D1_MCK3 Clock W30 O G1VDD ---
D1_MCK3_B Clock Complement V30 O G1VDD ---
D1_MCKE0 Clock Enable B29 O G1VDD 2
Table continues on the next page...
Pin assignments
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
10 NXP Semiconductors
Table 1. Pinout list by bus (continued)
Signal Signal description Package
pin
number
Pin
type
Power supply Notes
D1_MCKE1 Clock Enable B28 O G1VDD 2
D1_MCKE2 Clock Enable C30 O G1VDD 2
D1_MCKE3 Clock Enable A28 O G1VDD 2
D1_MCS0_B Chip Select AD30 O G1VDD ---
D1_MCS1_B Chip Select AH30 O G1VDD ---
D1_MCS2_B Chip Select AK28 O G1VDD ---
D1_MCS3_B Chip Select AJ28 O G1VDD ---
D1_MDIC0 Driver Impedence Calibration K30 IO G1VDD 3
D1_MDIC1 Driver Impedence Calibration N29 IO G1VDD 3
D1_MDM0 Data Mask A25 O G1VDD ---
D1_MDM1 Data Mask E27 O G1VDD ---
D1_MDM2 Data Mask G26 O G1VDD ---
D1_MDM3 Data Mask K25 O G1VDD ---
D1_MDM4 Data Mask T28 O G1VDD ---
D1_MDM5 Data Mask W25 O G1VDD ---
D1_MDM6 Data Mask AA26 O G1VDD ---
D1_MDM7 Data Mask AJ27 O G1VDD ---
D1_MDM8 Data Mask P25 O G1VDD ---
D1_MDQ00 Data B24 IO G1VDD ---
D1_MDQ01 Data A24 IO G1VDD ---
D1_MDQ02 Data C25 IO G1VDD ---
D1_MDQ03 Data D24 IO G1VDD ---
D1_MDQ04 Data D25 IO G1VDD ---
D1_MDQ05 Data C26 IO G1VDD ---
D1_MDQ06 Data B27 IO G1VDD ---
D1_MDQ07 Data C27 IO G1VDD ---
D1_MDQ08 Data H23 IO G1VDD ---
D1_MDQ09 Data G23 IO G1VDD ---
D1_MDQ10 Data F24 IO G1VDD ---
D1_MDQ11 Data F25 IO G1VDD ---
D1_MDQ12 Data E25 IO G1VDD ---
D1_MDQ13 Data E26 IO G1VDD ---
D1_MDQ14 Data D27 IO G1VDD ---
D1_MDQ15 Data G25 IO G1VDD ---
D1_MDQ16 Data J23 IO G1VDD ---
D1_MDQ17 Data H24 IO G1VDD ---
D1_MDQ18 Data H25 IO G1VDD ---
D1_MDQ19 Data J26 IO G1VDD ---
Table continues on the next page...
Pin assignments
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
NXP Semiconductors 11
Table 1. Pinout list by bus (continued)
Signal Signal description Package
pin
number
Pin
type
Power supply Notes
D1_MDQ20 Data J25 IO G1VDD ---
D1_MDQ21 Data J27 IO G1VDD ---
D1_MDQ22 Data H28 IO G1VDD ---
D1_MDQ23 Data K28 IO G1VDD ---
D1_MDQ24 Data L23 IO G1VDD ---
D1_MDQ25 Data M25 IO G1VDD ---
D1_MDQ26 Data K24 IO G1VDD ---
D1_MDQ27 Data K27 IO G1VDD ---
D1_MDQ28 Data M24 IO G1VDD ---
D1_MDQ29 Data L27 IO G1VDD ---
D1_MDQ30 Data M27 IO G1VDD ---
D1_MDQ31 Data M28 IO G1VDD ---
D1_MDQ32 Data T27 IO G1VDD ---
D1_MDQ33 Data V27 IO G1VDD ---
D1_MDQ34 Data U25 IO G1VDD ---
D1_MDQ35 Data U26 IO G1VDD ---
D1_MDQ36 Data R25 IO G1VDD ---
D1_MDQ37 Data T25 IO G1VDD ---
D1_MDQ38 Data T24 IO G1VDD ---
D1_MDQ39 Data U23 IO G1VDD ---
D1_MDQ40 Data Y28 IO G1VDD ---
D1_MDQ41 Data Y27 IO G1VDD ---
D1_MDQ42 Data Y25 IO G1VDD ---
D1_MDQ43 Data Y24 IO G1VDD ---
D1_MDQ44 Data V25 IO G1VDD ---
D1_MDQ45 Data Y23 IO G1VDD ---
D1_MDQ46 Data V24 IO G1VDD ---
D1_MDQ47 Data W23 IO G1VDD ---
D1_MDQ48 Data AA27 IO G1VDD ---
D1_MDQ49 Data AB28 IO G1VDD ---
D1_MDQ50 Data AB27 IO G1VDD ---
D1_MDQ51 Data AC27 IO G1VDD ---
D1_MDQ52 Data AB24 IO G1VDD ---
D1_MDQ53 Data AB23 IO G1VDD ---
D1_MDQ54 Data AA23 IO G1VDD ---
D1_MDQ55 Data AA25 IO G1VDD ---
D1_MDQ56 Data AD28 IO G1VDD ---
D1_MDQ57 Data AD27 IO G1VDD ---
Table continues on the next page...
Pin assignments
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
12 NXP Semiconductors
Table 1. Pinout list by bus (continued)
Signal Signal description Package
pin
number
Pin
type
Power supply Notes
D1_MDQ58 Data AE27 IO G1VDD ---
D1_MDQ59 Data AC25 IO G1VDD ---
D1_MDQ60 Data AF28 IO G1VDD ---
D1_MDQ61 Data AF27 IO G1VDD ---
D1_MDQ62 Data AG27 IO G1VDD ---
D1_MDQ63 Data AE26 IO G1VDD ---
D1_MDQS0 Data Strobe A26 IO G1VDD ---
D1_MDQS0_B Data Strobe B25 IO G1VDD ---
D1_MDQS1 Data Strobe F28 IO G1VDD ---
D1_MDQS1_B Data Strobe F27 IO G1VDD ---
D1_MDQS2 Data Strobe G27 IO G1VDD ---
D1_MDQS2_B Data Strobe H27 IO G1VDD ---
D1_MDQS3 Data Strobe L26 IO G1VDD ---
D1_MDQS3_B Data Strobe L25 IO G1VDD ---
D1_MDQS4 Data Strobe V28 IO G1VDD ---
D1_MDQS4_B Data Strobe U27 IO G1VDD ---
D1_MDQS5 Data Strobe W27 IO G1VDD ---
D1_MDQS5_B Data Strobe W26 IO G1VDD ---
D1_MDQS6 Data Strobe AB25 IO G1VDD ---
D1_MDQS6_B Data Strobe AC26 IO G1VDD ---
D1_MDQS7 Data Strobe AH26 IO G1VDD ---
D1_MDQS7_B Data Strobe AH27 IO G1VDD ---
D1_MDQS8 Data Strobe P27 IO G1VDD ---
D1_MDQS8_B Data Strobe P28 IO G1VDD ---
D1_MECC0 Error Correcting Code N25 IO G1VDD ---
D1_MECC1 Error Correcting Code N23 IO G1VDD ---
D1_MECC2 Error Correcting Code N26 IO G1VDD ---
D1_MECC3 Error Correcting Code N27 IO G1VDD ---
D1_MECC4 Error Correcting Code R27 IO G1VDD ---
D1_MECC5 Error Correcting Code R26 IO G1VDD ---
D1_MECC6 Error Correcting Code R23 IO G1VDD ---
D1_MECC7 Error Correcting Code P24 IO G1VDD ---
D1_MODT0 On Die Termination AG30 O G1VDD 2
D1_MODT1 On Die Termination AH29 O G1VDD 2
D1_MODT2 On Die Termination AF30 O G1VDD 2
D1_MODT3 On Die Termination AJ29 O G1VDD 2
D1_MRAS_B Row Address Strobe AC29 O G1VDD ---
D1_MWE_B Write Enable AE30 O G1VDD ---
Table continues on the next page...
Pin assignments
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
NXP Semiconductors 13
Table 1. Pinout list by bus (continued)
Signal Signal description Package
pin
number
Pin
type
Power supply Notes
Integrated Flash Controller
IFC_A16 IFC Address G15 O OVDD 1, 5
IFC_A17 IFC Address C15 O OVDD 1, 5
IFC_A18 IFC Address D15 O OVDD 1, 5
IFC_A19 IFC Address G14 O OVDD 1, 5
IFC_A20 IFC Address A16 O OVDD 1, 5
IFC_A21/cfg_dram_type IFC Address B14 O OVDD 1, 4
IFC_A22 IFC Address J15 O OVDD 1
IFC_A23 IFC Address B18 O OVDD 1
IFC_A24 IFC Address C16 O OVDD 1
IFC_A25/GPIO2_25/
IFC_WP1_B
IFC Address E17 O OVDD 1
IFC_A26/GPIO2_26/
IFC_WP2_B
IFC Address D16 O OVDD 1
IFC_A27/GPIO2_27/
IFC_WP3_B
IFC Address G17 O OVDD 1
IFC_A28/GPIO2_28 IFC Address F16 O OVDD 1
IFC_A29/GPIO2_29/
IFC_RB2_B
IFC Address G16 O OVDD 1
IFC_A30/GPIO2_30/
IFC_RB3_B
IFC Address B21 O OVDD 1
IFC_A31/GPIO2_31/
IFC_RB4_B
IFC Address E16 O OVDD 1
IFC_AD00/cfg_gpinput0 IFC Address / Data A13 IO OVDD 4
IFC_AD01/cfg_gpinput1 IFC Address / Data G13 IO OVDD 4
IFC_AD02/cfg_gpinput2 IFC Address / Data C14 IO OVDD 4
IFC_AD03/cfg_gpinput3 IFC Address / Data D13 IO OVDD 4
IFC_AD04/cfg_gpinput4 IFC Address / Data A15 IO OVDD 4
IFC_AD05/cfg_gpinput5 IFC Address / Data F13 IO OVDD 4
IFC_AD06/cfg_gpinput6 IFC Address / Data E14 IO OVDD 4
IFC_AD07/cfg_gpinput7 IFC Address / Data J13 IO OVDD 4
IFC_AD08/cfg_rcw_src0 IFC Address / Data E13 IO OVDD 4
IFC_AD09/cfg_rcw_src1 IFC Address / Data F14 IO OVDD 4
IFC_AD10/cfg_rcw_src2 IFC Address / Data H14 IO OVDD 4
IFC_AD11/cfg_rcw_src3 IFC Address / Data A14 IO OVDD 4
IFC_AD12/cfg_rcw_src4 IFC Address / Data C13 IO OVDD 4
IFC_AD13/cfg_rcw_src5 IFC Address / Data B15 IO OVDD 4
IFC_AD14/cfg_rcw_src6 IFC Address / Data F15 IO OVDD 4
IFC_AD15/cfg_rcw_src7 IFC Address / Data D14 IO OVDD 4
IFC_AVD IFC Address Valid C17 O OVDD 1, 5
Table continues on the next page...
Pin assignments
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
14 NXP Semiconductors
Table 1. Pinout list by bus (continued)
Signal Signal description Package
pin
number
Pin
type
Power supply Notes
IFC_BCTL IFC Buffer control H18 O OVDD 2
IFC_CLE/cfg_rcw_src8 IFC Command Latch Enable /
Write Enable
H19 O OVDD 1, 4
IFC_CLK0 IFC Clock A22 O OVDD 2
IFC_CLK1 IFC Clock B20 O OVDD 2
IFC_CS0_B IFC Chip Select H16 O OVDD 1, 6
IFC_CS1_B/GPIO2_10 IFC Chip Select F17 O OVDD 1, 6
IFC_CS2_B/GPIO2_11 IFC Chip Select D19 O OVDD 1, 6
IFC_CS3_B/GPIO2_12 IFC Chip Select B17 O OVDD 1, 6
IFC_CS4_B/GPIO1_09 IFC Chip Select E19 O OVDD 1, 6
IFC_CS5_B/GPIO1_10 IFC Chip Select C18 O OVDD 1, 6
IFC_CS6_B/GPIO1_11 IFC Chip Select D21 O OVDD 1, 6
IFC_CS7_B/GPIO1_12 IFC Chip Select G19 O OVDD 1, 6
IFC_NDDDR_CLK IFC NAND DDR Clock D18 O OVDD 2
IFC_NDDQS IFC DQS Strobe J19 IO OVDD ---
IFC_OE_B IFC Output Enable G18 O OVDD 1, 5
IFC_PAR0/GPIO2_13 IFC Address & Data Parity F18 IO OVDD ---
IFC_PAR1/GPIO2_14 IFC Address & Data Parity A17 IO OVDD ---
IFC_PERR_B/GPIO2_15 IFC Parity Error F19 I OVDD 1
IFC_RB0_B IFC Ready / Busy CS0 J17 I OVDD 8
IFC_RB1_B IFC Ready / Busy CS1 C19 I OVDD 8
IFC_RB2_B/IFC_A29/
GPIO2_29
IFC Ready / Busy CS 2 G16 I OVDD 1
IFC_RB3_B/IFC_A30/
GPIO2_30
IFC Ready / Busy CS 3 B21 I OVDD 1
IFC_RB4_B/IFC_A31/
GPIO2_31
IFC Ready / Busy CS 4 E16 I OVDD 1
IFC_TE/cfg_ifc_te IFC External Transceiver
Enable
A19 O OVDD 1, 4
IFC_WE0_B IFC Write Enable D17 O OVDD 1, 5
IFC_WP0_B IFC Write Protect A18 O OVDD 1, 5
IFC_WP1_B/IFC_A25/
GPIO2_25
IFC Write Protect E17 O OVDD 1
IFC_WP2_B/IFC_A26/
GPIO2_26
IFC Write Protect D16 O OVDD 1
IFC_WP3_B/IFC_A27/
GPIO2_27
IFC Write Protect G17 O OVDD 1
DUART
UART1_CTS_B/GPIO1_21/
UART3_SIN
Clear To Send L4 I DVDD 1
Table continues on the next page...
Pin assignments
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
NXP Semiconductors 15
Table 1. Pinout list by bus (continued)
Signal Signal description Package
pin
number
Pin
type
Power supply Notes
UART1_RTS_B/GPIO1_19/
UART3_SOUT
Ready to Send G1 O DVDD 1
UART1_SIN/GPIO1_17 Receive Data J3 I DVDD 1
UART1_SOUT/GPIO1_15 Transmit Data J1 O DVDD 1
UART2_CTS_B/GPIO1_22/
UART4_SIN
Clear To Send F1 I DVDD 1
UART2_RTS_B/GPIO1_20/
UART4_SOUT
Ready to Send J4 O DVDD 1
UART2_SIN/GPIO1_18 Receive Data F2 I DVDD 1
UART2_SOUT/GPIO1_16 Transmit Data K3 O DVDD 1
UART3_SIN/UART1_CTS_B/
GPIO1_21
Receive Data L4 I DVDD 1
UART3_SOUT/
UART1_RTS_B/GPIO1_19
Transmit Data G1 O DVDD 1
UART4_SIN/UART2_CTS_B/
GPIO1_22
Receive Data F1 I DVDD 1
UART4_SOUT/
UART2_RTS_B/GPIO1_20
Transmit Data J4 O DVDD 1
I2C
IIC1_SCL Serial Clock (supports PBL) H3 IO DVDD 7, 8
IIC1_SDA Serial Data (supports PBL) G2 IO DVDD 7, 8
IIC2_SCL Serial Clock H4 IO DVDD 7, 8
IIC2_SDA Serial Data K2 IO DVDD 7, 8
IIC3_SCL/GPIO4_00 Serial Clock J6 IO DVDD 7, 8
IIC3_SDA/GPIO4_01 Serial Data J2 IO DVDD 7, 8
IIC4_SCL/GPIO4_02/EVT5_B Serial Clock K1 IO DVDD 7, 8
IIC4_SDA/GPIO4_03/EVT6_B Serial Data M1 IO DVDD 7, 8
eSPI Interface
SPI_CLK SPI Clock B2 O CVDD 1
SPI_CS0_B/GPIO2_00/
SDHC_DAT4
SPI Chip Select E3 O CVDD 1, 18
SPI_CS1_B/GPIO2_01/
SDHC_DAT5
SPI Chip Select K6 O CVDD 1, 18
SPI_CS2_B/GPIO2_02/
SDHC_DAT6
SPI Chip Select H5 O CVDD 1, 18
SPI_CS3_B/GPIO2_03/
SDHC_DAT7/
SDHC_CLK_SYNC_OUT
SPI Chip Select L6 O CVDD 1, 18
SPI_MISO Master In Slave Out C2 I CVDD 1
SPI_MOSI Master Out Slave In C1 IO CVDD ---
eSDHC
Table continues on the next page...
Pin assignments
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
16 NXP Semiconductors
Table 1. Pinout list by bus (continued)
Signal Signal description Package
pin
number
Pin
type
Power supply Notes
SDHC_CD_B/GPIO4_24 SDHC Card Detect E4 I OVDD 1
SDHC_CLK/GPIO2_09 Host to Card Clock C4 IO OVDD ---
SDHC_CLK_SYNC_IN/IRQ10/
GPIO1_30
IN J5 I CVDD 1
SDHC_CLK_SYNC_OUT/
SPI_CS3_B/GPIO2_03/
SDHC_DAT7
OUT L6 O OVDD 1
SDHC_CMD/GPIO2_04 Command/Response A3 IO OVDD 18
SDHC_DAT0/GPIO2_05 Data D2 IO OVDD 18
SDHC_DAT1/GPIO2_06 Data D3 IO OVDD 18
SDHC_DAT2/GPIO2_07 Data H6 IO OVDD 18
SDHC_DAT3/GPIO2_08 Data G5 IO OVDD 18
SDHC_DAT4/SPI_CS0_B/
GPIO2_00
Data E3 IO CVDD ---
SDHC_DAT5/SPI_CS1_B/
GPIO2_01
Data K6 IO CVDD ---
SDHC_DAT6/SPI_CS2_B/
GPIO2_02
Data H5 IO CVDD ---
SDHC_DAT7/SPI_CS3_B/
GPIO2_03/
SDHC_CLK_SYNC_OUT
Data L6 IO CVDD ---
SDHC_WP/GPIO4_25 SDHC Write Protect F4 I OVDD 1
Programmable Interrupt Controller
IRQ00 External Interrupt G11 I OVDD 1
IRQ01 External Interrupt E11 I OVDD 1
IRQ02 External Interrupt D10 I OVDD 1
IRQ03/GPIO1_23 External Interrupt C10 I OVDD 1
IRQ04/GPIO1_24 External Interrupt H12 I OVDD 1
IRQ05/GPIO1_25 External Interrupt D11 I OVDD 1
IRQ06/GPIO1_26 External Interrupt P5 I LVDD 1
IRQ07/GPIO1_27 External Interrupt P3 I LVDD 1
IRQ08/GPIO1_28 External Interrupt P6 I LVDD 1
IRQ09/GPIO1_29 External Interrupt P4 I LVDD 1
IRQ10/GPIO1_30/
SDHC_CLK_SYNC_IN
External Interrupt J5 I CVDD 1
IRQ11/GPIO1_31 External Interrupt D1 I DVDD 1
IRQ_OUT_B/EVT9_B Interrupt Output C12 O OVDD 1, 6, 7
LP Trust
LP_TMP_DETECT_B Low Power Tamper Detect R7 I VDD_LP ---
Trust
Table continues on the next page...
Pin assignments
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
NXP Semiconductors 17
Table 1. Pinout list by bus (continued)
Signal Signal description Package
pin
number
Pin
type
Power supply Notes
TMP_DETECT_B Tamper Detect C21 I OVDD 1
System Control
HRESET_B Hard Reset F11 IO OVDD 6, 7
PORESET_B Power On Reset F10 I OVDD ---
RESET_REQ_B Reset Request (POR or Hard) D12 O OVDD 1, 5
Power Management
ASLEEP/GPIO1_13/
cfg_xvdd_sel
Asleep A11 O OVDD 1, 5
SYSCLK
SYSCLK System Clock A10 I OVDD ---
DDR Clocking
DDRCLK DDR Controller Clock E23 I OVDD ---
RTC
RTC/GPIO1_14 Real Time Clock A20 I OVDD 1
Debug
CKSTP_OUT_B Checkstop Out D20 O OVDD 1, 6, 7
CLK_OUT Clock Out E10 O OVDD 2
EVT0_B Event 0 A12 IO OVDD 9
EVT1_B Event 1 B12 IO OVDD ---
EVT2_B Event 2 G12 IO OVDD ---
EVT3_B Event 3 C11 IO OVDD ---
EVT4_B Event 4 F12 IO OVDD ---
EVT5_B/IIC4_SCL/GPIO4_02 Event 5 K1 IO DVDD ---
EVT6_B/IIC4_SDA/GPIO4_03 Event 6 M1 IO DVDD ---
EVT7_B/DMA2_DACK0_B/
GPIO4_08
Event 7 H1 IO DVDD ---
EVT8_B/DMA2_DDONE0_B/
GPIO4_09
Event 8 G3 IO DVDD ---
EVT9_B/IRQ_OUT_B Event 9 C12 IO OVDD ---
DFT
SCAN_MODE_B Reserved H11 I OVDD 10
TEST_SEL_B Reserved C9 I OVDD 10
JTAG
TCK Test Clock C20 I OVDD ---
TDI Test Data In D22 I OVDD 9
TDO Test Data Out E20 O OVDD 2
TMS Test Mode Select A21 I OVDD 9
TRST_B Test Reset B22 I OVDD 9
Analog Signals
Table continues on the next page...
Pin assignments
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
18 NXP Semiconductors
Table 1. Pinout list by bus (continued)
Signal Signal description Package
pin
number
Pin
type
Power supply Notes
D1_MVREF SSTL Reference Voltage F21 IO G1VDD/2 ---
D1_TPA DDR Controller 1 Test Point
Analog
C23 IO - 12
FA_ANALOG_G_V Reserved H21 IO - 15
FA_ANALOG_PIN Reserved G20 IO - 15
TD1_ANODE Thermal diode anode K22 IO Internal Diode 17
TD1_CATHODE Thermal diode cathode J21 IO Internal Diode 17
TH_TPA Thermal Test Point Analog F8 - - 12
Serdes 1
SD1_IMP_CAL_RX SerDes Receive Impedence
Calibration
AA15 I S1VDD 11
SD1_IMP_CAL_TX SerDes Transmit Impedance
Calibration
AC22 I X1VDD 16
SD1_PLL1_TPA Reserved for internal use only AE15 O AVDD_SD1_PLL1 12
SD1_PLL1_TPD Reserved for internal use only AE14 O X1VDD 12
SD1_PLL2_TPA Reserved for internal use only AF25 O AVDD_SD1_PLL2 12
SD1_PLL2_TPD Reserved for internal use only AG25 O X1VDD 12
SD1_REF_CLK1_N SerDes PLL 1 Reference Clock
Complement
AK15 I S1VDD ---
SD1_REF_CLK1_P SerDes PLL 1 Reference Clock AJ15 I S1VDD ---
SD1_REF_CLK2_N SerDes PLL 2 Reference Clock
Complement
AK25 I S1VDD ---
SD1_REF_CLK2_P SerDes PLL 2 Reference Clock AJ25 I S1VDD ---
SD1_RX0_N SerDes Receive Data
(negative)
AH13 I S1VDD ---
SD1_RX0_P SerDes Receive Data
(positive)
AH12 I S1VDD ---
SD1_RX1_N SerDes Receive Data
(negative)
AJ13 I S1VDD ---
SD1_RX1_P SerDes Receive Data
(positive)
AK13 I S1VDD ---
SD1_RX2_N SerDes Receive Data
(negative)
AK17 I S1VDD ---
SD1_RX2_P SerDes Receive Data
(positive)
AJ17 I S1VDD ---
SD1_RX3_N SerDes Receive Data
(negative)
AH18 I S1VDD ---
SD1_RX3_P SerDes Receive Data
(positive)
AH17 I S1VDD ---
SD1_RX4_N SerDes Receive Data
(negative)
AK20 I S1VDD ---
Table continues on the next page...
Pin assignments
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
NXP Semiconductors 19
Table 1. Pinout list by bus (continued)
Signal Signal description Package
pin
number
Pin
type
Power supply Notes
SD1_RX4_P SerDes Receive Data
(positive)
AJ20 I S1VDD ---
SD1_RX5_N SerDes Receive Data
(negative)
AH21 I S1VDD ---
SD1_RX5_P SerDes Receive Data
(positive)
AH20 I S1VDD ---
SD1_RX6_N SerDes Receive Data
(negative)
AK23 I S1VDD ---
SD1_RX6_P SerDes Receive Data
(positive)
AJ23 I S1VDD ---
SD1_RX7_N SerDes Receive Data
(negative)
AH24 I S1VDD ---
SD1_RX7_P SerDes Receive Data
(positive)
AH23 I S1VDD ---
SD1_TX0_N SerDes Transmit Data
(negative)
AG15 O X1VDD ---
SD1_TX0_P SerDes Transmit Data
(positive)
AG14 O X1VDD ---
SD1_TX1_N SerDes Transmit Data
(negative)
AF16 O X1VDD ---
SD1_TX1_P SerDes Transmit Data
(positive)
AE16 O X1VDD ---
SD1_TX2_N SerDes Transmit Data
(negative)
AD19 O X1VDD ---
SD1_TX2_P SerDes Transmit Data
(positive)
AD18 O X1VDD ---
SD1_TX3_N SerDes Transmit Data
(negative)
AE18 O X1VDD ---
SD1_TX3_P SerDes Transmit Data
(positive)
AF18 O X1VDD ---
SD1_TX4_N SerDes Transmit Data
(negative)
AD21 O X1VDD ---
SD1_TX4_P SerDes Transmit Data
(positive)
AD20 O X1VDD ---
SD1_TX5_N SerDes Transmit Data
(negative)
AE21 O X1VDD ---
SD1_TX5_P SerDes Transmit Data
(positive)
AF21 O X1VDD ---
SD1_TX6_N SerDes Transmit Data
(negative)
AE23 O X1VDD ---
SD1_TX6_P SerDes Transmit Data
(positive)
AF23 O X1VDD ---
SD1_TX7_N SerDes Transmit Data
(negative)
AD24 O X1VDD ---
Table continues on the next page...
Pin assignments
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
20 NXP Semiconductors
Table 1. Pinout list by bus (continued)
Signal Signal description Package
pin
number
Pin
type
Power supply Notes
SD1_TX7_P SerDes Transmit Data
(positive)
AD23 O X1VDD ---
Serdes 2
SD2_IMP_CAL_RX SerDes Receive Impedence
Calibration
AA8 I S2VDD 11
SD2_IMP_CAL_TX SerDes Transmit Impedance
Calibration
AE10 I X2VDD 16
SD2_PLL1_TPA Reserved for internal use only AC7 O AVDD_SD2_PLL1 12
SD2_PLL1_TPD Reserved for internal use only AC8 O X2VDD 12
SD2_PLL2_TPA Reserved for internal use only AG11 O AVDD_SD2_PLL2 12
SD2_PLL2_TPD Reserved for internal use only AF11 O X2VDD 12
SD2_REF_CLK1_N SerDes PLL 1 Reference Clock
Complement
AD5 I S2VDD ---
SD2_REF_CLK1_P SerDes PLL 1 Reference Clock AD6 I S2VDD ---
SD2_REF_CLK2_N SerDes PLL 2 Reference Clock
Complement
AJ11 I S2VDD ---
SD2_REF_CLK2_P SerDes PLL 2 Reference Clock AK11 I S2VDD ---
SD2_RX0_N SerDes Receive Data
(negative)
AA4 I S2VDD ---
SD2_RX0_P SerDes Receive Data
(positive)
AA3 I S2VDD ---
SD2_RX1_N SerDes Receive Data
(negative)
AC4 I S2VDD ---
SD2_RX1_P SerDes Receive Data
(positive)
AC3 I S2VDD ---
SD2_RX2_N SerDes Receive Data
(negative)
AD2 I S2VDD ---
SD2_RX2_P SerDes Receive Data
(positive)
AD1 I S2VDD ---
SD2_RX3_N SerDes Receive Data
(negative)
AJ3 I S2VDD ---
SD2_RX3_P SerDes Receive Data
(positive)
AK3 I S2VDD ---
SD2_RX4_N SerDes Receive Data
(negative)
AK5 I S2VDD ---
SD2_RX4_P SerDes Receive Data
(positive)
AJ5 I S2VDD ---
SD2_RX5_N SerDes Receive Data
(negative)
AJ6 I S2VDD ---
SD2_RX5_P SerDes Receive Data
(positive)
AK6 I S2VDD ---
SD2_RX6_N SerDes Receive Data
(negative)
AK8 I S2VDD ---
Table continues on the next page...
Pin assignments
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
NXP Semiconductors 21
Table 1. Pinout list by bus (continued)
Signal Signal description Package
pin
number
Pin
type
Power supply Notes
SD2_RX6_P SerDes Receive Data
(positive)
AJ8 I S2VDD ---
SD2_RX7_N SerDes Receive Data
(negative)
AJ9 I S2VDD ---
SD2_RX7_P SerDes Receive Data
(positive)
AK9 I S2VDD ---
SD2_TX0_N SerDes Transmit Data
(negative)
AB1 O X2VDD ---
SD2_TX0_P SerDes Transmit Data
(positive)
AB2 O X2VDD ---
SD2_TX1_N SerDes Transmit Data
(negative)
AB6 O X2VDD ---
SD2_TX1_P SerDes Transmit Data
(positive)
AB5 O X2VDD ---
SD2_TX2_N SerDes Transmit Data
(negative)
AF2 O X2VDD ---
SD2_TX2_P SerDes Transmit Data
(positive)
AF1 O X2VDD ---
SD2_TX3_N SerDes Transmit Data
(negative)
AH2 O X2VDD ---
SD2_TX3_P SerDes Transmit Data
(positive)
AH1 O X2VDD ---
SD2_TX4_N SerDes Transmit Data
(negative)
AG5 O X2VDD ---
SD2_TX4_P SerDes Transmit Data
(positive)
AF5 O X2VDD ---
SD2_TX5_N SerDes Transmit Data
(negative)
AF6 O X2VDD ---
SD2_TX5_P SerDes Transmit Data
(positive)
AG6 O X2VDD ---
SD2_TX6_N SerDes Transmit Data
(negative)
AG8 O X2VDD ---
SD2_TX6_P SerDes Transmit Data
(positive)
AF8 O X2VDD ---
SD2_TX7_N SerDes Transmit Data
(negative)
AF9 O X2VDD ---
SD2_TX7_P SerDes Transmit Data
(positive)
AG9 O X2VDD ---
USB PHY 1 & 2
USB1_DRVVBUS USB PHY Digital signal - Drive
VBUS
A8 O USB_HVDD ---
USB1_PWRFAULT USB PHY Digital signal -
Power Fault
B9 I USB_HVDD ---
USB1_UDM USB PHY Data Minus C7 IO USB_HVDD ---
Table continues on the next page...
Pin assignments
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
22 NXP Semiconductors
Table 1. Pinout list by bus (continued)
Signal Signal description Package
pin
number
Pin
type
Power supply Notes
USB1_UDP USB PHY Data Plus B8 IO USB_HVDD ---
USB1_UID USB PHY ID Detect E5 I USB_OVDD ---
USB1_VBUSCLMP USB PHY VBUS E7 I USB_HVDD ---
USB2_DRVVBUS USB PHY Digital signal - Drive
VBUS
B5 O USB_HVDD ---
USB2_PWRFAULT USB PHY Digital signal -
Power Fault
A5 I USB_HVDD ---
USB2_UDM USB PHY Data Minus B6 IO USB_HVDD ---
USB2_UDP USB PHY Data Plus A6 IO USB_HVDD ---
USB2_UID USB PHY ID Detect D7 I USB_OVDD ---
USB2_VBUSCLMP USB PHY VBUS C6 I USB_HVDD ---
USBCLK USB PHY Clock In B11 I OVDD ---
USB_IBIAS_REXT USB PHY Impedance
Calibration
F7 IO USB_OVDD 19
IEEE1588
TSEC_1588_ALARM_OUT1/
GPIO3_03
Alarm Out 1 U1 O LVDD 1
TSEC_1588_ALARM_OUT2/
GPIO3_04
Alarm Out 2 W5 O LVDD 1
TSEC_1588_CLK_IN/
GPIO3_00
Clock In T3 I LVDD 1
TSEC_1588_CLK_OUT/
GPIO3_05
Clock Out V3 O LVDD 1
TSEC_1588_PULSE_OUT1/
GPIO3_06
Pulse Out 1 W2 O LVDD 1
TSEC_1588_PULSE_OUT2/
GPIO3_07
Pulse Out 2 W1 O LVDD 1
TSEC_1588_TRIG_IN1/
GPIO3_01
Trigger In 1 V4 I LVDD 1
TSEC_1588_TRIG_IN2/
GPIO3_02
Trigger In 2 V2 I LVDD 1
Ethernet Management Interface 1
EMI1_MDC Management Data Clock T5 O LVDD ---
EMI1_MDIO Management Data In/Out N3 IO LVDD ---
Ethernet Management Interface 2
EMI2_MDC Management Data Clock (1.2V
open drain)
B3 O OVDD 7, 13
EMI2_MDIO Management Data In/Out (1.2V
open drain)
F5 IO OVDD 7, 13
Ethernet Controller (RGMII) 1
EC1_GTX_CLK/GPIO3_16 Transmit Clock Out P1 O LVDD 1
EC1_GTX_CLK125/GPIO3_17 Reference Clock M2 I LVDD 1
Table continues on the next page...
Pin assignments
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
NXP Semiconductors 23
Table 1. Pinout list by bus (continued)
Signal Signal description Package
pin
number
Pin
type
Power supply Notes
EC1_RXD0/GPIO3_21 Receive Data R5 I LVDD 1
EC1_RXD1/GPIO3_20 Receive Data N5 I LVDD 1
EC1_RXD2/GPIO3_19 Receive Data N6 I LVDD 1
EC1_RXD3/GPIO3_18 Receive Data L1 I LVDD 1
EC1_RX_CLK/GPIO3_23 Receive Clock M4 I LVDD 1
EC1_RX_CTL/GPIO3_22 Receive Data Valid L3 I LVDD 1
EC1_TXD0/GPIO3_14 Transmit Data T6 O LVDD 1
EC1_TXD1/GPIO3_13 Transmit Data N1 O LVDD 1
EC1_TXD2/GPIO3_12 Transmit Data N2 O LVDD 1
EC1_TXD3/GPIO3_11 Transmit Data R4 O LVDD 1
EC1_TX_CTL/GPIO3_15 Transmit Enable M3 O LVDD 1, 14
Ethernet Controller (RGMII) 2
EC2_GTX_CLK/GPIO4_28 Transmit Clock Out T1 O LVDD 1
EC2_GTX_CLK125/GPIO4_29 Reference Clock V1 I LVDD 1
EC2_RXD0/GPIO3_31 Receive Data R1 I LVDD 1
EC2_RXD1/GPIO3_30 Receive Data T2 I LVDD 1
EC2_RXD2/GPIO3_29 Receive Data U4 I LVDD 1
EC2_RXD3/GPIO3_28 Receive Data R2 I LVDD 1
EC2_RX_CLK/GPIO4_31 Receive Clock V6 I LVDD 1
EC2_RX_CTL/GPIO4_30 Receive Data Valid U6 I LVDD 1
EC2_TXD0/GPIO3_27 Transmit Data W6 O LVDD 1
EC2_TXD1/GPIO3_26 Transmit Data U5 O LVDD 1
EC2_TXD2/GPIO3_25 Transmit Data U3 O LVDD 1
EC2_TXD3/GPIO3_24 Transmit Data V5 O LVDD 1
EC2_TX_CTL/GPIO4_27 Transmit Enable R3 O LVDD 1, 14
DMA
DMA1_DACK0_B/GPIO4_05 DMA1 channel 0 acknowledge E1 O DVDD 1
DMA1_DDONE0_B/GPIO4_06 DMA1 channel 0 done K5 O DVDD 1
DMA1_DREQ0_B/GPIO4_04 DMA1 channel 0 request L5 I DVDD 1
DMA2_DACK0_B/GPIO4_08/
EVT7_B
DMA2 channel 0 acknowledge H1 O DVDD 1
DMA2_DDONE0_B/
GPIO4_09/EVT8_B
DMA2 channel 0 done G3 O DVDD 1
DMA2_DREQ0_B/GPIO4_07 DMA2 channel 0 request F3 I DVDD 1
Power-On-Reset Configuration
cfg_dram_type/IFC_A21 Power-On-Reset Configuration
Signal
B14 I OVDD 1, 4
cfg_gpinput0/IFC_AD00 Power-On-Reset Configuration
Signal
A13 I OVDD 1, 4
Table continues on the next page...
Pin assignments
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
24 NXP Semiconductors
Table 1. Pinout list by bus (continued)
Signal Signal description Package
pin
number
Pin
type
Power supply Notes
cfg_gpinput1/IFC_AD01 Power-On-Reset Configuration
Signal
G13 I OVDD 1, 4
cfg_gpinput2/IFC_AD02 Power-On-Reset Configuration
Signal
C14 I OVDD 1, 4
cfg_gpinput3/IFC_AD03 Power-On-Reset Configuration
Signal
D13 I OVDD 1, 4
cfg_gpinput4/IFC_AD04 Power-On-Reset Configuration
Signal
A15 I OVDD 1, 4
cfg_gpinput5/IFC_AD05 Power-On-Reset Configuration
Signal
F13 I OVDD 1, 4
cfg_gpinput6/IFC_AD06 Power-On-Reset Configuration
Signal
E14 I OVDD 1, 4
cfg_gpinput7/IFC_AD07 Power-On-Reset Configuration
Signal
J13 I OVDD 1, 4
cfg_ifc_te/IFC_TE Power-On-Reset Configuration
Signal
A19 I OVDD 1, 4
cfg_rcw_src0/IFC_AD08 Power-On-Reset Configuration
Signal
E13 I OVDD 1, 4
cfg_rcw_src1/IFC_AD09 Power-On-Reset Configuration
Signal
F14 I OVDD 1, 4
cfg_rcw_src2/IFC_AD10 Power-On-Reset Configuration
Signal
H14 I OVDD 1, 4
cfg_rcw_src3/IFC_AD11 Power-On-Reset Configuration
Signal
A14 I OVDD 1, 4
cfg_rcw_src4/IFC_AD12 Power-On-Reset Configuration
Signal
C13 I OVDD 1, 4
cfg_rcw_src5/IFC_AD13 Power-On-Reset Configuration
Signal
B15 I OVDD 1, 4
cfg_rcw_src6/IFC_AD14 Power-On-Reset Configuration
Signal
F15 I OVDD 1, 4
cfg_rcw_src7/IFC_AD15 Power-On-Reset Configuration
Signal
D14 I OVDD 1, 4
cfg_rcw_src8/IFC_CLE Power-On-Reset Configuration
Signal
H19 I OVDD 1, 4
cfg_xvdd_sel/ASLEEP/
GPIO1_13
Power-On-Reset Configuration
Signal
A11 I OVDD 1, 5, 5
General Purpose Input/Output
GPIO1_09/IFC_CS4_B General Purpose Input/Output E19 IO OVDD ---
GPIO1_10/IFC_CS5_B General Purpose Input/Output C18 IO OVDD ---
GPIO1_11/IFC_CS6_B General Purpose Input/Output D21 IO OVDD ---
GPIO1_12/IFC_CS7_B General Purpose Input/Output G19 IO OVDD ---
GPIO1_13/ASLEEP/
cfg_xvdd_sel
General Purpose Input/Output A11 O OVDD 1, 5, 5
Table continues on the next page...
Pin assignments
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
NXP Semiconductors 25
Table 1. Pinout list by bus (continued)
Signal Signal description Package
pin
number
Pin
type
Power supply Notes
GPIO1_14/RTC General Purpose Input/Output A20 IO OVDD ---
GPIO1_15/UART1_SOUT General Purpose Input/Output J1 IO DVDD ---
GPIO1_16/UART2_SOUT General Purpose Input/Output K3 IO DVDD ---
GPIO1_17/UART1_SIN General Purpose Input/Output J3 IO DVDD ---
GPIO1_18/UART2_SIN General Purpose Input/Output F2 IO DVDD ---
GPIO1_19/UART1_RTS_B/
UART3_SOUT
General Purpose Input/Output G1 IO DVDD ---
GPIO1_20/UART2_RTS_B/
UART4_SOUT
General Purpose Input/Output J4 IO DVDD ---
GPIO1_21/UART1_CTS_B/
UART3_SIN
General Purpose Input/Output L4 IO DVDD ---
GPIO1_22/UART2_CTS_B/
UART4_SIN
General Purpose Input/Output F1 IO DVDD ---
GPIO1_23/IRQ03 General Purpose Input/Output C10 IO OVDD ---
GPIO1_24/IRQ04 General Purpose Input/Output H12 IO OVDD ---
GPIO1_25/IRQ05 General Purpose Input/Output D11 IO OVDD ---
GPIO1_26/IRQ06 General Purpose Input/Output P5 IO LVDD ---
GPIO1_27/IRQ07 General Purpose Input/Output P3 IO LVDD ---
GPIO1_28/IRQ08 General Purpose Input/Output P6 IO LVDD ---
GPIO1_29/IRQ09 General Purpose Input/Output P4 IO LVDD ---
GPIO1_30/IRQ10/
SDHC_CLK_SYNC_IN
General Purpose Input/Output J5 IO CVDD ---
GPIO1_31/IRQ11 General Purpose Input/Output D1 IO DVDD ---
GPIO2_00/SPI_CS0_B/
SDHC_DAT4
General Purpose Input/Output E3 IO CVDD ---
GPIO2_01/SPI_CS1_B/
SDHC_DAT5
General Purpose Input/Output K6 IO CVDD ---
GPIO2_02/SPI_CS2_B/
SDHC_DAT6
General Purpose Input/Output H5 IO CVDD ---
GPIO2_03/SPI_CS3_B/
SDHC_DAT7/
SDHC_CLK_SYNC_OUT
General Purpose Input/Output L6 IO CVDD ---
GPIO2_04/SDHC_CMD General Purpose Input/Output A3 IO OVDD ---
GPIO2_05/SDHC_DAT0 General Purpose Input/Output D2 IO OVDD ---
GPIO2_06/SDHC_DAT1 General Purpose Input/Output D3 IO OVDD ---
GPIO2_07/SDHC_DAT2 General Purpose Input/Output H6 IO OVDD ---
GPIO2_08/SDHC_DAT3 General Purpose Input/Output G5 IO OVDD ---
GPIO2_09/SDHC_CLK General Purpose Input/Output C4 IO OVDD ---
GPIO2_10/IFC_CS1_B General Purpose Input/Output F17 IO OVDD ---
GPIO2_11/IFC_CS2_B General Purpose Input/Output D19 IO OVDD ---
GPIO2_12/IFC_CS3_B General Purpose Input/Output B17 IO OVDD ---
Table continues on the next page...
Pin assignments
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
26 NXP Semiconductors
Table 1. Pinout list by bus (continued)
Signal Signal description Package
pin
number
Pin
type
Power supply Notes
GPIO2_13/IFC_PAR0 General Purpose Input/Output F18 IO OVDD ---
GPIO2_14/IFC_PAR1 General Purpose Input/Output A17 IO OVDD ---
GPIO2_15/IFC_PERR_B General Purpose Input/Output F19 IO OVDD ---
GPIO2_25/IFC_A25/
IFC_WP1_B
General Purpose Input/Output E17 IO OVDD ---
GPIO2_26/IFC_A26/
IFC_WP2_B
General Purpose Input/Output D16 IO OVDD ---
GPIO2_27/IFC_A27/
IFC_WP3_B
General Purpose Input/Output G17 IO OVDD ---
GPIO2_28/IFC_A28 General Purpose Input/Output F16 IO OVDD ---
GPIO2_29/IFC_A29/
IFC_RB2_B
General Purpose Input/Output G16 IO OVDD ---
GPIO2_30/IFC_A30/
IFC_RB3_B
General Purpose Input/Output B21 IO OVDD ---
GPIO2_31/IFC_A31/
IFC_RB4_B
General Purpose Input/Output E16 IO OVDD ---
GPIO3_00/
TSEC_1588_CLK_IN
General Purpose Input/Output T3 IO LVDD ---
GPIO3_01/
TSEC_1588_TRIG_IN1
General Purpose Input/Output V4 IO LVDD ---
GPIO3_02/
TSEC_1588_TRIG_IN2
General Purpose Input/Output V2 IO LVDD ---
GPIO3_03/
TSEC_1588_ALARM_OUT1
General Purpose Input/Output U1 IO LVDD ---
GPIO3_04/
TSEC_1588_ALARM_OUT2
General Purpose Input/Output W5 IO LVDD ---
GPIO3_05/
TSEC_1588_CLK_OUT
General Purpose Input/Output V3 IO LVDD ---
GPIO3_06/
TSEC_1588_PULSE_OUT1
General Purpose Input/Output W2 IO LVDD ---
GPIO3_07/
TSEC_1588_PULSE_OUT2
General Purpose Input/Output W1 IO LVDD ---
GPIO3_11/EC1_TXD3 General Purpose Input/Output R4 IO LVDD ---
GPIO3_12/EC1_TXD2 General Purpose Input/Output N2 IO LVDD ---
GPIO3_13/EC1_TXD1 General Purpose Input/Output N1 IO LVDD ---
GPIO3_14/EC1_TXD0 General Purpose Input/Output T6 IO LVDD ---
GPIO3_15/EC1_TX_CTL General Purpose Input/Output M3 IO LVDD ---
GPIO3_16/EC1_GTX_CLK General Purpose Input/Output P1 IO LVDD ---
GPIO3_17/EC1_GTX_CLK125 General Purpose Input/Output M2 IO LVDD ---
GPIO3_18/EC1_RXD3 General Purpose Input/Output L1 IO LVDD ---
GPIO3_19/EC1_RXD2 General Purpose Input/Output N6 IO LVDD ---
GPIO3_20/EC1_RXD1 General Purpose Input/Output N5 IO LVDD ---
Table continues on the next page...
Pin assignments
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
NXP Semiconductors 27
Table 1. Pinout list by bus (continued)
Signal Signal description Package
pin
number
Pin
type
Power supply Notes
GPIO3_21/EC1_RXD0 General Purpose Input/Output R5 IO LVDD ---
GPIO3_22/EC1_RX_CTL General Purpose Input/Output L3 IO LVDD ---
GPIO3_23/EC1_RX_CLK General Purpose Input/Output M4 IO LVDD ---
GPIO3_24/EC2_TXD3 General Purpose Input/Output V5 IO LVDD ---
GPIO3_25/EC2_TXD2 General Purpose Input/Output U3 IO LVDD ---
GPIO3_26/EC2_TXD1 General Purpose Input/Output U5 IO LVDD ---
GPIO3_27/EC2_TXD0 General Purpose Input/Output W6 IO LVDD ---
GPIO3_28/EC2_RXD3 General Purpose Input/Output R2 IO LVDD ---
GPIO3_29/EC2_RXD2 General Purpose Input/Output U4 IO LVDD ---
GPIO3_30/EC2_RXD1 General Purpose Input/Output T2 IO LVDD ---
GPIO3_31/EC2_RXD0 General Purpose Input/Output R1 IO LVDD ---
GPIO4_00/IIC3_SCL General Purpose Input/Output J6 IO DVDD ---
GPIO4_01/IIC3_SDA General Purpose Input/Output J2 IO DVDD ---
GPIO4_02/IIC4_SCL/EVT5_B General Purpose Input/Output K1 IO DVDD ---
GPIO4_03/IIC4_SDA/EVT6_B General Purpose Input/Output M1 IO DVDD ---
GPIO4_04/DMA1_DREQ0_B General Purpose Input/Output L5 IO DVDD ---
GPIO4_05/DMA1_DACK0_B General Purpose Input/Output E1 IO DVDD ---
GPIO4_06/DMA1_DDONE0_B General Purpose Input/Output K5 IO DVDD ---
GPIO4_07/DMA2_DREQ0_B General Purpose Input/Output F3 IO DVDD ---
GPIO4_08/DMA2_DACK0_B/
EVT7_B
General Purpose Input/Output H1 IO DVDD ---
GPIO4_09/
DMA2_DDONE0_B/EVT8_B
General Purpose Input/Output G3 IO DVDD ---
GPIO4_24/SDHC_CD_B General Purpose Input/Output E4 IO OVDD ---
GPIO4_25/SDHC_WP General Purpose Input/Output F4 IO OVDD ---
GPIO4_27/EC2_TX_CTL General Purpose Input/Output R3 IO LVDD ---
GPIO4_28/EC2_GTX_CLK General Purpose Input/Output T1 IO LVDD ---
GPIO4_29/EC2_GTX_CLK125 General Purpose Input/Output V1 IO LVDD ---
GPIO4_30/EC2_RX_CTL General Purpose Input/Output U6 IO LVDD ---
GPIO4_31/EC2_RX_CLK General Purpose Input/Output V6 IO LVDD ---
Power and Ground Signals
GND001 GND AK27 --- --- ---
GND002 GND AH28 --- --- ---
GND003 GND AG28 --- --- ---
GND004 GND AG26 --- --- ---
GND005 GND AF26 --- --- ---
GND006 GND AE28 --- --- ---
GND007 GND AE25 --- --- ---
Table continues on the next page...
Pin assignments
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
28 NXP Semiconductors
Table 1. Pinout list by bus (continued)
Signal Signal description Package
pin
number
Pin
type
Power supply Notes
GND008 GND AD26 --- --- ---
GND009 GND AD25 --- --- ---
GND010 GND AC28 --- --- ---
GND011 GND AC24 --- --- ---
GND012 GND AB26 --- --- ---
GND013 GND AA28 --- --- ---
GND014 GND AA24 --- --- ---
GND015 GND AA22 --- --- ---
GND016 GND Y26 --- --- ---
GND017 GND Y22 --- --- ---
GND018 GND Y9 --- --- ---
GND019 GND Y8 --- --- ---
GND020 GND Y7 --- --- ---
GND021 GND Y6 --- --- ---
GND022 GND Y5 --- --- ---
GND023 GND Y2 --- --- ---
GND024 GND Y1 --- --- ---
GND025 GND W28 --- --- ---
GND026 GND W24 --- --- ---
GND027 GND W22 --- --- ---
GND028 GND W20 --- --- ---
GND029 GND W18 --- --- ---
GND030 GND W16 --- --- ---
GND031 GND W14 --- --- ---
GND032 GND W12 --- --- ---
GND033 GND W10 --- --- ---
GND034 GND W8 --- --- ---
GND035 GND W7 --- --- ---
GND036 GND W4 --- --- ---
GND037 GND W3 --- --- ---
GND038 GND V26 --- --- ---
GND039 GND V23 --- --- ---
GND040 GND V21 --- --- ---
GND041 GND V19 --- --- ---
GND042 GND V17 --- --- ---
GND043 GND V15 --- --- ---
GND044 GND V13 --- --- ---
GND045 GND V11 --- --- ---
Table continues on the next page...
Pin assignments
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
NXP Semiconductors 29
Table 1. Pinout list by bus (continued)
Signal Signal description Package
pin
number
Pin
type
Power supply Notes
GND046 GND V9 --- --- ---
GND047 GND V7 --- --- ---
GND048 GND U28 --- --- ---
GND049 GND U24 --- --- ---
GND050 GND U20 --- --- ---
GND051 GND U18 --- --- ---
GND052 GND U16 --- --- ---
GND053 GND U14 --- --- ---
GND054 GND U12 --- --- ---
GND055 GND U10 --- --- ---
GND056 GND U7 --- --- ---
GND057 GND U2 --- --- ---
GND058 GND T26 --- --- ---
GND059 GND T23 --- --- ---
GND060 GND T21 --- --- ---
GND061 GND T19 --- --- ---
GND062 GND T17 --- --- ---
GND063 GND T15 --- --- ---
GND064 GND T13 --- --- ---
GND065 GND T11 --- --- ---
GND066 GND T9 --- --- ---
GND067 GND T7 --- --- ---
GND068 GND T4 --- --- ---
GND069 GND R28 --- --- ---
GND070 GND R24 --- --- ---
GND071 GND R20 --- --- ---
GND072 GND R18 --- --- ---
GND073 GND R16 --- --- ---
GND074 GND R14 --- --- ---
GND075 GND R12 --- --- ---
GND076 GND R10 --- --- ---
GND077 GND R6 --- --- ---
GND078 GND P26 --- --- ---
GND079 GND P23 --- --- ---
GND080 GND P21 --- --- ---
GND081 GND P19 --- --- ---
GND082 GND P17 --- --- ---
GND083 GND P15 --- --- ---
Table continues on the next page...
Pin assignments
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
30 NXP Semiconductors
Table 1. Pinout list by bus (continued)
Signal Signal description Package
pin
number
Pin
type
Power supply Notes
GND084 GND P13 --- --- ---
GND085 GND P11 --- --- ---
GND086 GND P9 --- --- ---
GND087 GND P7 --- --- ---
GND088 GND P2 --- --- ---
GND089 GND N28 --- --- ---
GND090 GND N24 --- --- ---
GND091 GND N20 --- --- ---
GND092 GND N18 --- --- ---
GND093 GND N16 --- --- ---
GND094 GND N14 --- --- ---
GND095 GND N12 --- --- ---
GND096 GND N10 --- --- ---
GND097 GND N7 --- --- ---
GND098 GND N4 --- --- ---
GND099 GND M26 --- --- ---
GND100 GND M23 --- --- ---
GND101 GND M21 --- --- ---
GND102 GND M19 --- --- ---
GND103 GND M17 --- --- ---
GND104 GND M15 --- --- ---
GND105 GND M13 --- --- ---
GND106 GND M11 --- --- ---
GND107 GND M9 --- --- ---
GND108 GND M7 --- --- ---
GND109 GND M5 --- --- ---
GND110 GND L28 --- --- ---
GND111 GND L24 --- --- ---
GND112 GND L20 --- --- ---
GND113 GND L18 --- --- ---
GND114 GND L16 --- --- ---
GND115 GND L14 --- --- ---
GND116 GND L12 --- --- ---
GND117 GND L10 --- --- ---
GND118 GND L7 --- --- ---
GND119 GND L2 --- --- ---
GND120 GND K26 --- --- ---
GND121 GND K23 --- --- ---
Table continues on the next page...
Pin assignments
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
NXP Semiconductors 31
Table 1. Pinout list by bus (continued)
Signal Signal description Package
pin
number
Pin
type
Power supply Notes
GND122 GND K11 --- --- ---
GND123 GND K9 --- --- ---
GND124 GND K7 --- --- ---
GND125 GND K4 --- --- ---
GND126 GND J28 --- --- ---
GND127 GND J24 --- --- ---
GND128 GND J22 --- --- ---
GND129 GND J18 --- --- ---
GND130 GND J16 --- --- ---
GND131 GND J14 --- --- ---
GND132 GND J12 --- --- ---
GND133 GND J11 --- --- ---
GND134 GND J9 --- --- ---
GND135 GND H26 --- --- ---
GND136 GND H22 --- --- ---
GND137 GND H17 --- --- ---
GND138 GND H15 --- --- ---
GND139 GND H13 --- --- ---
GND140 GND H10 --- --- ---
GND141 GND H2 --- --- ---
GND142 GND G28 --- --- ---
GND143 GND G24 --- --- ---
GND144 GND G22 --- --- ---
GND145 GND G21 --- --- ---
GND146 GND G10 --- --- ---
GND147 GND G8 --- --- ---
GND148 GND G4 --- --- ---
GND149 GND F26 --- --- ---
GND150 GND F23 --- --- ---
GND151 GND F20 --- --- ---
GND152 GND F9 --- --- ---
GND153 GND E28 --- --- ---
GND154 GND E24 --- --- ---
GND155 GND E22 --- --- ---
GND156 GND E21 --- --- ---
GND157 GND E18 --- --- ---
GND158 GND E15 --- --- ---
GND159 GND E12 --- --- ---
Table continues on the next page...
Pin assignments
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
32 NXP Semiconductors
Table 1. Pinout list by bus (continued)
Signal Signal description Package
pin
number
Pin
type
Power supply Notes
GND160 GND E2 --- --- ---
GND161 GND D26 --- --- ---
GND162 GND D23 --- --- ---
GND163 GND D9 --- --- ---
GND164 GND D4 --- --- ---
GND165 GND C28 --- --- ---
GND166 GND C24 --- --- ---
GND167 GND C22 --- --- ---
GND168 GND C3 --- --- ---
GND169 GND B26 --- --- ---
GND170 GND B23 --- --- ---
GND171 GND B19 --- --- ---
GND172 GND B16 --- --- ---
GND173 GND B13 --- --- ---
GND174 GND B10 --- --- ---
GND175 GND B4 --- --- ---
GND176 GND B1 --- --- ---
GND177 GND A27 --- --- ---
GND178 GND A23 --- --- ---
GND179 GND A4 --- --- ---
GND180 GND A2 --- --- ---
USB_AGND01 USB PHY Transceiver GND H8 --- --- ---
USB_AGND02 USB PHY Transceiver GND H7 --- --- ---
USB_AGND03 USB PHY Transceiver GND G6 --- --- ---
USB_AGND04 USB PHY Transceiver GND E6 --- --- ---
USB_AGND05 USB PHY Transceiver GND D8 --- --- ---
USB_AGND06 USB PHY Transceiver GND D6 --- --- ---
USB_AGND07 USB PHY Transceiver GND D5 --- --- ---
USB_AGND08 USB PHY Transceiver GND C5 --- --- ---
USB_AGND09 USB PHY Transceiver GND B7 --- --- ---
USB_AGND10 USB PHY Transceiver GND A9 --- --- ---
X1GND01 Serdes1 transceiver GND AG23 --- --- ---
X1GND02 Serdes1 transceiver GND AG21 --- --- ---
X1GND03 Serdes1 transceiver GND AG18 --- --- ---
X1GND04 Serdes1 transceiver GND AG16 --- --- ---
X1GND05 Serdes1 transceiver GND AG13 --- --- ---
X1GND06 Serdes1 transceiver GND AF24 --- --- ---
X1GND07 Serdes1 transceiver GND AF22 --- --- ---
Table continues on the next page...
Pin assignments
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
NXP Semiconductors 33
Table 1. Pinout list by bus (continued)
Signal Signal description Package
pin
number
Pin
type
Power supply Notes
X1GND08 Serdes1 transceiver GND AF20 --- --- ---
X1GND09 Serdes1 transceiver GND AF19 --- --- ---
X1GND10 Serdes1 transceiver GND AF17 --- --- ---
X1GND11 Serdes1 transceiver GND AF15 --- --- ---
X1GND12 Serdes1 transceiver GND AF14 --- --- ---
X1GND13 Serdes1 transceiver GND AE24 --- --- ---
X1GND14 Serdes1 transceiver GND AE22 --- --- ---
X1GND15 Serdes1 transceiver GND AE20 --- --- ---
X1GND16 Serdes1 transceiver GND AE19 --- --- ---
X1GND17 Serdes1 transceiver GND AE17 --- --- ---
X1GND18 Serdes1 transceiver GND AD22 --- --- ---
X1GND19 Serdes1 transceiver GND AD17 --- --- ---
X1GND20 Serdes1 transceiver GND AC23 --- --- ---
X1GND21 Serdes1 transceiver GND AC21 --- --- ---
X1GND22 Serdes1 transceiver GND AB21 --- --- ---
S1GND01 Serdes core logic GND AK26 --- --- ---
S1GND02 Serdes core logic GND AK24 --- --- ---
S1GND03 Serdes core logic GND AK22 --- --- ---
S1GND04 Serdes core logic GND AK21 --- --- ---
S1GND05 Serdes core logic GND AK19 --- --- ---
S1GND06 Serdes core logic GND AK18 --- --- ---
S1GND07 Serdes core logic GND AK16 --- --- ---
S1GND08 Serdes core logic GND AK14 --- --- ---
S1GND09 Serdes core logic GND AK12 --- --- ---
S1GND10 Serdes core logic GND AJ26 --- --- ---
S1GND11 Serdes core logic GND AJ24 --- --- ---
S1GND12 Serdes core logic GND AJ22 --- --- ---
S1GND13 Serdes core logic GND AJ21 --- --- ---
S1GND14 Serdes core logic GND AJ19 --- --- ---
S1GND15 Serdes core logic GND AJ18 --- --- ---
S1GND16 Serdes core logic GND AJ16 --- --- ---
S1GND17 Serdes core logic GND AJ14 --- --- ---
S1GND18 Serdes core logic GND AJ12 --- --- ---
S1GND19 Serdes core logic GND AH25 --- --- ---
S1GND20 Serdes core logic GND AH22 --- --- ---
S1GND21 Serdes core logic GND AH19 --- --- ---
S1GND22 Serdes core logic GND AH16 --- --- ---
S1GND23 Serdes core logic GND AH15 --- --- ---
Table continues on the next page...
Pin assignments
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
34 NXP Semiconductors
Table 1. Pinout list by bus (continued)
Signal Signal description Package
pin
number
Pin
type
Power supply Notes
S1GND24 Serdes core logic GND AH14 --- --- ---
S1GND25 Serdes core logic GND AC20 --- --- ---
S1GND26 Serdes core logic GND AC19 --- --- ---
S1GND27 Serdes core logic GND AC18 --- --- ---
S1GND28 Serdes core logic GND AC17 --- --- ---
S1GND29 Serdes core logic GND AC16 --- --- ---
S1GND30 Serdes core logic GND AB18 --- --- ---
S1GND31 Serdes core logic GND AA21 --- --- ---
S1GND32 Serdes core logic GND AA20 --- --- ---
S1GND33 Serdes core logic GND AA19 --- --- ---
S1GND34 Serdes core logic GND AA18 --- --- ---
S1GND35 Serdes core logic GND AA17 --- --- ---
X2GND01 Serdes1 transceiver GND AJ2 --- --- ---
X2GND02 Serdes1 transceiver GND AJ1 --- --- ---
X2GND03 Serdes1 transceiver GND AG12 --- --- ---
X2GND04 Serdes1 transceiver GND AG10 --- --- ---
X2GND05 Serdes1 transceiver GND AG7 --- --- ---
X2GND06 Serdes1 transceiver GND AG4 --- --- ---
X2GND07 Serdes1 transceiver GND AG2 --- --- ---
X2GND08 Serdes1 transceiver GND AG1 --- --- ---
X2GND09 Serdes1 transceiver GND AF12 --- --- ---
X2GND10 Serdes1 transceiver GND AF10 --- --- ---
X2GND11 Serdes1 transceiver GND AF7 --- --- ---
X2GND12 Serdes1 transceiver GND AF4 --- --- ---
X2GND13 Serdes1 transceiver GND AF3 --- --- ---
X2GND14 Serdes1 transceiver GND AE9 --- --- ---
X2GND15 Serdes1 transceiver GND AE8 --- --- ---
X2GND16 Serdes1 transceiver GND AE7 --- --- ---
X2GND17 Serdes1 transceiver GND AE4 --- --- ---
X2GND18 Serdes1 transceiver GND AD11 --- --- ---
X2GND19 Serdes1 transceiver GND AD10 --- --- ---
X2GND20 Serdes1 transceiver GND AA7 --- --- ---
X2GND21 Serdes1 transceiver GND AA6 --- --- ---
X2GND22 Serdes1 transceiver GND AA5 --- --- ---
X2GND23 Serdes1 transceiver GND AA2 --- --- ---
X2GND24 Serdes1 transceiver GND AA1 --- --- ---
X2GND25 Serdes1 transceiver GND Y4 --- --- ---
X2GND26 Serdes1 transceiver GND Y3 --- --- ---
Table continues on the next page...
Pin assignments
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
NXP Semiconductors 35
Table 1. Pinout list by bus (continued)
Signal Signal description Package
pin
number
Pin
type
Power supply Notes
S2GND01 Serdes core logic GND AK10 --- --- ---
S2GND02 Serdes core logic GND AK7 --- --- ---
S2GND03 Serdes core logic GND AK4 --- --- ---
S2GND04 Serdes core logic GND AK2 --- --- ---
S2GND05 Serdes core logic GND AJ10 --- --- ---
S2GND06 Serdes core logic GND AJ7 --- --- ---
S2GND07 Serdes core logic GND AJ4 --- --- ---
S2GND08 Serdes core logic GND AH11 --- --- ---
S2GND09 Serdes core logic GND AH9 --- --- ---
S2GND10 Serdes core logic GND AH8 --- --- ---
S2GND11 Serdes core logic GND AH6 --- --- ---
S2GND12 Serdes core logic GND AH5 --- --- ---
S2GND13 Serdes core logic GND AH3 --- --- ---
S2GND14 Serdes core logic GND AE6 --- --- ---
S2GND15 Serdes core logic GND AE5 --- --- ---
S2GND16 Serdes core logic GND AE2 --- --- ---
S2GND17 Serdes core logic GND AE1 --- --- ---
S2GND18 Serdes core logic GND AD15 --- --- ---
S2GND19 Serdes core logic GND AD8 --- --- ---
S2GND20 Serdes core logic GND AD7 --- --- ---
S2GND21 Serdes core logic GND AD4 --- --- ---
S2GND22 Serdes core logic GND AD3 --- --- ---
S2GND23 Serdes core logic GND AC14 --- --- ---
S2GND24 Serdes core logic GND AC13 --- --- ---
S2GND25 Serdes core logic GND AC12 --- --- ---
S2GND26 Serdes core logic GND AC11 --- --- ---
S2GND27 Serdes core logic GND AC10 --- --- ---
S2GND28 Serdes core logic GND AC9 --- --- ---
S2GND29 Serdes core logic GND AC6 --- --- ---
S2GND30 Serdes core logic GND AC5 --- --- ---
S2GND31 Serdes core logic GND AC2 --- --- ---
S2GND32 Serdes core logic GND AC1 --- --- ---
S2GND33 Serdes core logic GND AB12 --- --- ---
S2GND34 Serdes core logic GND AB9 --- --- ---
S2GND35 Serdes core logic GND AB8 --- --- ---
S2GND36 Serdes core logic GND AB7 --- --- ---
S2GND37 Serdes core logic GND AB4 --- --- ---
S2GND38 Serdes core logic GND AB3 --- --- ---
Table continues on the next page...
Pin assignments
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
36 NXP Semiconductors
Table 1. Pinout list by bus (continued)
Signal Signal description Package
pin
number
Pin
type
Power supply Notes
S2GND39 Serdes core logic GND AA16 --- --- ---
S2GND40 Serdes core logic GND AA14 --- --- ---
S2GND41 Serdes core logic GND AA13 --- --- ---
S2GND42 Serdes core logic GND AA12 --- --- ---
S2GND43 Serdes core logic GND AA11 --- --- ---
S2GND44 Serdes core logic GND AA10 --- --- ---
AGND_SD1_PLL1 Serdes 1 PLL 1 GND AB16 --- --- ---
AGND_SD1_PLL2 Serdes 1 PLL 2 GND AB19 --- --- ---
AGND_SD2_PLL1 Serdes 2 PLL 1 GND AB10 --- --- ---
AGND_SD2_PLL2 Serdes 2 PLL 2 GND AB13 --- --- ---
SENSEGND GND Sense pin K21 --- --- ---
OVDD01 General I/O supply L8 --- OVDD ---
OVDD02 General I/O supply K20 --- OVDD ---
OVDD03 General I/O supply K19 --- OVDD ---
OVDD04 General I/O supply K18 --- OVDD ---
OVDD05 General I/O supply K17 --- OVDD ---
OVDD06 General I/O supply K16 --- OVDD ---
OVDD07 General I/O supply K15 --- OVDD ---
OVDD08 General I/O supply K14 --- OVDD ---
OVDD09 General I/O supply K13 --- OVDD ---
OVDD10 General I/O supply K12 --- OVDD ---
OVDD11 General I/O supply K8 --- OVDD ---
DVDD1 UART/I2C/DMA supply P8 --- DVDD ---
DVDD2 UART/I2C/DMA supply N8 --- DVDD ---
CVDD1 eSPI supply M8 --- CVDD ---
CVDD2 eSPI supply M6 --- CVDD ---
LVDD1 Ethernet controllers (RGMII),
EMI2 and GPIO supply
V8 --- LVDD ---
LVDD2 Ethernet controllers (RGMII),
EMI2 and GPIO supply
U8 --- LVDD ---
LVDD3 Ethernet controllers (RGMII),
EMI2 and GPIO supply
T8 --- LVDD ---
G1VDD01 DDR supply AK29 --- G1VDD ---
G1VDD02 DDR supply AJ30 --- G1VDD ---
G1VDD03 DDR supply AF29 --- G1VDD ---
G1VDD04 DDR supply AD29 --- G1VDD ---
G1VDD05 DDR supply AB29 --- G1VDD ---
G1VDD06 DDR supply Y29 --- G1VDD ---
G1VDD07 DDR supply V29 --- G1VDD ---
Table continues on the next page...
Pin assignments
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
NXP Semiconductors 37
Table 1. Pinout list by bus (continued)
Signal Signal description Package
pin
number
Pin
type
Power supply Notes
G1VDD08 DDR supply V22 --- G1VDD ---
G1VDD09 DDR supply U22 --- G1VDD ---
G1VDD10 DDR supply T30 --- G1VDD ---
G1VDD11 DDR supply T29 --- G1VDD ---
G1VDD12 DDR supply T22 --- G1VDD ---
G1VDD13 DDR supply R22 --- G1VDD ---
G1VDD14 DDR supply P29 --- G1VDD ---
G1VDD15 DDR supply P22 --- G1VDD ---
G1VDD16 DDR supply N22 --- G1VDD ---
G1VDD17 DDR supply M29 --- G1VDD ---
G1VDD18 DDR supply M22 --- G1VDD ---
G1VDD19 DDR supply L22 --- G1VDD ---
G1VDD20 DDR supply K29 --- G1VDD ---
G1VDD21 DDR supply H29 --- G1VDD ---
G1VDD22 DDR supply F29 --- G1VDD ---
G1VDD23 DDR supply D29 --- G1VDD ---
G1VDD24 DDR supply B30 --- G1VDD ---
G1VDD25 DDR supply A29 --- G1VDD ---
S1VDD1 SerDes1 core logic supply Y21 --- S1VDD ---
S1VDD2 SerDes1 core logic supply Y20 --- S1VDD ---
S1VDD3 SerDes1 core logic supply Y19 --- S1VDD ---
S1VDD4 SerDes1 core logic supply Y18 --- S1VDD ---
S1VDD5 SerDes1 core logic supply Y17 --- S1VDD ---
S1VDD6 SerDes1 core logic supply Y16 --- S1VDD ---
S2VDD1 SerDes1 core logic supply AA9 --- S2VDD ---
S2VDD2 SerDes1 core logic supply Y15 --- S2VDD ---
S2VDD3 SerDes1 core logic supply Y14 --- S2VDD ---
S2VDD4 SerDes1 core logic supply Y13 --- S2VDD ---
S2VDD5 SerDes1 core logic supply Y12 --- S2VDD ---
S2VDD6 SerDes1 core logic supply Y11 --- S2VDD ---
X1VDD1 SerDes1 transceiver supply AG24 --- X1VDD ---
X1VDD2 SerDes1 transceiver supply AG22 --- X1VDD ---
X1VDD3 SerDes1 transceiver supply AG20 --- X1VDD ---
X1VDD4 SerDes1 transceiver supply AG19 --- X1VDD ---
X1VDD5 SerDes1 transceiver supply AG17 --- X1VDD ---
X1VDD6 SerDes1 transceiver supply AD16 --- X1VDD ---
X1VDD7 SerDes1 transceiver supply AB22 --- X1VDD ---
X2VDD1 SerDes1 transceiver supply AH10 --- X2VDD ---
Table continues on the next page...
Pin assignments
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
38 NXP Semiconductors
Table 1. Pinout list by bus (continued)
Signal Signal description Package
pin
number
Pin
type
Power supply Notes
X2VDD2 SerDes1 transceiver supply AH7 --- X2VDD ---
X2VDD3 SerDes1 transceiver supply AH4 --- X2VDD ---
X2VDD4 SerDes1 transceiver supply AG3 --- X2VDD ---
X2VDD5 SerDes1 transceiver supply AE11 --- X2VDD ---
X2VDD6 SerDes1 transceiver supply AE3 --- X2VDD ---
FA_VL Reserved for internal use only H20 --- FA_VL 15
PROG_MTR Reserved for internal use only E8 --- PROG_MTR 15
PROG_SFP Security Fuse Programming
Override supply
E9 --- PROG_SFP ---
TH_VDD Thermal Monitor Unit supply K10 --- TH_VDD ---
VDD01 Supply for cores and platform Y10 --- VDD ---
VDD02 Supply for cores and platform W21 --- VDD ---
VDD03 Supply for cores and platform W19 --- VDD ---
VDD04 Supply for cores and platform W17 --- VDD ---
VDD05 Supply for cores and platform W15 --- VDD ---
VDD06 Supply for cores and platform W13 --- VDD ---
VDD07 Supply for cores and platform W11 --- VDD ---
VDD08 Supply for cores and platform W9 --- VDD ---
VDD09 Supply for cores and platform V20 --- VDD ---
VDD10 Supply for cores and platform V18 --- VDD ---
VDD11 Supply for cores and platform V16 --- VDD ---
VDD12 Supply for cores and platform V14 --- VDD ---
VDD13 Supply for cores and platform V12 --- VDD ---
VDD14 Supply for cores and platform V10 --- VDD ---
VDD15 Supply for cores and platform U21 --- VDD ---
VDD16 Supply for cores and platform U19 --- VDD ---
VDD17 Supply for cores and platform U17 --- VDD ---
VDD18 Supply for cores and platform U15 --- VDD ---
VDD19 Supply for cores and platform U13 --- VDD ---
VDD20 Supply for cores and platform U11 --- VDD ---
VDD21 Supply for cores and platform U9 --- VDD ---
VDD22 Supply for cores and platform T20 --- VDD ---
VDD23 Supply for cores and platform T18 --- VDD ---
VDD24 Supply for cores and platform T16 --- VDD ---
VDD25 Supply for cores and platform T14 --- VDD ---
VDD26 Supply for cores and platform T12 --- VDD ---
VDD27 Supply for cores and platform T10 --- VDD ---
VDD28 Supply for cores and platform R21 --- VDD ---
Table continues on the next page...
Pin assignments
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
NXP Semiconductors 39
Table 1. Pinout list by bus (continued)
Signal Signal description Package
pin
number
Pin
type
Power supply Notes
VDD29 Supply for cores and platform R19 --- VDD ---
VDD30 Supply for cores and platform R17 --- VDD ---
VDD31 Supply for cores and platform R15 --- VDD ---
VDD32 Supply for cores and platform R13 --- VDD ---
VDD33 Supply for cores and platform R11 --- VDD ---
VDD34 Supply for cores and platform R9 --- VDD ---
VDD35 Supply for cores and platform P20 --- VDD ---
VDD36 Supply for cores and platform P18 --- VDD ---
VDD37 Supply for cores and platform P16 --- VDD ---
VDD38 Supply for cores and platform P14 --- VDD ---
VDD39 Supply for cores and platform P12 --- VDD ---
VDD40 Supply for cores and platform P10 --- VDD ---
VDD41 Supply for cores and platform N21 --- VDD ---
VDD42 Supply for cores and platform N19 --- VDD ---
VDD43 Supply for cores and platform N17 --- VDD ---
VDD44 Supply for cores and platform N15 --- VDD ---
VDD45 Supply for cores and platform N13 --- VDD ---
VDD46 Supply for cores and platform N11 --- VDD ---
VDD47 Supply for cores and platform N9 --- VDD ---
VDD48 Supply for cores and platform M20 --- VDD ---
VDD49 Supply for cores and platform M18 --- VDD ---
VDD50 Supply for cores and platform M16 --- VDD ---
VDD51 Supply for cores and platform M14 --- VDD ---
VDD52 Supply for cores and platform M12 --- VDD ---
VDD53 Supply for cores and platform M10 --- VDD ---
VDD54 Supply for cores and platform L21 --- VDD ---
VDD55 Supply for cores and platform L19 --- VDD ---
VDD56 Supply for cores and platform L17 --- VDD ---
VDD57 Supply for cores and platform L15 --- VDD ---
VDD58 Supply for cores and platform L13 --- VDD ---
VDD59 Supply for cores and platform L11 --- VDD ---
VDD60 Supply for cores and platform L9 --- VDD ---
VDD_LP Low Power Security Monitor
supply
R8 --- VDD_LP ---
AVDD_CGA1 e6500 Cluster Group A PLL1
supply
H9 --- AVDD_CGA1 ---
AVDD_CGA2 e6500 Cluster Group A PLL2
supply
G9 --- AVDD_CGA2 ---
AVDD_PLAT Platform PLL supply J10 --- AVDD_PLAT ---
Table continues on the next page...
Pin assignments
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
40 NXP Semiconductors
Table 1. Pinout list by bus (continued)
Signal Signal description Package
pin
number
Pin
type
Power supply Notes
AVDD_D1 DDR1 PLL supply F22 --- AVDD_D1 ---
AVDD_SD1_PLL1 SerDes 1 PLL 1 supply AB17 --- AVDD_SD1_PLL1 ---
AVDD_SD1_PLL2 SerDes 1 PLL 2 supply AB20 --- AVDD_SD1_PLL2 ---
AVDD_SD2_PLL1 SerDes 2 PLL 1 supply AB11 --- AVDD_SD2_PLL1 ---
AVDD_SD2_PLL2 SerDes 2 PLL 2 supply AB14 --- AVDD_SD2_PLL2 ---
SENSEVDD Vdd Sense pin J20 --- SENSEVDD ---
USB_HVDD1 USB PHY Transceiver 3.3V
Supply
C8 --- USB_HVDD ---
USB_HVDD2 USB PHY Transceiver 3.3V
Supply
A7 --- USB_HVDD ---
USB_OVDD1 USB PHY Transceiver 1.8V
Supply
J8 --- USB_OVDD ---
USB_OVDD2 USB PHY Transceiver 1.8V
Supply
J7 --- USB_OVDD ---
USB_SVDD1 USB PHY Analog 1.0V Supply G7 --- USB_SVDD ---
USB_SVDD2 USB PHY Analog 1.0V Supply F6 --- USB_SVDD ---
No Connection Pins
NC_AB15 No Connection AB15 --- --- 12
NC_AC15 No Connection AC15 --- --- 12
NC_AD12 No Connection AD12 --- --- 12
NC_AD13 No Connection AD13 --- --- 12
NC_AD14 No Connection AD14 --- --- 12
NC_AD9 No Connection AD9 --- --- 12
NC_AE12 No Connection AE12 --- --- 12
NC_AE13 No Connection AE13 --- --- 12
NC_AF13 No Connection AF13 --- --- 12
1. Functionally, this pin is an output or an input, but structurally it is an I/O because it
either samples configuration input during reset, is a muxed pin, or has other
manufacturing test functions. This pin will therefore be described as an I/O for boundary
scan.
2. This output is actively driven during reset rather than being tri-stated during reset.
3. MDIC[0] is grounded through a 187 Ω precision 1% resistor and MDIC[1] is
connected to GVDD through a 187 Ω precision 1% resistor. For either full or half driver
strength calibration of DDR I/Os, use the same MDIC resistor value of 187 Ω. Memory
controller register setting can be used to determine automatic calibration is done to full or
half drive strength. These pins are used for automatic calibration of the DDR3/DDR3L
I/Os. The MDIC[0:1] pins must be connected to 187 Ω precision 1% resistors.
Pin assignments
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
NXP Semiconductors 41
4. This pin is a reset configuration pin. It has a weak (~20 kΩ) internal pull-up P-FET that
is enabled only when the device is in its reset state. This pull-up is designed to be
overpowered by an external 4.7 kΩ resistor. If the signal is intended to be high after reset,
and if there is any device on the net that might pull down the value of the net at reset, a
pull-up or active driver is needed.
5. Pin must NOT be pulled down during power-on reset. This pin may be pulled up,
driven high, or if there are any connected devices, left in tristate. If this pin is connected
to a device that pulls down during reset, an external pull-up is required to drive this pin to
a safe state during reset.
6. Recommend that a weak pull-up resistor (4.7 kΩ) be placed on this pin to the
respective power supply.
7. This pin is an open-drain signal.
8. Recommend that a weak pull-up resistor (1 kΩ) be placed on this pin to the respective
power supply.
9. This pin has a weak (~20 kΩ) internal pull-up P-FET that is always enabled.
10. This is a test signal for factory use only and must be pulled up (100 Ω to 1 kΩ) to the
respective power supply for normal operation.
11. This pin requires a 200 Ω pull-up to respective power supply.
12. Do not connect. This pin should be left floating.
13. These pins must be pulled up to 1.2 V through a 180 Ω ± 1% resistor for MDC and a
330 Ω ± 1% resistor for MDIO.
14. This pin requires an external 1 kΩ pull-down resistor to prevent PHY from seeing a
valid Transmit Enable before it is actively driven.
15. Must be pulled to ground (GND).
16. This pin requires a 698 Ω pull-up to respective power supply.
17. This pin should be tied to ground if the diode is not utilized for temperature
monitoring.
18. If used as an SDHC signal, pull up 10 kΩ to 100 kΩ to the respective I/O supply.
19. New board designs should leave a placeholder for a parallel series resistor and
capacitor filter to be used in very close proximity to the USB_IBAIS_REXT pin of NXP
QorIQ chips. When needed, this allows for flexibility in populating them, which helps
Pin assignments
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
42 NXP Semiconductors
avoid board-coupled noise to this pin. A 100 nF low-ESL SMD ceramic chip capacitor in
series with a 100 Ω SMD resistor performs the needed filtration with slight variations that
suit each board case.
Warning
See "Connection Recommendations" for additional details on
properly connecting these pins for specific applications.
3 Electrical characteristics
This section provides the AC and DC electrical specifications for the chip. The chip is
currently targeted to these specifications, some of which are independent of the I/O cell
but are included for a more complete reference. These are not purely I/O buffer design
specifications.
3.1 Overall DC electrical characteristics
This section describes the ratings, conditions, and other characteristics.
3.1.1 Absolute maximum ratings
This table provides the absolute maximum ratings.
Table 2. Absolute maximum ratings1
Characteristic Symbol Max Value Unit Note
s
Core and platform supply voltage VDD -0.3 to 1.1 V 2
PLL supply voltage (core, platform, DDR) AVDD_CGA1
AVDD_CGA2
AVDD_PLAT
AVDD_D1
-0.3 to 1.98 V —
PLL supply voltage (SerDes, filtered from XnVDD) AVDD_SDn_PLLn -0.3 to 1.48 V —
Fuse programming override supply PROG_SFP -0.3 to 1.98 V —
Thermal monitor unit supply TH_VDD -0.3 to 1.98 V —
eSHDC, MPIC, GPIO, system control and power management,
clocking, debug, IFC, DDRCLK supply, and JTAG I/O voltage
OVDD -0.3 to 1.98 V —
eSPI CVDD -0.3 to 2.75
-0.3 to 1.98
V —
DMA, DUART, I2C I/O voltage DVDD -0.3 to 2.75 V —
Table continues on the next page...
Electrical characteristics
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
NXP Semiconductors 43
Table 2. Absolute maximum ratings1 (continued)
Characteristic Symbol Max Value Unit Note
s
-0.3 to 1.98
DDR3 and DDR3L DRAM I/O voltage G1VDD -0.3 to 1.65
-0.3 to 1.45
V —
Main power supply for internal circuitry of SerDes and pad power
supply for SerDes receivers
SnVDD -0.3 to 1.1 V —
Pad power supply for SerDes transmitters XnVDD -0.3 to 1.45 V
Ethernet I/O, Ethernet management interface 1 (EMI1) 1588,
GPIO I/O voltage
LVDD -0.3 to 2.75
-0.3 to 1.98
V —
Ethernet management interface 2 (EMI2) I/O voltage — -0.3 to 1.32 V 4
USB PHY Transceiver supply voltage USB_HVDD -0.3 to 3.63 V —
USB_OVDD -0.3 to 1.98 V —
USB PHY Analog supply voltage USB_SVDD -0.3 to 1.1 V —
Low Power Security Monitor supply VDD_LP -0.3 to 1.1 V —
Input voltage DDR3 and DDR3L DRAM signals MVIN -0.3 to (GVDD + 0.3) V 5
DDR3 and DDR3L DRAM reference D1_MVREF -0.3 to (GVDD/2+
0.3)
V 6
Ethernet signals (except EMI2) LVIN -0.3 to (LVDD + 0.3) V 6, 7
eSHDC, MPIC, GPIO, system control and
power management, clocking, debug, IFC,
DDRCLK supply, and JTAG signals
OVIN -0.3 to (OVDD + 0.3) V 6, 8
eSPI CVIN -0.3 to (CVDD + 0.3) V 6, 8
DMA, DUART, I2C signals DVIN -0.3 to (DVDD + 0.3) V 8, 9
SerDes signals SVIN -0.4 to (SVDD + 0.3) V 6
USB PHY Transceiver signals USB_HVIN -0.3 to (USB_HVDD
+ 0.3)
V 6
USB_OVIN -0.3 to (USB_OVDD
+ 0.3)
V 6
Ethernet management interface 2 signals - -0.3 to (1.2 + 0.3) V —
Storage temperature range TSTG -55 to 150 °C —
Notes:
1. Functional operating conditions are given in Table 3. Absolute maximum ratings are stress ratings only, and functional
operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause permanent
damage to the device.
2. Supply voltage specified at the voltage sense pin. Voltage input pins should be regulated to provide specified voltage at the
sense pin.
4. Ethernet MII management interface 2 pins function as open drain I/Os. The interface shall conform to 1.2 V nominal
voltage levels.
5. Caution: MVIN must not exceed GVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during
power-on reset and power-down sequences.
6. (C, S,G,L,O,D)VIN, USBn_VIN_3P3, USBn_VIN_1P8 and D1_MVREF may overshoot/undershoot to a voltage and for a
maximum duration as shown in Figure 7.
Electrical characteristics
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
44 NXP Semiconductors
Table 2. Absolute maximum ratings1
Characteristic Symbol Max Value Unit Note
s
7. Caution: LVIN must not exceed LVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during
power-on reset and power-down sequences.
8. Caution: CVIN and OVIN must not exceed CVDD and OVDD by more than 0.3 V. This limit may be exceeded for a maximum
of 20 ms during power-on reset and power-down sequences.
9. Caution: DVIN must not exceed DVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during
power-on reset and power-down sequences.
3.1.2 Recommended operating conditions
This table provides the recommended operating conditions for this chip.
NOTE
The values shown are the recommended operating conditions
and proper device operation outside these conditions is not
guaranteed.
Table 3. Recommended operating conditions
Characteristic Symbol Recommended Value Unit Notes
Core and platform supply
voltage
At initial start-up VDD 1.025 ± 30 mV V 1, 2, 3,
7
During normal operation VID ± 30 mV V 1, 2, 3,
7
PLL supply voltage (core, platform, DDR) AVDD_CGA1
AVDD_CGA2
AVDD_PLAT
AVDD_D1
1.8 V ± 90 mV V 8
PLL supply voltage (SerDes, filtered from XnVDD) AVDD_SDn_PLLn
(n = 1 or 2)
1.35 V ± 67 mV V —
Fuse programming override supply PROG_SFP 1.80 V ± 90 mV V 4
Thermal monitor unit supply TH_VDD 1.8 V ± 90 mV V —
eSHDC, MPIC, GPIO, system control and power
management, clocking, debug, IFC, DDRCLK supply, and
JTAG I/O voltage
OVDD 1.8 V ± 90 mV V —
eSPI CVDD 2.5 V ± 125 mV
1.8 V ± 90 mV
V —
DMA, DUART, I2C I/O voltage DVDD 2.5 V ± 125 mV
1.8 V ± 90 mV
V —
DDR DRAM I/O voltage DDR3 G1VDD 1.5 V ± 75 mV V —
DDR3L 1.35 V ± 67 mV
Table continues on the next page...
Electrical characteristics
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
NXP Semiconductors 45
Table 3. Recommended operating conditions (continued)
Characteristic Symbol Recommended Value Unit Notes
Main power supply for internal circuitry of SerDes and pad
power supply for SerDes receivers
SnVDD (n = 1 or 2) 1.0 V + 50 mV
1.0 V - 30 mV
V —
Pad power supply for SerDes transmitters XnVDD (n= 1 or 2) 1.35 V ± 67 mV V —
Ethernet , Ethernet management interface 1 (EMI1), 1588,
GPIO I/O voltage
LVDD 2.5 V ± 125 mV
1.8 V ± 90 mV
V 5
Ethernet management interface 2 (EMI2) I/O voltage — 1.2 V ± 60 mV V —
USB PHY Transceiver supply voltage USB_HVDD 3.3 V ± 165 mV V —
USB_OVDD 1.8 V ± 90 mV V —
USB PHY Analog supply
voltage
At initial start-up USB_SVDD 1.025 ± 30 mV V 1, 3
During normal operation VID ± 30 mV
Low Power Security Monitor supply VDD_LP 1.0 V ± 50 mV V —
Input voltage DDR3 and DDR3L DRAM signals MVIN GND to GVDD V —
DDR3 and DDR3L DRAM
reference
D1_MVREF GVDD/2 ± 1% V —
Ethernet signals (except EMI2),
USB, 1588, GPIO signals
LVIN GND to LVDD V —
eSHDC, MPIC, GPIO, system
control and power management,
clocking, debug, IFC, DDRCLK
supply, and JTAG signals
OVIN GND to OVDD V —
eSPI CVIN GND to CVDD V —
DMA, DUART, I2C signals DVIN GND to DVDD V —
SerDes signals SVIN GND to SVDD V —
USB PHY Transceiver signals USB_HVIN GND to USB_HVDD V —
USB_OVIN GND to USB_OVDD V —
Ethernet management interface 2
(EMI2) signals
— GND to 1.2V V 6
Operating temperature
range
Normal operation TA,
TJ
TA = 0 (min) to
TJ = 105(max)
°C —
Extended Temperature TA,
TJ
TA = -40 (min) to
TJ = 105(max)
°C —
Secure boot fuse programming TA,
TJ
TA = 0 (min) to
TJ = 70 (max)
°C 4
Notes:
1. See Voltage ID (VID) controllable supply and Core and platform supply voltage filtering for additional information.
2. Supply voltage specified at the voltage sense pin. Voltage input pins should be regulated to provide specified voltage at the
sense pin.
3. Operation at 1.1 V is allowable for up to 25 ms at initial power on.
4. PROG_SFP must be supplied 1.80 V and the chip must operate in the specified fuse programming temperature range (0 -
70°C) only during secure boot fuse programming. For all other operating conditions, PROG_SFP must be tied to GND,
subject to the power sequencing constraints shown in Power sequencing.
Electrical characteristics
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
46 NXP Semiconductors
Table 3. Recommended operating conditions
Characteristic Symbol Recommended Value Unit Notes
5. Selecting RGMII limits to LVDD = 2.5 V.
6. Ethernet MII management interface 2 pins function as open drain I/Os. The interface conforms to 1.2 V nominal voltage
levels.
7. Voltage ID (VID) operating range is between 0.975 to 1.025V. Regulator selection should be based on Vout range of at
least 0.9 to 1.1 V, with resolution of 12.5 mV or better.
8. Keep the filter close to the pin. Voltage and tolerance for AVDD is defined at the input of the PLL supply filter and not the
pin of AVDD.
This figure shows the undershoot and overshoot voltages at the interfaces of the chip.
VIH
Nominal C/D/S/G/L/OVDD + 20%
VIL
GND
GND - 0.3 V
GND - 0.7 V
Not to exceed 10% of tCLOCK1
Note:
For I2C ODVDD, tCLOCK references SYSCLK.
C/D/S/G/L/OVDD + 5%
C/D/S/G/L/OVDD
tCLOCK refers to the clock period associated with the respective interface:
For DDR GVDD, tCLOCK references Dn_MCLK.
For eSPI OCVDD, tCLOCK references SPI_CLK.
For JTAG OVDD, tCLOCK references TCK.
For SerDes SVDD, tCLOCK references SD_REF_CLK.
For Ethernet LVDD, tCLOCK references ECn_GTX_CLK125.
Figure 7. Overshoot/Undershoot voltage for CVDD/GVDD/LVDD/OVDD/SVDD/DVDD
The core and platform voltages must always be provided at nominal VID. See Table 3 for
actual recommended core voltage. Voltage to the processor interface I/Os are provided
through separate sets of supply pins and must be provided at the voltages shown in Table
3. The input voltage threshold scales with respect to the associated I/O supply voltage.
Electrical characteristics
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
NXP Semiconductors 47
DVDD, OVDD and LVDD based receivers are simple CMOS I/O circuits and satisfy
appropriate LVCMOS type specifications. The DDR SDRAM interface uses differential
receivers referenced by the externally supplied D1_MVREF signal (nominally set to
GVDD/2) as is appropriate for the SSTL_1.35/SSTL_1.5 electrical signaling standard.
The DDR DQS receivers cannot be operated in single-ended fashion. The complement
signal must be properly driven and cannot be grounded.
3.1.3 Output driver characteristics
This chip provides information on the characteristics of the output driver strengths.
NOTE
These values are preliminary estimates.
Table 4. Output drive capability
Driver type Output impedance (Ω) Supply Voltage Notes
Minimu
m2Typical Maxim
um3
DDR3 signal — 18 (full-strength mode)
27 (half-strength mode)
— G1VDD = 1.5 V 1
DDR3L signal — 18 (full-strength mode)
27 (half-strength mode)
— G1VDD = 1.35 V 1
Ethernet signals 45 — 90 L1VDD / LVDD =
3.3 V
—
40 — 90 L1VDD / LVDD =
2.5 V
40 — 75 L1VDD / LVDD =
1.8 V
MPIC, GPIO, system control and power
management, clocking, debug, IFC, DDRCLK
supply, and JTAG I/O voltage
23 — 51 OVDD, O1VDD =
1.8 V
—
DUART, DMA, MPIC, QE, TDM, I2C, DIU 45 — 90 DVDD = 3.3 V —
40 — 90 DVDD = 2.5 V
40 — 75 DVDD = 1.8 V
eSPI, SDHC_WP, SDHC_CD 45 — 90 CVDD = 3.3 V —
40 — 75 CVDD = 1.8 V
eSDHC 45 — 90 EVDD = 3.3 V —
40 — 75 EVDD = 1.8 V
Notes:
1. The drive strength of the DDR3 or DDR3L interface in half-strength mode is at Tj = 105 °C and at G1VDD (min).
2. Estimated number based on best case processed device.
3. Estimated number based on worst case processed device.
Electrical characteristics
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
48 NXP Semiconductors
3.2 Power sequencing
The chip requires that its power rails be applied in a specific sequence in order to ensure
proper device operation. For power up, these requirements are as follows:
1. Bring up VDD, SnVDD, USB_SVDD, VDD_LP, USB_HVDD, LVDD, DVDD, CVDD,
USB_OVDD, OVDD, TH_VDD, AVDD (cores, platform, DDR), G1VDD, XnVDD, and
AVDD_ SDn_PLLn. Drive PROG_SFP = GND.
• PORESET_B input must be driven asserted and held during this step.
Power supplies in step 1 have no ordering requirement with respect to one another
except for the USB power supplies per the following note.
NOTE
a. USB_SVDD supply must ramp before or after the
USB_HVDD and USB_OVDD supplies have ramped.
The supply set that ramp first must reach 90% of its
final value before a supply from the other set can be
ramped up.
b. USB_HVDD and USB_OVDD supplies among
themselves are sequence independent.
c. USB_HVDD rise time (10% to 90%) has a minimum of
100 us.
2. Negate PORESET_B input as long as the required assertion/hold time has been met
per Table 19.
3. For secure boot fuse programming, use the following steps:
a. After negation of PORESET_B, drive PROG_SFP = 1.80 V after a required
minimum delay per Table 5.
b. After fuse programming is completed, it is required to return PROG_SFP =
GND before the system is power cycled (PORESET_B assertion) or powered
down (VDD ramp down) per the required timing specified in Table 5. See
Security fuse processor, for additional details.
Warning
No activity other than that required for secure boot fuse
programming is permitted while PROG_SFP is driven
to any voltage above GND, including the reading of the
fuse block. The reading of the fuse block may only
occur while PROG_SFP = GND.
Electrical characteristics
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
NXP Semiconductors 49
From a system standpoint, if any of the I/O power
supplies ramp prior to the VDD supplies, there will be a
brief period as the VDD powers up that the I/Os
associated with that I/O supply may go from being tri-
stated to an indeterminate state (either driven to a logic
one or zero) and extra current may be drawn by the
device.
Only 300,000 POR cycles are permitted per lifetime of
a device. Note that this value is based on design
estimates and is preliminary.
If using Trust Architecture Security Monitor battery-backed features, prior to VDD
ramping up to the 0.5 V level, ensure that OVDD is ramped to the recommended
operational voltage and SYSCLK is running. The clock should have a minimum
frequency of 800 Hz and a maximum frequency no greater than the supported system
clock frequency for the device.
All supplies must be at their stable values within 400 ms.
This figure provides the PROG_SFP timing diagram.
PROG_SFP
VDD
PORESET_B
90% OVDD
Fuse programming
tPROG_SFP_PROG
NOTE: PROG_SFP must be stable at 1.80 V prior to initiating fuse programming.
tPROG_SFP_DELAY
10% PROG_SFP
tPROG_SFP_RST
tPROG_SFP_VDD
10% PROG_SFP
90% VDD
90% OVDD
Figure 8. PROG_SFP timing diagram
This table provides information on the power-down and power-up sequence parameters
for PROG_SFP.
Table 5. PROG_SFP timing 5
Driver type Min Max Unit Notes
tPROG_SFP_DELAY 100 — SYSCLKs 1
Table continues on the next page...
Electrical characteristics
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
50 NXP Semiconductors
Table 5. PROG_SFP timing 5 (continued)
Driver type Min Max Unit Notes
tPROG_SFP_PROG 0 — μs 2
tPROG_SFP_VDD 0 — μs 3
tPROG_SFP_RST 0 — μs 4
Notes:
1. Delay required from the deassertion of PORESET_B to driving PROG_SFP ramp up. Delay measured from PORESET_B
deassertion at 90% OVDD to 10% PROG_SFP ramp up.
2. Delay required from fuse programming finished to PROG_SFP ramp down start. Fuse programming must complete while
PROG_SFP is stable at 1.80 V. No activity other than that required for secure boot fuse programming is permitted while
PROG_SFP driven to any voltage above GND, including the reading of the fuse block. The reading of the fuse block may
only occur while PROG_SFP = GND. After fuse programming is completed, it is required to return PROG_SFP = GND.
3. Delay required from PROG_SFP ramp down complete to VDD ramp down start. PROG_SFP must be grounded to
minimum 10% PROG_SFP before VDD is at 90% VDD.
4. Delay required from PROG_SFP ramp down complete to PORESET_B assertion. PROG_SFP must be grounded to
minimum 10% PROG_SFP before PORESET_B assertion reaches 90% OVDD.
5. Only two secure boot fuse programming events are permitted per lifetime of a device.
3.3 Power-down requirements
The power-down cycle must complete such that power supply values are below 0.4 V
before a new power-up cycle can be started.
If performing secure boot fuse programming per Power sequencing, it is required that
PROG_SFP = GND before the system is power cycled (PORESET_B assertion) or
powered down (VDD ramp down) per the required timing specified in Table 5.
NOTE
All input signals, including I/Os that are configured as inputs,
driven into the chip need to monotonically increase/decrease
through entire rise/fall durations.
3.4 Power characteristics
This table shows the power dissipations of the VDD and SnVDD supply for various
operating platform clock frequencies versus the core and DDR clock frequencies when
Altivec power is gated off. See the e6500 core reference manual, section 8.6.1, "Altivec
power down—software controlled entry" for details on how to place Altivec in low
power state.
Electrical characteristics
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
NXP Semiconductors 51
Table 6. T2080 power dissipation with Altivec power-gated off1
Power
mode
Core freq
(MHz)
Plat
freq
(MHz)
DDR
data
rate
(MT/s
)
FMan
freq
(MHz)
VDD8
(V)
SnVD
D
(V)
Junction
temperature
(ºC)
Core and
platform
power1
(W)
VDD
power
(W)
SnVDD
power
(W)
Notes
Typical 1800
(low-power
version)
600 2133 700 VID 1.0 65 12.9 11.9 1.0 2, 3, 9
Thermal 105 18.9 17.9 1.0 4, 5, 9
Maximum 21.1 20.1 1.0 5, 6, 7,
9
Typical 1800
(standard
version)
600 1867 700 VID 1.0 65 13.0 12.0 1.0 2, 3
Thermal 105 21.1 20.1 1.0 4, 5
Maximum 23.3 22.3 1.0 5, 6, 7
Typical 1533
(low-power
version)
600 2133 700 VID 1.0 65 11.9 10.9 1.0 2, 3, 9
Thermal 105 15.4 14.4 1.0 4, 5, 9
Maximum 17.3 16.3 1.0 5, 6, 7,
9
Typical 1533
(standard
version)
600 1867 700 VID 1.0 65 11.9 10.9 1.0 2, 3
Thermal 105 17.2 16.2 1.0 4, 5
Maximum 19.1 18.1 1.0 5, 6, 7
Typical 1200
(low-power
version)
533 1600 600 VID 1.0 65 10.4 9.4 1.0 2, 3, 9
Thermal 105 12.6 11.6 1.0 4, 5, 9
Maximum 14.1 13.1 1.0 5, 6, 7,
9
Typical 1200
(standard
version)
533 1600 600 VID 1.0 65 10.4 9.4 1.0 2, 3
Thermal 105 13.9 12.9 1.0 4, 5
Maximum 15.4 14.4 1.0 5, 6, 7
Notes:
1. Combined power of VDD and SnVDD with platform at power-on reset default state, the DDR controller and all SerDes banks
active. Does not include I/O power and Altivec is power-gated off.
2. Typical power assumes Dhrystone running with activity factor of 70% (on all cores) and is executing DMA on the platform
with 100% activity factor.
3. Typical power based on nominal, processed distribution for this device.
4. Thermal power assumes Dhrystone running with activity factor of 70% (on all cores) and executing DMA on the platform at
100% activity factor.
5. Thermal and maximum power are based on worst-case process distribution for this device.
6. Maximum power assumes Dhrystone running with activity factor at 100% (on all cores) and is executing DMA on the
platform at 115% activity factor.
7. Maximum power provided for power supply design sizing.
8. Voltage ID (VID) operating range is between 0.975 V to 1.025 V.
9. The difference between low-power and standard is shown in the product part number. The low-power version part numbers
end in "T1B", "P1B", and "QLB".
Electrical characteristics
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
52 NXP Semiconductors
This table shows the power dissipation of the VDD and SnVDD supply for various
operating platform clock frequencies versus the core and DDR clock frequencies when
Altivec power is gated on. See the e6500 core reference manual, section 8.6.4, "Altivec
power up—software-controlled entry" for details on how to enable Altivec.
Table 7. T2080 power dissipation with Altivec power-gated on1
Power
mode
Core freq
(MHz)
Plat
freq
(MHz)
DDR
data
rate
(MT/s
)
FMan
freq
(MHz)
VDD8
(V)
SnVD
D
Junction
temperature
(ºC)
Core and
platform
power1
(W)
VDD
power
(W)
SnVDD Notes
Typical 1800
(low-power
version)
600 2133 700 VID 1.0 65 13.8 12.8 1.0 2, 3, 9
Thermal 105 20.2 19.2 1.0 4, 5, 9
Maximum 22.3 21.3 1.0 5, 6, 7,
9
Typical 1800
(standard
version)
600 1867 700 VID 1.0 65 13.9 12.9 1.0 2, 3
Thermal 105 22.4 21.4 1.0 4, 5
Maximum 24.5 23.5 1.0 5, 6, 7
Typical 1533
(low-power
version)
600 2133 700 VID 1.0 65 12.8 11.8 1.0 2, 3, 9
Thermal 105 16.3 15.3 1.0 4, 5, 9
Maximum 18.1 17.1 1.0 5, 6, 7,
9
Typical 1533
(standard
version)
600 1867 700 VID 1.0 65 12.7 11.7 1.0 2, 3
Thermal 105 18.2 17.2 1.0 4, 5
Maximum 20.0 19.0 1.0 5, 6, 7
Typical 1200
(low-power
version)
533 1600 600 VID 1.0 65 11.0 10.0 1.0 2, 3, 9
Thermal 105 13.3 12.3 1.0 4, 5, 9
Maximum 16.1 15.1 1.0 5, 6, 7,
9
Typical 1200
(standard
version)
533 1600 600 VID 1.0 65 11.0 10.0 1.0 2, 3
Thermal 105 14.7 13.7 1.0 4, 5
Maximum 16.1 15.1 1.0 5, 6, 7
Notes:
1. Combined power of VDD and SnVDD with platform at power-on reset default state, the DDR controller and all SerDes banks
active. Does not include I/O power and Altivec is power-gated off.
2. Typical power assumes Dhrystone running with activity factor of 70% (on all cores) and is executing DMA on the platform
with 100% activity factor.
3. Typical power based on nominal, processed device.
4. Thermal power assumes Dhrystone running with activity factor of 70% (on all cores) and executing DMA on the platform at
100% activity factor.
5. Thermal and maximum power are based on worst-case processed device.
6. Maximum power assumes Dhrystone running with work power activity factor at 100% (on all cores) and is executing DMA
on the platform at 115% activity factor.
7. Maximum power provided for power supply design sizing.
Electrical characteristics
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
NXP Semiconductors 53
Table 7. T2080 power dissipation with Altivec power-gated on1
Power
mode
Core freq
(MHz)
Plat
freq
(MHz)
DDR
data
rate
(MT/s
)
FMan
freq
(MHz)
VDD8
(V)
SnVD
D
Junction
temperature
(ºC)
Core and
platform
power1
(W)
VDD
power
(W)
SnVDD Notes
8. Voltage ID (VID) operating range is between 0.975 V to 1.025 V.
9. The difference between low-power and standard is shown in the product part number. The low-power version part numbers
end in "T1B", "P1B", and "QLB".
This table provides all the estimated I/O power supply values based on preliminary
measurements.
Table 8. T2080 I/O power dissipation
I/O Power supply Parameter Typical (mW) Maximum (mW) Notes
LVCMOS OVDD 1.8 V — 50 60 1, 3, 4, 6
LVCMOS CVDD 1.8 V — 40 70
LVCMOS CVDD 2.5 V — 50 80
LVCMOS LVDD 1.8 V — 230 360
LVCMOS LVDD 2.5 V — 310 440
LVCMOS DVDD 1.8 V — 50 90
LVCMOS DVDD 2.5 V — 70 130
DDR I/O GVDD 1.5 V 2133 MT/s 1144 2200 1, 2, 5, 6
DDR I/O GVDD 1.35 V 1867 MT/s 840 1610
DDR I/O GVDD 1.5 V 1867 MT/s 1030 1990
DDR I/O GVDD 1.35 V 1600 MT/s 720 1380
DDR I/O GVDD 1.5 V 1600 MT/s 890 1700
USB_PHY USB_OVDD 1.8 V — 40 60 1, 6
USB_PHY USB_HVDD 3.3 V — 100 110
USB_SVDD USB_SVDD — 7 7
PLL core and
system
AVDD_CGA*,
AVDD_PLAT
— 20 20 1, 6
PLL DDR AVDD_D1 — 30 40
PLL LYNX AVDD_SRDS* — 50 50
SerDes, 1.35 V XVDD SGMII 1x 1.25 G-baud 50 60 1, 6, 7
SerDes, 1.35 V XVDD 2x 1.25 G-baud 70 90
SerDes, 1.35 V XVDD 4x 1.25 G-baud 130 140
SerDes, 1.35 V XVDD 8x 1.25 G-baud 230 240
SerDes, 1.35 V XVDD 1x 3.125 G-baud 50 60
SerDes, 1.35 V XVDD 2x 3.125 G-baud 80 90
SerDes, 1.35 V XVDD 4x 3.125 G-baud 140 150
SerDes, 1.35 V XVDD SATA 1x 3 G-baud 50 60
Table continues on the next page...
Electrical characteristics
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
54 NXP Semiconductors
Table 8. T2080 I/O power dissipation (continued)
I/O Power supply Parameter Typical (mW) Maximum (mW) Notes
SerDes, 1.35 V XVDD 2x 3 G-baud 70 80
SerDes, 1.35 V XVDD SRIO 1x 2.5 G-baud 50 60
SerDes, 1.35 V XVDD 2x 2.5 G-baud 80 90
SerDes, 1.35 V XVDD 4x 2.5 G-baud 140 150
SerDes, 1.35 V XVDD 1x 3.125 G-baud 50 60
SerDes, 1.35 V XVDD 2x 3.125 G-baud 80 90
SerDes, 1.35 V XVDD 4x 3.125 G-baud 140 150
SerDes, 1.35 V XVDD 1x 5 G-baud 50 70
SerDes, 1.35 V XVDD 2x 5 G-baud 90 100
SerDes, 1.35 V XVDD 4x 5 G-baud 150 160
SerDes, 1.35 V XVDD PEX2.0 1x 5 G-baud 50 70
SerDes, 1.35 V XVDD 2x 5 G-baud 90 100
SerDes, 1.35 V XVDD 4x 5 G-baud 150 160
SerDes, 1.35 V XVDD 8x 5 G-baud 280 290
SerDes, 1.35 V XVDD PEX3.0 1x 8 G-baud 60 70
SerDes, 1.35 V XVDD 2x 8 G-baud 100 110
SerDes, 1.35 V XVDD 4x 8 G-baud 170 190
SerDes, 1.35 V XVDD XFI 1x 10 G-baud 60 70
SerDes, 1.35 V XVDD 2x 10 G-baud 100 110
SerDes, 1.35 V XVDD 4x 10 G-baud 170 190
Fuse
Programming
Override
PROG_SFG — — 173 1, 8
Thermal Monitor
Unit
TH_VDD — — 18 1
Notes:
1. The maximum values are dependent on actual use case such as what application, external components used,
environmental conditions such as temperature voltage and frequency. This is not intended to be the maximum guaranteed
power. Expect different results depending on the use case. The maximum values are estimated and they are based on
simulations at 105 °C junction temperature.
2. Typical DDR power numbers are based on one 2-rank DIMM with 40% utilization.
3. Assuming 15 pF total capacitance load.
4. GPIOs are supported on 1.8 V and 2.5 V rails as specified in the hardware specification.
5. Maximum DDR power numbers are based on one 2-rank DIMM with 100% utilization.
6. The typical values are estimates and based on simulations at nominal recommended voltage for the I/O power supply and
assuming at 65° C junction temperature.
7. The total power numbers of XVDD is dependent on customer application use case. This table lists all the SerDes
configurations possible for the device. To get the XVDD power numbers, the user should add the combined lanes to match to
the total SerDes Lanes used, not simply multiply the power numbers by the number of lanes.
8. The max power requirement is during programming. No active power beyond leakage levels should be drawn and the
supply must be grounded when not programming.
Electrical characteristics
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
NXP Semiconductors 55
This table shows the preliminary power dissipation on the VDD_LP supply for the T2080
at allowable voltage levels.
Table 9. VDD_LP Power Dissipation
Supply Maximum Unit Notes
VDD_LP (T2080 on, 65C) 1.5 mW 1
VDD_LP (T2080 off, 65C) 360 uW 2
VDD_LP (T2080 off, 40C) 132 uW 2
Notes:
1. VDD_LP = 1.0 V, TJ = 65 °C
2. When T2080 is off, VDD_LP may be supplied by battery power to retain the Zeroizable Master Key and other Trust
Architecture state. Board should implement a PMIC which switches VDD_LP to battery when SoC powered down. See T2080
Reference Manual Trust Architecture chapter for more information.
Table 10. T2080 Rev 1.1 single core/single cluster low-power mode power savings, 1.0 V
105°C1,2,3
Mode Core
Frequency
= 1.8 GHz
Core
Frequency
= 1.533
GHz
Core
Frequency
= 1.2 GHz
Units Comments Notes
PH10 0.96 0.82 0.64 Watts Savings realized moving from PH00 to PH10
state, single core
1, 2, 4
PH15 0.27 0.23 0.19 Watts Savings realized moving from PH10 to PH15
state, single core
1, 4, 5
PH20 0.37 0.35 0.34 Watts Savings realized moving from PH15 to PH20
state, single core
1, 4
PCL10 0.95 0.91 0.73 Watts Savings realized moving from PH20 to PCL10
state, single cluster
1
LPM20 0.90 0.82 0.72 Watts Savings realized moving from PCL10 to
LPM20 state
1
LPM40 0.60 0.49 0.35 Watts Savings realized moving from LPM20 to
LPM40 state, single cluster
1
Notes:
1. Power for VDD only.
2. Typical power assumes Dhrystone running (PH00 state) with 70% activity factor.
3. Typical power based on nominal process distribution for this device.
4. PH10, PH15, PH20 power savings with one core. Maximum savings would be n times, where n is the number of used
cores.
5. Require both threads of the core to enter the same low-power mode.
Electrical characteristics
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
56 NXP Semiconductors
3.5 Power-on ramp rate
This section describes the AC electrical specifications for the power-on ramp rate
requirements. Controlling the maximum power-on ramp rate is required to avoid excess
in-rush current.
This table provides the power supply ramp rate specifications.
Table 11. Power supply ramp rate
Parameter Min Max Unit Notes
Required ramp rate for all voltage supplies (including OVDD/DVDD/ G1VDD/
SnVDD/XnVDD/LVDD, all core and platform VDD supplies, D1_MVREF, all AVDD, and
CVDD supplies.)
— 25 V/ms 1, 2
Required ramp rate for PROG_SFP — 25 V/ms 1, 2
Notes:
1. Ramp rate is specified as a linear ramp from 10 to 90%. If non-linear (for example, exponential), the maximum rate of
change from 200 to 500 mV is the most critical as this range might falsely trigger the ESD circuitry.
2. Over full recommended operating temperature range (see Table 3).
3.6 Input clocks
3.6.1 System clock (SYSCLK) timing specifications
This section provides the system clock DC and AC timing specifications.
3.6.1.1 System clock DC timing specifications
This table provides the system clock (SYSCLK) DC specifications.
Table 12. SYSCLK DC electrical characteristics3
Parameter Symbol Min Typical Max Unit Notes
Input high voltage VIH 1.25 — — V 1
Input low voltage VIL — — 0.6 V 1
Input capacitance CIN — 7 12 pF —
Input current (OVIN= 0 V or OVIN =
OVDD)
IIN -50 — +50 μA 2
Note:
1. The min VILand max VIH values are based on the respective min and max OVIN values found in Table 3.
2. The symbol OVIN, in this case, represents the OVIN symbol referenced in Recommended operating conditions.
3. At recommended operating conditions with OVDD = 1.8 V, see Table 3.
Electrical characteristics
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
NXP Semiconductors 57
3.6.1.2 System clock AC timing specifications
This table provides the system clock (SYSCLK) AC timing specifications.
Table 13. SYSCLK AC timing specifications5
Parameter/condition Symbol Min Typ Max Unit Notes
SYSCLK frequency fSYSCLK 66 — 133.3 MHz 1, 2
SYSCLK cycle time tSYSCLK 7.5 — 15 ns 1, 2
SYSCLK duty cycle tKHK / tSYSCLK 40 — 60 % 2
SYSCLK slew rate — 1 — 4 V/ns 3
SYSCLK peak period jitter — — — ± 150 ps —
SYSCLK jitter phase noise at -56 dBc — — — 500 KHz 4
AC Input Swing Limits at 1.8 V OVDD ΔVAC 0.6 x OVDD — 1 x OVDD V 6
Notes:
1. Caution: The relevant clock ratio settings must be chosen such that the resulting SYSCLK frequency do not exceed their
respective maximum or minimum operating frequencies.
2. Measured at the rising edge and/or the falling edge at OVDD/2.
3. Slew rate as measured from 0.35 x OVDD to 0.65 x OVDD.
4. Phase noise is calculated as FFT of TIE jitter.
5. At recommended operating conditions with OVDD = 1.8V, see Table 3.
6. AC swing measured relative to half OVDD or VIH and VIL have equal absolute offset from OVDD/2, So, Swing = (VIH-VIL)/
OVDD and ΔVAC = Swing x OVDD.
3.6.2 Spread-spectrum sources
Spread-spectrum clock sources are an increasingly popular way to control
electromagnetic interference emissions (EMI) by spreading the emitted noise to a wider
spectrum and reducing the peak noise magnitude in order to meet industry and
government requirements. These clock sources intentionally add long-term jitter to
diffuse the EMI spectral content. The jitter specification given in this table considers
short-term (cycle-to-cycle) jitter only. The clock generator's cycle-to-cycle output jitter
should meet the chip's input cycle-to-cycle jitter requirement. Frequency modulation and
spread are separate concerns; the chip is compatible with spread-spectrum sources if the
recommendations listed in this table are observed.
Table 14. Spread-spectrum clock source recommendations1
Parameter Min Max Unit Notes
Frequency modulation — 60 kHz —
Frequency spread — 1.0 % 2, 3
Table continues on the next page...
Electrical characteristics
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
58 NXP Semiconductors
Table 14. Spread-spectrum clock source recommendations1 (continued)
Parameter Min Max Unit Notes
Notes:
1. At recommended operating conditions with OVDD = 1.8 V, see Table 3.
2. SYSCLK frequencies that result from frequency spreading and the resulting core frequency must meet the minimum and
maximum specifications given in Table 13.
3. Maximum spread-spectrum frequency may not result in exceeding any maximum operating frequency of the device.
CAUTION
The processor's minimum and maximum SYSCLK and core/
platform/DDR frequencies must not be exceeded regardless of
the type of clock source. Therefore, systems in which the
processor is operated at its maximum rated core/platform/DDR
frequency should avoid violating the stated limits by using
down-spreading only.
3.6.3 Real-time clock timing
The real-time clock timing (RTC) input is sampled by the platform clock. The output of
the sampling latch is then used as an input to the counters of the MPIC and the time base
unit of the core; there is no need for jitter specification. The minimum period of the RTC
signal should be greater than or equal to 16x the period of the platform clock with a 50%
duty cycle. There is no minimum RTC frequency; RTC may be grounded if not needed.
3.6.4 Gigabit Ethernet reference clock timing
This table provides the Ethernet gigabit reference clock DC specifications.
Table 15. ECn_GTX_CLK125 DC electrical characteristics1
Parameter Symbol Min Typical Max Unit Notes
Input high
voltage
VIH 1.7 — — V 2
Input low
voltage
VIL — — 0.7 V 2
Input
capacitance
CIN — — 6 pF —
Input current
(LVIN = 0 V or
LVIN = LVDD)
IIN — — ± 50 μA 3
Notes:
Electrical characteristics
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
NXP Semiconductors 59
Table 15. ECn_GTX_CLK125 DC electrical characteristics1
Parameter Symbol Min Typical Max Unit Notes
1. At recommended operating conditions with LVDD = 2.5 V.
2. The min VIL and max VIH values are based on the respective min and max LVIN values found in Table 3.
3. The symbol LVIN, in this case, represents the LVIN symbol referenced in Recommended operating conditions.
This table provides the Ethernet gigabit reference clocks AC timing specifications.
Table 16. ECn_GTX_CLK125 AC timing specifications1
Parameter/Condition Symbol Min Typical Max Unit Notes
ECn_GTX_CLK125 frequency tG125 125 - 100 ppm 125 125 + 100 ppm MHz —
ECn_GTX_CLK125 cycle time tG125 — 8 — ns —
ECn_GTX_CLK125 rise and fall time
LVDD = 2.5 V
tG125R/tG125F — — 0.75 ns 2
ECn_GTX_CLK125 duty cycle
1000Base-T for RGMII
tG125H/tG125 47 — 53 % 3
ECn_GTX_CLK125 jitter — — — ± 150 ps 3
Notes:
1. At recommended operating conditions with LVDD = 2.5 V ± 125 mV.
2. Rise and fall times for ECn_GTX_CLK125 are measured from 0.5 and 2.0 V for LVDD = 2.5 V.
3. ECn_GTX_CLK125 is used to generate the GTX clock for the Ethernet transmitter with 2% degradation. The
ECn_GTX_CLK125 duty cycle can be loosened from 47%/53% as long as the PHY device can tolerate the duty cycle
generated by the GTX_CLK. See RGMII AC timing specifications for duty cycle for 10Base-T and 100Base-T reference clock.
3.6.5 DDR clock timing
This section provides the DDR clock DC and AC timing specifications. DDR3L
maximum supported data rate is 1866 MT/s.
3.6.5.1 DDR clock DC timing specifications
This table provides the DDR clock (DDRCLK) DC specifications.
Table 17. DDRCLK DC electrical characteristics3
Parameter Symbol Min Typical Max Unit Notes
Input high voltage VIH 1.25 — — V 1
Input low voltage VIL — — 0.6 V 1
Input capacitance CIN — — 12 pF —
Table continues on the next page...
Electrical characteristics
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
60 NXP Semiconductors
Table 17. DDRCLK DC electrical characteristics3 (continued)
Parameter Symbol Min Typical Max Unit Notes
Input current (OVIN= 0 V or OVIN =
OVDD)
IIN -50 — + 50 μA 2
Note:
1. The min VILand max VIH values are based on the respective min and max OVIN values found in Table 3.
2. The symbol OVIN, in this case, represents the OVIN symbol referenced in Recommended operating conditions.
3. At recommended operating conditions with OVDD = 1.8 V, see Table 3.
3.6.5.2 DDR clock AC timing specifications
This table provides the DDR clock (DDRCLK) AC timing specifications.
Table 18. DDRCLK AC timing specifications5
Parameter/Condition Symbol Min Typ Max Unit Notes
DDRCLK frequency fDDRCLK 66.7 — 133.3 MHz 1, 2
DDRCLK cycle time tDDRCLK 5 — 15 ns 1, 2
DDRCLK duty cycle tKHK / tDDRCLK 40 — 60 % 2
DDRCLK slew rate — 1 — 4 V/ns 3
DDRCLK peak period jitter — — — ± 150 ps —
DDRCLK jitter phase noise at -56 dBc — — — 500 KHz 4
AC Input Swing Limits at 1.8 V OVDD ΔVAC 0.35 x OVDD — 0.65 x OVDD V —
Notes:
1. Caution: The relevant clock ratio settings must be chosen such that the resulting DDRCLK frequency do not exceed their
respective maximum or minimum operating frequencies.
2. Measured at the rising edge and/or the falling edge at OVDD/2.
3. Slew rate as measured from 0.35 x OVDD to 0.65 x OVDD.
4. Phase noise is calculated as FFT of TIE jitter.
5. At recommended operating conditions with OVDD = 1.8V, see Table 3.
3.6.6 Other input clocks
A description of the overall clocking of this device is available in the chip reference
manual in the form of a clock subsystem block diagram. For information about the input
clock requirements of functional modules sourced external of the chip, such as SerDes,
Ethernet management, eSDHC, IFC, see the specific interface section.
Electrical characteristics
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
NXP Semiconductors 61
3.7 RESET initialization
This section describes the AC electrical specifications for the RESET initialization timing
requirements. This table describes the AC electrical specifications for the RESET
initialization timing.
Table 19. RESET Initialization timing specifications
Parameter/Condition Min Max Unit Notes
Required assertion time of PORESET_B 1 — ms 1
Required input assertion time of HRESET_B 32 — SYSCLKs 2, 3
Maximum rise/fall time of HRESET_B — 10 SYSCLK 4
Maximum rise/fall time of PORESET_B — 1 SYSCLK 4
PLL input setup time with stable SYSCLK before HRESET_B negation 100 — μs —
Input setup time for POR configs with respect to negation of
PORESET_B
4 — SYSCLKs 2
Input hold time for all POR configs with respect to negation of
PORESET_B
2 — SYSCLKs 2
Maximum valid-to-high impedance time for actively driven POR
configs with respect to negation of PORESET_B
— 5 SYSCLKs 2
Notes:
1. PORESET_B must be driven asserted before the core and platform power supplies are powered up.
2. SYSCLK is the primary clock input for the chip.
3. The device asserts HRESET_B as an output when PORESET_B is asserted to initiate the power-on reset process. The
device releases HRESET_B sometime after PORESET_B is deasserted. The exact sequencing of HRESET_B deassertion is
documented in section "Power-On Reset Sequence" in the chip reference manual.
4. System/board must be designed to ensure the input requirement to the device is achieved. Proper device operation is
guaranteed for inputs meeting this requirement by design, simulation, characterization, or functional testing.
3.8 DDR3 and DDR3L SDRAM controller
This section describes the DC and AC electrical specifications for the DDR3 and DDR3L
SDRAM controller interface. Note that the required GVDD(typ) voltage is 1.5 V when
interfacing to DDR3 SDRAM and the GVDD(typ) voltage is 1.35 V when interfacing to
DDR3L SDRAM.
NOTE
When operating at a DDR data rate greater than or equal to
1866 MT/s, only one dual-ranked module per memory
controller is supported. DDR3L is not supported at a DDR data
rate of 2133 MT/s.
Electrical characteristics
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
62 NXP Semiconductors
3.8.1 DDR3 and DDR3L SDRAM interface DC electrical
characteristics
This table provides the recommended operating conditions for the DDR SDRAM
controller when interfacing to DDR3 SDRAM.
Table 20. DDR3 SDRAM interface DC electrical characteristics (GVDD = 1.5 V)1, 7
Parameter Symbol Min Max Unit Note
I/O reference voltage MVREFn0.49 x GVDD 0.51 x GVDD V 2, 3, 4
Input high voltage VIH MVREFn + 0.100 GVDD V 5
Input low voltage VIL GND MVREFn - 0.100 V 5
I/O leakage current IOZ -50 50 μA 6
Notes:
1. GVDD is expected to be within 50 mV of the DRAM's voltage supply at all times. The DRAM's and memory controller's
voltage supply may or may not be from the same source.
2. MVREFn is expected to be equal to 0.5 x GVDD and to track GVDD DC variations as measured at the receiver. Peak-to-
peak noise on MVREFn may not exceed the MVREFn DC level by more than ±1% of GVDD (i.e. ±15 mV).
3. VTT is not applied directly to the device. It is the supply to which far end signal termination is made, and it is expected to be
equal to MVREFn with a min value of MVREFn - 0.04 and a max value of MVREFn + 0.04. VTT should track variations in the
DC level of MVREFn.
4. The voltage regulator for MVREFn must meet the specifications stated in Table 22.
5. Input capacitance load for DQ, DQS, and DQS_B are available in the IBIS models.
6. Output leakage is measured with all outputs disabled, 0 V ≤ VOUT ≤ GVDD.
7. For recommended operating conditions, see Table 3.
This table provides the recommended operating conditions for the DDR SDRAM
controller when interfacing to DDR3L SDRAM.
Table 21. DDR3L SDRAM interface DC electrical characteristics (GVDD = 1.35 V)1, 7
Parameter Symbol Min Max Unit Note
I/O reference voltage MVREFn0.49 x GVDD 0.51 x GVDD V 2, 3, 4
Input high voltage VIH MVREFn + 0.090 GVDD V 5
Input low voltage VIL GND MVREFn - 0.090 V 5
I/O leakage current IOZ -100 100 μA 6
Notes:
1. GVDD is expected to be within 50 mV of the DRAM's voltage supply at all times. The DRAM's and memory controller's
voltage supply may or may not be from the same source.
2. MVREFn is expected to be equal to 0.5 x GVDD and to track GVDD DC variations as measured at the receiver. Peak-to-
peak noise on MVREFn may not exceed the MVREFn DC level by more than ±1% of GVDD (i.e. ±13.5 mV).
3. VTT is not applied directly to the device. It is the supply to which far end signal termination is made, and it is expected to be
equal to MVREFn with a min value of MVREFn - 0.04 and a max value of MVREFn + 0.04. VTT should track variations in the
DC level of MVREFn.
Electrical characteristics
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
NXP Semiconductors 63
Table 21. DDR3L SDRAM interface DC electrical characteristics (GVDD = 1.35 V)1, 7
Parameter Symbol Min Max Unit Note
4. The voltage regulator for MVREFn must meet the specifications stated in Table 22.
5. Input capacitance load for DQ, DQS, and DQS_B are available in the IBIS models.
6. Output leakage is measured with all outputs disabled, 0 V ≤ VOUT ≤ GVDD.
7. For recommended operating conditions, see Table 3.
This table provides the current draw characteristics for MVREFn.
Table 22. Current draw characteristics for MVREFn1
Parameter Symbol Min Max Unit Notes
Current draw for DDR3 SDRAM for MVREFnIMVREFn— 500 μA —
Current draw for DDR3L SDRAM for
MVREFn
IMVREFn— 500 μA —
Note:
1. For recommended operating conditions, see Table 3.
3.8.2 DDR3 and DDR3L SDRAM interface AC timing specifications
This section provides the AC timing specifications for the DDR SDRAM controller
interface. The DDR controller supports DDR3 and DDR3L memories. Note that the
required GVDD(typ) voltage is 1.5 V when interfacing to DDR3 SDRAM and the
required GVDD(typ) voltage is 1.35 V when interfacing to DDR3L SDRAM.
3.8.2.1 DDR3 and DDR3L SDRAM interface input AC timing specifications
This table provides the input AC timing specifications for the DDR controller when
interfacing to DDR3 or DDR3L SDRAM.
Table 23. DDR3 and DDR3L SDRAM interface input AC timing specifications4
Parameter Symbol Min Max Unit Notes
Controller Skew for MDQS-MDQ/MECC tCISKEW — — ps 1, 3
2133 MT/s data rate -80 80
1866 MT/s data rate -93 93
1600 MT/s data rate -112 112
1333 MT/s data rate -125 125
1200 MT/s data rate -142 142
1066 MT/s data rate -170 170
Table continues on the next page...
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Table 23. DDR3 and DDR3L SDRAM interface input AC timing specifications4 (continued)
Parameter Symbol Min Max Unit Notes
Tolerated Skew for MDQS-MDQ/MECC tDISKEW — — ps 2, 3
2133 MT/s data rate -154 154
1866 MT/s data rate -175 175
1600 MT/s data rate -200 200
1333 MT/s data rate -250 250
1200 MT/s data rate -275 275
1066 MT/s data rate -300 300
1. tCISKEW represents the total amount of skew consumed by the controller between MDQS[n] and any corresponding bit that
is captured with MDQS[n]. This must be subtracted from the total timing budget.
2. The amount of skew that can be tolerated from MDQS to a corresponding MDQ signal is called tDISKEW.This can be
determined by the following equation: tDISKEW = ±(T ÷ 4 - abs(tCISKEW)) where T is the clock period and abs(tCISKEW) is the
absolute value of tCISKEW.
3. 2133 MT/s is only supported for DDR3, not DDR3L.
4. For recommended operating conditions, see Table 3.
This figure shows the DDR3 and DDR3L SDRAM interface input timing diagram.
tMCK
MCK[n]_B
MCK[n]
MDQS[n]
MDQ[x]
tDISKEW
tDISKEW
tDISKEW
D0 D1
Figure 9. DDR3 and DDR3L SDRAM interface input timing diagram
3.8.2.2 DDR3 and DDR3L SDRAM interface output AC timing
specifications
This table contains the output AC timing targets for the DDR3 SDRAM interface.
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Table 24. DDR3 and DDR3L SDRAM interface output AC timing specifications8
Parameter Symbol1Min Max Unit Notes
MCK[n] cycle time tMCK 0.938 2 ns 2
ADDR/CMD output setup with respect to MCK tDDKHAS — — ns 3, 7
2133 MT/s data rate 0.350 —
1866 MT/s data rate 0.410 —
1600 MT/s data rate 0.495 —
1333 MT/s data rate 0.606 —
1200 MT/s data rate 0.675 —
1066 MT/s data rate 0.744 —
ADDR/CMD output hold with respect to MCK tDDKHAX — — ns 3, 7
2133 MT/s data rate 0.350 —
1866 MT/s data rate 0.390 —
1600 MT/s data rate 0.495 —
1333 MT/s data rate 0.606 —
1200 MT/s data rate 0.675 —
1066 MT/s data rate 0.744 —
MCK to MDQS Skew tDDKHMH — — ns 4
> 1600 MT/s data rate -0.150 0.150 4, 6
> 1066 MT/s data rate, ≤ 1600 MT/s data rate -0.245 0.245 4, 6
MDQ/MECC/MDM output Data eye tDDKXDEYE — — ns 5, 7
2133 MT/s data rate 0.320 —
1866 MT/s data rate 0.350 —
1600 MT/s data rate 0.400 —
1333 MT/s data rate 0.500 —
1200 MT/s data rate 0.550 —
1066 MT/s data rate 0.600 —
MDQS preamble tDDKHMP 0.9 x tMCK — ns —
MDQS postamble tDDKHME 0.4 x tMCK 0.6 x tMCK ns —
1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. Output hold time can be read as DDR timing (DD)
from the rising or falling edge of the reference clock (KH or KL) until the output went invalid (AX or DX). For example, tDDKHAS
symbolizes DDR timing (DD) for the time tMCK memory clock reference (K) goes from the high (H) state until outputs (A) are
setup (S) or output valid time.
2. All MCK/MCK_B and MDQS/MDQS_B referenced measurements are made from the crossing of the two signals.
3. ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK_B, MCS_B, and MDQ/MECC/MDM/MDQS.
4. Note that tDDKHMH follows the symbol conventions described in note 1. For example, tDDKHMH describes the DDR timing
(DD) from the rising edge of the MCK[n] clock (KH) until the MDQS signal is valid (MH). tDDKHMH can be modified through
control of the MDQS override bits (called WR_DATA_DELAY) in the TIMING_CFG_2 register. This is typically set to the
same delay as in DDR_SDRAM_CLK_CNTL[CLK_ADJUST]. The timing parameters listed in the table assume that these two
parameters have been set to the same adjustment value. See the chip reference manual for a description and explanation of
the timing modifications enabled by the use of these bits.
5. Available eye for data (MDQ), ECC (MECC), and data mask (MDM) outputs at the pin of the processor. Memory controller
will center the strobe (MDQS) in the available data eye at the DRAM (end point) during the initialization.
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Table 24. DDR3 and DDR3L SDRAM interface output AC timing specifications8
Parameter Symbol1Min Max Unit Notes
6. Note that for data rates of 1200 MT/s or higher, it is required to program the start value of the DQS adjust for write leveling.
7. 2133 MT/s is only supported for DDR3, not DDR3L.
8. For recommended operating conditions, see Table 3.
NOTE
For the ADDR/CMD setup and hold specifications in Table 24,
it is assumed that the clock control register is set to adjust the
memory clocks by ½ applied cycle for data rates of 1866 MT/s
or less and 9/16 applied cycle for data rates greater than 1866
MT/s. It is recommended that, during system validation,
memory clocks are adjusted to best fit the particular system.
design.
This figure shows the DDR3 and DDR3L SDRAM interface output timing for the MCK
to MDQS skew measurement (tDDKHMH).
tMCK
MCK[n]_B
MCK[n]
MDQS
MDQS
tDDKHMH(max)
tDDKHMH(min)
Figure 10. tDDKHMH timing diagram
This figure shows the DDR3 and DDR3L SDRAM output timing diagram.
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tMCK
MCK_B
MCK
MDQS[n]
MDQ[x]
tDDKXDEYE
D0 D1
tDDKHMH
tDDKHME
tDDKHMP
ADDR/CMD Write A0 NOOP
tDDKHAS
tDDKHAX
tDDKXDEYE
Figure 11. DDR3 and DDR3L output timing diagram
3.9 eSPI interface
This section describes the DC and AC electrical specifications for the eSPI interface.
3.9.1 eSPI DC electrical characteristics
This table provides the DC electrical characteristics for the eSPI interface operating at
OVDD = 2.5 V.
Table 25. eSPI DC electrical characteristics (2.5 V)3
Parameter Symbol Min Max Unit Notes
Input high voltage VIH 1.7 — V 1
Input low voltage VIL — 0.7 V 1
Input current (OVIN = 0 V or OVIN = OVDD) IIN -50 +50 μA 2
Output high voltage (OVDD = min, IOH = -1 mA) VOH 2.0 — V —
Table continues on the next page...
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Table 25. eSPI DC electrical characteristics (2.5 V)3 (continued)
Parameter Symbol Min Max Unit Notes
Output low voltage (OVDD = min, IOL = 1mA) VOL — 0.4 V —
Notes:
1. The min VILand max VIH values are based on the min and max OVIN respective values found in Table 3.
2. The symbol OVIN represents the input voltage of the supply. It is referenced in Recommended operating conditions.
3. For recommended operating conditions, see Table 3.
This table provides the DC electrical characteristics for the eSPI interface operating at
OVDD = 1.8 V.
Table 26. eSPI DC electrical characteristics (1.8 V)3
Parameter Symbol Min Max Unit Notes
Input high voltage VIH 1.25 — V 1
Input low voltage VIL — 0.6 V 1
Input current (VIN = 0 V or VIN = OVDD) IIN — ±50 μA 2
Output high voltage
(OVDD = min, IOH = -0.5 mA)
VOH 1.35 — V —
Output low voltage
(OVDD = min, IOL = 0.5 mA)
VOL — 0.4 V —
Notes:
1. The min VILand max VIH values are based on the respective min and max OVIN values found in Table 3.
2. The symbol VIN, in this case, represents the OVIN symbol referenced in Recommended operating conditions.
3. For recommended operating conditions, see Table 3.
3.9.2 eSPI AC timing specifications
This table provides the eSPI input and output AC timing specifications.
Table 27. eSPI AC timing specifications3
Characteristic Symbol 2Min Max Unit Notes
SPI_MOSI output-Master data (internal
clock) hold time
tNIKHOX n1 + (tPLATFORM_CLK *
SPMODE[HO_ADJ])
— ns 1, 2 , 4
SPI_MOSI output-Master data (internal
clock) delay
tNIKHOV — n2 + (tPLATFORM_CLK *
SPMODE[HO_ADJ])
ns 1, 2 , 4
SPI_CS outputs-Master data (internal clock)
hold time
tNIKHOX2 0 — ns 1
SPI_CS outputs-Master data (internal clock)
delay
tNIKHOV2 — 6.0 ns 1
Table continues on the next page...
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Table 27. eSPI AC timing specifications3 (continued)
Characteristic Symbol 2Min Max Unit Notes
SPI inputs-Master data (internal clock) input
setup time
tNIIVKH 3.6 — ns —
SPI inputs-Master data (internal clock) input
hold time
tNIIXKH 0 — ns —
Clock-high time tNIKCKH 4 — ns
Clock-low time tNIKCKL 4 — ns —
Notes:
1. See the chip reference manual for details about the SPMODE register.
2. Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings
are measured at the pin.
3. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tNIKHOV symbolizes the NMSI outputs
internal timing (NI) for the time tSPI memory clock reference (K) goes from the high state (H) until outputs (O) are valid (V).
4. n1 and n2 values are -1.0 and 1.0 respectively.
This figure provides the AC test load for the eSPI.
Output Z0= 50 Ω
RL = 50 Ω
OVDD/2
Figure 12. eSPI AC test load
This figure provides the eSPI clock output timing diagram.
Figure 13. eSPI clock output timing diagram
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This figure represents the AC timing from Table 27 in master mode (internal clock). Note
that although the specifications generally reference the rising edge of the clock, these AC
timing diagrams also apply when the falling edge is the active edge. Also, note that the
clock edge is selectable on eSPI.
Figure 14. eSPI AC timing in master mode (internal clock) diagram
NOTE
SPICLK appears on the interface only after CS assertion.
3.10 DUART interface
This section describes the DC and AC electrical specifications for the DUART interface.
3.10.1 DUART DC electrical characteristics
This table provides the DC electrical characteristics for the DUART interface at DVDD =
2.5 V.
Table 28. DUART DC electrical characteristics(2.5 V)3
Parameter Symbol Min Max Unit Notes
Input high voltage VIH 1.7 — V 1
Input low voltage VIL — 0.7 V 1
Input current (DVIN = 0 V or DVIN = DVDD) IIN -50 +50 μA 2
Output high voltage (DVDD = min, IOH = -1 mA) VOH 2.0 — V —
Output low voltage (DVDD = min, IOL = 1mA) VOL — 0.4 V —
Table continues on the next page...
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Table 28. DUART DC electrical characteristics(2.5 V)3 (continued)
Parameter Symbol Min Max Unit Notes
Notes:
1. The min VILand max VIH values are based on the min and max DVIN respective values found in Table 3.
2. The symbol DVIN represents the input voltage of the supply. It is referenced in Recommended operating conditions.
3. For recommended operating conditions, see Table 3.
This table provides the DC electrical characteristics for the DUART interface at DVDD =
1.8 V.
Table 29. DUART DC electrical characteristics(1.8 V)3
Parameter Symbol Min Max Unit Notes
Input high voltage VIH 1.25 — V 1
Input low voltage VIL — 0.6 V 1
Input current (DVIN = 0 V or DVIN = DVDD) IIN -50 +50 μA 2
Output high voltage (DVDD = min, IOH = -0.5 mA) VOH 1.35 — V —
Output low voltage (DVDD = min, IOL = 0.5 mA) VOL — 0.4 V —
Notes:
1. The min VILand max VIH values are based on the min and max DVIN respective values found in Table 3.
2. The symbol DVIN represents the input voltage of the supply. It is referenced in Recommended operating conditions.
3. For recommended operating conditions, see Table 3.
3.10.2 DUART AC electrical specifications
This table provides the AC timing parameters for the DUART interface.
Table 30. DUART AC timing specifications
Parameter Value Unit Notes
Minimum baud rate fPLAT/(2 x 1,048,576) baud 1, 3
Maximum baud rate fPLAT/(2 x 16) baud 1, 2
Notes:
1. fPLAT refers to the internal platform clock.
2. The actual attainable baud rate is limited by the latency of interrupt processing.
3. The middle of a start bit is detected as the eighth sampled 0 after the 1-to-0 transition of the start bit. Subsequent bit values
are sampled each 16th sample.
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3.11 Ethernet interface, Ethernet management interface 1 and 2,
IEEE Std 1588™
This section provides the AC and DC electrical characteristics for the Ethernet controller
and the Ethernet management interfaces.
3.11.1 SGMII electrical specifications
See SGMII interface.
3.11.2 RGMII electrical specifications
This section discusses the electrical characteristics for the RGMII interface.
3.11.2.1 RGMII DC electrical characteristics
This table shows the DC electrical characteristics for the RGMII interface.
Table 31. RGMII DC electrical characteristics(LVDD = 2.5 V)3
Parameters Symbol Min Max Unit Notes
Input high voltage VIH 1.70 — V 1
Input low voltage VIL — 0.70 V 1
Input current (LVIN= 0 V or LVIN= LVDD) IIH -50 +50 μA 2
Output high voltage (LVDD = min, IOH = -1.0 mA) VOH 2.00 LVDD + 0.3 V —
Output low voltage (LVDD = min, IOL = 1.0 mA) VOL GND - 0.3 0.40 V —
1. The min VILand max VIH values are based on the respective min and max LVIN values found in Table 3.
2. The symbol LVIN, in this case, represents the LVIN symbol referenced in Recommended operating conditions.
3. For recommended operating conditions, see Table 3.
3.11.2.2 RGMII AC timing specifications
This table presents the RGMII AC timing specifications.
Table 32. RGMII AC timing specifications (LVDD = 2.5 V)8
Parameter/Condition Symbol1Min Typ Max Unit Notes
Data to clock output skew (at transmitter) tSKRGT_TX -750 0 1000 ps 7, 9
Data to clock input skew (at receiver) tSKRGT_RX 1.0 — 2.6 ns 2
Clock period duration tRGT 7.2 8.0 8.8 ns 3
Table continues on the next page...
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Table 32. RGMII AC timing specifications (LVDD = 2.5 V)8 (continued)
Parameter/Condition Symbol1Min Typ Max Unit Notes
Duty cycle for 10BASE-T and 100BASE-TX tRGTH/tRGT 40 50 60 % 3, 4
Duty cycle for Gigabit tRGTH/tRGT 45 50 55 % —
Rise time (20%-80%) tRGTR — — 0.75 ns 5, 6
Fall time (20%-80%) tRGTF — — 0.75 ns 5, 6
Notes:
1. In general, the clock reference symbol representation for this section is based on the symbols RGT to represent RGMII
timing. Note that the notation for rise (R) and fall (F) times follows the clock symbol that is being represented. For symbols
representing skews, the subscript is skew (SK) followed by the clock that is being skewed (RGT).
2. This implies that PC board design will require clocks to be routed such that an additional trace delay of greater than 1.5 ns
is added to the associated clock signal. Many PHY vendors already incorporate the necessary delay inside their device. If so,
additional PCB delay is probably not needed.
3. For 10 and 100 Mbps, tRGT scales to 400 ns ± 40 ns and 40 ns ± 4 ns, respectively.
4. Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's clock domains as
long as the minimum duty cycle is not violated and stretching occurs for no more than three tRGT of the lowest speed
transitioned between.
5. Applies to inputs and outputs.
6. System/board must be designed to ensure this input requirement to the chip is achieved. Proper device operation is
guaranteed for inputs meeting this requirement by design, simulation, characterization, or functional testing.
7. The frequency of ECn_RX_CLK (input) should not exceed the frequency of ECn_GTX_CLK (output) by more than 300
ppm.
8. For recommended operating conditions, see Table 3.
9. IEEE specification mandates tSKRGT_TX = ± 0.5 ns. Per erratum A-005177, we see tSKRGT_TX has a wider output skew
range from -0.75 ns to 1.00 ns, which is larger than the specification asks for. If the device cannot cope with this wide skew,
use RGMII at 100 Mbps or 10 Mbps, which allows larger maximum RX skews, or terminate 1000 Mbps RGMII links with
PHYs that accommodate larger RX skews. NOTE: MAC10 is not impacted by erratum A-005177, and it meets industry
specifications.
This figure shows the RGMII AC timing and multiplexing diagrams.
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TXD[3:0] TXD[7:4]
TXEN
RXD[3:0]
RXDV
TXERR
RXD[7:4]
RXERR
GTX_CLK
output
TXD[7:4][3:0]
output
TX_CTL
output
RXD[7:4][3:0]
input
RX_CTL
input
RX_CLK
input
tRGT
tRGTH
tSKRGT_TX tSKRGT_TX
tSKRGT_RX tSKRGT_RX
tRGTH
tRGT
Figure 15. RGMII AC timing and multiplexing diagrams
Warning
NXP guarantees timings generated from the MAC. Board
designers must ensure delays needed at the PHY or the MAC.
3.11.3 Ethernet management interface (EMI)
This section discusses the electrical characteristics for the EMI1 and EMI2 interfaces.
Frame Manager's external GE MDIO configures external GE PHYs connected to EMI1
pins. Frame Manager's external 10GE MDIO configures external XFI, XAUI, and HiGig/
HiGig2 PHY connected to EMI2 pins.
The EMI1 interface timing is compatible with IEEE Std 802.3™ clause 22 and EMI2
interface timing is compatible with IEEE Std 802.3™ clause 45.
3.11.3.1 Ethernet management interface 1 DC electrical characteristics
The DC electrical characteristics for EMI1_MDIO and EMI1_MDC are provided in this
section.
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Table 33. Ethernet management interface 1 DC electrical characteristics (LVDD = 2.5 V)3
Parameters Symbol Min Max Unit Notes
Input high voltage VIH 1.70 — V 1
Input low voltage VIL — 0.70 V 1
Input high current (VIN = LVDD) IIH — 50 μA 2
Input low current (VIN = GND) IIL -50 — μA —
Output high voltage (LVDD = min, IOH = -1.0 mA) VOH 2.00 LVDD + 0.3 V —
Output low voltage (LVDD = min, IOL = 1.0 mA) VOL GND - 0.3 0.40 V —
Notes:
1. The min VILand max VIH values are based on the respective min and max LVIN values found in Table 3.
2. The symbol VIN, in this case, represents the LVIN symbol referenced in Recommended operating conditions.
3. For recommended operating conditions, see Table 3.
Table 34. Ethernet management interface 1 DC electrical characteristics (LVDD = 1.8 V)3
Parameter Symbol Min Max Unit Notes
Input high voltage VIH 1.25 — V 1
Input low voltage VIL — 0.60 V 1
Input current (LVIN= 0V or LVIN=LVDD) IIN -50 50 μA 2
Output high voltage (LVDD = min, IOH = -0.5 mA) VOH 1.35 — V —
Output low voltage (LVDD = min, IOL = 0.5 mA) VOL — 0.40 V —
Notes:
1. The min VILand max VIH values are based on the respective min and max OVIN/QVIN values found in Table 3.
2. The symbol VIN, in this case, represents the OVIN symbol referenced in Table 3.
3.11.3.2 Ethernet management interface 2 DC electrical characteristics
Ethernet management interface 2 pins function as open drain I/Os. The interface
conforms to 1.2 V nominal voltage levels. The DC electrical characteristics for
EMI2_MDIO and EMI2_MDC are provided in this section.
Table 35. Ethernet management interface 2 DC electrical characteristics (1.2 V)1
Parameter Symbol Min Max Unit Notes
Input high voltage VIH 0.84 — V —
Input low voltage VIL — 0.36 V —
Output low voltage (IOL = 100 μA) VOL — 0.2 V —
Output low current (VOL = 0.2 V) IOL 4 — mA —
Input capacitance CIN — 10 pF —
Notes:
1. For recommended operating conditions, see Table 3.
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3.11.3.3 Ethernet management interface 1 AC electrical specifications
This table provides the Ethernet management interface 1 AC timing specifications.
Table 36. Ethernet management interface 1 AC timing specifications5
Parameter/Condition Symbol1Min Typ Max Unit Notes
MDC frequency fMDC — — 2.5 MHz 2
MDC clock pulse width high tMDCH 160 — — ns —
MDC to MDIO delay tMDKHDX (5 x tenet_clk) - 3 — (5 x tenet_clk) + 3 ns 3, 4
MDIO to MDC setup time tMDDVKH 8 — — ns —
MDIO to MDC hold time tMDDXKH 0 — — ns —
Notes:
1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMDKHDX symbolizes management
data timing (MD) for the time tMDC from clock reference (K) high (H) until data outputs (D) are invalid (X) or data hold time.
Also, tMDDVKH symbolizes management data timing (MD) with respect to the time data input signals (D) reach the valid state
(V) relative to the tMDC clock reference (K) going to the high (H) state or setup time.
2. This parameter is dependent on the Ethernet clock frequency (MDIO_CFG [MDIO_CLK_DIV] field determines the clock
frequency of the MgmtClk Clock EC_MDC).
3. This parameter is dependent on the Ethernet clock frequency. The delay is equal to 5 Ethernet clock periods ± 3 ns. For
example, with an Ethernet clock of 400 MHz, the min/max delay is 12.5 ns ± 3 ns.
4. tenet_clk is the Ethernet clock period (Frame Manager clock period).
5. For recommended operating conditions, see Table 3.
3.11.3.4 Ethernet management interface 2 AC electrical characteristics
This table provides the Ethernet management interface 2 AC timing specifications.
Table 37. Ethernet management interface 2 AC timing specifications5
Parameter/Condition Symbol1Min Typ Max Unit Notes
MDC frequency fMDC 2.5 — — MHz 2
MDC clock pulse width high tMDCH 160 — — ns —
MDC to MDIO delay tMDKHDX (5 x tenet_clk) - 3 — (5 x tenet_clk) + 3 ns 3, 4
MDIO to MDC setup time tMDDVKH 8 — — ns —
MDIO to MDC hold time tMDDXKH 0 — — ns —
Notes:
1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMDKHDX symbolizes management
data timing (MD) for the time tMDC from clock reference (K) high (H) until data outputs (D) are invalid (X) or data hold time.
Also, tMDDVKH symbolizes management data timing (MD) with respect to the time data input signals (D) reach the valid state
(V) relative to the tMDC clock reference (K) going to the high (H) state or setup time.
2. This parameter is dependent on the Ethernet clock frequency (MDIO_CFG [MDIO_CLK_DIV] field determines the clock
frequency of the MgmtClk Clock EC_MDC).
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Table 37. Ethernet management interface 2 AC timing specifications5
Parameter/Condition Symbol1Min Typ Max Unit Notes
3. This parameter is dependent on the Ethernet clock frequency. The delay is equal to 5 Ethernet clock periods ± 3 ns. For
example, with an Ethernet clock of 400 MHz, the min/max delay is 12.5 ns ± 3 ns.
4. tenet_clk is the Ethernet clock period (Frame Manager clock period).
5. For recommended operating conditions, see Table 3.
This figure shows the Ethernet management interface timing diagram
tMDC
tMDCH
tMDDVKH
tMDDXKH
tMDKHDX
MDC
MDIO
(Input)
MDIO
(Output)
Figure 16. Ethernet management interface timing diagram
3.11.4 IEEE 1588 electrical specifications
3.11.4.1 IEEE 1588 DC electrical characteristics
This table shows IEEE 1588 DC electrical characteristics when operating at LVDD = 2.5
V supply.
Table 38. IEEE 1588 DC electrical characteristics (LVDD = 2.5 V)3
Parameters Symbol Min Max Unit Notes
Input high voltage VIH 1.70 — V 1
Input low voltage VIL — 0.70 V 1
Input current (LVIN= 0 V or LVIN= LVDD) IIH -50 +50 μA 2
Output high voltage (LVDD = min, IOH = -1.0 mA) VOH 2.00 LVDD + 0.3 V —
Table continues on the next page...
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Table 38. IEEE 1588 DC electrical characteristics (LVDD = 2.5 V)3 (continued)
Parameters Symbol Min Max Unit Notes
Output low voltage (LVDD = min, IOL = 1.0 mA) VOL GND - 0.3 0.40 V —
1. The min VILand max VIH values are based on the respective min and max LVIN values found in Table 3.
2. The symbol LVIN, in this case, represents the LVIN symbol referenced in Recommended operating conditions.
3. For recommended operating conditions, see Table 3.
This table shows IEEE 1588 DC electrical characteristics when operating at LVDD = 1.8
V supply.
Table 39. IEEE 1588 DC electrical characteristics (LVDD = 1.8 V)3
Parameters Symbol Min Max Unit Notes
Input high voltage VIH 1.25 — V 1
Input low voltage VIL — 0.6 V 1
Input current (LVIN= 0 V or LVIN= LVDD) IIH -50 +50 μA 2
Output high voltage (LVDD = min, IOH = -0.5 mA) VOH 1.35 LVDD + 0.3 V —
Output low voltage (LVDD = min, IOL = 0.5 mA) VOL GND - 0.3 0.40 V —
1. The min VILand max VIH values are based on the respective min and max LVIN values found in Table 3.
2. The symbol LVIN, in this case, represents the LVIN symbol referenced in Recommended operating conditions.
3. For recommended operating conditions, see Table 3.
3.11.4.2 IEEE 1588 AC specifications
This table provides the IEEE 1588 AC timing specifications.
Table 40. IEEE 1588 AC timing specifications5
Parameter/Condition Symbol Min Typ Max Unit Notes
TSEC_1588_CLK_IN clock period tT1588CLK 3.3 — TRX_CLK x 7 ns 1, 3
TSEC_1588_CLK_IN duty cycle tT1588CLKH/
tT1588CLK
40 50 60 % 2
TSEC_1588_CLK_IN peak-to-peak jitter tT1588CLKINJ — — 250 ps —
Rise time TSEC_1588_CLK_IN (20%
-80%)
tT1588CLKINR 1.0 — 2.0 ns —
Fall time TSEC_1588_CLK_IN (80%
-20%)
tT1588CLKINF 1.0 — 2.0 ns —
TSEC_1588_CLK_OUT clock period tT1588CLKOUT 5.0 — — ns 4
TSEC_1588_CLK_OUT duty cycle tT1588CLKOTH/
tT1588CLKOUT
30 50 70 % —
TSEC_1588_PULSE_OUT1/2,
TSEC_1588_ALARM_OUT1/2
tT1588OV 0.5 — 3.0 ns —
Table continues on the next page...
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Table 40. IEEE 1588 AC timing specifications5 (continued)
Parameter/Condition Symbol Min Typ Max Unit Notes
TSEC_1588_TRIG_IN1/2 pulse width tT1588TRIGH 2 x tT1588CLK_MAX — — ns 3
Notes:
1.TRX_CLK is the maximum clock period of ethernet receiving clock selected by TMR_CTRL[CKSEL]. See the chip reference
manual for a description of TMR_CTRL registers.
2. It needs to be at least two times the clock period of the clock selected by TMR_CTRL[CKSEL]. See the chip reference
manual for a description of TMR_CTRL registers.
3. The maximum value of tT1588CLK is not only defined by the value of TRX_CLK, but also defined by the recovered clock. For
example, for 10/100/1000 Mbps modes, the maximum value of tT1588CLK will be 2800, 280, and 56 ns, respectively.
4. There are 3 input clock sources for 1588 i.e. TSEC_1588_CLK_IN, RTC and MAC clock / 2. When using
TSEC_1588_CLK_IN, the minimum clock period is 2 x tT1588CLK.
5. For recommended operating conditions, see Table 3.
This figure shows the data and command output AC timing diagram.
TSEC_1588_CLK_OUT
TSEC_1588_ALARM_OUT1/2
TSEC_1588_PULSE_OUT1/2
tT1588OV
tT1588CLKOUTH
tT1588CLKOUT
Note: The output delay is counted starting at the rising edge if tT1588CLKOUT is non-inverting.
Otherwise, it is counted starting at the falling edge.
Figure 17. IEEE 1588 output AC timing
This figure shows the data and command input AC timing diagram.
TSEC_1588_CLK_IN
TSEC_1588_TRIG_IN1/2
tT1588CLK
tT1588CLKH
tT1588TRIGH
Figure 18. IEEE 1588 input AC timing
3.12 USB interface
This section provides the AC and DC electrical specifications for the USB interface.
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3.12.1 USB DC electrical characteristics
This table provides the DC electrical characteristics for the USB interface at USB_HVDD
= 3.3 V.
Table 41. USB DC electrical characteristics (USB_HVDD = 3.3 V) 3
Parameter Symbol Min Max Unit Notes
Input high voltage VIH 2.0 - V 1, 4
Input low voltage VIL - 0.8 V 1, 4
Input current (USB_HVIN = 0 V or USB_HVIN=
USB_HVDD)
IIN -100 +100 μA 2, 4
Output high voltage (USB_HVDD = min, IOH = -2 mA) VOH 2.8 - V 5
Output low voltage (USB_HVDD = min, IOL = 2 mA) VOL - 0.3 V 5
Notes:
1. The min VILand max VIH values are based on the respective min and max USB_HVIN values found in Table 3.
2. The symbol USB_HVIN, in this case, represents the USB_HVIN symbol referenced in Recommended operating conditions
3. For recommended operating conditions, see Table 3
4. These specifications only apply to the following pins: USB1_PWRFAULT, USB2_PWRFAULT, USB1_UDM (full-speed
mode), USB2_UDM (full-speed mode), USB1_UDP (full-speed mode), and USB2_UDP (full-speed mode).
5. This specification only applies to USB1_DRVVBUS and USB2_DRVVBUS pins.
This table provides the DC electrical characteristics for the USBCLK at OVDD = 1.8 V.
Table 42. USBCLK DC electrical characteristics (1.8 V)3
Parameter Symbol Min Max Unit Notes
Input high voltage VIH 1.25 - V 1
Input low voltage VIL - 0.6 V 1
Input current (VIN = 0 V or VIN = OVDD) IIN - ±100 μA 2
Notes:
1. The min VIL and max VIH values are based on the respective min and max OVIN values found in Table 3.
2. The symbol VIN, in this case, represents the OVIN symbol referenced in Recommended operating conditions.
3. For recommended operating conditions, see Table 3.
3.12.2 USB AC timing specifications
This section describes the AC timing specifications for the on-chip USB PHY. See
Chapter 7 in the Universal Serial Bus Revision 2.0 Specification for more information.
This table provides the USB clock input (USBCLK) AC timing specifications.
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Table 43. USBCLK AC timing specifications1
Parameter Condition Symbol Min Typ Max Unit Note
s
Frequency range - fUSB_CLK_IN - 24 - MHz -
Rise/Fall time Measured between 10% and 90% tUSRF - - 6 ns 2
Clock frequency
tolerance
- tCLK_TOL -0.01 0 0.01 % -
Reference clock duty
cycle
Measured at rising edge and/or failing edge at
OVDD/2
tCLK_DUTY 40 50 60 % -
Total input jitter/time
interval error
RMS value measured with a second-order,
band-pass filter of 500 kHz to 4 MHz bandwidth
at 10-12 BER
tCLK_PJ - - 5 ps -
Notes:
1. For recommended operating conditions, see Table 3
2. System/board must be designed to ensure the input requirement to the device is achieved. Proper device operation is
guaranteed for inputs meeting this requirement by design, simulation, characterization, or functional testing.
3.13 Integrated flash controller
This section describes the DC and AC electrical specifications for the integrated flash
controller.
3.13.1 Integrated flash controller DC electrical characteristics
This table provides the DC electrical characteristics for the integrated flash controller
when operating at OVDD= 1.8 V.
Table 44. Integrated flash controller DC electrical characteristics (1.8 V)3
Parameter Symbol Min Max Unit Note
Input high voltage VIH 1.25 - V 1
Input low voltage VIL - 0.6 V 1
Input current
(VIN = 0 V or VIN = OVDD)
IIN -50 +50 μA 2
Output high voltage
(OVDD = min, IOH = -0.5 mA)
VOH 1.35 - V -
Output low voltage
(OVDD = min, IOL = 0.5 mA)
VOL - 0.4 V -
1. The min VILand max VIH values are based on the respective min and max OVIN values found in Table 3.
2. The symbol VIN, in this case, represents the OVIN symbol referenced in Recommended operating conditions.
3. For recommended operating conditions, see Table 3.
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3.13.2 Integrated flash controller AC timing
This section describes the AC timing specifications for the integrated flash controller.
3.13.2.1 Test condition
This figure provides the AC test load for the integrated flash controller.
Output Z0= 50 Ω
RL = 50 Ω
OVDD/2
Figure 19. Integrated flash controller AC test load
3.13.2.2 Integrated flash controller AC timing specifications
All output signal timings are relative to the falling edge of any IFC_CLK. The external
circuit must use the rising edge of the IFC_CLKs to latch the data.
All input timings are relative to the rising edge of IFC_CLKs.
This table describes the timing specifications of the integrated flash controller interface.
Table 45. Integrated flash controller timing specifications (OVDD = 1.8 V)5
Parameter Symbol1Min Max Unit Notes
IFC_CLK cycle time tIBK 10 - ns -
IFC_CLK duty cycle tIBKH/ tIBK 45 55 % -
IFC_CLK[n] skew to IFC_CLK[m] tIBKSKEW - 150 ps 2
Input setup tIBIVKH 4 - ns -
Input hold tIBIXKH 1 - ns -
Output delay tIBKLOV - 2.5 ns -
Output hold tIBKLOX -2 - ns 4
IFC_CLK to output high impedance for AD tIBKLOZ - 2 ns 3
1. All signals are measured from OVDD/2 of rising/falling edge of IFC_CLK to OVDD/2 of the signal in question.
2. Skew measured between different IFC_CLK signals at OVDD/2.
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Table 45. Integrated flash controller timing specifications (OVDD = 1.8 V)5
Parameter Symbol1Min Max Unit Notes
3. For purposes of active/float timing measurements, the high impedance or off state is defined to be when the total current
delivered through the component pin is less than or equal to the leakage current specification.
4. Here the negative sign means output transit happens earlier than the falling edge of IFC_CLK.
5. For recommended operating conditions, see Table 3.
This figure shows the AC timing diagram.
IFC_CLK[m]
Input signals
Output signals
AD (data phase)
tIBKLOX
tIBKLOZ
tIBKLOX
tIBKLOV
tIBIVKH
tIBIXKH
tIBIVKL
Figure 20. Integrated flash controller signals
The figure above applies to all the controllers that IFC supports.
• For input signals, the AC timing data is used directly for all controllers.
• For output signals, each type of controller provides its own unique method to control
the signal timing. The final signal delay value for output signals is the programmed
delay plus the AC timing delay.
This figure shows how the AC timing diagram applies to GPCM. The same principle also
applies to other controllers of IFC.
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IFC_CLK
AD
AVD
CE_B
OE_B
WE_B
BCTL
Address Address
Read data Write data
teahc + tIBKLOV
teadc + tIBKLOV
taco + tIBKLOV
trad + tIBKLOV
tcs + tIBKLOV
twp+ tIBKLOV
tch + tIBKLOV
tacse+ tIBKLOV
Write
Read
Figure 21. GPCM output timing diagram1, 2
Notes for figure:
1. taco, trad,teahc,teadc, tacse, tcs, tch,twp are programmable. See the chip reference manual.
2. For output signals, each type of controller provides its own unique method to control
the signal timing. The final signal delay value for output signals is the programmed delay
plus the AC timing delay.
3.14 Enhanced secure digital host controller (eSDHC)
This section describes the DC and AC electrical specifications for the eSDHC interface.
3.14.1 eSDHC DC electrical characteristics
This table provides the DC electrical characteristics for the eSDHC interface.
Table 46. eSDHC interface DC electrical characteristics (dual-voltage cards)3
Characteristic Symbol Condition Min Max Unit Notes
Input high voltage VIH - 0.7 x VDD - V 1
Input low voltage VIL - - 0.2 x VDD V 1
Input/Output leakage current IIN/IOZ - -50 50 μA -
Output high voltage VOH IOH = -100 μA at VDD
min
VDD - 0.2 V - V -
Output low voltage VOL IOL= 100 μA at VDD
min
- 0.2 V -
Table continues on the next page...
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Table 46. eSDHC interface DC electrical characteristics (dual-voltage cards)3 (continued)
Characteristic Symbol Condition Min Max Unit Notes
Output high voltage VOH IOH = -100 μA VDD - 0.2 - V 2
Output low voltage VOL IOL = 2 mA - 0.3 V 2
1. The min VIL and VIH values are based on the respective min and max VIN values found in Table 3.
2. Open-drain mode is for MMC cards only.
3. For recommended operating conditions, see Table 3.
4. SDHC interface is powered by OVDD and CVDD. The VDD and VIN in the table above should be replaced by the respective
I/O power supply.
3.14.2 eSDHC AC timing specifications
This table provides the eSDHC AC timing specifications as defined in Figure 22 and
Figure 23 (OVDD/CVDD = 1.8 V or 3.3 V).
Table 47. eSDHC AC timing specifications (High Speed/Full Speed)6
Parameter Symbol1Min Max Unit Notes
SDHC_CLK clock frequency SD/SDIO (full-speed/high-speed
mode)
fSCK 0 25/50 MHz 2, 4
MMC full-speed/high-speed mode 20/52
SDHC_CLK clock low time (full-speed/high-speed mode) tSCKL 10/7 — ns 4
SDHC_CLK clock high time (full-speed/high-speed mode) tSCKH 10/7 — ns 4
SDHC_CLK clock rise and fall times tSCKR/
tSCKF
— 3 ns 4
Input setup times: SDHC_CMD, SDHC_DATx to SDHC_CLK tNIIVKH 2.5 — ns 3, 4, 5
Input hold times: SDHC_CMD, SDHC_DATx to SDHC_CLK tNIIXKH 2.5 — ns 4, 5
Output hold time: SDHC_CLK to SDHC_CMD, SDHC_DATx valid tNIKHOX -3 — ns 4, 5
Output delay time: SDHC_CLK to SDHC_CMD, SDHC_DATx valid tNIKHOV — 3 ns 4, 5
Notes:
1. The symbols used for timing specifications herein follow the pattern of t(first three letters of functional block)(signal)(state) (reference)(state)
for inputs and (first three letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tFHSKHOV symbolizes eSDHC
high-speed mode device timing (SHS) clock reference (K) going to the high (H) state, with respect to the output (O) reaching
the invalid state (X) or output hold time. Note that in general, the clock reference symbol is based on five letters representing
the clock of a particular functional. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F
(fall).
2. In full-speed mode, the clock frequency value can be 0-25 MHz for an SD/SDIO card and 0-20 MHz for an MMC card. In
high-speed mode, the clock frequency value can be 0-50 MHz for an SD/SDIO card and 0-52 MHz for an MMC card.
3. To satisfy setup timing, one-way board-routing delay between Host and Card, on SDHC_CLK, SDHC_CMD, and
SDHC_DATx should not exceed 1 ns for any high speed MMC card. For any high speed or default speed mode SD card, the
one way board routing delay between Host and Card, on SDHC_CLK, SDHC_CMD, and SDHC_DATx should not exceed
1.5ns.
4. CCARD ≤ 10 pF, (1 card), and CL = CBUS + CHOST + CCARD ≤ 40 pF.
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Table 47. eSDHC AC timing specifications (High Speed/Full Speed)6
Parameter Symbol1Min Max Unit Notes
5. The parameter values apply to both full-speed and high-speed modes.
6. For recommended operating conditions, see Table 3.
This figure provides the eSDHC clock input timing diagram.
eSDHC
external clock
VM VM VM
tSCK
tSCKL tSCKH
tSCKR tSCKF
VM = Midpoint voltage (OVDD/2)
Figure 22. eSDHC clock input timing diagram
This figure provides the data and command input/output timing diagram.
SDHC_CLK
external clock
VM VM VM
tSHSIXKH
SDHC_DAT/CMD inputs
SDHC_DAT/CMD outputs
VM
tSHSIVKH
tSHSKHOV
VM = Midpoint voltage (OVDD/2)
tSHSKHOX
Figure 23. eSDHC data and command input/output timing diagram referenced to clock
This table provides the eSDHC AC timing specifications for eMMC HS200 mode as
defined in Figure 24 (EVDD/CVDD = 1.8 V).
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Table 48. eSDHC AC timing (eMMC HS200)
Parameter Symbol Min Max Units Notes
SDHC_CLK clock frequency eMMC HS200 mode fSCK — 175 MHz —
SDHC_CLK duty cycle — 47 53 % —
SDHC_CLK clock rise and fall times tSCKR/
tSCKF
— 1 ns 1
Output hold time: SDHC_CLK to
SDHC_CMD, SDHC DATx valid,
SDHC_CMD_DIR,
SDHC_DATx_DIR
eMMC HS200 mode tNIKHOX 1.6 — ns —
Output delay time: SDHC_CLK to
SDHC_CMD, SDHC DATx valid,
SDHC_CMD_DIR,
SDHC_DATx_DIR
eMMC HS200 mode tNIKHOV — 3.9 ns —
Input data window (UI) eMMC HS200 mode tIDV 0.475 — Unit
interval
—
Notes:
1. CL = CBUS + CHOST + CCARD ≤ 10 pF.
2. For recommended operating conditions, see Table 3.
This figure provides the HS200 mode timing diagram.
SDHC_CLK
SDHC_CMD/
SDHC_DAT input
SDHC_CMD/SDHC_CMD_DIR
SDHC_DAT/SDHC_DATn_DIR
output DATA DATA
DATA
TNIKHOX
TNIKHOV
TIDV
Tclk
Figure 24. eMMC HS200 mode timing diagram
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3.15 Multicore programmable interrupt controller (MPIC)
This section describes the DC and AC electrical specifications for the multicore
programmable interrupt controller.
3.15.1 MPIC DC specifications
This figure provides the DC electrical characteristics for the MPIC interface.
Table 49. MPIC DC electrical characteristics (OVDD = 1.8 V)3
Parameter Symbol Min Max Unit Notes
Input high voltage VIH 1.25 - V 1
Input low voltage VIL - 0.6 V 1
Input current (OVIN = 0 V or OVIN = OVDD) IIN -50 +50 μA 2
Output high voltage (OVDD = min, IOH = -0.5 mA) VOH 1.35 - V -
Output low voltage (OVDD = min, IOL = 0.5 mA) VOL - 0.4 V -
Note:
1. The min VILand max VIH values are based on the min and max OVIN respective values found in Table 3.
2. The symbol OVIN, in this case, represents the OVIN symbol referenced in Table 3.
3. For recommended operating conditions, see Table 3.
3.15.2 MPIC AC timing specifications
This table provides the MPIC input and output AC timing specifications.
Table 50. MPIC Input AC timing specifications2
Characteristic Symbol Min Max Unit Notes
MPIC inputs-minimum pulse width tPIWID 3 - SYSCLKs 1
1. MPIC inputs and outputs are asynchronous to any visible clock. MPIC outputs must be synchronized before use by any
external synchronous logic. MPIC inputs are required to be valid for at least tPIWID ns to ensure proper operation when
working in edge triggered mode.
2. For recommended operating conditions, see Table 3.
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3.16 JTAG controller
This section describes the DC and AC electrical specifications for the IEEE 1149.1
(JTAG) interface.
3.16.1 JTAG DC electrical characteristics
This table provides the JTAG DC electrical characteristics.
Table 51. JTAG DC electrical characteristics (OVDD = 1.8V)3
Parameter Symbol Min Max Unit Notes
Input high voltage VIH 1.25 - V 1
Input low voltage VIL - 0.6 V 1
Input current (OVIN = 0 V or OVIN = OVDD) IIN - -100/+50 μA 2, 4
Output high voltage (OVDD = min, IOH = -0.5 mA) VOH 1.35 - V -
Output low voltage (OVDD = min, IOL = 0.5 mA) VOL - 0.4 V -
Notes:
1. The min VILand max VIH values are based on the respective min and max OVIN values found in Table 3.
2. The symbol VIN, in this case, represents the OVIN symbol found in Table 3.
3. For recommended operating conditions, see Table 3.
4. TDI, TMS, and TRST_B have internal pull-ups per the IEEE Std. 1149.1 specification.
3.16.2 JTAG AC timing specifications
This table provides the JTAG AC timing specifications as defined in Figure 25 through
Figure 28.
Table 52. JTAG AC timing specifications4
Parameter Symbol1Min Max Unit Notes
JTAG external clock frequency of operation fJTG 0 33.3 MHz —
JTAG external clock cycle time tJTG 30 — ns —
JTAG external clock pulse width measured at 1.4 V tJTKHKL 15 — ns —
JTAG external clock rise and fall times tJTGR/tJTGF 0 2 ns —
TRST_B assert time tTRST 25 — ns 2
Input setup times tJTDVKH 4 — ns 5
Input hold times tJTDXKH 10 — ns —
Output valid times tJTKLDV ns 3
Boundary-scan data — 15
TDO — 10
Table continues on the next page...
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Table 52. JTAG AC timing specifications4 (continued)
Parameter Symbol1Min Max Unit Notes
Output hold times tJTKLDX 0 — ns 3
Notes:
1. The symbols used for timing specifications follow the pattern t(first two letters of functional block)(signal)(state)(reference)(state) for inputs
and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tJTDVKH symbolizes JTAG device timing (JT)
with respect to the time data input signals (D) reaching the valid state (V) relative to the tJTG clock reference (K) going to the
high (H) state or setup time. Also, tJTDXKH symbolizes JTAG timing (JT) with respect to the time data input signals (D)
reaching the invalid state (X) relative to the tJTG clock reference (K) going to the high (H) state. Note that in general, the clock
reference symbol representation is based on three letters representing the clock of a particular functional. For rise and fall
times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
2.TRST_B is an asynchronous level sensitive signal. The setup time is for test purposes only.
3. All outputs are measured from the midpoint voltage of the falling edge of tTCLK to the midpoint of the signal in question. The
output timings are measured at the pins. All output timings assume a purely resistive 50-Ω load. Time-of-flight delays must be
added for trace lengths, vias, and connectors in the system.
4. For recommended operating conditions, see Table 3.
5. LP_TMP_DETECT pin requires 9.5ns input setup time for the board JTAG test to go through runTESTIdle.
This figure provides the AC test load for TDO and the boundary-scan outputs of the
device.
Output Z0= 50 Ω
RL = 50 Ω
OVDD/2
Figure 25. AC test load for the JTAG interface
This figure provides the JTAG clock input timing diagram.
JTAG external clock
VM VM VM
tJTKHKL
tJTG
VM
VM = Midpoint voltage (OVDD/2)
tJTGR
tJTGF
Figure 26. JTAG clock input timing diagram
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This figure provides the TRST_B timing diagram.
tTRST
VM = Midpoint voltage (OVDD/2)
VM VM
TRST_B
Figure 27. TRST_B timing diagram
This figure provides the boundary-scan timing diagram.
JTAG External Clock
Boundary Data Inputs
Boundary Data Outputs
VMVM
Input Data Valid
Output Data Valid
VM = Midpoint Voltage (OVDD/2)
tJTKLDV
tJTKLDX
tJTDVKH
tJTDXKH
Figure 28. Boundary-scan timing diagram
3.17 I2C interface
This section describes the DC and AC electrical characteristics for the I2C interface.
3.17.1 I2C DC electrical characteristics
This table provides the DC electrical characteristics for the I2C interfaces operating at
2.5V.
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Table 53. I2C DC electrical characteristics (DVDD = 2.5V)5
Parameter Symbol Min Max Unit Notes
Input high voltage VIH 1.7 - V 1
Input low voltage VIL - 0.7 V 1
Output low voltage (OVDD = min, IOL = 3 mA) VOL 0 0.4 V 2
Pulse width of spikes which must be suppressed by the input filter tI2KHKL 0 50 ns 3
Input current each I/O pin (input voltage is between 0.1 x OVDD and 0.9
x OVDD(max)
II-50 50 μA 4
Capacitance for each I/O pin CI- 10 pF -
Notes:
1. The min VILand max VIH values are based on the respective min and max OVIN values found in Table 3.
2. The output voltage (open drain or open collector) condition = 3 mA sink current.
3. See the chip reference manual for information about the digital filter used.
4. I/O pins obstruct the SDA and SCL lines if OVDD is switched off.
5. For recommended operating conditions, see Table 3.
This table provides the DC electrical characteristics for the I2C interfaces operating at
1.8V.
Table 54. I2C DC electrical characteristics (DVDD = 1.8V)4
Parameter Symbol Min Max Unit Notes
Input high voltage VIH 1.25 - V 1
Input low voltage VIL - 0.6 V 1
Output low voltage (OVDD = min, IOL = 2 mA) VOL 0 0.36 V
Pulse width of spikes which must be suppressed by the input filter tI2KHKL 0 50 ns 2
Input current each I/O pin (input voltage is between 0.1 x OVDD and 0.9
x OVDD(max)
II-50 50 μA 3
Capacitance for each I/O pin CI- 10 pF -
Notes:
1. The min VILand max VIH values are based on the respective min and max OVIN values found in Table 3.
2. See the chip reference manual for information about the digital filter used.
3. I/O pins obstruct the SDA and SCL lines if OVDD is switched off.
4. For recommended operating conditions, see Table 3.
3.17.2 I2C AC timing specifications
This table provides the AC timing parameters for the I2C interfaces.
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Table 55. I2C AC timing specifications5
Parameter Symbol1Min Max Unit Notes
SCL clock frequency fI2C 0 400 kHz 2
Low period of the SCL clock tI2CL 1.3 - μs -
High period of the SCL clock tI2CH 0.6 - μs -
Setup time for a repeated START condition tI2SVKH 0.6 - μs -
Hold time (repeated) START condition (after this period, the first
clock pulse is generated)
tI2SXKL 0.6 - μs -
Data setup time tI2DVKH 100 - ns -
Data input hold time: tI2DXKL μs 3
CBUS compatible masters
I2C bus devices
-
0
-
-
Data output delay time tI2OVKL - 0.9 μs 4
Setup time for STOP condition tI2PVKH 0.6 - μs -
Bus free time between a STOP and START condition tI2KHDX 1.3 - μs -
Noise margin at the LOW level for each connected device
(including hysteresis)
VNL 0.1 x OVDD - V -
Noise margin at the HIGH level for each connected device
(including hysteresis)
VNH 0.2 x OVDD - V -
Capacitive load for each bus line Cb - 400 pF -
Notes:
1. The symbols used for timing specifications herein follow the pattern t(first two letters of functional block)(signal)(state)(reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tI2DVKH symbolizes I2C timing (I2) with
respect to the time data input signals (D) reaching the valid state (V) relative to the tI2C clock reference (K) going to the high
(H) state or setup time. Also, tI2SXKL symbolizes I2C timing (I2) for the time that the data with respect to the START condition
(S) went invalid (X) relative to the tI2C clock reference (K) going to the low (L) state or hold time. Also, tI2PVKH symbolizes I2C
timing (I2) for the time that the data with respect to the STOP condition (P) reaches the valid state (V) relative to the tI2C clock
reference (K) going to the high (H) state or setup time.
2. The requirements for I2C frequency calculation must be followed. See Determining the I2C Frequency Divider Ratio for
SCL (AN2919).
3. As a transmitter, the chip provides a delay time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL
signal) to bridge the undefined region of the falling edge of SCL to avoid unintended generation of a START or STOP
condition. When the chip acts as the I2C bus master while transmitting, it drives both SCL and SDA. As long as the load on
SCL and SDA are balanced, the chip does not generate an unintended START or STOP condition. Therefore, the 300 ns
SDA output delay time is not a concern. If, under some rare condition, the 300 ns SDA output delay time is required for the
chip as transmitter, see Determining the I2C Frequency Divider Ratio for SCL (AN2919).
4. The maximum tI2OVKL has to be met only if the device does not stretch the LOW period (tI2CL) of the SCL signal.
5. For recommended operating conditions, see Table 3.
This figure provides the AC test load for the I2C.
Electrical characteristics
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
94 NXP Semiconductors
Output Z0= 50 Ω
RL = 50 Ω
DVDD/2
Figure 29. I2C AC test load
This figure shows the AC timing diagram for the I2C bus.
SDA
SCL
SSr PS
tI2KHDX
tI2PVKH
tI2KHKL
tI2SVKH
tI2SXKL
tI2CH
tI2DVKH
tI2DXKL, tI2OVKL
tI2CL
tI2SXKL
Figure 30. I2C Bus AC timing diagram
3.18 GPIO interface
This section describes the DC and AC electrical characteristics for the GPIO interface.
3.18.1 GPIO DC electrical characteristics
This table provides the DC electrical characteristics for GPIO pins operating at LVDD =
2.5 V.
Table 56. GPIO DC electrical characteristics (2.5 V)3
Parameter Symbol Min Max Unit Notes
Input high voltage VIH 1.7 - V 1
Input low voltage VIL - 0.7 V 1
Input current (VIN = 0 V or VIN = LVDD) IIN -50 +50 μA 2
Output high voltage
(LVDD = min, IOH = -1 mA)
VOH 2.0 - V -
Table continues on the next page...
Electrical characteristics
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
NXP Semiconductors 95
Table 56. GPIO DC electrical characteristics (2.5 V)3 (continued)
Parameter Symbol Min Max Unit Notes
Output low voltage
(LVDD = min, IOL = 1 mA)
VOL - 0.4 V -
1. The min VILand max VIH values are based on the respective min and max LVIN values found in Table 3 .
2. The symbol VIN, in this case, represents the LVIN symbol referenced in Recommended operating conditions.
3. For recommended operating conditions, see Table 3.
This table provides the DC electrical characteristics for GPIO pins operating at LVDD or
OVDD= 1.8 V.
Table 57. GPIO DC electrical characteristics (1.8 V)3
Parameter Symbol Min Max Unit Notes
Input high voltage VIH 1.25 - V 1
Input low voltage VIL - 0.6 V 1
Input current (VIN = 0 V or VIN = L/OVDD) IIN - ±50 μA 2
Output high voltage
(L/OVDD = min, IOH = -0.5 mA)
VOH 1.35 - V -
Output low voltage
(L/OVDD = min, IOL = 0.5 mA)
VOL - 0.4 V -
1. The min VILand max VIH values are based on the respective min and max L/OVIN values found in Table 3.
2. The symbol VIN, in this case, represents the L/OVIN symbol referenced in Recommended operating conditions.
3. For recommended operating conditions, see Table 3.
3.18.2 GPIO AC timing specifications
This table provides the GPIO input and output AC timing specifications.
Table 58. GPIO input AC timing specifications2
Parameter Symbol Min Unit Notes
GPIO inputs—minimum pulse width tPIWID 20 ns 1
Notes:
1. GPIO inputs and outputs are asynchronous to any visible clock. GPIO outputs should be synchronized before use by any
external synchronous logic. GPIO inputs are required to be valid for at least tPIWID to ensure proper operation.
2. For recommended operating conditions, see Table 3.
This figure provides the AC test load for the GPIO.
Electrical characteristics
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
96 NXP Semiconductors
Output Z0= 50 Ω
RL = 50 Ω
(L/O) VDD/2
Figure 31. GPIO AC test load
3.19 High-speed serial interfaces (HSSI)
The chip features a serializer/deserializer (SerDes) interface to be used for high-speed
serial interconnect applications. The SerDes interface can be used for PCI Express,
SATA, Serial RapidIO, XAUI, XFI, Aurora, HiGig, SGMII and QSGMII data transfers.
This section describes the common portion of SerDes DC electrical specifications: the
DC requirement for SerDes reference clocks. The SerDes data lane's transmitter (Tx) and
receiver (Rx) reference circuits are also shown.
3.19.1 Signal terms definition
The SerDes utilizes differential signaling to transfer data across the serial link. This
section defines the terms that are used in the description and specification of differential
signals.
This figure shows how the signals are defined. For illustration purposes only, one SerDes
lane is used in the description. This figure shows the waveform for either a transmitter
output (SD_TXn_P and SD_TXn_N) or a receiver input (SD_RXn_P and SD_RXn_N).
Each signal swings between A volts and B volts where A > B.
Electrical characteristics
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
NXP Semiconductors 97
A Volts
B Volts
SD_TXn_P or
SD_RXn_P
SD_TXn_N or
SD_RXn_N
Vcm= (A + B)/2
Differential swing, VID orVOD = A - B
Differential peak voltage, VDIFFp = |A - B|
Differential peak-to-peak voltage, VDIFFpp =2 x VDIFFp (not shown)
Figure 32. Differential voltage definitions for transmitter or receiver
Using this waveform, the definitions are as shown in the following list. To simplify the
illustration, the definitions assume that the SerDes transmitter and receiver operate in a
fully symmetrical differential signaling environment:
Single-Ended Swing
The transmitter output signals and the receiver input signals SD_TXn_P, SD_TXn_N,
SD_RXn_P and SD_RXn_N each have a peak-to-peak swing of A - B volts. This is
also referred as each signal wire's single-ended swing.
Differential Output Voltage, VOD (or Differential Output Swing)
The differential output voltage (or swing) of the transmitter, VOD, is defined as the
difference of the two complimentary output voltages: VSD_TXn_P- VSD_TXn_N. The VOD
value can be either positive or negative.
Differential Input Voltage, VID (or Differential Input Swing)
The differential input voltage (or swing) of the receiver, VID, is defined as the
difference of the two complimentary input voltages: VSD_RXn_P- VSD_RXn_N. The VID
value can be either positive or negative.
Differential Peak Voltage, VDIFFp
The peak value of the differential transmitter output signal or the differential receiver
input signal is defined as the differential peak voltage, VDIFFp = |A - B| volts.
Differential Peak-to-Peak, VDIFFp-p
Since the differential output signal of the transmitter and the differential input signal of
the receiver each range from A - B to -(A - B) volts, the peak-to-peak value of the
differential transmitter output signal or the differential receiver input signal is defined
as differential peak-to-peak voltage, VDIFFp-p = 2 x VDIFFp = 2 x |(A - B)| volts, which
is twice the differential swing in amplitude, or twice of the differential peak. For
example, the output differential peak-to-peak voltage can also be calculated as VTX-
DIFFp-p = 2 x |VOD|.
Differential Waveform
The differential waveform is constructed by subtracting the inverting signal
(SD_TXn_N, for example) from the non-inverting signal (SD_TXn_P, for example)
Electrical characteristics
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
98 NXP Semiconductors
within a differential pair. There is only one signal trace curve in a differential
waveform. The voltage represented in the differential waveform is not referenced to
ground. See Figure 37 as an example for differential waveform.
Common Mode Voltage, Vcm
The common mode voltage is equal to half of the sum of the voltages between each
conductor of a balanced interchange circuit and ground. In this example, for SerDes
output, Vcm_out = (VSD_TXn_P+ VSD_TXn_N) ÷ 2 = (A + B) ÷ 2, which is the arithmetic
mean of the two complimentary output voltages within a differential pair. In a system,
the common mode voltage may often differ from one component's output to the other's
input. It may be different between the receiver input and driver output circuits within
the same component. It is also referred to as the DC offset on some occasions.
To illustrate these definitions using real values, consider the example of a current mode
logic (CML) transmitter that has a common mode voltage of 2.25 V and outputs, TD and
TD_B. If these outputs have a swing from 2.0 V to 2.5 V, the peak-to-peak voltage swing
of each signal (TD or TD_B) is 500 mV p-p, which is referred to as the single-ended
swing for each signal. Because the differential signaling environment is fully symmetrical
in this example, the transmitter output's differential swing (VOD) has the same amplitude
as each signal's single-ended swing. The differential output signal ranges between 500
mV and -500 mV. In other words, VOD is 500 mV in one phase and -500 mV in the other
phase. The peak differential voltage (VDIFFp) is 500 mV. The peak-to-peak differential
voltage (VDIFFp-p) is 1000 mV p-p.
3.19.2 SerDes reference clocks
The SerDes reference clock inputs are applied to an internal PLL whose output creates
the clock used by the corresponding SerDes lanes. The SerDes reference clocks inputs are
SD1_REF_CLK[1:2]_P and SD1_REF_CLK[1:2]_N for SerDes 1,
SD2_REF_CLK[1:2]_P and SD2_REF_CLK[1:2]_N for SerDes 2.
SerDes 1-2 may be used for various combinations of the following IP blocks based on the
RCW Configuration field SRDS_PRTCLn:
• SerDes 1: SGMII (1.25 and 3.125 GBaud), PEX3 (2.5, 5 and 8 GT/s), PEX4 (2.5 and
5 GT/s), HiGig/HiGig2 (3.125GBaud), HiGig/HiGig2 (3.75GBaud) or XAUI
(3.125GBaud)XFI (10.3125 GBaud only), 1000Base-KX (3.125GBaud), 10GBase-
KR (10.3125 GBaud only)
• SerDes 2: PEX1 (2.5, 5 and 8 GT/s), PEX2 (2.5 and 5 GT/s), Aurora (2.5 and 5
GBaud), SATA1/2 (1.5 and 3.0 Gbps) and SRIO1/2 (2.5, 3.125 and 5 GBaud)
The following sections describe the SerDes reference clock requirements and provide
application information.
Electrical characteristics
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
NXP Semiconductors 99
3.19.2.1 SerDes spread-spectrum clock source recommendations
SDn_REF_CLKn_P/SDn_REF_CLKn_N are designed to work with spread-spectrum
clock for PCI Express protocol only with the spreading specification defined in Table 59.
When using spread-spectrum clocking for PCI Express, both ends of the link partners
should use the same reference clock. For best results, a source without significant
unintended modulation must be used.
For SATA protocol, the SerDes transmitter does not support spread-spectrum clocking.
The SerDes receiver does support spread-spectrum clocking on receive, which means the
SerDes receiver can receive data correctly from a SATA serial link partner using spread-
spectrum clocking
The spread-spectrum clocking cannot be used if the same SerDes reference clock is
shared with other non-spread-spectrum supported protocols. For example, if the spread-
spectrum clocking is desired on a SerDes reference clock for PCI Express and the same
reference clock is used for any other protocol such as SATA/SGMII/QSGMII/SRIO/
XAUI due to the SerDes lane usage mapping option, spread-spectrum clocking cannot be
used at all.
Table 59. SerDes spread-spectrum clock source recommendations1
Parameter Min Max Unit Notes
Frequency modulation 30 33 kHz -
Frequency spread +0 -0.5 % 2
Notes:
1. At recommended operating conditions. See Table 3.
2. Only down-spreading is allowed.
3.19.2.2 SerDes reference clock receiver characteristics
This figure shows a receiver reference diagram of the SerDes reference clocks.
Electrical characteristics
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
100 NXP Semiconductors
Input
amp
50 Ω
50 Ω
SDn_REF_CLKn_P
SDn_REF_CLKn_N
Figure 33. Receiver of SerDes reference clocks
The characteristics of the clock signals are as follows:
•The SerDes transceivers core power supply voltage requirements (SVDDn) are as
specified in Recommended operating conditions.
• The SerDes reference clock receiver reference circuit structure is as follows:
•The SDn_REF_CLKn_P and SDn_REF_CLKn_N are internally AC-coupled
differential inputs as shown in Figure 33. Each differential clock input
(SDn_REF_CLKn_P or SDn_REF_CLKn_N) has on-chip 50-Ω termination to
SGNDnfollowed by on-chip AC-coupling.
• The external reference clock driver must be able to drive this termination.
• The SerDes reference clock input can be either differential or single-ended. See
the differential mode and single-ended mode descriptions below for detailed
requirements.
• The maximum average current requirement also determines the common mode
voltage range.
• When the SerDes reference clock differential inputs are DC coupled externally
with the clock driver chip, the maximum average current allowed for each input
pin is 8 mA. In this case, the exact common mode input voltage is not critical as
long as it is within the range allowed by the maximum average current of 8 mA
because the input is AC-coupled on-chip.
• This current limitation sets the maximum common mode input voltage to be less
than 0.4 V (0.4 V ÷ 50 = 8 mA) while the minimum common mode input level is
0.1 V above SGNDn. For example, a clock with a 50/50 duty cycle can be
produced by a clock driver with output driven by its current source from 0 mA to
16 mA (0-0.8 V), such that each phase of the differential input has a single-
ended swing from 0 V to 800 mV with the common mode voltage at 400 mV.
•If the device driving the SDn_REF_CLKn_P and SDn_REF_CLKn_N inputs
cannot drive 50 Ω to SGNDn DC or the drive strength of the clock driver chip
exceeds the maximum input current limitations, it must be AC-coupled off-chip.
• The input amplitude requirement is described in detail in the following sections.
Electrical characteristics
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
NXP Semiconductors 101
3.19.2.3 DC-level requirement for SerDes reference clocks
The DC level requirement for the SerDes reference clock inputs is different depending on
the signaling mode used to connect the clock driver chip and SerDes reference clock
inputs, as described below.
Differential mode:
• The input amplitude of the differential clock must be between 400 mV and 1600 mV
differential peak-to-peak (or between 200 mV and 800 mV differential peak). In
other words, each signal wire of the differential pair must have a single-ended swing
of less than 800 mV and greater than 200 mV. This requirement is the same for both
external DC-coupled or AC-coupled connection.
• For an external DC-coupled connection, as described in SerDes reference clock
receiver characteristics, the maximum average current requirements sets the
requirement for average voltage (common mode voltage) as between 100 mV and
400 mV. Figure 34 shows the SerDes reference clock input requirement for DC-
coupled connection scheme.
SDn_REF_CLKn_P
SDn_REF_CLKn_N
200 mV < Input amplitude or differential peak < 800 mV
Vmax < 800mV
100 mV < Vcm < 400 mV
Vmin > 0 V
Figure 34. Differential reference clock input DC requirements (external DC-coupled)
• For an external AC-coupled connection, there is no common mode voltage
requirement for the clock driver. Because the external AC-coupling capacitor blocks
the DC level, the clock driver and the SerDes reference clock receiver operate in
different common mode voltages. The SerDes reference clock receiver in this
connection scheme has its common mode voltage set to SGNDn. Each signal wire of
the differential inputs is allowed to swing below and above the common mode
voltage (SGNDn). Figure 35 shows the SerDes reference clock input requirement for
AC-coupled connection scheme.
Electrical characteristics
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
102 NXP Semiconductors
SDn_REF_CLKn_P
SDn_REF_CLK_N
200 mV < Input amplitude or differential peak < 800 mV
Vmax < Vcm + 400 mV
Vmin > Vcm - 400 mV
Vcm
Figure 35. Differential reference clock input DC requirements (external AC-coupled)
Single-ended mode:
• The reference clock can also be single-ended. The SDn_REF_CLKn_P input
amplitude (single-ended swing) must be between 400 mV and 800 mV peak-to-peak
(from VMIN to VMAX) with SDn_REF_CLKn_N either left unconnected or tied to
ground.
• The SDn_REF_CLKn_P input average voltage must be between 200 and 400 mV.
Figure 36 shows the SerDes reference clock input requirement for single-ended
signaling mode.
• To meet the input amplitude requirement, the reference clock inputs may need to be
DC- or AC-coupled externally. For the best noise performance, the reference of the
clock could be DC- or AC-coupled into the unused phase (SDn_REF_CLKn_N)
through the same source impedance as the clock input (SDn_REF_CLKn_P) in use.
400 mV < SD_REF_CLKn input amplitude < 800 mV
SDn_REF_CLKn_P
SDn_REF_CLKn_N
0 V
Figure 36. Single-ended reference clock input DC requirements
3.19.2.4 AC requirements for SerDes reference clocks
This table lists the AC requirements for SerDes reference clocks for protocols running at
data rates up to 8 GBaud.
Electrical characteristics
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
NXP Semiconductors 103
This includes PCI Express (2.5, 5 and 8 GT/s), SGMII (1.25GBaud), 2.5x SGMII (3.125
GBaud), Serial RapidIO (2.5, 3.125 and 5 GBaud), Aurora (2.5 and 5 GBaud), HiGig/
HiGig2 (3.125 GBaud), HiGig/HiGig2 (3.75 GBaud), XAUI (3.125 GBaud), SATA (1.5
and 3 Gbps), 1000Base-KX (3.125 GBaud) and SerDes reference clocks to be guaranteed
by the customer's application design.
Table 60. SDn_REF_CLKn_P/ SDn_REF_CLKn_N input clock requirements (SVDDn = 1.0 V)1
Parameter Symbol Min Typ Max Unit Notes
SDn_REF_CLKn_P/ SDn_REF_CLKn_N frequency
range
tCLK_REF - 100/125/156.25 - MHz 2
SDn_REF_CLKn_P/ SDn_REF_CLKn_N clock
frequency tolerance
tCLK_TOL -300 - 300 ppm 3
SDn_REF_CLKn_P/ SDn_REF_CLKn_N clock
frequency tolerance
tCLK_TOL -100 - 100 ppm 4
SDn_REF_CLKn_P/ SDn_REF_CLKn_N reference
clock duty cycle
tCLK_DUTY 40 50 60 % 5
SDn_REF_CLKn_P/ SDn_REF_CLKn_N max
deterministic peak-to-peak jitter at 10-6 BER
tCLK_DJ - - 42 ps -
SDn_REF_CLKn_P/ SDn_REF_CLKn_N total
reference clock jitter at 10-6 BER (peak-to-peak jitter
at refClk input)
tCLK_TJ - - 86 ps 6
SDn_REF_CLKn_P/ SDn_REF_CLKn_N 10 kHz to
1.5 MHz RMS jitter
tREFCLK-LF-RMS - - 3 ps
RMS
7
SDn_REF_CLKn_P/ SDn_REF_CLKn_N > 1.5 MHz
to Nyquist RMS jitter
tREFCLK-HF-RMS - - 3.1 ps
RMS
7
SDn_REF_CLKn_P/ SDn_REF_CLKn_N RMS
reference clock jitter
tREFCLK-RMS-DC - - 1 ps
RMS
8
SDn_REF_CLKn_P/ SDn_REF_CLKn_N rising/
falling edge rate
tCLKRR/tCLKFR 1 - 4 V/ns 9
Differential input high voltage VIH 200 - - mV 5
Differential input low voltage VIL - - -200 mV 5
Rising edge rate (SDn_REF_CLKn_P) to falling
edge rate (SDn_REF_CLKn_P) matching
Rise-Fall
Matching
- - 20 % 10, 11
Notes:
1. For recommended operating conditions, see Table 3.
2. Caution: Only 100, 125 and 156.25 have been tested.In-between values do not work correctly with the rest of the system.
3. For PCI Express (2.5, 5, 8 GT/s)
4. For SGMII, 2.5x SGMII, QSGMII, sRIO, HiGig/HiGig2, XAUI
5. Measurement taken from differential waveform
6. Limits from PCI Express CEM Rev 2.0
7. For PCI Express-5 GT/s, per PCI Express base specification rev 3.0
8. For PCI-Express-8 GT/s, per PCI-Express base specification rev 3.0
9. Measured from -200 mV to +200 mV on the differential waveform (derived from SDn_REF_CLKn_P minus
SDn_REF_CLKn_N). The signal must be monotonic through the measurement region for rise and fall time. The 400 mV
measurement window is centered on the differential zero crossing. See Figure 37.
Electrical characteristics
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
104 NXP Semiconductors
Table 60. SDn_REF_CLKn_P/ SDn_REF_CLKn_N input clock requirements (SVDDn = 1.0 V)1
Parameter Symbol Min Typ Max Unit Notes
10. Measurement taken from single-ended waveform
11. Matching applies to rising edge for SDn_REF_CLKn_P and falling edge rate for SDn_REF_CLKn_N. It is measured using
a 200 mV window centered on the median cross point where SDn_REF_CLKn_P rising meets SDn_REF_CLKn_N falling.
The median cross point is used to calculate the voltage thresholds that the oscilloscope uses for the edge rate calculations.
The rise edge rate of SDn_REF_CLKn_P must be compared to the fall edge rate of SDn_REF_CLKn_N, the maximum
allowed difference should not exceed 20% of the slowest edge rate. See Figure 38.
This table lists the AC requirements for SerDes reference clocks for protocols running at
data rates greater than 8 GBaud.
This includes XFI (10.3125 GBaud) and 10GBase-KR (10.3125 GBaud), SerDes
reference clocks to be guaranteed by the customer's application design.
Table 61. SDn_REF_CLKn_P/ SDn_REF_CLKn_N input clock requirements (SVDDn = 1.0 V)1
Parameter Symbol Min Typ Max Unit Notes
SDn_REF_CLKn_P/ SDn_REF_CLKn_N frequency range tCLK_REF - 156.25 - MHz 2
SDn_REF_CLKn_P/ SDn_REF_CLKn_N clock frequency
tolerance
tCLK_TOL -100 - 100 ppm -
SDn_REF_CLKn_P/ SDn_REF_CLKn_N reference clock
duty cycle
tCLK_DUTY 40 50 60 % 3
SDn_REF_CLKn_P/ SDn_REF_CLKn_N single side band
noise
@1 kHz - - -85 dBC/Hz 4
SDn_REF_CLKn_P/ SDn_REF_CLKn_N single side band
noise
@10 kHz - - -108 dBC/Hz 4
SDn_REF_CLKn_P/ SDn_REF_CLKn_N single side band
noise
@100
kHz
- - -128 dBC/Hz 4
SDn_REF_CLKn_P/ SDn_REF_CLKn_N single side band
noise
@1 MHz - - -138 dBC/Hz 4
SDn_REF_CLKn-P/ SDn_REF_CLKn_N single side band
noise
@10MHz - - -138 dBC/Hz 4
SDn_REF_CLKn_P/ SDn_REF_CLKn_N random jitter (1.2
MHz to 15 MHz)
tCLK_RJ - - 0.8 ps -
SDn_REF_CLKn_P/ SDn_REF_CLKn_N total reference
clock jitter at 10-12 BER (1.2 MHz to 15 MHz)
tCLK_TJ - - 11 ps -
SDn_REF_CLKn_P/ SDn_REF_CLKn_N spurious noise (1.2
MHz to 15 MHz)
- - - -75 dBC -
Notes:
1. For recommended operating conditions, see Table 3.
2. Caution: Only 156.25 have been tested. In-between values do not work correctly with the rest of the system.
3. Measurement taken from differential waveform.
4. Per XFP Spec. Rev 4.5, the Module Jitter Generation spec at XFI Optical Output is 10mUI (RMS) and 100 mUI (p-p). In the
CDR mode the host is contributing 7 mUI (RMS) and 50 mUI (p-p) jitter.
Electrical characteristics
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
NXP Semiconductors 105
Rise-edge rate Fall-edge rate
VIH = + 200 mV
0.0 V
VIL = - 200 mV
SDn_REF_CLKn_P
SDn_REF_CLKn_N
Figure 37. Differential measurement points for rise and fall time
TFALL TRISE
SDn_REF_CLKn_N
SDn_REF_CLKn_P
VCROSS MEDIAN + 100 mV
VCROSS MEDIAN - 100 mV
SDn_REF_CLKn_N
SDn_REF_CLKn_P
VCROSS MEDIAN
VCROSS MEDIAN
Figure 38. Single-ended measurement points for rise and fall time matching
3.19.3 SerDes transmitter and receiver reference circuits
This figure shows the reference circuits for SerDes data lane's transmitter and receiver.
50 Ω
50 Ω
SDn_RXn_P
SDn_RXn_N
Receiver
100 ΩTransmitter
SDn_TXn_P
SDn_TXn_N
Figure 39. SerDes transmitter and receiver reference circuits
Electrical characteristics
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
106 NXP Semiconductors
The DC and AC specification of SerDes data lanes are defined in each interface protocol
section below based on the application usage:
•PCI Express
•Serial RapidIO (sRIO)
•XAUI interface
•Aurora interface
•Serial ATA (SATA) interface
•SGMII interface
•HiGig/HiGig2 interface
•XFI interface
•10GBase-KR interface
•1000Base-KX interface
Note that external AC-coupling capacitor is required for the above serial transmission
protocols with the capacitor value defined in the specification of each protocol section.
3.19.4 PCI Express
This section describes the clocking dependencies, DC and AC electrical specifications for
the PCI Express bus.
3.19.4.1 Clocking dependencies
The ports on the two ends of a link must transmit data at a rate that is within 600 parts per
million (ppm) of each other at all times. This is specified to allow bit rate clock sources
with a ±300 ppm tolerance.
3.19.4.2 PCI Express clocking requirements for SDn_REF_CLKn_P and
SDn_REF_CLKn_N
SerDes 1-2 (SD[1:2]_REF_CLK[1:2]_P and SD[1:2]_REF_CLK[1:2]_N) may be used
for various SerDes PCI Express configurations based on the RCW Configuration field
SRDS_PRTCL. PCI Express is not supported on SerDes 1 and 2.
NOTE
PCI Express operating in x8 mode is only supported at 2.5 and
5.0 GT/s.
For more information on these specifications, see SerDes reference clocks.
Electrical characteristics
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
NXP Semiconductors 107
3.19.4.3 PCI Express DC physical layer specifications
This section contains the DC specifications for the physical layer of PCI Express on this
chip.
3.19.4.3.1 PCI Express DC physical layer transmitter specifications
This section discusses the PCI Express DC physical layer transmitter specifications for
2.5 GT/s, 5 GT/s and 8 GT/s.
This table defines the PCI Express 2.0 (2.5 GT/s) DC specifications for the differential
output at all transmitters. The parameters are specified at the component pins.
Table 62. PCI Express 2.0 (2.5 GT/s) differential transmitter output DC specifications (XVDD
= 1.35 V)1
Parameter Symbol Min Typical Max Units Notes
Differential peak-to-peak
output voltage
VTX-DIFFp-p 800 1000 1200 mV VTX-DIFFp-p = 2 x │ VTX-D+ - VTX-D- │
De-emphasized differential
output voltage (ratio)
VTX-DE-RATIO 3.0 3.5 4.0 dB Ratio of the VTX-DIFFp-p of the second and
following bits after a transition divided by the VTX-
DIFFp-p of the first bit after a transition.
DC differential transmitter
impedance
ZTX-DIFF-DC 80 100 120 Ω Transmitter DC differential mode low Impedance
Transmitter DC impedance ZTX-DC 40 50 60 Ω Required transmitter D+ as well as D- DC
Impedance during all states
Notes:
1. For recommended operating conditions, see Table 3.
This table defines the PCI Express 2.0 (5 GT/s) DC specifications for the differential
output at all transmitters. The parameters are specified at the component pins.
Table 63. PCI Express 2.0 (5 GT/s) differential transmitter output DC specifications (XVDD =
1.35 V)1
Parameter Symbol Min Typical Max Units Notes
Differential peak-to-peak
output voltage
VTX-DIFFp-p 800 1000 1200 mV VTX-DIFFp-p = 2 x │ VTX-D+ - VTX-D- │
Low power differential
peak-to-peak output
voltage
VTX-DIFFp-p_low 400 500 1200 mV VTX-DIFFp-p = 2 x │ VTX-D+ - VTX-D- │
De-emphasized differential
output voltage (ratio)
VTX-DE-RATIO-3.5dB 3.0 3.5 4.0 dB Ratio of the VTX-DIFFp-p of the second and
following bits after a transition divided by the
VTX-DIFFp-p of the first bit after a transition.
De-emphasized differential
output voltage (ratio)
VTX-DE-RATIO-6.0dB 5.5 6.0 6.5 dB Ratio of the VTX-DIFFp-p of the second and
following bits after a transition divided by the
VTX-DIFFp-p of the first bit after a transition.
Table continues on the next page...
Electrical characteristics
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
108 NXP Semiconductors
Table 63. PCI Express 2.0 (5 GT/s) differential transmitter output DC specifications (XVDD =
1.35 V)1 (continued)
Parameter Symbol Min Typical Max Units Notes
DC differential transmitter
impedance
ZTX-DIFF-DC 80 100 120 Ω Transmitter DC differential mode low
impedance
Transmitter DC
Impedance
ZTX-DC 40 50 60 Ω Required transmitter D+ as well as D- DC
impedance during all states
Notes:
1. For recommended operating conditions, see Table 3.
This table defines the PCI Express 3.0 (8 GT/s) DC specifications for the differential
output at all transmitters. The parameters are specified at the component pins.
Table 64. PCI Express 3.0 (8 GT/s) differential transmitter output DC specifications (XVDD =
1.35 V )3
Parameter Symbol Min Typical Max Units Notes
Full swing transmitter
voltage with no TX Eq
VTX-FS-NO-EQ 800 - 1300 mVp-p See Note 1.
Reduced swing
transmitter voltage with
no TX Eq
VTX-RS-NO-EQ 400 - 1300 mV See Note 1.
De-emphasized
differential output voltage
(ratio)
VTX-DE-RATIO-3.5dB 3.0 3.5 4.0 dB -
De-emphasized
differential output voltage
(ratio)
VTX-DE-RATIO-6.0dB 5.5 6.0 6.5 dB -
Minimum swing during
EIEOS for full swing
VTX-EIEOS-FS 250 - - mVp-p See Note 2
Minimum swing during
EIEOS for reduced swing
VTX-EIEOS-RS 232 - - mVp-p See Note 2
DC differential transmitter
impedance
ZTX-DIFF-DC 80 100 120 Ω Transmitter DC differential mode low
impedance
Transmitter DC
Impedance
ZTX-DC 40 50 60 Ω Required transmitter D+ as well as D- DC
impedance during all states
Notes:
1. Voltage measurements for VTX-FS-NO-EQ and VTX-RS-NO-EQ are made using the 64-zeroes/64-ones pattern in the compliance
pattern.
2. Voltage limits comprehend both full swing and reduced swing modes. The transmitter must reject any changes that would
violate this specification. The maximum level is covered in the VTX-FS-NO-EQ measurement which represents the maximum
peak voltage the transmitter can drive. The VTX-EIEOS-FS and VTX-EIEOS-RS voltage limits are imposed to guarantee the EIEOS
threshold of 175 mVP-P at the receiver pin. This parameter is measured using the actual EIEOS pattern that is part of the
compliance pattern and then removing the ISI contribution of the breakout channel.
3. For recommended operating conditions, see Table 3.
Electrical characteristics
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
NXP Semiconductors 109
3.19.4.4 PCI Express DC physical layer receiver specifications
This section discusses the PCI Express DC physical layer receiver specifications for 2.5
GT/s, 5 GT/s and 8 GT/s.
This table defines the DC specifications for the PCI Express 2.0 (2.5 GT/s) differential
input at all receivers. The parameters are specified at the component pins.
Table 65. PCI Express 2.0 (2.5 GT/s) differential receiver input DC specifications (SVDD = 1.0
V)4
Parameter Symbol Min Typ Max Units Notes
Differential input peak-to-peak
voltage
VRX-DIFFp-p 120 1000 1200 mV VRX-DIFFp-p = 2 x |VRX-D+ - VRX-D-| See
Note 1.
DC differential input impedance ZRX-DIFF-DC 80 100 120 Ω Receiver DC differential mode
impedance. See Note 2
DC input impedance ZRX-DC 40 50 60 Ω Required receiver D+ as well as D- DC
Impedance (50 ± 20% tolerance). See
Notes 1 and 2.
Powered down DC input impedance ZRX-HIGH-IMP-DC 50 - - kΩ Required receiver D+ as well as D- DC
Impedance when the receiver
terminations do not have power. See
Note 3.
Electrical idle detect threshold VRX-IDLE-DET-
DIFFp-p
65 - 175 mV VRX-IDLE-DET-DIFFp-p = 2 x |VRX-D+ -VRX-
D-|
Measured at the package pins of the
receiver
Notes:
1. Measured at the package pins with a test load of 50Ω to GND on each pin.
2. Impedance during all LTSSM states. When transitioning from a fundamental reset to detect (the initial state of the LTSSM)
there is a 5 ms transition time before receiver termination values must be met on all unconfigured lanes of a port.
3. The receiver DC common mode impedance that exists when no power is present or fundamental reset is asserted. This
helps ensure that the receiver detect circuit does not falsely assume a receiver is powered on when it is not. This term must
be measured at 300 mV above the receiver ground.
4. For recommended operating conditions, see Table 3.
This table defines the DC specifications for the PCI Express 2.0 (5 GT/s) differential
input at all receivers. The parameters are specified at the component pins.
Table 66. PCI Express 2.0 (5 GT/s) differential receiver input DC specifications (SVDD = 1.0
V)4
Parameter Symbol Min Typ Max Units Notes
Differential input peak-to-peak voltage VRX-DIFFp-p 120 1000 1200 mV VRX-DIFFp-p = 2 x |VRX-D+ - VRX-D-|
See Note 1.
DC differential input impedance ZRX-DIFF-DC 80 100 120 Ω Receiver DC differential mode
impedance. See Note 2
Table continues on the next page...
Electrical characteristics
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
110 NXP Semiconductors
Table 66. PCI Express 2.0 (5 GT/s) differential receiver input DC specifications (SVDD = 1.0
V)4 (continued)
Parameter Symbol Min Typ Max Units Notes
DC input impedance ZRX-DC 40 50 60 Ω Required receiver D+ as well as D-
DC Impedance (50 ± 20%
tolerance). See Notes 1 and 2.
Powered down DC input impedance ZRX-HIGH-IMP-DC 50 - - kΩ Required receiver D+ as well as D-
DC Impedance when the receiver
terminations do not have power.
See Note 3.
Electrical idle detect threshold VRX-IDLE-DET-
DIFFp-p
65 - 175 mV VRX-IDLE-DET-DIFFp-p = 2 x |VRX-D+ -
VRX-D-|
Measured at the package pins of
the receiver
Notes:
1. Measured at the package pins with a test load of 50 Ω to GND on each pin.
2. Impedance during all LTSSM states. When transitioning from a fundamental reset to detect (the initial state of the LTSSM)
there is a 5 ms transition time before receiver termination values must be met on all unconfigured lanes of a port.
3. The receiver DC common mode impedance that exists when no power is present or fundamental reset is asserted. This
helps ensure that the receiver detect circuit does not falsely assume a receiver is powered on when it is not. This term must
be measured at 300 mV above the receiver ground.
4. For recommended operating conditions, see Table 3.
This table defines the DC specifications for the PCI Express 3.0 (8 GT/s) differential
input at all receivers. The parameters are specified at the component pins.
Table 67. PCI Express 3.0 (8 GT/s) differential receiver input DC specifications (SVDD = 1.0
V)6
Parameter Symbol Min Typ Max Units Notes
DC differential input impedance ZRX-DIFF-DC 80 100 120 Ω Receiver DC differential mode
impedance. See Note 2
DC input impedance ZRX-DC 40 50 60 Ω Required receiver D+ as well as D-
DC Impedance (50 ± 20%
tolerance). See Notes 1 and 2.
Powered down DC input impedance ZRX-HIGH-IMP-DC 50 - - kΩ Required receiver D+ as well as D-
DC Impedance when the receiver
terminations do not have power.
See Note 3.
Generator launch voltage VRX-LAUNCH-8G - 800 - mV Measured at TP1 per PCI Express
base spec. rev 3.0
Eye height (-20dB Channel) VRX-SV-8G 25 - - mV Measured at TP2P per PCI Express
base spec. rev 3.0. See Notes 4, 5
Eye height (-12dB Channel) VRX-SV-8G 50 - - mV Measured at TP2P per PCI Express
base spec. rev 3.0. See Notes 4, 5
Eye height (-3dB Channel) VRX-SV-8G 200 - - mV Measured at TP2P per PCI Express
base spec. rev 3.0. See Notes 4, 5
Table continues on the next page...
Electrical characteristics
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
NXP Semiconductors 111
Table 67. PCI Express 3.0 (8 GT/s) differential receiver input DC specifications (SVDD = 1.0
V)6 (continued)
Parameter Symbol Min Typ Max Units Notes
Electrical idle detect threshold VRX-IDLE-DET-
DIFFp-p
65 - 175 mV VRX-IDLE-DET-DIFFp-p = 2 x |VRX-D+ -
VRX-D-|
Measured at the package pins of
the receiver
Notes:
1. Measured at the package pins with a test load of 50Ω to GND on each pin.
2. Impedance during all LTSSM states. When transitioning from a fundamental reset to detect (the initial state of the LTSSM)
there is a 5 ms transition time before receiver termination values must be met on all unconfigured lanes of a port.
3. The receiver DC common mode impedance that exists when no power is present or fundamental reset is asserted. This
helps ensure that the receiver detect circuit does not falsely assume a receiver is powered on when it is not. This term must
be measured at 300 mV above the receiver ground.
4. VRX-SV-8G is tested at three different voltages to ensure the receiver device under test is capable of equalizing over a range
of channel loss profiles. The "SV" in the parameter names refers to stressed voltage.
5. VRX-SV-8G is referenced to TP2P and is obtained after post processing data captured at TP2.
6. For recommended operating conditions, see Table 3.
3.19.4.5 PCI Express AC physical layer specifications
This section contains the AC specifications for the physical layer of PCI Express on this
device.
3.19.4.5.1 PCI Express AC physical layer transmitter specifications
This section discusses the PCI Express AC physical layer transmitter specifications for
2.5 GT/s, 5 GT/s and 8 GT/s.
This table defines the PCI Express 2.0 (2.5 GT/s) AC specifications for the differential
output at all transmitters. The parameters are specified at the component pins. The AC
timing specifications do not include RefClk jitter.
Table 68. PCI Express 2.0 (2.5 GT/s) differential transmitter output AC specifications4
Parameter Symbol Min Typ Max Units Notes
Unit interval UI 399.88 400 400.12 ps Each UI is 400 ps ± 300 ppm. UI does not
account for spread-spectrum clock dictated
variations.
Minimum transmitter eye
width
TTX-EYE 0.75 - - UI The maximum transmitter jitter can be
derived as TTX-MAX-JITTER = 1 - TTX-EYE =
0.25 UI. Does not include spread-spectrum
or RefCLK jitter. Includes device random
jitter at 10-12.
See Notes 1 and 2.
Table continues on the next page...
Electrical characteristics
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
112 NXP Semiconductors
Table 68. PCI Express 2.0 (2.5 GT/s) differential transmitter output AC specifications4
(continued)
Parameter Symbol Min Typ Max Units Notes
Maximum time between the
jitter median and maximum
deviation from the median
TTX-EYE-MEDIAN-
to- MAX-JITTER
- - 0.125 UI Jitter is defined as the measurement
variation of the crossing points (VTX-DIFFp-p =
0 V) in relation to a recovered transmitter
UI. A recovered transmitter UI is calculated
over 3500 consecutive unit intervals of
sample data. Jitter is measured using all
edges of the 250 consecutive UI in the
center of the 3500 UI used for calculating
the transmitter UI. See Notes 1 and 2.
AC coupling capacitor CTX 75 - 200 nF All transmitters must be AC coupled. The
AC coupling is required either within the
media or within the transmitting component
itself. See Note 3.
Notes:
1. Specified at the measurement point into a timing and voltage test load as shown in Figure 41 and measured over any 250
consecutive transmitter UIs.
2. A TTX-EYE = 0.75 UI provides for a total sum of deterministic and random jitter budget of TTX-JITTER-MAX = 0.25 UI for the
transmitter collected over any 250 consecutive transmitter UIs. The TTX-EYE-MEDIAN-to-MAX-JITTER median is less than half of the
total transmitter jitter budget collected over any 250 consecutive transmitter UIs. It must be noted that the median is not the
same as the mean. The jitter median describes the point in time where the number of jitter points on either side is
approximately equal as opposed to the averaged time value.
3. The chip's SerDes transmitter does not have CTX built-in. An external AC coupling capacitor is required.
4. For recommended operating conditions, see Table 3.
This table defines the PCI Express 2.0 (5 GT/s) AC specifications for the differential
output at all transmitters. The parameters are specified at the component pins. The AC
timing specifications do not include RefClk jitter.
Table 69. PCI Express 2.0 (5 GT/s) differential transmitter output AC specifications3
Parameter Symbol Min Typ Max Units Notes
Unit Interval UI 199.94 200.00 200.06 ps Each UI is 200 ps ± 300 ppm. UI does not
account for spread-spectrum clock dictated
variations.
Minimum transmitter eye width TTX-EYE 0.75 - - UI The maximum transmitter jitter can be
derived as: TTX-MAX-JITTER = 1 - TTX-EYE =
0.25 UI.
See Note 1.
Transmitter RMS deterministic
jitter > 1.5 MHz
TTX-HF-DJ-DD - - 0.15 ps -
Transmitter RMS deterministic
jitter < 1.5 MHz
TTX-LF-RMS - 3.0 - ps Reference input clock RMS jitter (< 1.5
MHz) at pin < 1 ps
AC coupling capacitor CTX 75 - 200 nF All transmitters must be AC coupled. The
AC coupling is required either within the
media or within the transmitting component
itself. See Note 2.
Table continues on the next page...
Electrical characteristics
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
NXP Semiconductors 113
Table 69. PCI Express 2.0 (5 GT/s) differential transmitter output AC specifications3
(continued)
Parameter Symbol Min Typ Max Units Notes
Notes:
1. Specified at the measurement point into a timing and voltage test load as shown in Figure 41 and measured over any 250
consecutive transmitter UIs.
2. The chip's SerDes transmitter does not have CTX built-in. An external AC coupling capacitor is required.
3. For recommended operating conditions, see Table 3.
This table defines the PCI Express 3.0 (8 GT/s) AC specifications for the differential
output at all transmitters. The parameters are specified at the component pins. The AC
timing specifications do not include RefClk jitter.
Table 70. PCI Express 3.0 (8 GT/s) differential transmitter output AC specifications4
Parameter Symbol Min Typ Max Units Notes
Unit Interval UI 124.9625 125.00 125.0375 ps Each UI is 125 ps ± 300 ppm. UI does
not account for spread-spectrum clock
dictated variations.
Transmitter uncorrelated total
jitter
TTX-UTJ - - 31.25 ps p-p -
Transmitter uncorrelated
deterministic jitter
TTX-UDJ-DD - - 12 ps p-p -
Total uncorrelated pulse width
jitter (PWJ)
TTX-UPW-TJ - - 24 ps p-p See Note 1, 2
Deterministic data dependent
jitter (DjDD) uncorrelated
pulse width jitter (PWJ)
TTX-UPW-DJDD - - 10 ps p-p See Note 1, 2
Data dependent jitter TTX-DDJ - - 18 ps p-p See Note 2
AC coupling capacitor CTX 176 - 265 nF All transmitters must be AC coupled.
The AC coupling is required either
within the media or within the
transmitting component itself. See
Note 3.
Notes:
1. PWJ parameters shall be measured after data dependent jitter (DDJ) separation.
2. Measured with optimized preset value after de-embedding to transmitter pin.
3. The chip's SerDes transmitter does not have CTX built-in. An external AC coupling capacitor is required.
4. For recommended operating conditions, see Table 3.
3.19.4.5.2 PCI Express AC physical layer receiver specifications
This section discusses the PCI Express AC physical layer receiver specifications for 2.5
GT/s, 5 GT/s and 8 GT/s.
Electrical characteristics
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
114 NXP Semiconductors
This table defines the AC specifications for the PCI Express 2.0 (2.5 GT/s) differential
input at all receivers. The parameters are specified at the component pins. The AC timing
specifications do not include RefClk jitter.
Table 71. PCI Express 2.0 (2.5 GT/s) differential receiver input AC specifications4
Parameter Symbol Min Typ Max Units Notes
Unit Interval UI 399.88 400.00 400.12 ps Each UI is 400 ps ± 300 ppm. UI does not
account for spread-spectrum clock
dictated variations.
Minimum receiver eye width TRX-EYE 0.4 - - UI The maximum interconnect media and
transmitter jitter that can be tolerated by
the receiver can be derived as TRX-MAX-
JITTER = 1 - TRX-EYE= 0.6 UI.
See Notes 1 and 2.
Maximum time between the
jitter median and maximum
deviation from the median.
TRX-EYE-MEDIAN-
to-MAX-JITTER
- - 0.3 UI Jitter is defined as the measurement
variation of the crossing points (VRX-DIFFp-p
= 0 V) in relation to a recovered
transmitter UI. A recovered transmitter UI
is calculated over 3500 consecutive unit
intervals of sample data. Jitter is
measured using all edges of the 250
consecutive UI in the center of the 3500
UI used for calculating the transmitter UI.
See Notes 1, 2 and 3.
Notes:
1. Specified at the measurement point and measured over any 250 consecutive UIs. The test load in Figure 41 must be used
as the receiver device when taking measurements. If the clocks to the receiver and transmitter are not derived from the same
reference clock, the transmitter UI recovered from 3500 consecutive UI must be used as a reference for the eye diagram.
2. A TRX-EYE = 0.40 UI provides for a total sum of 0.60 UI deterministic and random jitter budget for the transmitter and
interconnect collected any 250 consecutive UIs. The TRX-EYE-MEDIAN-to-MAX-JITTER specification ensures a jitter
distribution in which the median and the maximum deviation from the median is less than half of the total. UI jitter budget
collected over any 250 consecutive transmitter UIs. It must be noted that the median is not the same as the mean. The jitter
median describes the point in time where the number of jitter points on either side is approximately equal as opposed to the
averaged time value. If the clocks to the receiver and transmitter are not derived from the same reference clock, the
transmitter UI recovered from 3500 consecutive UI must be used as the reference for the eye diagram.
3. It is recommended that the recovered transmitter UI is calculated using all edges in the 3500 consecutive UI interval with a
fit algorithm using a minimization merit function. Least squares and median deviation fits have worked well with experimental
and simulated data.
4. For recommended operating conditions, see Table 3.
This table defines the AC specifications for the PCI Express 2.0 (5 GT/s) differential
input at all receivers. The parameters are specified at the component pins. The AC timing
specifications do not include RefClk jitter.
Electrical characteristics
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
NXP Semiconductors 115
Table 72. PCI Express 2.0 (5 GT/s) differential receiver input AC specifications1
Parameter Symbol Min Typ Max Units Notes
Unit Interval UI 199.94 200.00 200.06 ps Each UI is 200 ps ± 300 ppm. UI does
not account for spread-spectrum clock
dictated variations.
Max receiver inherent timing
error
TRX-TJ-CC - - 0.4 UI The maximum inherent total timing error
for common RefClk receiver architecture
Max receiver inherent
deterministic timing error
TRX-DJ-DD-CC - - 0.30 UI The maximum inherent deterministic
timing error for common RefClk receiver
architecture
Note:
1. For recommended operating conditions, see Table 3.
This table defines the AC specifications for the PCI Express 3.0 (8 GT/s) differential
input at all receivers. The parameters are specified at the component pins. The AC timing
specifications do not include RefClk jitter.
Table 73. PCI Express 3.0 (8 GT/s) differential receiver input AC specifications5
Parameter Symbol Min Typ Max Units Notes
Unit Interval UI 124.9625 125.00 125.0375 ps Each UI is 125 ps ± 300 ppm. UI
does not account for spread-
spectrum clock dictated variations.
See Note 1.
Eye Width at TP2P TRX-SV-8G 0.3 - 0.35 UI See Note 1
Differential mode interference VRX-SV-DIFF-8G 14 - - mV Frequency = 2.1GHz. See Note 2.
Sinusoidal Jitter at 100 MHz TRX-SV-SJ-8G - - 0.1 UI p-p Fixed at 100 MHz. See Note 3.
Random Jitter TRX-SV-RJ-8G - - 2.0 ps
RMS
Random jitter spectrally flat before
filtering. See Note 4.
Note:
1. TRX-SV-8G is referenced to TP2P and obtained after post processing data captured at TP2. TRX-SV-8G includes the effects of
applying the behavioral receiver model and receiver behavioral equalization.
2. VRX-SV-DIFF-8G voltage may need to be adjusted over a wide range for the different loss calibration channels.
3. The sinusoidal jitter in the total jitter tolerance may have any amplitude and frequency as shown in Figure 40.
4. Random jitter (Rj) is applied over the following range: The low frequency limit may be between 1.5 and 10 MHz, and the
upper limit is 1.0 GHz. See Figure 40 for details. Rj may be adjusted to meet the 0.3 UI value for TRX-SV-8G.
5. For recommended operating conditions, see Table 3.
Electrical characteristics
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
116 NXP Semiconductors
20 dB
decade
~ 3.0 ps RMS
1000 MHz100 MHz10 MHz1.0 MHz0.1 MHz0.01 MHz
1.0 UI
0.1 UI
0.03 MHz 100 MHz
Rj
Sj
Sj sweep range
Rj (ps RMS)
Sj (UI PP)
Figure 40. Swept sinusoidal jitter mask
3.19.4.6 Test and measurement load
The AC timing and voltage parameters must be verified at the measurement point. The
package pins of the device must be connected to the test/measurement load within 0.2
inches of that load, as shown in the following figure.
NOTE
The allowance of the measurement point to be within 0.2 inches
of the package pins is meant to acknowledge that package/
board routing may benefit from D+ and D- not being exactly
matched in length at the package pin boundary. If the vendor
does not explicitly state where the measurement point is
located, the measurement point is assumed to be the D+ and D-
package pins.
Electrical characteristics
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
NXP Semiconductors 117
Transmitter
silicon
+ package
D + package pin
D - package pin
C = CTX
C = CTX
R = 50 Ω R = 50 Ω
Figure 41. Test/measurement load
3.19.5 Serial RapidIO (sRIO)
This section describes the DC and AC electrical specifications for the serial RapidIO
interface of the LP-Serial physical layer. The electrical specifications cover both single
and multiple-lane links. Two transmitters (short run and long run) and a single receiver
are specified for each of three baud rates: 2.50, 3.125 and 5 GBaud.
Two transmitter specifications allow for solutions ranging from simple board-to-board
interconnect to driving two connectors across a backplane. A single receiver specification
is given that accepts signals from both the short run and long run transmitter
specifications.
The short run transmitter must be used mainly for chip-to-chip connections on either the
same printed circuit board or across a single connector. This covers the case where
connections are made to a mezzanine (daughter) card. The minimum swings of the short
run specification reduce the overall power used by the transceivers.
The long run transmitter specifications use larger voltage swings that are capable of
driving signals across backplanes. This allows a user to drive signals across two
connectors and a backplane.
All unit intervals are specified with a tolerance of ± 100 ppm. The worst case frequency
difference between any transmit and receive clock is 200 ppm.
To ensure interoperability between drivers and receivers of different vendors and
technologies, AC coupling at the receiver input must be used.
Electrical characteristics
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
118 NXP Semiconductors
3.19.5.1 Signal definitions
This section defines the terms used in the description and specification of the differential
signals used by the LP-Serial links. The following figure shows how the signals are
defined. The figures show waveforms for either a transmitter output (TD and TD_B) or a
receiver input (RD and RD_B). Each signal swings between A volts and B volts where A
> B. Using these waveforms, the definitions are as follows:
• The transmitter output signals and the receiver input signals-TD, TD_B, RD, and
RD_B-each have a peak-to-peak swing of A - B volts.
• The differential output signal of the transmitter, VOD, is defined as VTD - VTD_B
• The differential input signal of the receiver, VID, is defined as VRD - VRD_B
• The differential output signal of the transmitter and the differential input signal of the
receiver each range from A - B to -(A - B) volts
• The peak value of the differential transmitter output signal and the differential
receiver input signal is A - B volts.
• The peak-to-peak value of the differential transmitter output signal and the
differential receiver input signal is 2 x (A - B) volts.
A volts
B volts
TD or RD
Differential peak-to-peak = 2 x (A - B)
TD or RD
Figure 42. Differential peak-to-peak voltage of transmitter or receiver
To illustrate these definitions using real values, consider the case of a CML (current
mode logic) transmitter that has a common mode voltage of 2.25 V, and each of its
outputs TD and TD_B, has a swing that goes between 2.5 V and 2.0 V. Using these
values, the peak-to-peak voltage swing of the signals TD and TD_B is 500 mV p-p. The
differential output signal ranges between 500 mV and -500 mV. The peak differential
voltage is 500 mV. The peak-to-peak differential voltage is 1000 mV p-p.
3.19.5.2 Equalization
With the use of high-speed serial links, the interconnect media causes degradation of the
signal at the receiver and produces effects such as inter-symbol interference (ISI) or data-
dependent jitter. This loss can be large enough to degrade the eye opening at the receiver
Electrical characteristics
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
NXP Semiconductors 119
beyond what is allowed in the specification. To negate a portion of these effects,
equalization can be used. The most common equalization techniques that can be used are
as follows:
• Pre-emphasis on the transmitter
• A passive high-pass filter network placed at the receiver, often referred to as passive
equalization.
• The use of active circuits in the receiver, often referred to as adaptive equalization.
3.19.5.3 Serial RapidIO clocking requirements for SDn_REF_CLKn_P and
SDn_REF_CLKn_N
SerDes 2 (SD2_REF_CLK[1:2]_P and SD2_REF_CLK[1:2]_N) may be used for various
SerDes serial RapidIO configurations based on the RCW Configuration field
SRDS_PRTCL. Serial RapidIO is not supported on SerDes 1 and 2.
For more information on these specifications, see SerDes reference clocks.
3.19.5.4 DC requirements for serial RapidIO
This section explains the DC requirements for the serial RapidIO interface.
3.19.5.4.1 DC serial RapidIO timing transmitter specifications
LP-Serial transmitter electrical and timing specifications are stated in the text and tables
of this section.
The differential return loss, S11, of the transmitter in each case is better than the
following:
• -10 dB for (Baud Frequency) ÷ 10 < Freq(f) < 625 MHz
• -10 dB + 10log(f ÷ 625 MHz) dB for 625 MHz ≤ Freq(f) ≤ Baud Frequency
The reference impedance for the differential return loss measurements is 100-Ω resistive.
Differential return loss includes contributions from on-chip circuitry, chip packaging, and
any off-chip components related to the driver. The output impedance requirement applies
to all valid output levels.
It is recommended that the 20%-80% rise/fall time of the transmitter, as measured at the
transmitter output, have a minimum value 60 ps in each case.
It is recommended that the timing skew at the output of an LP-Serial transmitter between
the two signals that comprise a differential pair not exceed 20 ps at 2.50 GBaud and 15 ps
at 3.125 GBaud and 10ps at 5 GBaud.
Electrical characteristics
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
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This table defines the transmitter DC specifications for serial RapidIO operating at 2.5
and 3.125 GBaud.
Table 74. Serial RapidIO transmitter DC timing specifications-2.5 GBaud, 3.125 GBaud2
Parameter Symbol Min Typ Max Unit Notes
Output voltage VO-0.40 - 2.30 V 1
Long-run differential output voltage VDIFFPP 800 - 1600 mV p-p -
Short-run differential output voltage VDIFFPP 500 - 1000 mV p-p -
DC Differential transmitter impedance ZTX-DIFF-DC 80 100 120 Ω Transmitter DC differential
impedance
Notes:
1. Voltage relative to COMMON of either signal comprising a differential pair
2. For recommended operating conditions, see Table 3.
This table defines the transmitter DC specifications for serial RapidIO operating at 5
GBaud.
Table 75. Serial RapidIO transmitter DC timing specifications-5 GBaud1
Parameter Symbol Min Typ Max Unit Notes
Long-run differential output voltage VDIFF 800 - 1200 mV -
Short-run differential output voltage VDIFF 400 - 750 mV -
Long-run de-emphasized differential output voltage (ratio) VTX-DE-RATIO-3.5dB 3 3.5 4 dB -
Long-run de-emphasized differential output voltage (ratio) VTX-DE-RATIO-6.0dB 5.5 6.0 6.5 dB -
Differential resistance TRD 80 100 120 Ω -
Notes:
1. For recommended operating conditions, see Table 3.
3.19.5.4.2 DC serial RapidIO receiver specifications
LP-Serial receiver electrical and timing specifications are stated in the text and tables of
this section.
Receiver input impedance results in a differential return loss better than 10 dB and a
common mode return loss better than 6 dB from 100 MHz to (0.8) x (Baud Frequency).
This includes contributions from on-chip circuitry, the chip package, and any off-chip
components related to the receiver. AC coupling components are included in this
requirement. The reference impedance for return loss measurements is 100-Ω resistive for
differential return loss and 25-Ω resistive for common mode.
This table defines the receiver DC specifications for serial RapidIO operating at 2.5 and
3.125 GBaud.
Electrical characteristics
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Table 76. Serial RapidIO receiver DC timing specifications-2.5 GBaud, 3.125 GBaud2
Parameter Symbol Min Typ Max Unit Notes
Differential input voltage VIN 200 - 1600 mV p-p 1
DC differential receiver input impedance ZRX-DIFF-DC 80 100 120 Ω Receiver DC differential
impedance
Notes:
1. Measured at the receiver
2. For recommended operating conditions, see Table 3.
This table defines the receiver DC specifications for serial RapidIO operating at 5
GBaud.
Table 77. Serial RapidIO receiver DC timing specifications-5 GBaud2
Parameter Symbol Min Typ Max Unit Notes
Long-run differential input voltage VDIFF - - 1200 mV 1
Short-run differential input voltage VDIFF 125 - 1200 mV 1
Differential resistance RRD 80 - 120 Ω -
Notes:
1. Measured at the receiver.
2. For recommended operating conditions, see Table 3.
3.19.5.5 AC requirements for serial RapidIO
This section explains the AC requirements for the serial RapidIO interface.
3.19.5.5.1 AC requirements for serial RapidIO transmitter
This table defines the transmitter AC specifications for the serial RapidIO operating at
2.5 and 3.125 GBaud. The AC timing specifications do not include RefClk jitter.
Table 78. Serial RapidIO transmitter AC timing specifications1
Parameter Symbol Min Typical Max Unit
Deterministic jitter JD- - 0.17 UI p-p
Total jitter JT- - 0.35 UI p-p
Unit Interval: 2.5 GBaud UI 400 - 100ppm 400 400 + 100ppm ps
Unit Interval: 3.125 GBaud UI 320 - 100ppm 320 320 + 100ppm ps
Notes:
1. For recommended operating conditions, see Table 3.
Electrical characteristics
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122 NXP Semiconductors
This table defines the transmitter AC specifications for the serial RapidIO operating at 5
GBaud. The AC timing specifications do not include RefClk jitter.
Table 79. Serial RapidIO transmitter AC timing specifications1
Parameter Symbol Min Typical Max Unit
Baud rate TBAUD 5.000 - 100ppm 5.000 5.000 +
100ppm
Gb/s
Uncorrelated high probability jitter TUHPJ - - 0.15 UI p-p
Total jitter TJ- - 0.30 UI p-p
Notes:
1. For recommended operating conditions, see Table 3.
This table defines the receiver AC specifications for serial RapidIO operating at 2.5 and
3.125 GBaud. The AC timing specifications do not include RefClk jitter.
Table 80. Serial RapidIO receiver AC timing specifications3
Parameter Symbol Min Typical Max Unit Notes
Deterministic jitter tolerance JD- - 0.37 UI p-p 1
Combined deterministic and random
jitter tolerance
JDR - - 0.55 UI p-p 1
Total jitter tolerance2JT- - 0.65 UI p-p 1
Bit error rate BER - - 10-12 - -
Unit Interval: 2.5 GBaud UI 400 - 100ppm 400 400 + 100ppm ps -
Unit Interval: 3.125 GBaud UI 320 - 100ppm 320 320 + 100ppm ps -
Notes:
1. Measured at receiver
2. Total jitter is composed of three components: deterministic jitter, random jitter and single frequency sinusoidal jitter. The
sinusoidal jitter may have any amplitude and frequency in the unshaded region of Figure 43. The sinusoidal jitter component
is included to ensure margin for low-frequency jitter, wander, noise, crosstalk, and other variable system effects.
3. For recommended operating conditions, see Table 3.
This figure shows the single-frequency sinusoidal jitter limits for 2.5GBaud and
3.125GBaud rates.
Electrical characteristics
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20 dB/dec
0.10 UI p-p
20 MHz
Sinuosidal
Jitter
Amplitude
Frequency
8.5 UI p-p
baud/142000 baud/1667
Figure 43. Single-frequency sinusoidal jitter limits
This table defines the receiver AC specifications for serial RapidIO operating at 5
GBaud. The AC timing specifications do not include RefClk jitter.
Table 81. Serial RapidIO receiver AC timing specifications1
Parameter Symbol Min Typical Max Unit Notes
Receiver baud rate RBAUD 5.000 - 100ppm 5.000 5.000 + 100ppm Gb/s -
Long-run Gaussian jitter RGJ - - 0.275 UI p-p -
Uncorrelated bounded high probability jitter RDJ - - 0.15 UI p-p -
Long-run correlated bounded high probability
jitter
RCBHPJ - - 0.525 UI p-p -
Short-run correlated bounded high probability
jitter
RCBHPJ - - 0.30 UI p-p -
Long-run bounded high probability jitter RBHPJ - - 0.675 UI p-p -
Short-run bounded high probability jitter RBHPJ - - 0.45 UI p-p -
Sinusoidal jitter, maximum RSJ-max - - 5.00 UI p-p -
Sinusoidal jitter, high frequency RSJ-hf - - 0.05 UI p-p -
Long-run total jitter (does not include
sinusoidal jitter)
RTj - - 0.95 UI p-p -
Short-run total jitter (does not include
sinusoidal jitter)
RTj - - 0.60 UI p-p -
Notes:
1. For recommended operating conditions, see Table 3.
Electrical characteristics
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124 NXP Semiconductors
This figure shows the single-frequency sinusoidal jitter limits for 5GBaud rate.
20 dB/dec
0.05 UI p-p
20 MHz
Sinuosidal
Jitter
Amplitude
Frequency
5 UI p-p
35.2 kHz 3 MHz
Figure 44. Single-frequency sinusoidal jitter limits
3.19.6 XAUI interface
This section describes the DC and AC electrical specifications for the XAUI bus.
3.19.6.1 XAUI DC electrical characteristics
This section discusses the XAUI DC electrical characteristics for the clocking signals,
transmitter, and receiver.
3.19.6.1.1 DC requirements for XAUI SDn_REF_CLKn_P and SDn_REF_CLKn_N
Only SerDes 1 (SD1_REF_CLK[1:2]_P and SD1_REF_CLK[1:2]_N) may be used for
various SerDes XAUI configurations based on the RCW Configuration field
SRDS_PRTCL.
For more information on these specifications, see SerDes reference clocks.
Electrical characteristics
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3.19.6.1.2 XAUI transmitter DC electrical characteristics
This table defines the XAUI transmitter DC electrical characteristics.
Table 82. XAUI transmitter DC electrical characteristics (XVDD = 1.35 V)1
Parameter Symbol Min Typical Max Unit Notes
Output voltage VO-0.40 - 2.30 V 2
Differential output voltage VDIFFPP 800 1000 1600 mV p-p -
DC Differential transmitter impedance ZTX-DIFF-DC 80 100 120 Ω 3
Notes:
1. For recommended operating conditions, see Table 3.
2. Absolute output voltage limit
3. Transmitter DC differential impedance
3.19.6.1.3 XAUI receiver DC electrical characteristics
This table defines the XAUI receiver DC electrical characteristics.
Table 83. XAUI receiver DC timing specifications (SVDD = 1.0 V)1
Parameter Symbol Min Typical Max Unit Notes
Differential input voltage VIN 200 - 1600 mV p-p 2
DC Differential receiver input
impedance
ZRX-DIFF-DC 80 100 120 Ω 3
Notes:
1. For recommended operating conditions, see Table 3.
2. Measured at the receiver
3. Receiver DC differential impedance
3.19.6.2 XAUI AC timing specifications
This section explains the AC requirements for the XAUI interface.
3.19.6.2.1 XAUI transmitter AC timing specifications
This table defines the XAUI transmitter AC timing specifications. RefClk jitter is not
included.
Table 84. XAUI transmitter AC timing specifications1
Parameter Symbol Min Typical Max Unit
Deterministic jitter JD- - 0.17 UI p-p
Table continues on the next page...
Electrical characteristics
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Table 84. XAUI transmitter AC timing specifications1 (continued)
Parameter Symbol Min Typical Max Unit
Total jitter JT- - 0.35 UI p-p
Unit Interval: 3.125 GBaud UI 320 - 100 ppm 320 320 + 100 ppm ps
Notes:
1. For recommended operating conditions, see Table 3.
3.19.6.2.2 XAUI receiver AC timing specifications
This table defines the receiver AC specifications for XAUI. RefClk jitter is not included.
Table 85. XAUI receiver AC timing specifications1
Parameter Symbol Min Typical Max Unit Notes
Deterministic jitter tolerance JD- - 0.37 UI p-p 2
Combined deterministic and random
jitter tolerance
JDR - - 0.55 UI p-p 2
Total jitter tolerance JT- - 0.65 UI p-p 2, 3
Bit error rate BER - - 10-12 - -
Unit Interval: 3.125 GBaud UI 320 - 100 ppm 320 320 + 100 ppm ps -
Notes:
1. For recommended operating conditions, see Table 3.
2. Measured at receiver
3. Total jitter is composed of three components: deterministic jitter, random jitter, and single frequency sinusoidal jitter. The
sinusoidal jitter may have any amplitude and frequency in the unshaded region of Figure 44. The sinusoidal jitter component
is included to ensure margin for low frequency jitter, wander, noise, crosstalk, and other variable system effects.
3.19.7 Aurora interface
This section describes the Aurora clocking requirements and its DC and AC electrical
characteristics.
3.19.7.1 Aurora clocking requirements for SDn_REF_CLKn_P and
SDn_REF_CLKn_N
Only SerDes 2 (SD2_REF_CLK[1:2]_P and SD2_REF_CLK[1:2]_N) may be used for
SerDes Aurora configurations based on the RCW Configuration field SRDS_PRTCL.
Aurora is not supported on SerDes 1-3.
For more information on these specifications, see SerDes reference clocks.
Electrical characteristics
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3.19.7.2 Aurora DC electrical characteristics
This section describes the DC electrical characteristics for the Aurora interface.
3.19.7.2.1 Aurora transmitter DC electrical characteristics
This table defines the Aurora transmitter DC electrical characteristics.
Table 86. Aurora transmitter DC electrical characteristics (XVDD = 1.35 V)1
Parameter Symbol Min Typical Max Unit
Differential output voltage VDIFFPP 800 1000 1600 mV p-p
DC Differential transmitter impedance ZTX-DIFF-DC 80 100 120 Ω
Notes:
1. For recommended operating conditions, see Table 3.
3.19.7.2.2 Aurora receiver DC electrical characteristics
This table defines the Aurora receiver DC electrical characteristics for the Aurora
interface.
Table 87. Aurora receiver DC electrical characteristics (SVDD = 1.0 V)1
Parameter Symbol Min Typical Max Unit Notes
Differential input voltage VIN 200 - 1600 mV p-p 2
DC Differential receiver impedance ZRX-DIFF-DC 80 100 120 Ω 3
Notes:
1. For recommended operating conditions, see Table 3.
2. Measured at receiver
3. C Differential receiver impedance
3.19.7.3 Aurora AC timing specifications
This section describes the AC timing specifications for Aurora.
3.19.7.3.1 Aurora transmitter AC timing specifications
This table defines the Aurora transmitter AC timing specifications. RefClk jitter is not
included.
Electrical characteristics
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128 NXP Semiconductors
Table 88. Aurora transmitter AC timing specifications1
Parameter Symbol Min Typical Max Unit
Deterministic jitter JD- - 0.17 UI p-p
Total jitter JT- - 0.35 UI p-p
Unit interval: 2.5 GBaud UI 400 - 100 ppm 400 400 + 100 ppm ps
Unit interval: 3.125 GBaud UI 320 - 100 ppm 320 320 + 100 ppm ps
Unit interval: 5.0 GBaud UI 200 - 100 ppm 200 200 + 100 ppm ps
Notes:
1. For recommended operating conditions, see Table 3.
3.19.7.3.2 Aurora receiver AC timing specifications
This table defines the Aurora receiver AC timing specifications. RefClk jitter is not
included.
Table 89. Aurora receiver AC timing specifications3
Parameter Symbol Min Typical Max Unit Notes
Deterministic jitter tolerance JD- - 0.37 UI p-p 1
Combined deterministic and random
jitter tolerance
JDR - - 0.55 UI p-p 1
Total jitter tolerance JT- - 0.65 UI p-p 1, 2
Bit error rate BER - - 10-12 - -
Unit Interval: 2.5 GBaud UI 400 - 100 ppm 400 400 + 100 ppm ps -
Unit Interval: 3.125 GBaud UI 320 - 100 ppm 320 320 + 100 ppm ps -
Unit Interval: 5.0 GBaud UI 200 - 100 ppm 200 200 + 100 ppm ps -
Notes:
1. Measured at receiver
2. Total jitter is composed of three components: deterministic jitter, random jitter, and single frequency sinusoidal jitter. The
sinusoidal jitter may have any amplitude and frequency in the unshaded region of Figure 43. The sinusoidal jitter component
is included to ensure margin for low frequency jitter, wander, noise, crosstalk and other variable system effects.
3. For recommended operating conditions, see Table 3.
3.19.8 Serial ATA (SATA) interface
This section describes the DC and AC electrical specifications for the serial ATA
(SATA) interface.
3.19.8.1 SATA DC electrical characteristics
This section describes the DC electrical characteristics for SATA.
Electrical characteristics
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3.19.8.1.1 SATA DC transmitter output characteristics
This table provides the differential transmitter output DC characteristics for the SATA
interface at Gen1i/1m or 1.5 Gbits/s transmission.
Table 90. Gen1i/1m 1.5G transmitter DC specifications (XVDD = 1.35 V)3
Parameter Symbol Min Typ Max Units Notes
Tx differential output voltage VSATA_TXDIFF 400 500 600 mV p-p 1
Tx differential pair impedance ZSATA_TXDIFFIM 85 100 115 Ω 2
Notes:
1. Terminated by 50 Ω load
2. DC impedance
3. For recommended operating conditions, see Table 3.
This table provides the differential transmitter output DC characteristics for the SATA
interface at Gen2i/2m or 3.0 Gbits/s transmission.
Table 91. Gen 2i/2m 3G transmitter DC specifications (XVDD = 1.35 V)2
Parameter Symbol Min Typ Max Units Notes
Transmitter differential output voltage VSATA_TXDIFF 400 - 700 mV p-p 1
Transmitter differential pair impedance ZSATA_TXDIFFIM 85 100 115 Ω -
Notes:
1. Terminated by 50 Ω load.
2. For recommended operating conditions, see Table 3.
3.19.8.1.2 SATA DC receiver input characteristics
This table provides the Gen1i/1m or 1.5 Gbits/s differential receiver input DC
characteristics for the SATA interface.
Table 92. Gen1i/1m 1.5 G receiver input DC specifications (SVDD = 1.0 V)3
Parameter Symbol Min Typical Max Units Notes
Differential input voltage VSATA_RXDIFF 240 500 600 mV p-p 1
Differential receiver input impedance ZSATA_RXSEIM 85 100 115 Ω 2
OOB signal detection threshold VSATA_OOB 50 120 240 mV p-p -
Notes:
1. Voltage relative to common of either signal comprising a differential pair
2. DC impedance
3. For recommended operating conditions, see Table 3.
Electrical characteristics
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130 NXP Semiconductors
This table provides the Gen2i/2m or 3 Gbits/s differential receiver input DC
characteristics for the SATA interface.
Table 93. Gen2i/2m 3 G receiver input DC specifications (SVDD = 1.0 V)3
Parameter Symbol Min Typical Max Units Notes
Differential input voltage VSATA_RXDIFF 240 - 750 mV p-p 1
Differential receiver input impedance ZSATA_RXSEIM 85 100 115 Ω 2
OOB signal detection threshold VSATA_OOB 75 120 240 mV p-p 2
Notes:
1. Voltage relative to common of either signal comprising a differential pair
2. DC impedance
3. For recommended operating conditions, see Table 3.
3.19.8.2 SATA AC timing specifications
This section discusses the SATA AC timing specifications.
3.19.8.2.1 AC requirements for SATA REF_CLK
The AC requirements for the SATA reference clock listed in this table are to be
guaranteed by the customer's application design.
Table 94. SATA reference clock input requirements6
Parameter Symbol Min Typ Max Unit Notes
SDn_REF_CLKn_P/SDn_REF_CLKn_N
frequency range
tCLK_REF - 100/125 - MHz 1
SDn_REF_CLKn_P/SDn_REF_CLKn_N clock
frequency tolerance
tCLK_TOL -350 - +350 ppm -
SDn_REF_CLKn_P/SDn_REF_CLKn_N
reference clock duty cycle
tCLK_DUTY 40 50 60 % 5
SDn_REF_CLKn_P/SDn_REF_CLKn_N cycle-
to-cycle clock jitter (period jitter)
tCLK_CJ - - 100 ps 2
SDn_REF_CLKn_P/SDn_REF_CLKn_N total
reference clock jitter, phase jitter (peak-to-peak)
tCLK_PJ -50 - +50 ps 2, 3, 4
Notes:
1. Caution: Only 100 and 125MHz have been tested. In-between values do not work correctly with the rest of the system.
2. At RefClk input
3. In a frequency band from 150 kHz to 15 MHz at BER of 10-12
4. Total peak-to-peak deterministic jitter must be less than or equal to 50 ps.
5. Measurement taken from differential waveform
6. For recommended operating conditions, see Table 3.
Electrical characteristics
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NXP Semiconductors 131
This figure shows the reference clock timing waveform.
Ref_CLK
TH
TL
Figure 45. Reference clock timing waveform
3.19.8.3 AC transmitter output characteristics
This table provides the differential transmitter output AC characteristics for the SATA
interface at Gen1i/1m or 1.5 Gbits/s transmission. The AC timing specifications do not
include RefClk jitter.
Table 95. Gen1i/1m 1.5 G transmitter AC specifications2
Parameter Symbol Min Typ Max Units Notes
Channel speed tCH_SPEED - 1.5 - Gbps -
Unit Interval TUI 666.4333 666.6667 670.2333 ps -
Total jitter data-data 5 UI USATA_TXTJ5UI - - 0.355 UI p-p 1
Total jitter, data-data 250 UI USATA_TXTJ250UI - - 0.47 UI p-p 1
Deterministic jitter, data-data 5 UI USATA_TXDJ5UI - - 0.175 UI p-p 1
Deterministic jitter, data-data 250 UI USATA_TXDJ250UI - - 0.22 UI p-p 1
Notes:
1. Measured at transmitter output pins peak to peak phase variation, random data pattern
2. For recommended operating conditions, see Table 3.
This table provides the differential transmitter output AC characteristics for the SATA
interface at Gen2i/2m or 3.0 Gbits/s transmission. The AC timing specifications do not
include RefClk jitter.
Electrical characteristics
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132 NXP Semiconductors
Table 96. Gen 2i/2m 3 G transmitter AC specifications2
Parameter Symbol Min Typ Max Units Notes
Channel speed tCH_SPEED - 3.0 - Gbps -
Unit Interval TUI 333.2167 333.3333 335.1167 ps -
Total jitter fC3dB = fBAUD ÷ 500 USATA_TXTJfB/500 - - 0.37 UI p-p 1
Total jitter fC3dB = fBAUD ÷ 1667 USATA_TXTJfB/1667 - - 0.55 UI p-p 1
Deterministic jitter, fC3dB = fBAUD ÷ 500 USATA_TXDJfB/500 - - 0.19 UI p-p 1
Deterministic jitter, fC3dB = fBAUD ÷
1667
USATA_TXDJfB/1667 - - 0.35 UI p-p 1
Notes:
1. Measured at transmitter output pins peak-to-peak phase variation, random data pattern
2. For recommended operating conditions, see Table 3.
3.19.8.4 AC differential receiver input characteristics
This table provides the Gen1i/1m or 1.5 Gbits/s differential receiver input AC
characteristics for the SATA interface. The AC timing specifications do not include
RefClk jitter.
Table 97. Gen 1i/1m 1.5G receiver AC specifications2
Parameter Symbol Min Typical Max Units Notes
Unit Interval TUI 666.4333 666.6667 670.2333 ps -
Total jitter data-data 5 UI USATA_RXTJ5UI - - 0.43 UI p-p 1
Total jitter, data-data 250 UI USATA_RXTJ250UI - - 0.60 UI p-p 1
Deterministic jitter, data-data 5 UI USATA_RXDJ5UI - - 0.25 UI p-p 1
Deterministic jitter, data-data 250 UI USATA_RXDJ250UI - - 0.35 UI p-p 1
Notes:
1. Measured at receiver.
2. For recommended operating conditions, see Table 3.
This table provides the differential receiver input AC characteristics for the SATA
interface at Gen2i/2m or 3.0 Gbits/s transmission. The AC timing specifications do not
include RefClk jitter.
Table 98. Gen 2i/2m 3G receiver AC specifications2
Parameter Symbol Min Typical Max Units Notes
Unit Interval TUI 333.2167 333.3333 335.1167 ps -
Total jitter fC3dB = fBAUD ÷ 500 USATA_RXTJfB/500 - - 0.60 UI p-p 1
Total jitter fC3dB = fBAUD ÷ 1667 USATA_RXTJfB/1667 - - 0.65 UI p-p 1
Deterministic jitter, fC3dB = fBAUD ÷ 500 USATA_RXDJfB/500 - - 0.42 UI p-p 1
Table continues on the next page...
Electrical characteristics
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Table 98. Gen 2i/2m 3G receiver AC specifications2 (continued)
Parameter Symbol Min Typical Max Units Notes
Deterministic jitter, fC3dB = fBAUD ÷ 1667 USATA_RXDJfB/1667 - - 0.35 UI p-p 1
Notes:
1. Measured at receiver
2. For recommended operating conditions, see Table 3.
3.19.9 SGMII interface
Each SGMII port features a 4-wire AC-coupled serial link from the SerDes interface of
the chip, as shown in Figure 46, where CTX is the external (on board) AC-coupled
capacitor. Each SerDes transmitter differential pair features 100-Ω output impedance.
Each input of the SerDes receiver differential pair features 50-Ω on-die termination to
XGNDn. The reference circuit of the SerDes transmitter and receiver is shown in Figure
39 .
3.19.9.1 SGMII clocking requirements for SDn_REF_CLKn_P and
SDn_REF_CLKn_N
When operating in SGMII mode, the ECn_GTX_CLK125 clock is not required for this
port. Instead, a SerDes reference clock is required on SD1_REF_CLK[1:2]_P and
SD1_REF_CLK[1:2]_Npins. SerDes 1 may be used for SerDes SGMII configurations
based on the RCW Configuration field SRDS_PRTCL.
For more information on these specifications, see SerDes reference clocks.
3.19.9.2 SGMII DC electrical characteristics
This section discusses the electrical characteristics for the SGMII interface.
3.19.9.2.1 SGMII and SGMII 2.5x transmit DC specifications
This table describes the SGMII SerDes transmitter AC-coupled DC electrical
characteristics. Transmitter DC characteristics are measured at the transmitter outputs
( SDn_TXn_P and SDn_TXn_N)as shown in Figure 47.
Table 99. SGMII DC transmitter electrical characteristics (XVDD = 1.35 V)4
Parameter Symbol Min Typ Max Unit Notes
Output high voltage VOH - - 1.5 x │VOD│-max mV 1
Table continues on the next page...
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Table 99. SGMII DC transmitter electrical characteristics (XVDD = 1.35 V)4 (continued)
Parameter Symbol Min Typ Max Unit Notes
Output low voltage VOL │VOD│-min/2 - - mV 1
Output differential voltage2, 3
(XVDD-Typ at 1.35 V)
│VOD│320 500.0 725.0 mV -
293.8 459.0 665.6 -
266.9 417.0 604.7 -
240.6 376.0 545.2 -
213.1 333.0 482.9 -
186.9 292.0 423.4 -
160.0 250.0 362.5 -
Output impedance (differential) RO80 100 120 Ω -
Notes:
1. This does not align to DC-coupled SGMII.
2. │VOD│ = │VSD_TXn_P - VSD_TXn_N│. │VOD│ is also referred to as output differential peak voltage. VTX-DIFFp-p = 2 x │VOD│.
3. The │VOD│ value shown in the Typ column is based on the condition of XVDD_SRDSn-Typ = 1.35 V, no common mode
offset variation. SerDes transmitter is terminated with 100-Ω differential load between SDn_TXn_P and SDn_TXn_N.
4. For recommended operating conditions, see Table 3.
This figure shows an example of a 4-wire AC-coupled SGMII serial link connection.
Electrical characteristics
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NXP Semiconductors 135
100 Ω
50 Ω
50 Ω
Transmitter
SGMII
SerDes Interface
SDn_TXn_P
SDn_TXn_N SDn_RXn_N
SDn_RXn_P
CTX
CTX
Receiver
100 Ω
50 Ω
50 Ω
Transmitter
SDn_TXn_P
SDn_TXn_NSDn_RXn_N
SDn_RXn_P CTX
CTX
Receiver
Figure 46. 4-wire AC-coupled SGMII serial link connection example
This figure shows the SGMII transmitter DC measurement circuit.
Electrical characteristics
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
136 NXP Semiconductors
100 Ω
50 Ω
50 Ω
Transmitter
SGMII
SerDes Interface
SDn_TXn_P
SDn_TXn_N
VOD
Figure 47. SGMII transmitter DC measurement circuit
This table defines the SGMII 2.5x transmitter DC electrical characteristics for 3.125
GBaud.
Table 100. SGMII 2.5x transmitter DC electrical characteristics (XVDD = 1.35 V)1
Parameter Symbol Min Typical Max Unit Notes
Output differential voltage │VOD│400 - 600 mV -
Output impedance (differential) RO80 100 120 Ω -
Notes:
1. For recommended operating conditions, see Table 3.
3.19.9.2.2 SGMII and SGMII 2.5x DC receiver electrical characteristics
This table lists the SGMII DC receiver electrical characteristics. Source synchronous
clocking is not supported. Clock is recovered from the data.
Table 101. SGMII DC receiver electrical characteristics (SVDD = 1.0V)4
Parameter Symbol Min Typ Max Unit Notes
DC input voltage range - N/A - 1
Input differential voltage - VRX_DIFFp-p 100 - 1200 mV 2
- 175 -
Loss of signal threshold - VLOS 30 - 100 mV 3
- 65 - 175
Table continues on the next page...
Electrical characteristics
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
NXP Semiconductors 137
Table 101. SGMII DC receiver electrical characteristics (SVDD = 1.0V)4 (continued)
Parameter Symbol Min Typ Max Unit Notes
Receiver differential input impedance ZRX_DIFF 80 - 120 Ω -
Notes:
1. Input must be externally AC coupled.
2. VRX_DIFFp-p is also referred to as peak-to-peak input differential voltage.
3. The concept of this parameter is equivalent to the electrical idle detect threshold parameter in PCI Express. See PCI
Express DC physical layer receiver specifications, and PCI Express AC physical layer receiver specifications, for further
explanation.
4. For recommended operating conditions, see Table 3.
This table defines the SGMII 2.5x receiver DC electrical characteristics for 3.125 GBaud.
Table 102. SGMII 2.5x receiver DC timing specifications (SVDD = 1.0V)1
Parameter Symbol Min Typical Max Unit Notes
Input differential voltage VRX_DIFFp-p 200 - 1200 mV -
Loss of signal threshold VLOS 75 - 200 mV -
Receiver differential input impedance ZRX_DIFF 80 - 120 Ω -
Notes:
1. For recommended operating conditions, see Table 3.
3.19.9.3 SGMII AC timing specifications
This section discusses the AC timing specifications for the SGMII interface.
3.19.9.3.1 SGMII and SGMII 2.5x transmit AC timing specifications
This table provides the SGMII and SGMII 2.5x transmit AC timing specifications. A
source synchronous clock is not supported. The AC timing specifications do not include
RefClk jitter.
Table 103. SGMII transmit AC timing specifications4
Parameter Symbol Min Typ Max Unit Notes
Deterministic jitter JD — — 0.17 UI p-p —
Total jitter JT — — 0.35 UI p-p 2
Unit Interval: 1.25 GBaud (SGMII) UI 800 - 100 ppm 800 800 + 100 ppm ps 1
Unit Interval: 3.125 GBaud (2.5x SGMII]) UI 320 - 100 ppm 320 320 + 100 ppm ps 1
AC coupling capacitor CTX 10 — 200 nF 3
Notes:
1. Each UI is 800 ps ± 100 ppm or 320 ps ± 100 ppm.
Electrical characteristics
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
138 NXP Semiconductors
Table 103. SGMII transmit AC timing specifications4
Parameter Symbol Min Typ Max Unit Notes
2. See Figure 43 for single frequency sinusoidal jitter measurements.
3. The external AC coupling capacitor is required. It is recommended that it be placed near the device transmitter outputs.
4. For recommended operating conditions, see Table 3.
3.19.9.3.2 SGMII AC measurement details
Transmitter and receiver AC characteristics are measured at the transmitter outputs
( SDn_TXn_P and SDn_TXn_N) or at the receiver inputs ( SDn_RXn_P and
SDn_RXn_N) respectively, as depicted in this figure.
Transmitter
silicon
+ package
D + package pin
D - package pin
C = CTX
C = CTX
R = 50 Ω R = 50 Ω
Figure 48. SGMII AC test/measurement load
3.19.9.3.3 SGMII and SGMII 2.5x receiver AC timing specification
This table provides the SGMII and SGMII 2.5x receiver AC timing specifications. The
AC timing specifications do not include RefClk jitter. Source synchronous clocking is not
supported. Clock is recovered from the data.
Table 104. SGMII Receive AC timing specifications3
Parameter Symbol Min Typ Max Unit Notes
Deterministic jitter tolerance JD— — 0.37 UI p-p 1
Combined deterministic and random jitter tolerance JDR — — 0.55 UI p-p 1
Total jitter tolerance JT— — 0.65 UI p-p 1, 2
Bit error ratio BER — — 10-12 — —
Unit Interval: 1.25 GBaud (SGMII) UI 800 - 100 ppm 800 800 + 100 ppm ps 1
Unit Interval: 3.125 GBaud (2.5x SGMII]) UI 320 - 100 ppm 320 320 + 100 ppm ps 1
Table continues on the next page...
Electrical characteristics
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
NXP Semiconductors 139
Table 104. SGMII Receive AC timing specifications3 (continued)
Parameter Symbol Min Typ Max Unit Notes
Notes:
1. Measured at receiver
2. Total jitter is composed of three components: deterministic jitter, random jitter, and single frequency sinusoidal jitter. The
sinusoidal jitter may have any amplitude and frequency in the unshaded region of Figure 43. The sinusoidal jitter component
is included to ensure margin for low frequency jitter, wander, noise, crosstalk and other variable system effects.
3. For recommended operating conditions, see Table 3.
The sinusoidal jitter in the total jitter tolerance may have any amplitude and frequency in
the unshaded region of Figure 43.
3.19.10 HiGig/HiGig2 interface
This section describes the HiGig/HiGig2 clocking requirements and its DC and AC
electrical characteristics.
3.19.10.1 HiGig/HiGig2 clocking requirements for SDn_REF_CLKn_P and
SDn_REF_CLKn_N
Only SerDes 1 (SD1_REF_CLK[1:2]_P and SD1_REF_CLK[1:2]_N) may be used for
SerDes HiGig/HiGig2 configurations based on the RCW Configuration field
SRDS_PRTCL.
For more information on these specifications, see SerDes reference clocks.
3.19.10.2 HiGig/HiGig2 DC electrical characteristics
This section describes the DC electrical characteristics for HiGig/HiGig2.
3.19.10.2.1 HiGig/HiGig2 transmitter DC electrical characteristics
This table defines the HiGig/HiGig2 transmitter DC electrical characteristics.
Table 105. HiGig/HiGig2 transmitter DC electrical characteristics (XVDD = 1.35 V)2
Parameter Symbol Min Typical Max Unit Notes
Output voltage VO-0.40 - 2.30 V 1
Differential output voltage VDIFFPP 800 1000 1600 mV p-p -
DC Differential transmitter impedance ZTX-DIFF-DC 80 100 120 Ω Transmitter DC
differential impedance
Table continues on the next page...
Electrical characteristics
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
140 NXP Semiconductors
Table 105. HiGig/HiGig2 transmitter DC electrical characteristics (XVDD = 1.35 V)2
(continued)
Parameter Symbol Min Typical Max Unit Notes
Notes:
1. Absolute output voltage limit
2. For recommended operating conditions, see Table 3.
3.19.10.2.2 HiGig/HiGig2 receiver DC electrical characteristics
This table defines the HiGig/HiGig2 receiver DC electrical characteristics.
Table 106. HiGig/HiGig2 receiver DC electrical characteristics (SVDD = 1.0V)2
Parameter Symbol Min Typical Max Unit Notes
Differential input voltage VIN 200 - 1600 mV p-p 1
DC Differential receiver impedance ZRX-DIFF-DC 80 100 120 Ω DC Differential receiver
impedance
1. Measured at receiver
2. For recommended operating conditions, see Table 3.
3.19.10.3 HiGig/HiGig2 AC timing specifications
This section describes the AC timing specifications for HiGig/HiGig2.
3.19.10.3.1 HiGig/HiGig2 transmitter AC timing specifications
This table defines the HiGig/HiGig2 transmitter AC timing specifications. RefClk jitter is
not included.
Table 107. HiGig/HiGig2 transmitter AC timing specifications1
Parameter Symbol Min Typical Max Unit
Deterministic jitter JD- - 0.17 UI p-p
Total jitter JT- - 0.35 UI p-p
Unit Interval: 3.125 GBaud (HiGig/HiGig2) UI 320 - 100 ppm 320 320 + 100 ppm ps
Unit Interval: 3.75 GBaud (HiGig/HiGig2) UI 266.66 - 100 ppm 266.66 266.66 + 100
ppm
ps
Notes:
1. For recommended operating conditions, see Table 3.
Electrical characteristics
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
NXP Semiconductors 141
3.19.10.3.2 HiGig/HiGig2 receiver AC timing specifications
This table defines the HiGig/HiGig2 receiver AC timing specifications. RefClk jitter is
not included.
Table 108. HiGig/HiGig2 receiver AC timing specifications3
Parameter Symbol Min Typical Max Unit Notes
Deterministic jitter tolerance JD- - 0.37 UI p-p 1
Combined deterministic and random
jitter tolerance
JDR - - 0.55 UI p-p 1
Total jitter tolerance JT- - 0.65 UI p-p 1, 2
Unit Interval: 3.125 GBaud (HiGig/
HiGig2)
UI 320 - 100ppm 320 320 + 100ppm ps -
Unit Interval: 3.75 GBaud (HiGig/
HiGig2)
UI 266.66 -
100ppm
266.66 266.66 +
100ppm
ps -
1. Measured at receiver
2. Total jitter is composed of three components: deterministic jitter, random jitter, and single frequency sinusoidal jitter. The
sinusoidal jitter may have any amplitude and frequency in the unshaded region of Figure 44. The sinusoidal jitter component
is included to ensure margin for low frequency jitter, wander, noise, crosstalk and other variable system effects.
3. For recommended operating conditions, see Table 3.
3.19.11 XFI interface
This section describes the XFI clocking requirements and its DC and AC electrical
characteristics.
3.19.11.1 XFI clocking requirements for SDn_REF_CLKn_P and
SDn_REF_CLKn_N
Only SerDes 1 (SD1_REF_CLK[1:2]_P and SD1_REF_CLK[1:2]_N) may be used for
SerDes XFI configurations based on the RCW Configuration field SRDS_PRTCL.
For more information on these specifications, see SerDes reference clocks.
3.19.11.2 XFI DC electrical characteristics
This section describes the DC electrical characteristics for XFI.
3.19.11.2.1 XFI transmitter DC electrical characteristics
This table defines the XFI transmitter DC electrical characteristics.
Electrical characteristics
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
142 NXP Semiconductors
Table 109. XFI transmitter DC electrical characteristics (XVDD = 1.35 V)1
Parameter Symbol Min Typical Max Unit Notes
Output differential voltage VTX-DIFF 360 - 770 mV -
De-emphasized differential output
voltage (ratio)
VTX-DE-
RATIO-1.14 dB
0.6 1.1 1.6 dB -
De-emphasized differential output
voltage (ratio)
VTX-DE-
RATIO-3.5 dB
3 3.5 4 dB -
De-emphasized differential output
voltage (ratio)
VTX-DE-
RATIO-4.66 dB
4.1 4.6 5.1 dB -
De-emphasized differential output
voltage (ratio)
VTX-DE-
RATIO-6.0 dB
5.5 6.0 6.5 dB -
De-emphasized differential output
voltage (ratio)
VTX-DE-
RATIO-9.5 dB
9 9.5 10 dB -
Differential resistance TRD 80 100 120 Ω -
Notes:
1. For recommended operating conditions, see Table 3.
3.19.11.2.2 XFI receiver DC electrical characteristics
This table defines the XFI receiver DC electrical characteristics.
Table 110. XFI receiver DC electrical characteristics (SVDD = 1.0V)2
Parameter Symbol Min Typical Max Unit Notes
Input differential voltage VRX-DIFF 110 - 1050 mV 1
Differential resistance RRD 80 100 120 Ω -
1. Measured at receiver
2. For recommended operating conditions, see Table 3.
3.19.11.3 XFI AC timing specifications
This section describes the AC timing specifications for XFI.
3.19.11.3.1 XFI transmitter AC timing specifications
This table defines the XFI transmitter AC timing specifications. RefClk jitter is not
included.
Electrical characteristics
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
NXP Semiconductors 143
Table 111. XFI transmitter AC timing specifications1
Parameter Symbol Min Typical Max Unit
Transmitter baud rate TBAUD 10.3125 - 100ppm 10.3125 10.3125 +
100ppm
Gb/s
Unit Interval UI - 96.96 - ps
Deterministic jitter DJ- - 0.15 UI p-p
Total jitter TJ- - 0.30 UI p-p
Notes:
1. For recommended operating conditions, see Table 3.
3.19.11.3.2 XFI receiver AC timing specifications
This table defines the XFI receiver AC timing specifications. RefClk jitter is not
included.
Table 112. XFI receiver AC timing specifications3
Parameter Symbol Min Typical Max Unit Notes
Receiver baud rate RBAUD 10.3125 -
100ppm
10.3125 10.3125 +
100ppm
Gb/s -
Unit Interval UI - 96.96 - ps -
Total non-EQJ jitter TNON-EQJ - - 0.45 UI p-p 1
Total jitter tolerance TJ- - 0.65 UI p-p 1, 2
1. The total jitter (TJ) consists of Random Jitter (RJ), Duty Cycle Distortion (DCD), Periodic Jitter (PJ), and Inter symbol
Interference (ISI). Non-EQJ jitter can include duty cycle distortion (DCD), random jitter (RJ), and periodic jitter (PJ). Non-EQJ
jitter is uncorrelated to the primary data stream with exception of the DCD and so cannot be equalized by the receiver under
test. It can exhibit a wide spectrum. Non - EQJ = TJ - ISI = RJ + DCD + PJ
2. The XFI channel has a loss budget of 9.6 dB @5.5GHz. The channel loss including connector @ 5.5GHz is 6dB. The
channel crosstalk and reflection margin is 3.6dB. Manual tuning of TX Equalization and amplitude will be required for
performance optimization.
3. For recommended operating conditions, see Table 3.
This figure shows the sinusoidal jitter tolerance of XFI receiver.
Electrical characteristics
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
144 NXP Semiconductors
1.13x 0.2 + 0.1
f, f in MHz
-20 dB/Dec
0.17
0.05
0.04
4 8 27.2
80
Sinuosidal Jitter Tolerance (UIp-p)
Frequency (MHz)
Figure 49. XFI host receiver input sinusoidal jitter tolerance
3.19.12 10GBase-KR interface
This section describes the 10GBase-KR clocking requirements and its DC and AC
electrical characteristics.
3.19.12.1 10GBase-KR clocking requirements for SDn_REF_CLKn and
SDn_REF_CLKn_B
Only SerDes 1 (SD1_REF_CLK[1:2]_Pand SD1_REF_CLK[1:2]_N) may be used for
SerDes 10GBase-KR configurations based on the RCW Configuration field
SRDS_PRTCL.
For more information on these specifications, see SerDes reference clocks .
Electrical characteristics
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
NXP Semiconductors 145
3.19.12.2 10GBase-KR DC electrical characteristics
This section describes the DC electrical characteristics for 10GBase-KR.
3.19.12.2.1 10GBase-KR transmitter DC electrical characteristics
This table defines the 10GBase-KR transmitter DC electrical characteristics.
Table 113. 10GBaseKR transmitter DC electrical characteristics (XVDD = 1.35V or 1.5V)1
Parameter Symbol Min Typical Max Unit Notes
Output differential voltage VTX-DIFF 800 - 1200 mV -
De-emphasized differential output
voltage (ratio)
VTX-DE-
RATIO-1.14dB
0.6 1.1 1.6 dB -
De-emphasized differential output
voltage (ratio)
VTX-DE-
RATIO-3.5dB
3 3.5 4 dB -
De-emphasized differential output
voltage (ratio)
VTX-DE-
RATIO-4.66dB
4.1 4.6 5.1 dB -
De-emphasized differential output
voltage (ratio)
VTX-DE-
RATIO-6.0dB
5.5 6.0 6.5 dB -
De-emphasized differential output
voltage (ratio)
VTX-DE-
RATIO-9.5dB
9 9.5 10 dB -
Differential resistance TRD 80 100 120 Ω -
1. For recommended operating conditions, see Table 3.
3.19.12.2.2 10GBase-KR receiver DC electrical characteristics
This table defines the 10GBase-KR receiver DC electrical characteristics.
Table 114. 10GBase-KR receiver DC electrical characteristics (XVDD = 1.35V or 1.5V)1
Parameter Symbol Min Typical Max Unit Notes
Input differential voltage VRX-DIFF - - 1200 mV -
Differential resistance RRD 80 - 120 Ω -
1. For recommended operating conditions, see Table 3.
3.19.12.3 10GBase-KR AC timing specifications
This section describes the AC timing specifications for 10GBase-KR.
Electrical characteristics
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
146 NXP Semiconductors
3.19.12.3.1 10GBase-KR transmitter AC timing specifications
This table defines the 10GBase-KR transmitter AC timing specifications. RefClk jitter is
not included.
Table 115. 10GBase-KR transmitter AC timing specifications1
Parameter Symbol Min Typical Max Unit
Transmitter baud rate TBAUD 10.3125 - 100
ppm
10.3125 10.3125 + 100
ppm
Gb/s
Uncorrelated high probability jitter/Random
jitter
UHPJ/RJ- - 0.15 UI p-p
Deterministic jitter DJ- - 0.15 UI p-p
Total jitter TJ- - 0.30 UI p-p
1. For recommended operating conditions, see Table 3.
3.19.12.3.2 10GBase-KR receiver AC timing specifications
This table defines the 10GBase-KR receiver AC timing specifications. RefClk jitter is not
included.
Table 116. 10GBase-KR receiver AC timing specifications2
Parameter Symbol Min Typical Max Unit Notes
Receiver baud rate RBAUD 10.3125 - 100
ppm
10.3125 10.3125 + 100
ppm
Gb/s -
Random jitter RJ- - 0.130 UI p-p -
Sinusodial jitter, maximum SJ-max - - 0.115 UI p-p -
Duty cycle distortion DCD - - 0.035 UI p-p -
Total jitter TJ- - See Note 1 UI p-p 1
1. The total jitter (TJ) is per Interference tolerance test IEEE Standard 802.3ap-2007 specified in Annex 69A.
2. For recommended operating conditions, see Table 3.
3.19.13 1000Base-KX interface
This section discusses the electrical characteristics for the 1000Base-KX. Only AC-
coupled operation is supported.
3.19.13.1 1000Base-KX DC electrical characteristics
Electrical characteristics
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
NXP Semiconductors 147
3.19.13.1.1 1000Base-KX Transmitter DC Specifications
This table describes the 1000Base-KX SerDes transmitter DC specification at TP1 per
IEEE Std 802.3ap-2007. Transmitter DC characteristics are measured at the transmitter
outputs ( SDn_TXn_P and SDn_TXn_N).
Table 117. 1000Base-KX Transmitter DC Specifications
Parameter Symbols Min Typ Max Units Notes
Output differential
voltage
VTX-DIFFp-p 800 - 1600 mV 1
Differential
resistance
TRD 80 100 120 ohm -
Notes:
1. SRDSxLNmTECR0[AMP_RED]=00_0000.
2. For recommended operating conditions, see Table 3.
3.19.13.1.2 1000Base-KX Receiver DC Specifications
Table below provides the 1000Base-KX receiver DC timing specifications.
Table 118. 1000Base-KX Receiver DC Specifications
Parameter Symbols Min Typical Max Units Notes
Input differential
voltage
VRX-DIFFp-p - - 1600 mV 1
Differential
resistance
TRDIN 80 - 120 ohm -
Notes:
1. For recommended operating conditions, see Table 3.
3.19.13.2 1000Base-KX AC electrical characteristics
3.19.13.2.1 1000Base-KX Transmitter AC Specifications
Table below provides the 1000Base-KX transmitter AC specification.
Table 119. 1000Base-KX Transmitter AC Specifications
Parameter Symbols Min Typical Max Units Notes
Baud Rate TBAUD 1.25-100ppm 1.25 1.25+100pp
m
Gb/s -
Uncorrelated High
Probability Jitter/
Random Jitter
TUHPJTRJ - - 0.15 UI p-p -
Table continues on the next page...
Electrical characteristics
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
148 NXP Semiconductors
Table 119. 1000Base-KX Transmitter AC Specifications (continued)
Parameter Symbols Min Typical Max Units Notes
Deterministic Jitter TDJ - - 0.10 UI p-p -
Total Jitter TTJ - - 0.25 UI p-p 1
Notes:
1. Total jitter is specified at a BER of 10-12.
2. For recommended operating conditions, see Table 3.
3.19.13.2.2 1000Base-KX Receiver AC Specifications
Table below provides the 1000Base-KX receiver AC specification with parameters
guided by IEEE Std 802.3ap-2007.
Table 120. 1000Base-KX Receiver AC Specifications
Parameter Symbols Min Typical Max Units Notes
Receiver Baud Rate RBAUD 1.25-100ppm 1.25 1.25+100pp
m
Gb/s -
Random Jitter RRJ - - 0.15 UI p-p 1
Sinusoidal Jitter,
maximum
RSJ-max - - 0.10 UI p-p 2
Total Jitter RTJ - - See Note 3 UI p-p 2
Notes:
1. Random jitter is specified at a BER of 10-12.
2. The receiver interference tolerance level of this parameter shall be measured as described in Annex 69A of the IEEE Std
802.3ap-2007.
3. Per IEEE 802.3ap-clause 70.
4. The AC specifications do not include Refclk jitter.
5. For recommended operating conditions, see Table 3.
4 Hardware design considerations
4.1 System clocking
This section describes the PLL configuration of the chip.
Hardware design considerations
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
NXP Semiconductors 149
4.1.1 PLL characteristics
Characteristics of the chip's PLLs include the following:
• There are two selectable core cluster PLLs which generate a clock for each core
cluster from the externally supplied SYSCLK input.
• Core cluster 1 (cores 0-3) can select from cluster group A PLL 1 or 2 (CGA1 or
2 PLL).
• The frequency ratio between each of the core cluster PLLs and SYSCLK is
selected using the configuration bits. The frequency for each core cluster is
selected using the configuration bits.
• The platform PLL generates the platform clock from the externally supplied
SYSCLK input. The frequency ratio between the platform and SYSCLK is selected
using the platform PLL ratio configuration bits.
• Cluster group A generates an asynchronous clock for eSDHC SDR mode from
cluster group A PLL1 or cluster group A PLL 2.
• Cluster group A generates an asynchronous clock for FMan from the platform PLL,
cluster group A PLL1 or cluster group A PLL 2.
• The DDR block PLL generates an asynchronous DDR clock from the externally
supplied DDRCLK input. The frequency ratio is selected using the Memory
Controller Complex PLL multiplier/ratio configuration bits.
• Each of the two SerDes blocks has 2 PLLs which generate a core clock from their
respective externally supplied SDn_REF_CLKn_P/SDn_REF_CLKn_N inputs. The
frequency ratio is selected using the SerDes PLL RCW configuration bits as
described in SerDes PLL ratio.
4.1.2 Clock ranges
This table provides the clocking specifications for the processor core, platform, memory,
and integrated flash controller.
Table 121. Processor, platform, and memory clocking specifications
Characteristic Maximum processor core frequency Unit Notes
1200 MHz 1533 MHz 1800 MHz
Min Max Min Max Min Max
Core cluster group PLL frequency 1000 1200 1000 1533 1000 1800 MHz 1, 2
Core cluster frequency 250 1200 250 1533 250 1800 MHz 2
Platform clock frequency 400 533 400 600 400 600 MHz 1, 7
Memory bus clock frequency 533 800 533 933 533 1066 MHz 1, 3, 4
IFC clock frequency — 100 — 100 — 100 MHz 5
Table continues on the next page...
Hardware design considerations
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
150 NXP Semiconductors
Table 121. Processor, platform, and memory clocking specifications (continued)
Characteristic Maximum processor core frequency Unit Notes
1200 MHz 1533 MHz 1800 MHz
Min Max Min Max Min Max
FMan see note
6
600 see note
6
700 see note
6
700 MHz 6
Notes:
1. Caution:The platform clock to SYSCLK ratio and core to SYSCLK ratio settings must be chosen such that the resulting
SYSCLK frequency, core frequency, and platform clock frequency do not exceed their respective maximum or minimum
operating frequencies.
2. The core cluster can run at cluster group PLL/1, PLL/2, or PLL/4. For the PLL/1 case, the minimum frequency is 1000
MHz. With a minimum cluster group PLL frequency of 1000 MHz, this results in a minimum allowable core cluster frequency
of 250 MHz for PLL/4.
3. The memory bus clock speed is half the DDR3/DDR3L data rate. DDR3/3L memory bus clock frequency is limited to min =
533 MHz.
4. The memory bus clock speed is dictated by its own PLL.
5. The integrated flash controller (IFC) clock speed on IFC_CLK[0:1] is determined by half of the platform clock divided by the
IFC ratio programmed in CCR[CLKDIV]. See the chip reference manual for more information.
6. The FMan minimum frequency is 132 MHz for SGMII (1.25G), 330 MHz for SGMII (2.5G), 359 MHz for XAUI, 391 MHz for
HiGig, 469 MHz for HiGig2, and 330 MHz for XFI.
7. The minimum platform frequency should meet the requirements in Minimum platform frequency requirements for high-
speed interfaces.
4.1.2.1 DDR clock ranges
The DDR memory controller can run only in asynchronous mode, where the memory bus
is clocked with the clock provided on the DDRCLK input pin, which has its own
dedicated PLL.
This table provides the clocking specifications for the memory bus.
Table 122. Memory bus clocking specifications
Characteristic Min Max Unit Notes
Memory bus clock frequency 533 1066 MHz 1, 2, 3
Notes:
1. Caution: The platform clock to SYSCLK ratio and core to platform clock ratio settings must be chosen such that the
resulting SYSCLK frequency, core frequency, and platform frequency do not exceed their respective maximum or minimum
operating frequencies.
2. The memory bus clock refers to the chip's memory controllers' Dn_MCK[0:3] and Dn_MCK[0:3]_B output clocks, running at
half of the DDR data rate.
3. The memory bus clock speed is dictated by its own PLL.
Hardware design considerations
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
NXP Semiconductors 151
4.1.3 SerDes PLL ratio
The clock ratio between each of the two SerDes PLLs and their respective externally
supplied SDn_REF_CLKn_P/SDn_REF_CLKn_N inputs is determined by a set of RCW
Configuration fields-SRDS_PRTCL_Sn, SRDS_PLL_REF_CLK_SEL_Sn, and
SRDS_DIV_*_Sn-as shown in this table.
Table 123. Valid SerDes RCW encodings and reference clocks
SerDes protocol (given
lane)
Valid reference
clock
frequency
Legal setting for
SRDS_PRTCL_Sn
Legal setting
for
SRDS_PLL_RE
F_CLK_SEL_Sn
Legal setting for
SRDS_DIV_*_Sn
Notes
High-speed serial and debug interfaces
PCI Express 2.5 GT/s
(doesn't negotiate upwards)
100 MHz Any PCIe 0b0: 100 MHz 2b10: 2.5 G 1
125 MHz 0b1: 125 MHz 1
PCI Express 5 GT/s
(can negotiate up to 5 GT/s)
100 MHz Any PCIe 0b0: 100 MHz 2b01: 5.0 G 1
125 MHz 0b1: 125 MHz 1
PCI Express 8 GT/s
(can negotiate up to 8 GT/s)
100 MHz Any PCIe 0b0: 100 MHz 2b00: 8.0 G 1
125 MHz 0b1: 125 MHz 1
Serial RapidIO 2.5 GBaud 100 MHz SRIO @ 2.5/5 GBaud 0b0: 100 MHz 0b1: 2.5 G -
125 MHz 0b1: 125 MHz -
Serial RapidIO 3.125 GBaud 125 MHz SRIO @ 3.125 GBaud 0b0: 125 MHz Don't care -
156.25 MHz 0b1: 156.25 MHz -
Serial RapidIO 5 GBaud 100 MHz SRIO @ 2.5/5 GBaud 0b0: 100 MHz 0b0: 5.0 G -
125 MHz 0b1: 125 MHz -
SATA (1.5 or 3 Gbps) 100 MHz Any SATA 0b0: 100 MHz Don't care 2
125 MHz 0b1: 125 MHz
Debug (2.5 GBaud) 100 MHz Aurora @ 2.5/5 GBaud 0b0: 100 MHz 0b1: 2.5 G -
125 MHz 0b1: 125 MHz -
Debug (5 GBaud) 100 MHz Aurora @ 2.5/5 GBaud 0b0: 100 MHz 0b0: 5.0 G -
125 MHz 0b1: 125 MHz -
Networking interfaces
SGMII (1.25 GBaud) 100 MHz SGMII @ 1.25 GBaud
1000Base-KX @ 1.25
GBaud
0b0: 100 MHz Don't care -
125 MHz 0b1: 125 MHz -
2.5x SGMII (3.125 GBaud) 125 MHz SGMII @ 3.125 GBaud 0b0: 125 MHz Don't care -
156.25 MHz 0b1: 156.25 MHz -
XAUI (3.125 GBaud) 125 MHz XAUI @ 3.125 GBaud 0b0: 125 MHz Don't care -
156.25 MHz 0b1: 156.25 MHz -
HiGig or HiGig2 (3.125
GBaud)
125 MHz HiGig @ 3.125 GBaud 0b0: 125 MHz Don't care -
156.25 MHz 0b1: 156.25 MHz -
HiGig or HiGig2 (3.75 GBaud) 125 MHz HiGig @ 3.75 GBaud 0b0: 125 MHz Don't care -
156.25 MHz 0b1: 156.25 MHz -
Table continues on the next page...
Hardware design considerations
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Table 123. Valid SerDes RCW encodings and reference clocks (continued)
SerDes protocol (given
lane)
Valid reference
clock
frequency
Legal setting for
SRDS_PRTCL_Sn
Legal setting
for
SRDS_PLL_RE
F_CLK_SEL_Sn
Legal setting for
SRDS_DIV_*_Sn
Notes
XFI (10.3125 GBaud) 156.25 MHz XFI @ 10.3125 GBaud 0b0: 156.25 MHz Don't care -
10GBase-KR (10.3125GBaud) 156.25 MHz 10GBase-KR @ 10.3125
GBaud
0b0: 156.25 MHz Don't care -
Notes:
1. A spread-spectrum reference clock is permitted for PCI Express. However, if any other high-speed interfaces such as
sRIO, SATA, or debug is used concurrently on the same SerDes bank, spread-spectrum clocking is not permitted.
2. SerDes lanes configured as SATA initially operate at 3.0 Gbps. 1.5 Gbps operation may later be enabled through the
SATA IP itself. It is possible for software to set each SATA at different rates.
4.1.4 Frequency options
This section discusses interface frequency options.
4.1.4.1 SYSCLK and platform frequency options
This table shows the expected frequency options for SYSCLK and platform frequencies.
Table 124. SYSCLK and platform frequency options
Platform: SYSCLK ratio SYSCLK (MHz)
66.67 100.00 133.33
Platform frequency (MHz)1
3:1 400
4:1 400 533
5:1 500
6:1 400 600
7:1 466
8:1 533
9:1 600
Notes:
1. Platform frequency values are shown rounded down to the nearest whole number (decimal place accuracy removed).
4.1.4.2 Minimum platform frequency requirements for high-speed
interfaces
The platform clock frequency must be considered for proper operation of high-speed
interfaces as described below.
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For proper PCI Express operation, the platform clock frequency must be greater than or
equal to:
527 MHz x (PCI Express link width)
16
Figure 50. Gen 1 PEX minimum platform frequency
527 MHz x (PCI Express link width)
8
Figure 51. Gen 2 PEX minimum platform frequency
527 MHz x (PCI Express link width)
4
Figure 52. Gen 3 PEX minimum platform frequency
See section "Link Width," in the chip reference manual for PCI Express interface width
details. Note that "PCI Express link width" in the above equation refers to the negotiated
link width as the result of PCI Express link training, which may or may not be the same
as the link width POR selection. It refers to the widest port in use, not the combined
width of the number ports in use. For instance, if two x4 PCIe Gen3 ports are in use, 527
MHz platform frequency is needed to support by using Gen 3 equation (527 x 4 / 4, not
527 x 4 x 2 / 4).
For proper serial RapidIO operation, the platform clock frequency must be greater than or
equal to 525MHz.
4.2 Power supply design
4.2.1 Voltage ID (VID) controllable supply
To guarantee performance and power specifications, a specific method of selecting the
optimum voltage-level must be implemented when the chip is used. As part of the chip's
boot process, software must read the VID efuse values stored in the Fuse Status register
(FUSESR) and then configure the external voltage regulator based on this information.
This method requires a point of load voltage regulator for each chip. The VDD supply
should be separated from the Serdes 1.0V supply SnVDD. It is required in order to control
the VDD supply only.
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NOTE
During the power-on reset process, the fuse values are read and
stored in the FUSESR. It is expected that the chip's boot code
reads the FUSESR value very early in the boot sequence and
updates the regulator accordingly.
The default voltage regulator setting that is safe for the system to boot is the
recommended operating VDD at initial start-up of 1.025V. It is highly recommended to
select a regulator with a Vout range of at least 0.9V to 1.1V, with a resolution of 12.5mV
or better, when implementing a VID solution.
The table below lists the valid VID efuse values that will be programmed at the factory
for this chip.
Table 125. Fuse Status Register
(DCFG_CCSR_FUSESR)
Binary value of DA_V / DA_ALT_V VDD voltage
00000 1.0250 V
00001 0.9875 V
00010 0.9750 V
10000 1.0000 V
10001 1.0125 V
10010 1.0250 V
For additional information on VID, please refer to the chip reference manual.
4.2.1.1 Options for system design
There are several widely-accepted options available to the system designer for obtaining
the benefits of a VID solution. The most common option is to use the VID solution to
drive a system's controllable voltage-regulators through a sideband interface such as a
simple parallel bus or PMBus interface. PMbus is similar to I2C but with extensions to
improve robustness and address shortcomings of I2C; the PMBus specification can be
found at www.pmbus.org. The simple parallel bus is supported by the chip through GPIO
pins and the PMBus interface is supported by an I2C interface. Other VID solutions may
be to access an FPGA/ASIC or separate power management chip through the IFC, SPI, or
other chip-specific interface, where the other device then manages the voltage regulator.
The method chosen for implementing the chip-specific voltage in the system is decided
by the user.
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4.2.1.1.1 Example 1: Regulators supporting parallel bus configuration
In this example, a user builds a VID solution using controllable regulators with a parallel
bus. In this implementation, the user chooses to utilize any subset of the available GPIO
pins on the chip except those noted below.
NOTE
GPIO pins that are muxed on an interface used by the
application for loading RCW information are not available for
VID use.
It is recommended that all GPIO pins used for VID are located
in the same 32-bit GPIO IP block so that all bits can be
accessed with a single read or write.
The general procedure for setting the core voltage regulator to the desired operating
voltage is as follows:
1. The GPIO pins are released to high-impedance at POR. Because GPIO pins default
to being inputs, they do not begin automatically driving after POR, and only work as
outputs under software control.
2. The board is responsible for a default voltage regulator setting that is "safe" for the
system to boot. To achieve this, the user puts pull-up and/or pull-down resistors on
the GPIO pins as needed for that specific system. For the case where the regulator's
interface operates at a different voltage than OVDD, the chip's GPIO module can be
operated in an open drain configuration.
3. There is no direct connection between the Fuse Status Register (FUSESR) and the
chip's pins. As part of the chip's boot process, software must read the efuse values
stored in the FUSESR and then configure the voltage regulator based on this
information. The software determines the proper value for the parallel interface and
writes it to the GPIO block data (GPDAT) register. It then changes the GPIO
direction (GPDIR) register from input to output to drive the new value on the device
pins, thus overriding the board configuration default value. Note that some regulators
may require a series of writes so that the voltage is slowly stepped from its old to its
new value.
4. When the voltage has stabilized, software adjusts the operating frequencies as
desired.
Upon completion of configuration, some regulators may have a write-protect pin to
prevent undesired data changes after configuration is complete. A single GPIO pin on the
chip could be allocated for this task if desired.
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4.2.1.1.2 Example 2: Regulators supporting PMBus configuration
In this example, a user builds a VID solution using controllable regulators with a PMBus
interface. For the case where the regulator's interface operates at a different voltage than
DVDD, the chip's I2C module can be operated in an open-drain configuration.
In this implementation, the user chooses to utilize any I2C interface available on the chip.
These regulators have a means for setting a safe, default, operating value either through
strapping pins or through a default, non-volatile store.
NOTE
If I2C1 controller is selected, it is important that its calling
address is different than the 7-bit value of 0x50h used by the
pre-boot loader (PBL) for RCW and pre-boot initialization.
The general procedure for setting the core voltage regulator to the desired operating
voltage is as follows:
1. The board is responsible for configuring a safe default value for the controllable
regulator either through dedicated pins or its non-volatile store.
2. As part of the chip's boot process, software must read the efuse values stored in the
FUSESR register and then configure the voltage regulator based on this information.
The software decides on a new configuration and sends this value across the I2C
interface connected to the regulator's PMBus interface. Note that some regulators
may require a series of writes so that the voltage is slowly stepped from its old to its
new value.
3. When the voltage has stabilized, software adjusts the operating frequencies as
desired.
Upon completion of configuration, some regulators may have a write-protect pin to
prevent undesired data changes after configuration is complete. A single GPIO pin on the
chip could be allocated for this task, if desired.
4.2.1.1.3 Example 3: Regulators supporting FPGA/ASIC or separate power
management device configuration
In this example, a user builds a VID solution using controllable regulators that are
managed by a FPGA/ASIC or a separate power-management device. In this
implementation, the user chooses to utilize the IFC, eSPI or any other available chip
interface to connect to the power-management device.
The general procedure for setting the core voltage regulator to the desired operating
voltage is as follows:
1. The board is responsible for configuring a safe default value for the controllable
regulator either through dedicated pins or its non-volatile store.
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2. As part of the chip's boot process, software must read the efuse values stored in the
FUSESR and then configure the voltage regulator based on this information. The
software decides on a new configuration and sends this value across the IFC, eSPI, or
any other interface that is used to connect to the FPGA/ASIC or separate power-
management device that manages the regulator. Note that some regulators may
require a series of writes so that the voltage is slowly stepped from its old to its new
value.
3. When the voltage has stabilized, software adjusts the operating frequencies as
desired.
Upon completion of configuration, some regulators may have a write-protect pin to
prevent undesired data changes after configuration is complete. A single GPIO pin on the
chip could be allocated for this task, if desired.
4.2.2 Core and platform supply voltage filtering
The VDD supply is normally derived from a high current capacity linear or switching
power supply which can regulate its output voltage very accurately despite changes in
current demand from the chip within the regulator's relatively low bandwidth. Several
bulk decoupling capacitors must be distributed around the PCB to supply transient
current demand above the bandwidth of the voltage regulator.
These bulk capacitors should have a low ESR (equivalent series resistance) rating to
ensure the quick response time necessary. They should also be connected to the power
and ground planes through two vias to minimize inductance. However, customers should
work directly with their power regulator vendor for best values and types of bulk
capacitors.
As a guideline for customers and their power regulator vendors, NXP recommends that
these bulk capacitors should be chosen to maintain the positive transient power surges to
less than VID + 50 mV (negative transient undershoot should comply with specification
of VID - 30mV) for current steps of up to 10 A with a slew rate of 12 A/us.
These bulk decoupling capacitors will ideally supply a stable voltage for current
transients into the megahertz range. Above that, see Decoupling recommendations for
further decoupling recommendations.
4.2.3 PLL power supply filtering
Each of the PLLs described in System clocking is provided with power through
independent power supply pins (AVDD_PLAT, AVDD_CGAn, AVDD_CGBn and
AVDD_Dn and AVDD_ SDn_PLLn). AVDD_PLAT, AVDD_CGAn, AVDD_CGBn and
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AVDD_Dn voltages must be derived directly from a 1.8 V voltage source through a low
frequency filter scheme. AVDD_ SDn_PLLn voltages must be derived directly from the
XnVDD source through a low frequency filter scheme. The recommended solution for
PLL filtering is to provide independent filter circuits per PLL power supply, as illustrated
in Figure 53, one for each of the AVDD pins. By providing independent filters to each
PLL, the opportunity to cause noise injection from one PLL to the other is reduced. This
circuit is intended to filter noise in the PLL's resonant frequency range from a 500 kHz to
10 MHz range.
Each circuit should be placed as close as possible to the specific AVDD pin being
supplied to minimize noise coupled from nearby circuits. It should be possible to route
directly from the capacitors to the AVDD pin, which is on the periphery of the footprint,
without the inductance of vias.
This figure shows the PLL power supply filter circuit.
Where:
• R = 5 Ω ± 5%
• C1 = 10 μF ± 10%, 0603, X5R, with ESL ≤ 0.5 nH
• C2 = 1.0 μF ± 10%, 0402, X5R, with ESL ≤ 0.5 nH
NOTE
A higher capacitance value for C2 may be used to improve
the filter as long as the other C2 parameters do not change
(0402 body, X5R, ESL ≤ 0.5 nH).
NOTE
Voltage for AVDD is defined at the input of the PLL supply
filter and not the pin of AVDD.
1.8 V source R
C1 C2
GND
Low-ESL surface-mount capacitors
AVDD_PLAT, AVDD_CGAn, AVDD_D1
Figure 53. PLL power supply filter circuit
The AVDD_ SDn_PLLn signals provides power for the analog portions of the SerDes
PLL. To ensure stability of the internal clock, the power supplied to the PLL is filtered
using a circuit similar to the one shown in following Figure 54. For maximum
effectiveness, the filter circuit is placed as closely as possible to the AVDD_ SDn_PLLn
balls to ensure it filters out as much noise as possible. The ground connection should be
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near the AVDD_ SDn_PLLn balls. The 0.003-µF capacitors closest to the balls, followed
by a 4.7-µF and 47-µF capacitor, and finally the 0.33 Ω resistor to the board supply plane.
The capacitors are connected from AVDD_ SDn_PLLn to the ground plane. Use ceramic
chip capacitors with the highest possible self-resonant frequency. All traces should be
kept short, wide, and direct.
XnVDD
0.33 Ω AVDD_SDn_PLLn
47 µF 4.7 µF 0.003 µF
AGND_SDn_PLLn
Figure 54. SerDes PLL power supply filter circuit
Note the following:
•AVDD_ SDn_PLLn should be a filtered version of XnVDD.
•Signals on the SerDes interface are fed from the XnVDD power plane.
•Voltage for AVDD_ SDn_PLLn is defined at the PLL supply filter and not the pin of
AVDD_ SDn_PLLn.
• A 47-µF 0805 XR5 or XR7, 4.7-µF 0603, and 0.003-µF 0402 capacitor are
recommended. The size and material type are important. A 0.33-Ω ± 1% resistor is
recommended.
•There needs to be dedicated analog ground, AGND_ SDn_PLLn for each AVDD_
SDn_PLLn pin up to the physical local of the filters themselves.
4.2.4 SnVDD power supply filtering
For initial system bring-up, the linear regulator option is highly recommended.
An example solution for SnVDD filtering, where SnVDD is sourced from a linear
regulator, is illustrated in Figure 55. The component values in this example filter are
system dependent and are still under characterization, component values may need
adjustment based on the system or environment noise.
Where:
• C1 = 0.003 μF ± 10%, X5R, with ESL ≤ 0.5 nH
• C2 and C3 = 2.2 μF ± 10%, X5R, with ESL ≤ 0.5 nH
• F1 and F2 = 120 Ω at 100 MHz 2A 25% 0603 Ferrite (for example, Murata
BLM18PG121SH1)
• Bulk and decoupling capacitors are added, as needed, per power supply design.
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160 NXP Semiconductors
SnVDD Linear regulator output
C1 C2 C3
GND
Bulk and
decoupling
capacitors
F1
F2
Figure 55. SnVDD power supply filter circuit
Note the following:
•Please refer to Power-on ramp rate, for maximum SnVDD power-up ramp rate.
• There needs to be enough output capacitance or a soft start feature to assure ramp
rate requirement is met.
• The ferrite beads should be placed in parallel to reduce voltage droop.
• Besides a linear regulator, a low noise dedicated switching regulator can also be
used. 10 mVp-p, 50kHz - 500MHz is the noise goal.
4.2.5 XnVDD power supply filtering
XnVDD may be supplied by a linear regulator or sourced by a filtered G1VDD. Systems
may design in both options to allow flexibility to address system noise dependencies.
However, for initial system bring-up, the linear regulator option is highly recommended.
An example solution for XnVDD filtering, where XnVDD is sourced from a linear
regulator, is illustrated in Figure 56. The component values in this example filter are
system dependent and are still under characterization, component values may need
adjustment based on the system or environment noise.
Where:
• C1 = 0.003 μF ± 10%, X5R, with ESL ≤ 0.5 nH
• C2 and C3 = 2.2 μF ± 10%, X5R, with ESL ≤ 0.5 nH
• F1 and F2 = 120 Ω at 100 MHz 2A 25% 0603 Ferrite (for example, Murata
BLM18PG121SH1)
• Bulk and decoupling capacitors are added, as needed, per power supply design.
XnVDD Linear regulator output
C1 C2 C3
GND
Bulk and
decoupling
capacitors
F1
F2
Figure 56. XnVDD power supply filter circuit
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Note the following:
•See Power-on ramp rate for maximum XnVDD power-up ramp rate.
• There needs to be enough output capacitance or a soft-start feature to assure ramp
rate requirement is met.
• The ferrite beads should be placed in parallel to reduce voltage droop.
• Besides a linear regulator, a low-noise, dedicated switching regulator can be used. 10
mVp-p, 50 kHz - 500 MHz is the noise goal.
4.2.6 USB_HVDD and USB_OVDD power supply filtering
USB_HVDD and USB_OVDD must be sourced by a filtered 3.3 V and 1.8 V voltage
source using a star connection. An example solution for USB_HVDD and USB_OVDD
filtering, where USB_HVDD and USB_OVDD are sourced from a 3.3 V and 1.8 V voltage
source, is illustrated in the following figure. The component values in this example filter
is system dependent and are still under characterization, component values may need
adjustment based on the system or environment noise.
Where:
• C1 = 0.003 μF ± 10%, X5R, with ESL ≤ 0.5 nH
• C2 and C3 = 2.2 μF ± 10%, X5R, with ESL ≤ 0.5 nH
• F1 = 120 Ω at 100 MHz 2A 25% 0603 Ferrite (for example, Murata
BLM18PG121SH1)
• Bulk and decoupling capacitors are added, as needed, per power supply design.
USB_HVDD
or USB_OVDD
3.3 V or 1.8 V source
C1 C2 C3
GND
Bulk and
decoupling
capacitors
F1
Figure 57. USB_HVDD and USB_OVDD power supply filter circuit
4.2.7 USB_SVDD power supply filtering
USB_SVDD must be sourced by a filtered VDD using a star connection. An example
solution for USB_SVDD filtering, where USB_SVDD is sourced from VDD, is illustrated
in the following figure. The component values in this example filter is system dependent
and are still under characterization, component values may need adjustment based on the
system or environment noise.
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162 NXP Semiconductors
Where:
• C1 = 2.2 μF ± 20%, X5R, with Low ESL (for example, Panasonic ECJ0EB0J225M)
• F1 = 120 Ω at 100-MHz 2A 25% Ferrite (for example, Murata BLM18PG121SH1)
• Bulk and decoupling capacitors are added, as needed, per power supply design.
USB_SVDD VDD
C1
GND
Bulk and
decoupling
capacitors
F1
C1
USB_SVDD VDD
C1
GND
Bulk and
decoupling
capacitors
F1
C1
Figure 58. USB_SVDD power supply filter circuit
4.3 Decoupling recommendations
Due to large address and data buses, and high operating frequencies, the device can
generate transient power surges and high frequency noise in its power supply, especially
while driving large capacitive loads. This noise must be prevented from reaching other
components in the chip system, and the chip itself requires a clean, tightly regulated
source of power. Therefore, it is recommended that the system designer place at least one
decoupling capacitor at each VDD, OVDD, DVDD, G1VDD, and LVDD pin of the device.
These decoupling capacitors should receive their power from separate VDD, OVDD,
DVDD, G1VDD, LVDD, and GND power planes in the PCB, utilizing short traces to
minimize inductance. Capacitors may be placed directly under the device using a
standard escape pattern. Others may surround the part.
These capacitors should have a value of 0.1 µF. Only ceramic SMT (surface mount
technology) capacitors should be used to minimize lead inductance, preferably 0402 or
0603 sizes.
As presented in Core and platform supply voltage filtering, it is recommended that there
be several bulk storage capacitors distributed around the PCB, feeding the VDD and other
planes (for example, OVDD, DVDD, G1VDD, and LVDD), to enable quick recharging of
the smaller chip capacitors.
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4.4 SerDes block power supply decoupling recommendations
The SerDes block requires a clean, tightly regulated source of power (SnVDD and
XnVDD) to ensure low jitter on transmit and reliable recovery of data in the receiver. An
appropriate decoupling scheme is outlined below.
NOTE
Only SMT capacitors should be used to minimize inductance.
Connections from all capacitors to power and ground should be
done with multiple vias to further reduce inductance.
1. The board should have at least 1 x 0.1-uF SMT ceramic chip capacitor placed as
close as possible to each supply ball of the device. Where the board has blind vias,
these capacitors should be placed directly below the chip supply and ground
connections. Where the board does not have blind vias, these capacitors should be
placed in a ring around the device as close to the supply and ground connections as
possible.
2. Between the device and any SerDes voltage regulator there should be a lower bulk
capacitor for example a 10-uF, low ESR SMT tantalum or ceramic and a higher bulk
capacitor for example a 100uF - 300-uF low ESR SMT tantalum or ceramic
capacitor.
4.5 Connection recommendations
The following is a list of connection recommendations:
• To ensure reliable operation, it is highly recommended to connect unused inputs to
an appropriate signal level. Unless otherwise noted in this document, all unused
active low inputs should be tied to VDD, OVDD, DVDD, G1VDD, and LVDD as
required. All unused active high inputs should be connected to GND. All NC (no-
connect) signals must remain unconnected. Power and ground connections must be
made to all external VDD, OVDD, DVDD, G1VDD, LVDD and GND pins of the device.
• The TEST_SEL_B pin must be pulled high.
• The chip has temperature diodes on the microprocessor that can be used in
conjunction with other system temperature monitoring devices (such as on
Semiconductor, NCT72). Even if a temperature diode monitoring device is not
utilized on production systems, being able to access these pins for debug or problem
analysis can be valuable. Therefore, it is suggested to connect these pins to test points
connected to ground through low value resistors, which can be removed if a
temperature monitoring device is ever to be connected. The chip temperature diode
specifications are as follows:
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• Operating range: 10 - 230 µA
• Ideality factor over 13.5 - 220 µA: Temperature range 25°C - 105°C n =
1.006833 ± 0.008
4.5.1 Legacy JTAG configuration signals
Correct operation of the JTAG interface requires configuration of a group of system
control pins as demonstrated in Figure 60. Care must be taken to ensure that these pins
are maintained at a valid deasserted state under normal operating conditions as most have
asynchronous behavior and spurious assertion will give unpredictable results.
Boundary-scan testing is enabled through the JTAG interface signals. The TRST_B
signal is optional in the IEEE Std 1149.1 specification, but it is provided on all processors
built on Power Architecture technology. The device requires TRST_B to be asserted
during power-on reset flow to ensure that the JTAG boundary logic does not interfere
with normal chip operation. While the TAP controller can be forced to the reset state
using only the TCK and TMS signals, generally systems assert TRST_B during the
power-on reset flow. Simply tying TRST_B to PORESET_B is not practical because the
JTAG interface is also used for accessing the common on-chip processor (COP), which
implements the debug interface to the chip.
The COP function of these processors allow a remote computer system (typically, a PC
with dedicated hardware and debugging software) to access and control the internal
operations of the processor. The COP interface connects primarily through the JTAG port
of the processor, with some additional status monitoring signals. The COP port requires
the ability to independently assert PORESET_B or TRST_B in order to fully control the
processor. If the target system has independent reset sources, such as voltage monitors,
watchdog timers, power supply failures, or push-button switches, then the COP reset
signals must be merged into these signals with logic.
The arrangement shown in Figure 60 allows the COP port to independently assert
PORESET_B or TRST_B, while ensuring that the target can drive PORESET_B as well.
The COP interface has a standard header, shown in Figure 59, for connection to the target
system, and is based on the 0.025" square-post, 0.100" centered header assembly (often
called a Berg header). The connector typically has pin 14 removed as a connector key.
The COP header adds many benefits such as breakpoints, watchpoints, register and
memory examination/modification, and other standard debugger features. An inexpensive
option can be to leave the COP header unpopulated until needed.
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There is no standardized way to number the COP header; so emulator vendors have
issued many different pin numbering schemes. Some COP headers are numbered top-to-
bottom then left-to-right, while others use left-to-right then top-to-bottom. Still others
number the pins counter-clockwise from pin 1 (as with an IC). Regardless of the
numbering scheme, the signal placement recommended in Figure 59 is common to all
known emulators.
4.5.1.1 Termination of unused signals
If the JTAG interface and COP header will not be used, NXP recommends the following
connections:
• TRST_B should be tied to PORESET_B through a 0 kΩ isolation resistor so that it is
asserted when the system reset signal (PORESET_B) is asserted, ensuring that the
JTAG scan chain is initialized during the power-on reset flow. NXP recommends
that the COP header be designed into the system as shown in Figure 60. If this is not
possible, the isolation resistor will allow future access to TRST_B in case a JTAG
interface may need to be wired onto the system in future debug situations.
• No pull-up/pull-down is required for TDI, TMS or TDO.
1 2
3
5
7
9
11
13
15
4
6
8
10
12
KEY
No pin
16
COP_TDO
COP_TDI
NC
COP_TCK
COP_TMS
COP_SRESET_B
COP_HRESET_B
COP_CHKSTP_OUT_B GND
NC
NC
NC
COP_TRST_B
COP_VDD_SENSE
COP_CHKSTP_IN_B
Figure 59. Legacy COP connector physical pinout
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166 NXP Semiconductors
1 2
3
5
7
9
11
13
15
4
6
8
10
12
16
COP connector
physical pinout
5
6
4
11
13
Notes:
1. The COP port and target board should be able to independently assert PORESET_B and TRST_B to the processor in
order to fully control the processor as shown here.
2. Populate this with a 10 Ω resistor for short-circuit/current-limiting protection.
3. The KEY location (pin 14) is not physically present on the COP header.
4. Although pin 12 is defined as a no-connect, some debug tools may use pin 12 as an additional GND pin for improved signal integrity.
5. This switch is included as a precaution for BSDL testing. The switch should be closed to position A during BSDL testing to avoid accidentally
asserting the TRST_B line. If BSDL testing is not being performed, this switch should be closed to position B.
6. Asserting HRESET_B causes a hard reset on the device
7. This is an open-drain output gate.
10 kΩ
NC
COP_VDD_SENSE2
COP_TRST_B
10 kΩ
10 kΩ
10 kΩ
10 kΩ
10 kΩ
1 kΩ
HRESET_B6
PORESET_B1
TRST_B1
TMS
TDO
TDI
TCK
OVDD
7
HRESET_B
PORESET_B
From target
board sources
(if any)
COP_HRESET_B
B
A
5
10 Ω
KEY
No pin
10 kΩ
4
16
12
NC
NC
10
2
7
3
1
9
8
COP_TCK
COP_TDI
COP_TDO
COP_TMS
COP_CHKSTP_IN_B System logic
COP_SRESET_B
COP_CHKSTP_OUT_B
COP header
15
143
CKSTP_OUT_B
10 kΩ
Figure 60. Legacy JTAG interface connection
Hardware design considerations
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
NXP Semiconductors 167
4.5.2 Aurora configuration signals
Correct operation of the Aurora interface requires configuration of a group of system
control pins as demonstrated in the figures below. Care must be taken to ensure that these
pins are maintained at a valid deasserted state under normal operating conditions as most
have asynchronous behavior and spurious assertion will give unpredictable results.
NXP recommends that the Aurora 34 pin duplex connector be designed into the system as
shown in Figure 63 or the 70 pin duplex connector be designed into the system as shown
in Figure 64.
If the Aurora interface will not be used, NXP recommends the legacy COP header be
designed into the system as described in "Termination of unused signals" in the chip
reference manual.
Hardware design considerations
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
168 NXP Semiconductors
1 2
3
5
7
9
11
13
15
4
6
8
10
12
16
TX0_P
TX0_N
GND
TX1_P
TX1_N
GND
RX0_P
RX0_N
VIO (VSense)
TDO
TRST
TCK
TMS
TDI
GND
RX1_P
RX1_N
GND
TX2_P
TX2_N
GND
TX3_P
TX3_N
Vendor I/O 0
Vendor I/O 1
Vendor I/O 2
Vendor I/O 3
RESET
GND
CLK_P
CLK_N
GND
Vendor I/O 4
Vendor I/O 5
14
17
19
21
23
25
27
29
31
33
18
20
22
24
26
28
30
32
34
Figure 61. Aurora 34 pin connector duplex pinout
Hardware design considerations
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
NXP Semiconductors 169
1 2
3
5
7
9
11
13
15
4
6
8
10
12
16
TX0_P
TX0_N
GND
TX1_P
TX1_N
GND
RX0_P
RX0_N
VIO (VSense)
TDO
TRST
TCK
TMS
TDI
GND
RX1_P
RX1_N
GND
TX2_P
TX2_N
GND
TX3_P
TX3_N
Vendor I/O 0
Vendor I/O 1
Vendor I/O 2
Vendor I/O 3
RESET
GND
CLK_P
CLK_N
GND
Vendor I/O 4
Vendor I/O 5
GND
RX2_P
RX2_N
14
17
19
21
23
25
27
29
31
33
18
20
22
24
26
28
30
32
34
35 36
37
39
41
43
45
47
49
38
40
42
44
46
50
RX3_P
RX3_N
TX4_P
N/C
N/C
GND
TX4_N
GND
TX5_P
TX5_N
GND
TX6_P
TX6_N
GND
TX7_P
N/C
N/C
N/C
N/C
GND
GND
N/C
GND
N/C
GND
GND
GND
N/C
N/C
N/C
TX7_N
GND
N/C
48
51
53
55
57
59
61
63
65
67
52
54
56
58
60
62
64
66
68
69 70
Figure 62. Aurora 70 pin connector duplex pinout
Hardware design considerations
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
170 NXP Semiconductors
1 2
3
5
7
9
11
13
15
4
6
8
10
12
16
14
17
19
21
23
25
27
29
31
33
18
20
22
24
26
28
30
32
34
Duplex 34 Connector
Physical Pinout
29, 30
23, 24
5, 11, 17
21
19
15
13
9
7
3
1
28
14
16
18
34
4
8
10
6
2
12
32, 33
27, 31
20, 25
22
Notes:
1. The Aurora port and target board should be able to independently assert PORESET_B and TRST_B to the processor in
order to fully control the processor as shown here.
2. Populate this with a 1 kΩ resistor for short-circuit/current-limiting protection.
3. This switch is included as a precaution for BSDL testing. The switch should be closed to position A during BSDL testing to avoid accidentally
asserting the TRST_B line. If BSDL testing is not being performed, this switch should be closed to position B.
4. Asserting HREST_B causes a hard reset on the device
5. This is an open-drain output gate.
6. REF_CLK_P/REF_CLK_N and REF_CLK1_P/REFCLK1_N are buffered clocks from the same common source.
26
NC
REF_CLK_P
REF_CLK_N
REF_CLK1_P
REF_CLK1_N
66
0.01 uF
0.01 uF
0.01 uF
0.01 uF
RX1_N
RX1_P
RX0_N
RX0_P
TX1_N
TX1_P
TX0_N
TX0_P
CLK_N
CLK_P
100 nF
100 nF
Vendor I/O 0 (Aurora_HALT_B)
Vendor I/O 1 (Aurora_Event_In_B)
Vendor I/O 2 (Aurora_Event_Out_B)
Vendor I/O 5 (Aurora_HRESET_B)
10 kΩ
AURORA_TCK
AURORA_TDI
AURORA_TDO
AURORA_TMS
VIO VSense2
AURORA_TRST_B
10 kΩ
10 kΩ
10 kΩ
10 kΩ
10 kΩ
1 kΩ
HRESET_B4
PORESET_B1
TRST_B1
TMS
TDO
TDI
TCK
EVT[4]
EVT[1]
EVT[0]
SD2_REF_CLKn_P
SD2_REF_CLKn_N
SD2_TX5_P
SD2_TX5_N
SD2_TX4_P
SD2_TX4_N
SD2_RX5_P
SD2_RX5_N
SD2_RX4_P
SD2_RX4_N
OVDD
5
HRESET_B
PORESET_B
From target
board sources
(if any)
RESET
B
A
3
1 kΩ
Figure 63. Aurora 34 pin connector duplex interface connection
Hardware design considerations
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
NXP Semiconductors 171
Duplex 70 Connector
Physical Pinout 5, 11, 17, 23, 24,
29, 30, 35, 36, 41,
42, 47, 48, 53, 54,
59, 60, 65, 66
21
19
15
13
9
7
3
1
14
16
18
34
4
8
10
6
2
12
20, 25, 27, 31,
32, 33, 37, 38,
39, 40, 43, 44,
45, 46, 49, 50,
51, 52, 55, 56,
57, 58, 61, 62,
63, 64, 67, 68,
69, 70
22
Notes:
1. The Aurora port and target board should be able to independently assert PORESET_B and TRST_B to the processor in
order to fully control the processor as shown here.
2. Populate this with a 1 kΩ resistor for short-circuit/current-limiting protection.
3. This switch is included as a precaution for BSDL testing. The switch should be closed to position A during BSDL testing to avoid accidentally
asserting the TRST_B line. If BSDL testing is not being performed, this switch should be closed to position B.
4. Asserting HREST_B causes a hard reset on the device
5. This is an open-drain output gate.
6. REF_CLK_P/REF_CLK_N and REF_CLK1_P/REFCLK1_N are buffered clocks from the same common source.
NC
REF_CLK_P
REF_CLK_N
REF_CLK1_P
REF_CLK1_N
66
0.01 uF
0.01 uF
0.01 uF
0.01 uF
RX1_N
RX1_P
RX0_N
RX0_P
TX1_N
TX1_P
TX0_N
TX0_P
CLK_N
CLK_P
100 nF
100 nF
Vendor I/O 5 (Aurora_HRESET_B)
10 kΩ
AURORA_TCK
AURORA_TDI
AURORA_TDO
AURORA_TMS
VIO VSense2
AURORA_TRST_B
10 kΩ
10 kΩ
10 kΩ
10 kΩ
10 kΩ
1 kΩ
HRESET_B4
PORESET_B1
TRST_B1
TMS
TDO
TDI
TCK
SD2_REF_CLKn_P
SD2_REF_CLKn_N
SD2_TX5_P
SD2_TX5_N
SD2_TX4_P
SD2_TX4_N
SD2_RX5_P
SD2_RX5_N
SD2_RX4_P
SD2_RX4_N
1 2
3
5
7
9
11
13
15
4
6
8
10
12
16
14
17
19
21
23
25
27
29
31
33
18
20
22
24
26
28
30
32
34
35 36
37
39
41
43
45
47
49
38
40
42
44
46
50
48
51
53
55
57
59
61
63
65
67
52
54
56
58
60
62
64
66
68
69 70
28
26
Aurora Header
OVDD
5
HRESET_B
PORESET_B
From target
board sources
(if any)
Reset
3
B
A
Vendor I/O 0 (Aurora_HALT_B)
Vendor I/O 1 (Aurora_Event_In_B)
Vendor I/O 2 (Aurora_Event_Out_B) EVT[4]
EVT[1]
EVT[0]
1 kΩ
Figure 64. Aurora 70 pin connector duplex interface connection
Hardware design considerations
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
172 NXP Semiconductors
4.5.3 Guidelines for high-speed interface termination
4.5.3.1 SerDes interface entirely unused
If the high-speed SerDes interface is not used at all, the unused pin should be terminated
as described in this section.
Note that SnVDD, XnVDD and AVDD_SDn_PLLn must remain powered.
For AVDD_SDn_PLLn, it must be connected to XnVDD through a zero ohm resistor
(instead of filter circuit shown in Figure 54).
The following pins must be left unconnected:
•SDn_TX[7:0]_P
•SDn_TX[7:0]_N
The following pins must be connected to SnGND:
•SDn_RX[7:0]_P
•SDn_RX[7:0]_N
•SDn_REF_CLK1_P, SDn_REF_CLK2_P
•SDn_REF_CLK1_N, SDn_REF_CLK2_N
The following pins must be left unconnected:
•SDn_IMP_CAL_RX
•SDn_IMP_CAL_TX
It is possible to independently disable each SerDes module by disabling all PLLs
associated with it.
SerDes n = 1:2 is disabled as follows:
•SRDS_PLL_PD_Sn = 2’b11 (both PLLs configured as powered down)
•SRDS_PLL_REF_CLK_SEL_Sn = 2’b00
•SRDS_PRTCL_Sn = 2 (no other values permitted when both PLLs are powered
down
4.5.3.2 SerDes interface partly unused
If only part of the high speed SerDes interface pins are used, the remaining high-speed
serial I/O pins should be terminated as described in this section.
Note that both SnVDD and XnVDD must remain powered.
Hardware design considerations
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
NXP Semiconductors 173
If any of the PLLs are un-used, the corresponding AVDD_SDn_PLLn must be connected
to XnVDD through a zero ohm resistor (instead of filter circuit shown in Figure 54).
The following unused pins must be left unconnected:
•SDn_TX[n]_P
•SDn_TX[n]_N
The following unused pins must be connected to SnGND:
•SDn_RX[n]_P
•SDn_RX[n]_N
• SD1_REF_CLK[1:2]_P, SD1_REF_CLK[1:2]_N (If entire SerDes 1 unused)
• SD2_REF_CLK[1:2]_P, SD2_REF_CLK[1:2]_N (If entire SerDes 2 unused)
In the RCW configuration field SRDS_PLL_PD_Sn, the respective bits for each unused
PLL must be set to power it down. A module is disabled when both its PLLs are turned
off.
After POR, if an entire SerDes module is unused, it must be powered down by clearing
the SDEN fields of its corresponding PLL1 and PLL2 reset control registers
(SRDSxPLLnRSTCTL).
Unused lanes must be powered down by clearing the RRST and TRST fields and setting
the RX_PD and TX_PD fields in the corresponding lane's general control register
(SRDSxLNmGCR0).
4.5.4 USB controller connections
This section details the hardware connections required for the USB controllers.
4.5.4.1 USB divider network
This figure shows the required divider network for the VBUS interface for the chip.
Additional requirements for the external components are:
• Both resistors require 1% accuracy and a current capability of up to 1 mA. They must
both have the same temperature coefficient and accuracy.
• The zener diode must have a value of 5 V−5.25 V.
• The 0.6 V diode requires an IF = 10 mA, IR < 500 nA and VF(Max) = 0.8 V. If the
USB PHY does not support OTG mode, this diode can be removed from the
schematic or made a DNP component.
Hardware design considerations
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
174 NXP Semiconductors
VBUS
(USB connector)
5 VZ
51.2 k Ω
18.1 k Ω
0.6 VF
VBUS charge
pump
USBn_DRVVBUS
USBn_PWRFAULT
USBn_VBUSCLMP
Chip
Figure 65. Divider network at VBUS
4.6 Thermal
This table shows the thermal characteristics for the chip. Note that these numbers are
based on design estimates and are preliminary.
Table 126. Package thermal characteristics1 (Rev 1.1)
Rating Board Symbol Value Unit Notes
Junction to ambient, natural convection Single-layer board (1s) RΘJA 20 °C/W 2, 3
Junction to ambient, natural convection Four-layer board (2s2p) RΘJA 13 °C/W 2, 4
Junction to ambient (at 200 ft./min.) Single-layer board (1s) RΘJMA 14 °C/W 2, 3
Junction to ambient (at 200 ft./min.) Four-layer board (2s2p) RΘJMA 10 °C/W 2, 3
Junction to board — RΘJB 4 °C/W 4
Junction to case top — RΘJCTOP 0.6 °C/W 5
Junction to lid top — RΘJCLID 0.25 °C/W 6
Notes:
1. See Thermal management information for additional details.
2. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site
(board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal
resistance.
3. Per JEDEC JESD51-3 and JESD51-6 with the board (JESD51-9) horizontal.
4. Thermal resistance between the die and the printed-circuit board per JEDEC JESD51-8. Board temperature is measured
on the top surface of the board near the package.
5. Junction-to-case-top at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate temperature
is used for the case temperature. Reported value includes the thermal resistance of the interface layer.
6. Junction-to-lid-top thermal resistance determined using the MIL-STD 883 Method 1012.1. However, instead of the cold
plate, the lid top temperature is used here for the reference case temperature. Reported value does not include the thermal
resistance of the interface layer between the package and cold plate.
Hardware design considerations
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
NXP Semiconductors 175
4.7 Recommended thermal model
Information about Flotherm models of the package or thermal data not available in this
document can be obtained from your local NXP sales office.
4.8 Thermal management information
This section provides thermal management information for the flip-chip, plastic-ball, grid
array (FC-PBGA) package for air-cooled applications. Proper thermal control design is
primarily dependent on the system-level design-the heat sink, airflow, and thermal
interface material.
The recommended attachment method to the heat sink is illustrated in Figure 66. The heat
sink should be attached to the printed-circuit board with the spring force centered over
the die. This spring force should not exceed 18 pounds force (80 Newton).
Heat sink
Heat sink clip
Adhesive or
thermal interface material
Printed circuit-board
Lid adhesive
Die
Die lid
FC-PBGA package (with lid)
Figure 66. Package exploded, cross-sectional view-FC-PBGA (with lid) - Rev 1.1
The system board designer can choose between several types of heat sinks to place on the
device. There are several commercially-available thermal interfaces to choose from in the
industry. Ultimately, the final selection of an appropriate heat sink depends on many
factors, such as thermal performance at a given air velocity, spatial volume, mass,
attachment method, assembly, and cost.
For additional information regarding thermal management of lid-less flip-chip packages,
refer to application note AN4871 "Assembly Handling and Thermal Solutions for Lidless
Flip Chip Ball Grid Array Packages".
Hardware design considerations
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
176 NXP Semiconductors
4.8.1 Internal package conduction resistance
For the package, the intrinsic internal conduction thermal resistance paths are as follows:
• The die junction-to-case thermal resistance
• The die junction-to-board thermal resistance
This figure depicts the primary heat transfer path for a package with an attached heat sink
mounted to a printed-circuit board.
External resistance
External resistance
Internal resistance
(Note the internal versus external package resistance)
Radiation Convection
Radiation Convection
Heat sink
Thermal interface material
Die/Package
Die junction
Package/Solder balls
Printed-circuit board
Figure 67. Package with heat sink mounted to a printed-circuit board
The heat sink removes most of the heat from the device. Heat generated on the active side
of the chip is conducted through the silicon and through the heat sink attach material (or
thermal interface material), and finally to the heat sink. The junction-to-case thermal
resistance is low enough that the heat sink attach material and heat sink thermal
resistance are the dominant terms.
Hardware design considerations
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
NXP Semiconductors 177
4.8.2 Thermal interface materials
A thermal interface material is required at the package-to-heat sink interface to minimize
the thermal contact resistance. The performance of thermal interface materials improves
with increasing contact pressure; this performance characteristic chart is generally
provided by the thermal interface vendor. The recommended method of mounting heat
sinks on the package is by means of a spring clip attachment to the printed-circuit board
(see Figure 66).
The system board designer can choose among several types of commercially-available
thermal interface materials.
5Package information
5.1 Package parameters for the FC-PBGA
The package parameters are as provided in the following list. The package type is 25 mm
x 25 mm, 896 flip-chip, plastic-ball, grid array (FC-PBGA).
Rev 1.1:
• Package outline - 25 mm x 25 mm
• Interconnects - 896
• Ball pitch - 0.8 mm
• Ball diameter (typical) - 0.45 mm
• Solder balls - 96.5% Sn, 3% Ag, 0.5% Cu
• Module height - 2.31 mm (minimum), 2.46 mm (typical), 2.61 (maximum)
5.2 Mechanical dimensions of the FC-PBGA
This figure shows the mechanical dimensions and bottom surface nomenclature of the
chip for Rev 1.1 silicon.
Package information
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
178 NXP Semiconductors
Figure 68. Mechanical dimensions of the FC-PBGA, with lid
Package information
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
NXP Semiconductors 179
NOTES:
1. All dimensions are in millimeters.
2. Dimensions and tolerances per ASME Y14.5M-1994.
3. Maximum solder ball diameter measured parallel to datum A.
4. Datum A, the seating plane, is determined by the spherical crowns of the solder balls.
5. Parallelism measurement shall exclude any effect of mark on top surface of package.
6 Security fuse processor
This chip implements the QorIQ platform's Trust Architecture, supporting capabilities
such as secure boot. Use of the Trust Architecture features is dependent on programming
fuses in the Security Fuse Processor (SFP). The details of the Trust Architecture and SFP
can be found in the chip reference manual.
To program SFP fuses, the user is required to supply 1.80 V to the PROG_SFP pin per
Power sequencing. PROG_SFP should only be powered for the duration of the fuse
programming cycle, with a per device limit of eight fuse programming cycles. All other
times PROG_SFP should be connected to GND. The sequencing requirements for raising
and lowering PROG_SFP are shown in Figure 8. To ensure device reliability, fuse
programming must be performed within the recommended fuse programming
temperature range per Table 3.
NOTE
Users not implementing the QorIQ platform's Trust
Architecture features should connect PROG_SFP to GND.
7Ordering information
Contact your local NXP sales office or regional marketing team for order information.
7.1 Part numbering nomenclature
This table provides the NXP QorIQ platform part numbering nomenclature.
Security fuse processor
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
180 NXP Semiconductors
Table 127. Part numbering nomenclature
pt or t n nn n x t e n c d r
Generation
Platform
Number of virtual cores
Derivative
Qual status
Temperature range
Encryption
Package type
CPU speed
DDR data rate
Die revision
PT = 28nm
(PT=Prototype)
(T=Production)
2 08 = 8
virtual
cores
0-9 P = Prototype
N = Qualified
to industrial
tier
S =
Standard
temp
X =
Extended
temp
E = SEC
present
N = SEC
not
present
7 = FC-
PBGA
C4 and
sphere
Pb-free
(lidless)
8 = FC-
PBGA
C4 and
sphere
Pb-free
(with
lid)
M = 1200
MHz
P = 1533
MHz
T = 1800
MHz
Q(L) =
1600 MT/s
T = 1866
MT/s
1 = 2133
MT/s
A = Rev
1.0
B = Rev
1.1
7.2 Orderable part numbers addressed by this document
This table provides the NXP orderable part numbers addressed by this document for the
chip.
Table 128. Orderable part numbers addressed by this document
Part number pt or t n nn n x t e n c d r
T2080NSE8MQB T =
28nm
2 08 = 8
virtual
cores
0 N =
Qualified
S = Std
temp
E = SEC
present
8 M = 1200
MHz
Q = 1600
MT/s
B =
Rev
1.1
T2080NSN8MQB T =
28nm
2 08 = 8
virtual
cores
0 N =
Qualified
S = Std
temp
N = SEC
not
present
8 M = 1200
MHz
Q = 1600
MT/s
B =
Rev
1.1
T2080NXE8MQB T =
28nm
2 08 = 8
virtual
cores
0 N =
Qualified
X = Ext
temp
E = SEC
present
8 M = 1200
MHz
Q = 1600
MT/s
B =
Rev
1.1
T2080NXN8MQB T =
28nm
2 08 = 8
virtual
cores
0 N =
Qualified
X = Ext
temp
N = SEC
not
present
8 M = 1200
MHz
Q = 1600
MT/s
B =
Rev
1.1
Table continues on the next page...
Ordering information
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
NXP Semiconductors 181
Table 128. Orderable part numbers addressed by this document (continued)
Part number pt or t n nn n x t e n c d r
T2080NSE8PTB T =
28nm
2 08 = 8
virtual
cores
0 N =
Qualified
S = Std
temp
E = SEC
present
8 P = 1533
MHz
T = 1866
MT/s
B =
Rev
1.1
T2080NSN8PTB T =
28nm
2 08 = 8
virtual
cores
0 N =
Qualified
S = Std
temp
N = SEC
not
present
8 P = 1533
MHz
T = 1866
MT/s
B =
Rev
1.1
T2080NXE8PTB T =
28nm
2 08 = 8
virtual
cores
0 N =
Qualified
X = Ext
temp
E = SEC
present
8 P = 1533
MHz
T = 1866
MT/s
B =
Rev
1.1
T2080NXN8PTB T =
28nm
2 08 = 8
virtual
cores
0 N =
Qualified
X = Ext
temp
N = SEC
not
present
8 P = 1533
MHz
T = 1866
MT/s
B =
Rev
1.1
T2080NSE8TTB T =
28nm
2 08 = 8
virtual
cores
0 N =
Qualified
S = Std
temp
E = SEC
present
8 T = 1800
MHz
T = 1866
MT/s
B =
Rev
1.1
T2080NSN8TTB T =
28nm
2 08 = 8
virtual
cores
0 N =
Qualified
S = Std
temp
N = SEC
not
present
8 T = 1800
MHz
T = 1866
MT/s
B =
Rev
1.1
T2080NXE8TTB T =
28nm
2 08 = 8
virtual
cores
0 N =
Qualified
X = Ext
temp
E = SEC
present
8 T = 1800
MHz
T = 1866
MT/s
B =
Rev
1.1
T2080NXN8TTB T =
28nm
2 08 = 8
virtual
cores
0 N =
Qualified
X = Ext
temp
N = SEC
not
present
8 T = 1800
MHz
T = 1866
MT/s
B =
Rev
1.1
T2080NSE8T1B T =
28nm
2 08 = 8
virtual
cores
0 N =
Qualified
S = Std
temp
E = SEC
present
8 T = 1800
MHz
1 = 2133
MT/s
B =
Rev
1.1
T2080NSN8T1B T =
28nm
2 08 = 8
virtual
cores
0 N =
Qualified
S = Std
temp
N = SEC
not
present
8 T = 1800
MHz
1 = 2133
MT/s
B =
Rev
1.1
T2080NXE8T1B T =
28nm
2 08 = 8
virtual
cores
0 N =
Qualified
X = Ext
temp
E = SEC
present
8 T = 1800
MHz
1 = 2133
MT/s
B =
Rev
1.1
T2080NXN8T1B T =
28nm
2 08 = 8
virtual
cores
0 N =
Qualified
X = Ext
temp
N = SEC
not
present
8 T = 1800
MHz
1 = 2133
MT/s
B =
Rev
1.1
T2080NSE8MQLB T =
28nm
2 08 = 8
virtual
cores
0 N =
Qualified
S = Std
temp
E = SEC
present
8 M = 1200
MHz
QL =
1600
MT/s
B =
Rev
1.1
T2080NSN8MQLB T =
28nm
2 08 = 8
virtual
cores
0 N =
Qualified
S = Std
temp
N = SEC
not
present
8 M = 1200
MHz
QL =
1600
MT/s
B =
Rev
1.1
T2080NXE8MQLB T =
28nm
2 08 = 8
virtual
cores
0 N =
Qualified
X = Ext
temp
E = SEC
present
8 M = 1200
MHz
QL =
1600
MT/s
B =
Rev
1.1
T2080NXN8MQLB T =
28nm
2 08 = 8
virtual
cores
0 N =
Qualified
X = Ext
temp
N = SEC
not
present
8 M = 1200
MHz
QL =
1600
MT/s
B =
Rev
1.1
Table continues on the next page...
Ordering information
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
182 NXP Semiconductors
Table 128. Orderable part numbers addressed by this document (continued)
Part number pt or t n nn n x t e n c d r
T2080NSE8P1B T =
28nm
2 08 = 8
virtual
cores
0 N =
Qualified
S = Std
temp
E = SEC
present
8 P = 1533
MHz
1 = 2133
MT/s
B =
Rev
1.1
T2080NSN8P1B T =
28nm
2 08 = 8
virtual
cores
0 N =
Qualified
S = Std
temp
N = SEC
not
present
8 P = 1533
MHz
1 = 2133
MT/s
B =
Rev
1.1
T2080NXE8P1B T =
28nm
2 08 = 8
virtual
cores
0 N =
Qualified
X = Ext
temp
E = SEC
present
8 P = 1533
MHz
1 = 2133
MT/s
B =
Rev
1.1
T2080NXN8P1B T =
28nm
2 08 = 8
virtual
cores
0 N =
Qualified
X = Ext
temp
N = SEC
not
present
8 P = 1533
MHz
1 = 2133
MT/s
B =
Rev
1.1
7.2.1 Part marking
Parts are marked as in the example shown in this figure.
T2080xtencdr
MMMMMM CCCCC
YWWLAZ
FC-PBGA
ATWLYYWW
Legend:
T2080xtencdr is the orderable part number.
ATWLYYWW is the traceability code.
MMMMMM is the mask number.
CCCCC is the country code.
YWWLAZ is the assembly traceability code.
Figure 69. Part marking for FC-PBGA chip
8Revision history
This table summarizes revisions to this document.
Revision history
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
NXP Semiconductors 183
Table 129. Revision history
Revision Date Description
3 03/2018 • Changed XVDD to SVDD in Figure 7
• Updated the row "AC Input Swing Limits at 1.8 V OVDD" in Table 13
• Updated the row "Input capacitance" in Table 15
• Removed the table "PLL lock times" from the section RESET initialization
• Added Table 48 and Figure 24
• Updated the row "Input current (OVIN = 0 V or OVIN = OVDD)" in Table 51
• Updated note 5 in Table 121
• Changed "two fuse programming cycles" to "eight fuse programming cycles" in Security fuse
processor
2 07/2016 • Updated the document title to conform with new document naming requirements.
• In the pin list table:
• Revealed alternate pin SDHC_CLK_SYNC_IN on primary pin IRQ[10].
• Revealed alternate pin SDHC_CLK_SYNC_OUT on primary pin SPI_CS_B[3].
• In Power sequencing, added a note for the frequency requirements when using Trust
Architecture Security Monitor battery-backed features and changed the stable value from 75
ms to 400 ms.
• In Table 6 and Table 7, added the 1533 MHz and 1200 MHz low-power numbers and added
footnote 9.
• In eSPI AC timing specifications, added a note for the master mode internal clock diagram
that SPICLK appears on the interface only after CS assertion.
• In RGMII AC timing specifications, added a note to footnote 9 that MAC10 is not impacted by
erratum A-005177 and meets industry specifications.
• In Orderable part numbers addressed by this document, added the following part numbers:
• T2080NSE8MQLB
• T2080NSN8MQLB
• T2080NXE8MQLB
• T2080NXN8MQLB
• T2080NSE8P1B
• T2080NSN8P1B
• T2080NXE8P1B
• T2080NXN8P1B
103/2016 • Throughout the document, removed Rev 1.0 information and the preliminary data disclaimers.
• In Table 3, added table footnote 8.
• Updated Table 4, "Output driver capability."
• In Table 6 and Table 7, added the 2133 MT/s (low-power version) numbers and re-ordered
the rows from largest to smallest MHz power number.
• In Table 8 :
• Added rows for DDR I/O 2133 MT/s and USB_SVDD.
• Updated the SerDes 1.35 V parameter to "4x 5 G-baud".
• In Table 10, updated the PH10 core frequencies.
• In Table 19, added the maximum rise/fall of PORESET_B and changed the HRESET_B max
from 1 to 10.
• In DDR3 and DDR3L SDRAM controller, added to the NOTE that DDR3L is not supported at a
DDR data rate of 2133 MT/s.
• In the tables of DDR3 and DDR3L SDRAM interface DC electrical characteristics, changed
"Dn_MVREF" to "MVREFn".
• In Table 20, updated the I/O leakage current min/max from -100/100 to -50/50.
• In Table 23 and Table 24, added the 2133 MT/s data rates and added notes that only DDR3
supports 2133 MT/s.
• In Table 32, added "10 Mbps" to note 9 as an option for RGMII if the device cannot cope with
a wide skew.
• Added Table 34, "Ethernet management interface 1 DC electrical characteristics (LVDD = 1.8
V)."
• In Table 37, removed "x2" from "(Frame Manager x2)" in table footnote 4.
Table continues on the next page...
Revision history
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
184 NXP Semiconductors
Table 129. Revision history (continued)
Revision Date Description
• In Table 39, changed the input current min and max to -50 and 50.
• In Table 71, updated the unit interval minimum from 199.40 to 199.94.
• In note 2 of Table 103 and in the final paragraph of SGMII and SGMII 2.5x receiver AC timing
specification, changed the figure reference from Figure 43 to Figure 42.
• In Table 121, updated the 1800 MHz memory bus clock frequency maximum from 933 to
1066 and, in table footnote 6, changed the XFI minimum frequency from 359 MHz to 300
MHz.
• In Table 122, changed the maximum frequency from 933 MHz to 1066 MHz.
• Removed the following sections:
• "Platform to SYSCLK PLL ratio"
• "Core cluster to SYSCLK PLL ratio"
• "Core complex PLL select"
• "DDR controller PLL ratios"
• "Frame Manager clock select"
• "eSDHC SDR mode clock select"
• In Connection recommendations, changed the example from "Analog Devices, ADT7461A" to
"Semiconductor, NCT72" and added the chip temperature diode specifications.
• In Thermal management information, updated the recommended spring force maximum from
10 pounds to 18 pounds.
• Updated Mechanical dimensions of the FC-PBGA, to include package parameters.
• In Orderable part numbers addressed by this document, added the following part numbers:
• T2080NSE8T1B
• T2080NSN8T1B
• T2080NXE8T1B
• T2080NXN8T1B
001/2015 Initial release
Revision history
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
NXP Semiconductors 185
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Document Number T2080
Revision 3, 03/2018