XEMICS Data Book XX-XE88LC01/03/05 Ultra low-power mixed-signal microcontroller 300 uA at 1 MIPS 16 + 6 bits ADC 20000327 Preliminary information XX-XE88LC01/03/05, Data Book Copyright XEMICS All rights are reserved. Reproduction whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in Switzerland Date of release 03-00 DB004-74 - Data book XX-XE88LC01-03-05 Page 2 XX-XE88LC01/03/05, Data Book Table of contents List of figures List of tables 3 9 11 1 1.1 Introduction Conventions used in this document 15 15 2 2.1 2.2 XE8000 MCU Family Features Family 17 17 17 3 3.1 3.2 3.3 3.4 Power supply In circuit power supply principle Voltage regulator Voltage multiplier Current requirement 21 21 22 23 24 4 4.1 Central processing unit Introduction 25 25 4.1.1 4.1.2 4.1.3 4.1.4 4.1.5 4.2 25 27 28 28 28 Programmer's Model 4.2.1 4.2.2 4.2.3 4.2.4 4.2.5 4.2.6 4.2.7 4.2.8 4.2.9 4.2.10 4.2.11 4.2.12 4.2.13 4.2.14 4.2.15 5 5.1 5.2 5.3 5.4 5.5 5.6 Pipeline Gated clocks Low frequency modes Stand-by Mode CoolRISC(c) Core Features 28 CoolRISC(c) 816 Architecture Instruction Set Register bank Program Memory addressing modes Data Memory addressing modes Flags Z, C & V ALU output register: a Program counter Branch conditions Call, Branch and Link Events and Interrupts Pipeline exception HALT mode Hardware Reset Low frequency modes 28 29 33 34 34 38 38 38 38 39 39 41 41 41 41 Memory Memory organisation Program memory Data memory Peripherals mapping Address pack MTP Flash memory programmation 43 43 43 43 44 44 44 Page 3 Preliminary information Table of contents XX-XE88LC01/03/05, Data Book 5.6.1 5.6.2 Preliminary information 6 6.1 System operating modes Operating modes 6.1.1 6.1.2 6.1.3 6.1.4 6.2 Start-up and Reset states Active mode Standby mode Sleep mode Resets 6.2.1 6.2.2 6.2.3 6.2.4 6.2.5 6.2.6 6.2.7 6.2.8 6.3 Initial reset from the Power-On-Circuit External Reset from the RESET pin PortA programmed Reset combination. Watch-Dog timer Reset BusError reset Reset Registers Oscillators and prescaler control Other features Interrupt 6.3.1 6.3.2 6.3.3 6.3.4 6.3.5 6.3.6 6.3.7 6.3.8 6.4 Features Overview PortA interrupts Counters A, B, C and D interrupts Prescaler interrupts Voltage Level Detector interrupt Acquisition chain interrupt Interrupt priorities Events 6.4.1 6.4.2 6.4.3 6.4.4 6.4.5 6.4.6 6.5 Features Overview PortA events Counters A, B, C and D events Prescaler events Event priorities Miscellaneous 6.5.1 6.5.2 6.6 Port configuration reset Prescaler interrupt synchronization Digital debouncer 6.6.1 6.7 7 7.1 Introduction MTP Registers Description System peripheral addresses Oscillators RC Oscillator 7.1.1 7.1.2 7.2 7.2.1 7.2.2 7.2.3 7.2.4 Page 4 RC oscillator principle RC divider cold start Xtal Oscillator General description Typical external component Xtal divider cold start Description 44 45 47 47 47 47 47 48 49 51 51 51 51 51 51 52 52 52 52 53 53 53 53 54 54 54 56 56 57 57 57 57 57 59 59 59 60 60 60 61 61 61 62 63 63 63 63 63 XX-XE88LC01/03/05, Data Book 7.4.1 7.4.2 7.5 CPU clock Oscillator register 64 65 65 Features Description Registers 65 66 67 Parallel IO ports Port A 8.1.1 8.1.2 8.1.3 8.1.4 8.2 69 69 Features Overview Port A configuration PortA registers 69 69 69 71 Port B 8.2.1 8.2.2 8.2.3 8.2.4 8.3 72 Features Overview Port B digital capabilities Port B analog capability 72 72 72 74 Port C 8.3.1 8.3.2 8.3.3 9 9.1 9.2 9.3 9.4 9.5 9.6 64 64 Prescaler 7.5.1 7.5.2 7.5.3 8 8.1 External clock Oscillators control 75 Features Overview Port D 75 75 77 Universal Asynchronous Receiver/Transmitter (UART) Features Overview Uart Prescaler Function description Interrupt or polling Software hints 79 79 79 79 79 80 80 10 Universal Synchronous Receiver/Transmitter (USRT) 10.1 Overview 10.1.1 10.1.2 10.2 85 85 Enabling the serial interface Reading the serial interface 85 85 Registers 85 11 Counters/timers 11.1 Introduction 11.2 Watchdog 11.3 Counters 11.3.1 11.3.2 11.3.3 11.3.4 11.3.5 11.3.6 87 87 87 87 Overview Features Block schematics Counter Registers Clock selection 16 bit counters 87 88 88 88 89 90 Page 5 Preliminary information 7.3 7.4 XX-XE88LC01/03/05, Data Book Preliminary information 11.3.7 11.3.8 11.3.9 11.3.10 Up/down counting Capture functions PWM functions Counter registers 91 92 94 96 12 Voltage Level Detector 12.1 Features 12.2 Overview 12.3 VLD operation 12.4 Registers 99 99 99 99 100 13 101 Power-on reset 14 Acquisition chain 14.1 Introduction 14.2 Block diagram 14.3 Input signal multiplexing 14.4 Input reference multiplexing 14.5 Amplifier chain 14.5.1 14.5.2 14.5.3 14.6 14.6.1 14.6.2 14.6.3 14.6.4 14.6.5 14.6.6 14.7 14.7.1 14.7.2 14.7.3 14.7.4 14.8 PGA 1 PGA2 PGA3 ADC Input-Output relation Operation mode Conversion sequence Conversion duration Resolution ADC performances Control part Starting a convertion Clocks generation Default operation mode (not yet implemented) Registers Acquisition of a sample 15 Analog outputs 15.1 Signal DAC 15.1.1 15.1.2 15.1.3 15.1.4 15.1.5 15.1.6 15.2 15.2.1 15.2.2 15.2.3 15.2.4 Page 6 Application Typical external components Block diagram The generic DAC The amplifier Signal DAC registers Bias DAC Application Typical external components Block diagram The DAC 103 103 103 103 104 104 105 105 106 106 106 106 107 107 107 107 108 108 108 108 108 110 111 111 111 111 111 112 112 113 115 115 115 115 115 XX-XE88LC01/03/05, Data Book The amplifier Bias DAC registers 115 116 16 Pin-out, package and electrical specifications 16.1 XE88LC01 pin-out 16.2 XE88LC03 pin-out 117 117 119 16.2 16.3 16.4 121 121 123 XE88LC05 pin-out Electrical specifications 16.4.1 16.4.2 16.4.3 Absolute maximum ratings Operating conditions IO pins operation 123 123 123 17 Index 125 18 Contact 127 Page 7 Preliminary information 15.2.5 15.2.6 Preliminary information XX-XE88LC01/03/05, Data Book Page 8 XX-XE88LC01/03/05, Data Book Figure 2.1: XE88LC03 block schematics Figure 2.2: XE88LC05 block schematics. Figure 3.1: Power supply strategy. Figure 3.2: Selection of the operation mode with respect to the power supply range. Figure 3.3: b) Power supply connection for wide voltage operation. Figure 3.3: a) Power supply connection for low voltage operation. Figure 3.4: Power supply connection for middle voltage operation. Figure 3.5: Power supply connection for high voltage operation. Figure 4.1: CoolRISC 816 core Figure 4.2: CoolRISC Pipeline Figure 4.3: Pipeline execution of different instructions Figure 4.4: Direct addressing Figure 4.5: Indexed addressing Figure 4.6: Indexed addressing with an immediate offset Figure 4.7: Indexed addressing with a register offset Figure 4.8: Indexed addressing with post-modification of the Index Figure 4.9: Indexed addressing with pre-modification of the index Figure 5.1: Memory organization Figure 5.2: MTP registers organisation Figure 6.1: System block Figure 6.2: sleep mode structure Figure 6.3: System operating modes. Most peripherals also have several low power modes Figure 6.4: power-on reset start Figure 6.5: wake from sleep (short reset) Figure 6.6: wake from sleep (long reset) Figure 6.7: reset in active mode Figure 6.8: Port configuration reset Figure 6.9: Prescaler interrupt synchronization Figure 7.1: RC programming principle Figure 7.2: RC frequencies programming example for low range (typical values) Figure 7.3: CPU clock selection Figure 7.4: prescaler principle Figure 8.1: Port A Figure 8.2: digital debouncer Figure 8.3: Port B Figure 8.4: Port C Figure 9.1: example of UART messages Figure 11.1: Counters/timers block schematics Figure 11.2: start synchronization Figure 11.3: interrupt generation Figure 11.4: counter examples Figure 11.5: Capture Architecture (counter A) Figure 11.6: Edge detector (1) principle Figure 11.7: Edge detector (2) principle Figure 11.8: PWM output examples Page 9 18 18 21 21 22 22 22 22 25 26 27 35 35 36 36 37 37 43 45 47 48 49 50 50 50 51 59 59 61 61 65 66 69 70 72 76 81 88 90 90 92 92 93 94 95 Preliminary information List of figures Preliminary information XX-XE88LC01/03/05, Data Book Figure 12.1: VLD timing Figure 13.1: reset conditions Figure 14.1: Acquisition channel block diagram with ZoomingADCTM Figure 14.2: PGA stage principle implementation Figure 14.3: Conversion sequence. smax is the oversampling rate. Figure 14.4: Acquisition flow Figure 15.1: General block diagram Figure 15.2: The DAC signal structure Figure 15.3: General block diagram of the bias DAC 16.1 Pinout of the XE88LC01 in TQFP44 package 16.2 Pinout of the XX-XE88LC03 in SOP28 package 16.2 Pinout of the XX-XE88LC03 in TQFP32 package Figure 16.1: Pinout of the XE88LC05 in TQFP64 package Page 10 99 101 103 105 107 110 111 112 115 117 119 119 121 XX-XE88LC01/03/05, Data Book Table 1.1: access code convention Table 2.1: List of the XE8000 family members functions Table 3.1: Voltage Regulator specifications for ROM Table 3.2: Voltage Regulator specifications for MTP Table 3.3: RegVmultCfg0 Table 3.4: Vmult specifications Table 3.5: Current requirement of the XE8000 family members Table 4.1: CoolRISC core main characteristics Table 4.2: CoolRISC 816 Instruction Set Table 4.3: CoolRISC 816 addressing modes Table 4.4: CoolRISC 816 conditional jump (Jcc) conditions Table 4.5: CoolRISC 816 instruction construction Table 4.6: CoolRISC 816 internal registers Table 4.7: CoolRISC 816 registers organization Table 4.8: CoolRISC 816 interrupts Table 4.9: Registers Roles Table 4.10: Branch Conditions Table 4.11: CALL addresses and priorities Table 5.1: Program addresses Table 5.2: RAM addresses Table 5.3: Peripherals addresses Table 5.4: MTP Registers Table 6.1: System registers Table 6.2: EnResPConf Table 6.3: RegSysReset Table 6.4: RegSysCtrl Table 6.5: Debouncer frequency Table 6.6: RegSysMisc Table 6.7: all interrupts and their priorities Table 6.8: Interrupt registers Table 6.9: RegIrqHig Table 6.10: RegIrqMid Table 6.11: RegIrqLow Table 6.12: RegIrqEnHig Table 6.13: RegIrqEnMid Table 6.14: RegIrqEnLow Table 6.15: RegIrqPriority Table 6.16: RegIrqIrq Table 6.17: RegIrqTest Table 6.18: all events and their priorities Table 6.19: Event registers Table 6.20: RegEvn Table 6.21: RegEvnEn Table 6.22: RegEvnPriority Table 6.23: RegEvnEvn 15 18 23 23 23 23 24 28 30 32 32 32 33 33 33 34 39 40 43 44 44 45 49 51 52 52 52 52 54 54 55 55 55 55 56 56 56 56 56 58 58 58 58 58 59 Page 11 Preliminary information List of tables Preliminary information XX-XE88LC01/03/05, Data Book Table 6.24: RegEvnTest 59 Table 6.25: Port config reset 59 Table 6.26: Debouncer frequency 60 Table 6.27: system address ranges 60 Table 7.1: RC specifications 62 Table 7.2: RegSysRCTrim1 62 Table 7.3: RegSysRCTrim2 62 Table 7.4: Xtal oscillator specifications. 63 Table 7.5: External crystal specifications. 32 kHz Xtal outside these specifications will must probably delivers correct frequency, but some precision specifications will be released. 63 Table 7.6: Board design specifications 63 Table 7.7: CPU clock selection 64 Table 7.8: RegSysClock, address h0012 65 Table 7.9: frequency examples, typical values for RC setting, range is set to 1 66 Table 7.10: automatic input frequency selection, typical values. Values in italic are not allowed and may result in unpredictable CPU behaviour. 67 Table 7.11: RegSysPre0 67 Table 8.1: reset selection for each pin 70 Table 8.2: clock inputs for counters 70 Table 8.3: Port A registers 71 Table 8.4: Register RegPAIn 71 Table 8.5: Register RegPADebounce 71 Table 8.6: Register RegPAEdge 71 Table 8.7: Register RegPAPullup 71 Table 8.8: RegPARes0 71 Table 8.9: RegPARes1 71 Table 8.10: RegPATest 71 Table 8.11: different PortB functions 73 Table 8.12: selection for analog lines with RegPBDir (pads B0, B2, B4 and B6) or RegPBout (pads B1, B3, B5 and B7) 74 Table 8.13: Port B registers 74 Table 8.14: RegPBIn 74 Table 8.15: RegPBOpen 74 Table 8.16: RegPBAna 75 Table 8.17: RegPBPullup 75 Table 8.18: RegPBOut 75 Table 8.19: RegPBDir 75 Table 8.20: Port C registers 76 Table 8.21: RegPCOut 76 Table 8.22: RegPCIn 76 Table 8.23: RegPCDir 77 Table 9.1: RC frequencies for Uart 79 Table 9.2: uart internal prescaler 79 Table 9.3: baud rate selection 81 Table 9.4: word length 81 Page 12 Table 9.5: parity mode Table 9.6: parity enable Table 9.7: UART registers Table 9.8: echo modes Table 9.9: RegUartCmd Table 9.10: RegUartCtrl Table 9.11: RegUartRx Table 9.12: RegUartRxSta Table 9.13: RegUartTx Table 9.14: RegUartTxSta Table 10.1: serial interface registers Table 10.2: RegUSRTSIN Table 10.3: RegUSRTSCL Table 10.4: RegUSRTCtrl Table 10.5: RegUSRTData Table 10.6: RegUSRTEdgeSCL Table 11.1: RegSysWD Table 11.2: clock source for Counter A Table 11.3: clock source for Counter B Table 11.4: clock source for Counter C Table 11.5: clock source for Counter D Table 11.6: cascading counter A & B Table 11.7: cascading counter C & D Table 11.8: selection for up/down-counting Table 11.9: capture source Table 11.10: capture function selection Table 11.11: PWM1 Table 11.12: PWM0 Table 11.13: PWM1 size selection Table 11.14: PWM0 size selection Table 11.15: Counters registers Table 11.16: RegCntA Table 11.17: RegCntB Table 11.18: RegCntC Table 11.19: RegCntD Table 11.20: RegCntCtrlCk Table 11.21: RegCntConfig1 Table 11.22: RegCntConfig2 Table 11.23: RegCntOn Table 12.1: Voltage level detector operation Table 12.2: RegVldCtrl Table 12.3: RegVldStat Table 13.1: POR specifications Table 14.1: AMUX selection Table 14.2: PGA1 Performances 81 81 82 82 82 82 82 82 82 83 85 85 86 86 86 86 87 89 89 89 89 90 91 91 94 94 95 95 95 95 96 96 96 96 96 96 96 96 97 99 100 100 101 104 105 Page 13 Preliminary information XX-XE88LC01/03/05, Data Book Preliminary information XX-XE88LC01/03/05, Data Book Table 14.3: PGA2 Performances Table 14.4: PGA3 Performances Table 14.5: ADC Performances Table 14.6: Peripheral register memory map Table 14.7: Peripheral register memory map, bits description Table 15.1: DAC signal amplifier performances Table 15.2: Signal DAC registers Table 15.3: RegDasCfg0 Table 15.4: RegDasCfg1 Table 15.5: Noise shaping setting Table 15.6: PWM setting Table 15.7: DAC status Table 15.8: Clock setting Table 15.9: PWM polarity Table 15.10: DAC performances Table 15.11: Amplifier performances Table 15.12: Bias DAC registers Table 15.13: RegDab1Cfg 16.1 Pin-out of the XX-XE88LC01 in TQFP44 16.2 Pin-out of the XX-XE88LC03 in SO28 and TQFP32 Table 16.1: Pin-out of the XE88LC05 in TQFP64 Table 16.2: Absolute maximum ratings Table 16.3: Operating conditions Table 16.4: IO pins performances Page 14 105 106 107 108 109 112 113 113 113 113 113 113 114 114 115 115 116 116 117 119 121 123 123 123 XX-XE88LC01/03/05, Data Book 1 1 Introduction Introduction The XE8000 is conceived as an evolutionary family of MCU that can address many applications. As there are always applications that can not be covered by such a product line, XEMICS also offers full custom ASICs based on the XE8000, including additional peripherals on request. The intellectual property that the XE8000 relies on, as well as the low power digital libraries, are available from XEMICS. This document describes the functional components of the XE8000 family and their performance. Additional information relative to specific applications is available as "Application Notes". 1.1 Conventions used in this document The negative power supply is named VSS. VSS is internally connected to the substrate of the chip. Unless otherwise stated, all voltages are given with respect to VSS. Current is positive when flowing into a pin. This pin is said to be "sinking" current. When the current is going out of the chip, its value is negative and the pin is said "sourcing" current. All digital words are written from MSB to LSB (MSB left, LSB right). These words are expressed with all their digits either in binary, decimal or hexadecimal format. When expressed in binary, the word has a "b" at its beginning, when expressed in decimal, the word has nothing or a "d" at its beginning, when expressed in hexadecimal, the word has an "h" at its beginning. Unless otherwise stated, all digital signals are active high. RegSystem this is a register EnableRC this is a bit in a register An unreadable bit will output 0 when read. code bit (register) read-write access r w c1 c readable write able readable, cleared by writing 1 readable, cleared by writing any value Table 1.1: access code convention Sometimes the abbreviation for "micro-" is "u" instead of "". Page 15 Preliminary information The XE8000 is a family of microcontrollers (MCU) characterised by their very low power requirement. These MCUs are perfectly adapted to manage systems working on batteries or remotely powered. Preliminary information 1 Introduction Page 16 XX-XE88LC01/03/05, Data Book XX-XE88LC01/03/05, Data Book 2.1 XE8000 MCU Family Features The main characteristics of the XE8000 MCU family are * Ultra low power operation * Low voltage operation (1.2 V or 2.4 V to 5.5 V) * High efficiency CPU * 1 instruction per clock cycle, for all instructions * 22 bits wide instructions * Integrated 8x8 -> 16 bits multiplier * 8 bit data bus * 64k instruction program addressing space * 64kB data addressing space * 8 addressing modes * MTP (multiple time programmable) memory available * Dual clock (X-tal and/or RC) * Each peripheral can be set on/off individually for minimal power consumption * UART and synchronous serial interface * Watch dog * Four 8 bit timers with PWM ability * Advanced acquisition path * Fully differential analog signal path for signal and reference * 4x2 or 7x1 + 1 signal input * 2x2 reference input * 0.5 - 1000 programmable gain amplifier * Offset programmed over +- 10 full scale * 5 - 16 bits resolution ADC * Low speed modes with reduced bias current for minimal power consumption * Bias and signal DACs for resistive bridge sensing and analog output * Complete development tools using Windows 95 or NT graphical interface * Assembler * ANSI-C compiler * Source level debugger * CPU Simulator * CPU Emulator XE8000HaCE * Starter kits (in preparation) * Programmer (ProStart, includes an eval board) * Hardware emulators (works with XE8000HaCE, in preparation) 2.2 Family The XE8000 Family ultra low-power microcontroller is made up of several members, all using the same microprocessor core and differing by the peripherals available. The XE88LC01 is a low-power sensing microcontroller, based on the XE88LC01, with an advanced acquisition path including diferential programmable gain amplifiers and a high resolution analog to digital converter. Its main applications are dataloggers and process control. The XE88LC02 is a low-power sensing microcontroller, based on the XE88LC01, with an additionnal LCD driver. Its main applications are metering and dataloggers. The XE88LC03 is a low-power, low-voltage, general purpose microcontroller. Its main features are the very efficient CoolRISC core, the low voltage function and the real time clock. Its main applications are low voltage control and supervision. XE88LC03 will be superseeded by the XE88LC06 later this year. Page 17 Preliminary information 2 2 XE8000 MCU Family 2 XE8000 MCU Family XX-XE88LC01/03/05, Data Book The XE88LC04 is a low-power, low-voltage, general purpose microcontroller, based on the XE88LC03, with an additionnal LCD driver. Its main features are the very efficient CoolRISC core, the low voltage function and the real time clock. Its main applications are low voltage control and supervision. Preliminary information The XE88LC05 is a low power sensing microcontroller, based on the XE88LC01, with analog outputs. Its main applications are piezoresistive sensors and 4 - 20 mA loops systems. Watchdog RC oscillator Xtal oscillator Power-on reset Volt. level detection Voltage regulator Port A Port B Port C UART USRT Counters 16 System 8 16 data RAM CPU CoolRISC instructions 22 XE8301 ROM / MTP Figure 2.1: XE88LC03 block schematics Watchdog RC oscillator Xtal oscillator Power-on reset Volt. level detection 2 voltage regulators PGA ADC Port A Port B Port C UART USRT Counters DACs 16 System 8 data RAM 16 CPU CoolRISC instructions 22 XE8301 ROM / MTP blocks specific to the XE88LC05 Figure 2.2: XE88LC05 block schematics. Other microcontrollers derived from the XE8000 family members can be produced on request, either as new standard products or as customer specific circuits. XE88LC01 XE88LC02 XE88LC03 Supply voltage 2.7 - 5.5 V 2.4 - 5.5 V 2.7 - 5.5 V Max speed Operating temperature 2 MIPS -40 - 85 C -40 - 125 C CoolRISC 816, 22 bits instructions 8 bits data HW multiplier 4 MIPS -40 - 85 C -40 - 125 C CoolRISC 816, 22 bits instructions 8 bits data HW multiplier 2 MIPS CPU XE88LC04 1.2- 5.5 V for ROM 2.4 - 5.5 V for MTP 4 MIPS at 2.4 V -40 - 85 C -40 - 85 C CoolRISC 816, 22 bits instructions 8 bits data HW multiplier CoolRISC 816, 22 bits instructions 8 bits data HW multiplier Table 2.1: List of the XE8000 family members functions Page 18 XE88LC05 2.7 - 5.5 V 2 MIPS -40 - 85 C -40 - 125 C CoolRISC 816, 22 bits instructions 8 bits data HW multiplier XE88LC06 XE88LC07 1.2- 5.5 V for ROM 2.4 - 5.5 V for MTP 4 MIPS at 2.4 V -40 - 85 C -40 - 125 C CoolRISC 816, 22 bits instructions 8 bits data HW multiplier 1.2- 5.5 V for ROM 2.4 - 5.5 V for MTP 4 MIPS at 2.4 V -40 - 85 C -40 - 125 C CoolRISC 816, 22 bits instructions 8 bits data HW multiplier XE88LC01 XE88LC02 2 XE8000 MCU Family XE88LC03 XE88LC04 XE88LC05 8k Instruction 8k Instructions 8k Instructions 8k Instructions 8k Instructions = 22 kB MTP or = 22 kB MTP or Program memory = 22 kB = 22 kB = 22 kB MTP 6k Intructions 6k Intructions MTP MTP = 16 kB ROM = 16 kB ROM Data memory 512 Bytes 512 Bytes 512 Bytes 512 Bytes 512 Bytes 8 input and 8 input and 8 input and 8 input and 8 input and Port A external interrupt external interrupt external interrupt external interrupt external interrupt 8 input/output and 8 input/output and 8 input/output and 8 input/output and 8 input/output and Port B analog analog analog analog analog Port C 8 input/output 8 input/output 4 to 8 input/output 4 to 8 input/output 8 input/output Watchdog timer yes yes yes yes yes General purpose 4 x 8 bits 4 x 8 bits 4 x 8 bits 4 x 8 bits 4 x 8 bits timers with PWM UART yes yes yes yes yes transition transition transition transition transition 2-3 wires serial detection detection detection detection detection interface + software + software + software + software + software Voltage level yes yes yes yes yes detector 32 kHz quartz, 32 kHz quartz, 32 kHz quartz, 32 kHz quartz, 32 kHz quartz, Oscillators internal RC internal RC internal RC internal RC internal RC LCD drivers yes yes Port B and Port B and Port B and Port B Port B Analog mux 4x2 or 7x1+1 4x2 or 7x1+1 4x2 or 7x1+1 LP comparators 4 4 PGA gain 0.5 - 1000 gain 0.5 - 1000 gain 0.5 - 1000 5 - 16 bits 5 - 16 bits 5 - 16 bits ADC resolution resolution resolution PWM in timers 8 bit bias DAC, DAC PWM PWM PWM PWM 4 - 16 bits signal DAC SO28, TQFP32, TQFP64, die Package TQFP44, die die Q2/00 LC06 is a better Availability Q2/00 samples Q1/01 samples Q1/01 yes choice for new designs XE88LC06 XE88LC07 8k Instructions 2k Instructions = 22 kB MTP or = 5.5 kB 6k Intructions ROM or MTP = 16 kB ROM 512 Bytes 128 Bytes 8 input and 0-4 input and external interrupt external interrupt 8 input/output and 8 input/output and analog analog 8 input/output yes yes 4 x 8 bits 4 x 8 bits yes transition detection + software yes transition detection + software yes yes 32 kHz quartz, internal RC 32 kHz quartz, internal RC Port B Port B 4 4 PWM PWM SO28, TQFP32, SO16, SO20, die die samples Q3/00 Table 2.1: List of the XE8000 family members functions Page 19 Preliminary information XX-XE88LC01/03/05, Data Book Preliminary information 2 XE8000 MCU Family Page 20 XX-XE88LC01/03/05, Data Book XX-XE88LC01/03/05, Data Book 3 3 Power supply Power supply 3.1 In circuit power supply principle VDD= Vbat VREG Vmult VREG IO pad Level shifters VMULT continuous analog digital, POR, oscillators switched analog Vreg optional capacitor Vmult optional capacitor VSS substrate Digital, services on some models only Figure 3.1: Power supply strategy. VDD (V) 5.5 Wide voltage operation 3.3 Middle voltage operation High voltage operation 2.4 1.4 Low voltage operation 1.2 VSS Figure 3.2: Selection of the operation mode with respect to the power supply range. Voltage for the digital and for regular service blocks when operating in wide, middle and high voltage mode is regulated below power supply to have a minimal current requirement. An additional high-voltage is generated when operating in middle voltage for controlling the internal analog switches. Page 21 Preliminary information The power supply uses two regulators (Figure 3.1), Vreg should be connected to VDD for low voltage operation, Vmult should be connected to VDD for high voltage operation. There are several operation modes depending on the voltage range of the power supply (Figure 3.2). MTP and mixed signal blocks are limited to Middle and High voltage ranges. 3 Power supply 3.2 XX-XE88LC01/03/05, Data Book Voltage regulator All digital parts are powered through the voltage regulator. An external capacitor is needed for the regulated voltage. It should be bypassed to VDD if working in low voltage mode. The Vreg output value depends on the program memory implementation. Preliminary information VDD VDD VREG VREG VREG VREG digital, POR, oscillators Level shifters digital, POR, oscillators Level shifters Vreg capacitor VSS VSS substrate Digital, services substrate Figure 3.3: a) Power supply connection for low voltage operation. Digital, services Figure 3.3: b) Power supply connection for wide voltage operation. VDD VREG Vmult VREG VMULT digital, POR, oscillators Level shifters Vreg capacitor continuous analog switched analog Vmult capacitor VSS substrate Digital, services Figure 3.4: Power supply connection for middle voltage operation. VDD Vmult VREG VREG Level shifters VMULT continuous analog digital, POR, oscillators switched analog Vreg capacitor VSS substrate Digital, services Analog for some chips Figure 3.5: Power supply connection for high voltage operation. Page 22 XX-XE88LC01/03/05, Data Book 3 Power supply symbol description min VREG regulated voltage 1.4 tSTART start-up time Creg external load capacitor 80 typ 100 max unit 1.9 V 0.5 ms 120 nF max unit comments Table 3.1: Voltage Regulator specifications for ROM description VREG regulated voltage min typ 2 V tSTART start-up time tbd ms CL external load capacitor tbd nF comments Table 3.2: Voltage Regulator specifications for MTP 3.3 Voltage multiplier The Vmult block generates a voltage that is higher or equal to the supply voltage. The output voltage is intended for use in analog switch drivers, for example in the ADC and PGA block. The voltage multiplier should be on when using switched analog blocks, like ADC, DAC or analog properties of the Port B under middle voltage conditions. The clock source of Vmult is selected from the 2-bit register Vmult_fin. The normal usage is with the clock frequency of the acquisition chain. Other settings are reserved. An example of setting the regulator is as follows: MOVE RegVmultCfg0, #0b00000100; sets Vmult enable bit An example of setting the regulator off follows: MOVE bit RegVmultCfg0, #0b00000000; resets Vmult enable bit name 7-3 reset rw 00000 rw 2 enable 0 rw 1-0 fin[1:0] 00 rw description reserved 0: multiplier is stopped 1: multiplier is active Clock source for Vmult: 00 : identical to acquisition chain clock (see corresponding chapter) 01 : reserved 10 : reserved 11 : reserved Table 3.3: RegVmultCfg0 symbol description Tsu start-up time Cext external capacitor min 1.1 typ 1.8 max unit comments 1 ms defined as the time to reach the minimum output voltage Vout 2.5 nF Table 3.4: Vmult specifications Page 23 Preliminary information symbol 3 Power supply 3.4 Current requirement Operation conditions Preliminary information XX-XE88LC01/03/05, Data Book CPU running at 1 MIPS CPU running at 32 kHz on Xtal, RC off CPU halt, timer on Xtal, RC off CPU halt, timer on Xtal, RC ready CPU halt, Xtal off timer on RC at 100 kHz CPU halt, ADC 12 bits at 4 kHz, PGA off CPU halt, ADC 12 bits at 4 kHz, PGA gain 100 CPU halt, LCD on, timer on Xtal CPU at 1 MIPS, ADC 12 bits, signal DAC 10 bits at 4 kHz, PGA off CPU at 1 MIPS, ADC 12 bits, signal DAC 10 bits at 4 kHz, PGA gain 10 CPU at 1 MIPS, ADC 12 bits, signal DAC 10 bits at 4 kHz, PGA gain 100 CPU at 1 MIPS, ADC 12 bits, signal DAC 10 bits at 4 kHz, PGA gain 1000 Voltage level detection XE88LC01R XE88LC01M XE88LC03R XE88LC03M XE88LC05R XE88LC05M Remarks 310 uA 310 uA 310 uA 1 10 uA 10 uA 10 uA 1 1 uA 1 uA 1 uA 1 1.7 uA 1.7 uA 1.7 uA 1 1.4 uA 1.4 uA 1.4 uA 1 200 uA 200 uA 1,4 480 uA 480 uA 1,4 1 10 uA 10 uA 725 uA 3,4,5 870 uA 3,4,5 1 mA 3,4,5 1.2 mA 3,4,5 10 uA 2 Table 3.5: Current requirement of the XE8000 family members Note: Note: Note: Note: Note: 1) Over 2.4 - 5.5 V, at 27 C, max values. 2) Additional current, duration of the request is shorter than 2 ms. 3) Output not loaded. 4) Current requirement can be divided by a factor of 2 or 4 by reducing the speed accordingly. 5) At 2.4 V, at 27 C, max values. Page 24 XX-XE88LC01/03/05, Data Book 4 4.1 4 Central processing unit Central processing unit Introduction +1 nPM Sel P C < 16 > P C 2..9 P C 1 P C 0 M U X 16 PM Inst <22> C A L L to In te rru p t A d d re s s ip < 1 6 > P ro g ra m M e m o ry m ax 6 4 K in stru ctio n s PM A ddr <16> 16 MUX IR < 2 2 > B ra n c h A d d re ss < 1 6 > O p -co d e C o n tro l U n it D ata <8> B Bus <8> DataO ut <8> A Bus <8> RegB DataIn <8> RegA D M A ddr <16> A L U <8 > M U L T 8 *8 R e g is te r ReadnW rite Bank DM S el 8 LSB C, V, Z 8 M SB D a ta M e m o ry and P e rip h m ax 6 4 K b yte s a S B us <8> C o o lR IS C TM C ore 81 6 Figure 4.1: CoolRISC 816 core 4.1.1 Pipeline The CoolRISC architecture is based on a 3-stage pipeline. One instruction enters the pipeline at each clock cycle and executes in a maximum of 3 cycles. The CoolRISC pipeline suffers no penalty such as delay slots or branch delays present in most RISC processors. Thus the clock count per instruction (CPI) is exactly one. As a result the number of cycles needed to execute a task is easily determined, since it matches the number of executed instructions. Figure 4.2 shows the timing diagram for the pipeline. Arithmetic instructions go through all three stages of the pipeline, thus executes in 3 clock cycles. A bypass mechanism is used to avoid any load delay[10]. Page 25 Preliminary information The XE8000 family is built around the CoolRISC 816 processor core. This is a Harvard type RISC processor (Program address is separated from data address). It is extremely efficient using large instruction words (22 bits), one clock per cycle instruction set (inclusive multiplication) and efficient pipeline. 4 Central processing unit XX-XE88LC01/03/05, Data Book It should be mentioned that existing 4-bit and 8-bit microprocessors typically need between 4 to 20 clocks per instruction (CPI), some newer CPU use 1 clock cycle for simple operations (MOVE) but 2 to 6 cycles for more complex operations (ADD, JPC). The efficiency of the CoolRISC architecture is far better than these microprocessors. Preliminary information 3-stag e P ipelin e N o load/b ranch delays 1 cloc k cyc le 1 cloc k c yc le fe tc h & b ra n c h fe tc h e x e c u te w rite reg is te r b ra n c h in s tru c tio n s a rith m e tic in s tru c tio n s E x ac tly 1 cloc k cy cle per in stru ctio n(C PI=1 ). It is n ot a p ea k va lu e . Figure 4.2: CoolRISC Pipeline Figure 4.2 presents the timing diagram for the execution of different types of instructions. The first instruction on Figure 4.3 is a typical ALU operation with a first operand in Data Memory (DM) and a second operand in a register. The result is stored in the destination register. During the first clock cycle, the Program Memory (PM) is pre-charged in the first phase and the instruction is read and is decoded in the second phase. During the second clock cycle, the register and the DM are read in phase 3 and the ALU operation is executed in phase 4. The last clock cycle contains only a single phase (phase 5) used to store the result in the destination register. The second instruction shown is a Data Memory store instruction. The first clock cycle is identical for all instructions. The second clock cycle contains only phase 3 in which the value of a register is written into the DM. Page 26 XX-XE88LC01/03/05, Data Book phase 1 phase 2 phase 3 phase 4 clock 1 clock 2 PM Prech. PM Read phase 5 clock 3 PM Prech. PM Read PM Prech. Reg/DM Read ALU DM Write PM Read Register Write Data Memory-Reg ALU instruction Data Memory Store instruction Branch instruction Figure 4.3: Pipeline execution of different instructions The last instruction shown is a branch instruction. A single clock cycle is necessary for all branch instructions (conditional or unconditional jump, call, return). During phase 2, the next Program Memory address can be determined while considering an already computed test condition (computed during phase 4 of the previous instruction, which is phase 2 of the considered branch instruction). The new address is loaded into the PC at the high-to-low transition of the clock between phase 2 and 3. Branch instructions executed in one clock do not result in branch delays that generally degrade the pipeline performance [10]. Thus, CPI=1 is not a peak value, but rather a characteristic of the CoolRISC(c) architecture. Figure 4.3 shows a Data Memory-reg ALU instruction followed by a DM store instruction. The first instruction stores its result in a register during phase 5 which is phase 3 of the DM store instruction. A bypass mechanism allows the DM store instruction to read the register that is written by the preceding ALU instruction. Such a mechanism does not require load delays. As the CoolRISC pipeline is not affected by branch or load delays [11], the pipeline hardware is simplified (no branch prediction needs to be performed [10]). This makes the CoolRISC(c) pipeline very efficient and low in power. 4.1.2 Gated clocks The gated clock technique has been extensively used in the CoolRISC(c) design. It uses the ALU with input and control registers that are loaded only when an ALU operation has to be executed. During the execution of another type of instruction (branch, store, etc...), these registers are not clocked, thus no transitions occur in the ALU. This reduces power consumption. A similar mechanism is used for the instruction registers, thus in a branch, which is executed only in the first pipeline stage, no transitions occur in the second and third stages of the pipeline. Gated clocks can be advantageously combined with the pipeline architecture. When input and control registers have to be implemented to obtain a gated clock ALU, they are naturally used as pipeline registers. Page 27 Preliminary information Ck 4 Central processing unit 4 Central processing unit 4.1.3 XX-XE88LC01/03/05, Data Book Low frequency modes The processor internal frequency can be reduced by a factor of 2, 4, 8 or 16. The division factor is both hardware and software controlled. Preliminary information The FREQ instruction sets the basic division factor which is output on the processor FreqOut[3:0] bus. This value can be combined with other signals in an external hardware decoder to compute the final division factor which is then input on the FreqIn[3:0] bus. Power consumption can be further decreased by putting the processor in the low-power standby mode with the HALT instruction. It will restart when an Event or an Interrupt occurs. 4.1.4 Stand-by Mode The HALT instruction puts the processor in standby mode in which power consumption is minimum. The clock is stopped at the entrance of the processor to prevent any transition in the core. 4.1.5 CoolRISC(c) Core Features CoolRISC(c) Core CoolRISC816 as implemented in XE88LC01-03-05 Maximal CoolRISC816 capabilities CPI (clock per instruction) Pipeline Branch/Load delay Data Width No. of Registers Max. Program Memory size Max. Data Memory size Instruction size No. of Program Memory Index Registers No. of Data Memory Index Registers No. of Program Memory pages No. of Data Memory pages No. of Data Memory addressing modes Software CALL (branch & link) No. of nested hardware CALL No. of Interrupt Levels Nested Interrupts No. of EVENT levels Test access Halt mode 8 by 8 to 16 multiplication in one instruction Barrel Shifter Two-Complement capabilities 1 3 stages no 8 8 8k * 22 (= 22 kBytes) 512 * 8 22 1 4 1 * 8k 2 * 256 8 yes 4 3 yes 2 serial yes yes yes yes 1 3 stages no 8 16 64k * 22 (= 360 kBytes) 64k * 8 22 1 4 1 * 64k 256 * 256 8 yes 8 3 yes 2 serial yes yes yes yes Table 4.1: CoolRISC core main characteristics 4.2 Programmer's Model 4.2.1 CoolRISC(c) 816 Architecture Figure 4.1 shows the CoolRISC(c) Core 816 architecture which is a 8-bit microprocessor core available with 16 registers and 22-bit wide instructions. Page 28 XX-XE88LC01/03/05, Data Book 4.2.2 4 Central processing unit Instruction Set Table 4.2 presents the instruction set of the CoolRISC(c) 816. Unlike most RISC microprocessors, the CoolRISC(c) core provides instructions that can operate with operands stored either in registers or in the Data Memory. All arithmetic and logic instructions can be executed with a first operand in a register and a second operand either in the Data Memory or in a second register. The result can be stored either in a third register or in the first one. Furthermore, unlike RISC microprocessors and similarly to classic 8-bit microprocessors, the CoolRISC(c) architecture provides an accumulator (a) located at the ALU output. This accumulator stores the last ALU result and should be used as an intermediate result for the next ALU operation. This accumulator is mapped in the register bank. Similarly, both the Branch & Link instruction of RISC microprocessors (Software Call) and the classic hardware Call are provided by the CoolRISC(c) architecture. CoolRISC(c) architecture can be used from the programming point of view, either as a true RISC architecture or as a more classic 8-bit architecture. The CoolRISC(c) 816, with its overflow flag (V) and its arithmetic instructions (SHRA, CMPA, MULA, MSHRA) fully supports signed numbers in the two-complement representation. The MUL & MULA instructions execute a 8 by 8 multiplication. Because the result is on 16 bits, the 8 MSB bits are stored in the destination register and the 8 LSB bits are stored in the accumulator a. All the flags (C, Z, V) must be considered as unknown after these instructions. The multiple shift instructions MSHL, MSHR & MSHRA use the multiplication instructions with an immediate operand. For this reason, the value of a is different from the destination register, as in the MUL & MULA instructions. This implies that the shifted "out" bits are never lost (they are either in a or in the destination register), and these instructions can be used to split a byte into two bytes, with a single instruction. For example, a "SWAP r0" can be implemented as follows: MSHL ADD ; r0 = 0xYZ ; r0 <- 0Y, a <- Z0 ; r0 <- ZY r0, #4 r0, a The conditional move instructions (CMVD & CMVS) can be used to find the maximum (or minimum) value in a table. If i0 is a pointer to the table, r0 will contain its maximum value after the following sequence: CMP(A) r0, (i0) CMVS r0, (i0)+ CMP(A)r0, (i0) CMVS r0, (i0)+ ........... ; r0 <- DM(i0) if r0 < DM(i0) ; r0 <- DM(i0) if r0 < DM(i0) Page 29 Preliminary information The CoolRISC(c) provides a RISC instruction set with four main categories: - branch instructions - transfer instructions - arithmetic and logic instructions - special instructions. 4 Central processing unit NAME Parameters op1 op2 addr:16 ip addr:16 ip addr:16 ip addr:16 ip JUMP Jcc CALL Preliminary information res XX-XE88LC01/03/05, Data Book CALLS PC0 <- addr PC0 <- ip if cc then PC0 <- addr if cc then PC0 <- ip PCn <- PCn-1 (n>1), PC1 <- PC0+1, PC0 <- addr PCn <- PCn-1 (n>1), PC1 <- PC0+1, PC0 <- ip ip <- PC0+1, PC0 <- addr:16 ip <- PC0+1, PC0 <- ip PCn-1 (n>0) <- PCn PC0 <- ip PCn-1 (n>0) <- PCn, GIE <- 1 PCn <- PCn-1 (n>1), PC1 <- ip, PC0 <- PC0+1 ip <- PC1, PCn-1 (n>1) <- PCn, PC0 <- PC0+1 RET RETS RETI PUSH POP MOVE CMVD CMVS SHL SHLC SHR SHRC SHRA CPL1 CPL2 CPL2C INC INCC DEC DECC reg, data:8 reg1, reg2 reg, eaddr eaddr, reg addr:8, data:8 reg1, reg2 reg, eaddr reg1, reg2 reg reg, eaddr reg1, reg2 reg reg, eaddr reg1, reg2 reg reg, eaddr reg1, reg2 reg reg, eaddr reg1, reg2 reg reg, eaddr reg1, reg2 reg reg, eaddr reg1, reg2 reg reg, eaddr reg1, reg2 reg reg, eaddr reg1, reg2 reg reg, eaddr reg1, reg2 reg reg, eaddr reg1, reg2 reg reg, eaddr reg1, reg2 reg reg, eaddr FUNCTION reg reg1 reg eaddr addr reg1 reg reg1 reg reg reg1 reg reg reg1 reg reg reg1 reg reg reg1 reg reg reg1 reg reg reg1 reg reg reg1 reg reg reg1 reg reg reg1 reg reg reg1 reg reg reg1 reg reg data reg2 eaddr reg data reg2 eaddr reg2 reg eaddr reg2 reg eaddr reg2 reg eaddr reg2 reg eaddr reg2 reg eaddr reg2 reg eaddr reg2 reg eaddr reg2 reg eaddr reg2 reg eaddr reg2 reg eaddr reg2 reg eaddr reg2 reg eaddr -,-,-,- -,-,-,- -,-,Z,a res <- op1 -,-,-,if C=0 then res <- op1 if C=1 then res <- op1 -,-,Z,a res(bitn) <- op1(bitn-1) (0<n<8), res(0) <- 0, C <- op1(7) C, V, Z, a res(bitn) <- op1(bitn-1) (0<n<8), res(0) <- C, C <- op1(7) C, V, Z, a res(bitn-1) <- op1(bitn) (0<n<8), res(7) <- 0, C <- op1(0) C, V, Z, a res(bitn-1) <- op1(bitn) (0<n<8), res(7) <- C, C <- op1(0) C, V, Z, a res(bitn-1) <- op1(bitn) (0<n<8), res(7) <- op1(7), C <- op1(0) C, V, Z, a Table 4.2: CoolRISC 816 Instruction Set Page 30 MODIF. res <- NOT (op1) -, -, Z, a res <- NOT (op1) +1, if op1 = 0 then C = 1 C, V, Z, a res <- NOT (op1) +C, if op1 = 0 then C = 1 C, V, Z, a res <- op1 +1, if overflow then C = 1 C, V, Z, a res <- op1 +C, if overflow then C = 1 C, V, Z, a res <- op1 -1, if underflow then C = 0 C, V, Z, a res <- op1 -(1 -C), if underflow then C = 0 C, V, Z, a NAME AND OR XOR ADD ADDC SUBD SUBDC SUBS SUBSC MUL MULA Parameters res op1 op2 reg, data:8 reg1, reg2, reg3 reg1, reg2 reg reg, data:8 reg1, reg2, reg3 reg1, reg2 reg reg, data:8 reg1, reg2, reg3 reg1, reg2 reg reg, data:8 reg1, reg2, reg3 reg1, reg2 reg reg, data:8 reg1, reg2, reg3 reg1, reg2 reg reg, data:8 reg1, reg2, reg3 reg1, reg2 reg reg, data:8 reg1, reg2, reg3 reg1, reg2 reg reg, data:8 reg1, reg2, reg3 reg1, reg2 reg reg, data:8 reg1, reg2, reg3 reg1, reg2 reg reg, data:8 reg1, reg2, reg3 reg1, reg2 reg reg, data:8 reg1, reg2, reg3 reg1, reg2 reg reg reg1 reg1 reg reg reg1 reg1 reg reg reg1 reg1 reg reg reg1 reg1 reg reg reg1 reg1 reg reg reg1 reg1 reg reg reg1 reg1 reg reg reg1 reg1 reg reg reg1 reg1 reg reg reg1 reg1 reg reg reg1 reg1 reg reg reg2 reg2 reg reg reg2 reg2 reg reg reg2 reg2 reg reg reg2 reg2 reg reg reg2 reg2 reg reg reg2 reg2 reg reg reg2 reg2 reg reg reg2 reg2 reg reg reg2 reg2 reg reg reg2 reg2 reg reg reg2 reg2 reg MSHL reg, shift:3 MSHR reg, shift:3 MSHRA reg, shift:3 CMP CMPA TSTB SETB CLRB INVB SFLAG reg, data:8 reg1, reg2 reg, eaddr reg, data:8 reg1, reg2 reg, eaddr reg, bit:3 reg, bit:3 reg, bit:3 reg, bit:3 4 Central processing unit data reg3 reg1 eaddr data reg3 reg1 eaddr data reg3 reg1 eaddr data reg3 reg1 eaddr data reg3 reg1 eaddr data reg3 reg1 eaddr data reg3 reg1 eaddr data reg3 reg1 eaddr data reg3 reg1 eaddr data reg3 reg1 eaddr data reg3 reg1 eaddr FUNCTION MODIF. res <- op1 AND op2 -, -, Z, a res <- op1 OR op2 -, -, Z, a res <- op1 XOR op2 -, -, Z, a res <- op1 + op2, if overflow then C=1 C, V, Z, a res <- op1 + op2 + C, if overflow then C=1 C, V, Z, a res <- op1 -op2, if underflow then C=0 C, V, Z, a res <- op1 -op2 - (1-C), if underflow then C=0 C, V, Z, a res <- op2 -op1, if underflow then C=0 C, V, Z, a res <- op2 -op1 - (1-C), if underflow then C=0 C, V, Z, a res <- op1 * op2 (15:8), a <- op1 * op2 (7:0), unsigned -, -, -, a res <- op1 * op2 (15:8), a <- op1 * op2 (7:0), signed (2 complement) -, -, -, a a(bitn) <- reg(bitn-shift) for (bitn >= shift), reg(bitn) <- reg (bitn+8-shift) for (bitn < shift) reg(bitn) <- reg(bitn+shift) for (bitn + shift < 8), a(bitn) <- reg (bitn-8+shift) for (bitn + shift >= 8) a <- SHRA(shift,reg), a <- SHL(8-shift,reg), SHRA propagates sign, do not use with shift=0x01 reg reg1 reg reg reg1 reg data reg2 eaddr data reg2 eaddr Preliminary information XX-XE88LC01/03/05, Data Book -, -, -, a -, -, -, a -, -, -, a if op2 > op1 then C <- 0, V = C AND NOT(Z), unsigned C, V, Z, a if op2 > op1 then C <- 0, V = C AND NOT(Z), signed C, V, Z, a Z <- NOT(reg(bit)) reg(bit) <- 1 reg(bit) <- 0 reg(bit) <- NOT(reg(bit)) a(7) <- C, a(6) <- C XOR V -, -, Z, a -, -, Z, a -, -, Z, a -, -, Z, a -, -, -, a Table 4.2: CoolRISC 816 Instruction Set Page 31 4 Central processing unit NAME Parameters RFLAG FREQ HALT NOP PMD XX-XE88LC01/03/05, Data Book res op1 op2 reg eaddr divn:4 FUNCTION MODIF. flags <- op1, SHL op1, SHL a C, V, Z, a set cpu frequency divider stops CPU no operation if s=1 then starts program dump, if s=0 stops program dump -, -, -, -, -, -, -, -, -, -, -, -, - reg eaddr s:1 Preliminary information Table 4.2: CoolRISC 816 Instruction Set eaddr Parameters Data Memory (DM) access addr:8 (ix) DM(addr) DM(ix) (ix, offset:8) DM(ix+offset) (ix, r3) DM(ix+r3) (ix)+ DM(ix) ix <- ix+1 (ix, offset:7)+ DM(ix) ix <- ix+offset -(ix) DM(ix-1) -(ix, offset:7) DM(ix-offset) Table 4.3: CoolRISC 816 addressing modes 11 Conditions cc CS CC ZS ZC VS VC EV EQ NE GT GE LT LE Test C=1 C=0 Z=1 Z=0 V=1 V=0 (EV0 OR EV1) = 1 After CMP d, s d=s d <> s d>s d >= s d<s d <= s Table 4.4: CoolRISC 816 conditional jump (Jcc) conditions information type addr:8 addr:16 ip 8-bit address 16-bit address Program Memory Index ix 4 Data Memory (DM) Indexes i0, i1, i2, i3 data:8 offset:8 offset:7 bit:3 shift:3 divn:4 8-bit data 8-bit positive offset 7-bit positive offset 3-bit Bit select value : 0..7 3-bit shift value : 2..7 0b0000: nodiv, 0b1000: div by 2, 0b1100: div by 4, 0b1110: div by 8, 0b1111: div by 16 Table 4.5: CoolRISC 816 instruction construction Page 32 Index update Addressing mode name Direct addressing Indexed addressing Indexed addressing with immediate offset Indexed addressing with register offset ix <- ix-1 ix <- ix-offset Indexed addressing with post-modification of index Indexed addressing with pre-modification of index XX-XE88LC01/03/05, Data Book Function r0 r1 r2 r3 i0l i0h i1l i1h i2l i2h i3l i3h ipl iph stat a reg reg1 reg2 reg3 DM offset i0[7:0] i0[15:8] i1[7:0] i1[15:8] i2[7:0] i2[15:8] i3[7:0] i3[15:8] ip[7:0] ip[15:8] status accu Table 4.6: CoolRISC 816 internal registers 15 14 13 12 11 10 registers organization 9 8 7 6 5 4 3 2 1 0 register name EV0 PC ip i0 i1 i2 i3 a r0 r1 r2 r3 stat PC iph i0h i1h i2h i3h ipl i0l i1l i2l i3l a r0 r1 r2 r3 IE2 IE1 GIE IN2 IN1 IN0 EV1 Table 4.7: CoolRISC 816 registers organization Interrupt CALL address IN0 IN1 IN2 3 1 2 Table 4.8: CoolRISC 816 interrupts The PUSH & POP instructions allow the processor to read and write its hardware stack. This can be used to "extend the depth" of the stack when nested interrupts are needed. The software implementation of nested interrupts can be achieved with the following instructions : Interrupt POP MOVE eaddr1, ipl MOVE eaddr2, iph ...... MOVE ipl, eaddr1 MOVE iph, eaddr2 PUSH RET(I) 4.2.3 ; ; ; ; ; ; ; ; ; PC1 <- return address ip <- PC1 eaddr1 <- return. address eaddr2 <- return. address 1 stack level is now freed ipl <- eaddr1 iph <- eaddr2 PC1 <- ip PC0 <- PC1 Register bank The register bank of the 8-bit CoolRISC core 816 is described in Table 4.6 and Table 4.7. Page 33 Preliminary information 16 Registers 4 Central processing unit 4 Central processing unit XX-XE88LC01/03/05, Data Book Four data registers and an accu register are available, as well as a two-byte Program Memory Index (ip) and four two-byte Data Memory Index (ix) registers. These Index registers allow the user to address up to 64k instructions and up to 64k Data bytes. ip is also used to save the return address with the Software Call instruction (CALLS). A Status register (stat) is used only to control Interrupts and Events. r3 can also be used as an offset register in the indexed addressing mode of the Data Memory. Preliminary information If some of the 10 Data & Program Memory Index registers are not used permanently as indexes, they can be used as data registers. Furthermore, if some of them are not used in a given routine, they can also be advantageously used as temporary data registers. Table 4.9 summarises the names and the roles of the registers. Register Names Data Regs Data Mem. Index a "X" r0 X r1 X r2 X r3 X DM offset i0l X X i0h X X i1l X X i1h X X i2l X X i2h X X Prog. Mem. Index Soft. Call i3l X X i3h X X ipl X X X iph X X X stat Table 4.9: Registers Roles 4.2.4 Program Memory addressing modes The CoolRISC 816 provides one 16-bit Program Memory index called ip in order to address indirectly the 64K of Program Memory (ipl for the LSB bits, iph for the MSB). The address field in a direct Jump instruction is of 16 bits. This allows addressing directly to the whole Program Memory space. 4.2.5 Data Memory addressing modes The CoolRISC(c) 816 provides four 16-bit Data Memory Indexes called ix (i0, i1, i2 & i3) in order to address 64K bytes of Data Memory (ixl for the LSB bits, ixh for the MSB). The Data Memory is organised as 256 pages of 256 bytes. The whole memory can be addressed indirectly using ix, while only page 0 can be addressed directly. 4.2.5.1 Direct addressing Data Memory access : DM(addr:8) Page 34 XX-XE88LC01/03/05, Data Book 4 Central processing unit This mode is limited to the addressing of page 0. The field addr:8 of the corresponding instructions is used as a direct address (DMAddr[7:0]) while the MSB bits of the Data Memory address (DMAddr[15:8]) are equal to 0. o ffse t [7:0] r3 M U X addr[7:0] 8 16 +/- i0 i1 i2 M U X 16 M U X DM Addr[7:0] M U X DMAddr[15:8] 16 8 M U X 0 i3 Direct addressing Figure 4.4: Direct addressing 4.2.5.2 Indexed addressing Data Memory access : DM(ix) The complete Data Memory space can be addressed with this mode. The value of the index ix is the Data Memory address (DMAddr[15:0]). The 8 LSB bits (ixl) define the offset in the page while the 8 MSB bits (ixh) define the page number. Therefore 256 pages of 256 bytes can be addressed. 8 o ffs e t [7:0] r3 M U X ad dr[7:0] 8 16 +/- i0 i1 i2 M U X 16 M U X DMAddr[7:0] M U X DMAddr[15:8] 16 M U X 8 0 i3 Dire ct add ressing Figure 4.5: Indexed addressing 4.2.5.3 Indexed addressing with an immediate offset Data Memory access : DM(ix+offset:8) Page 35 Preliminary information 8 4 Central processing unit XX-XE88LC01/03/05, Data Book The 16-bit Data Memory address DMAddr[15:0] is calculated by the addition of an 8-bit positive offset:8 taken in the instruction to one of the 16-bit Index ix. Preliminary information 8 offset[7:0] r3 addr[7:0] M U X 8 + i0 i1 i2 16 M U X 16 M U X DMAddr[7:0] M U X DMAddr[15:8] 16 8 M U X 0 i3 D irect ad dressin g Figure 4.6: Indexed addressing with an immediate offset 4.2.5.4 Indexed addressing with a register offset Data Memory access : DM(ix+r3) The 16-bit Data Memory address DMAddr[15:0] is calculated by the addition of the 8-bit positive value of the r3 register to one of the 16-bit Index ix. 8 o ffs e t [7:0] r3 ad dr[7:0] M U X i0 i1 i2 M U X 8 16 + 16 M U X DMAddr[7:0] M U X DMAddr[15:8] 16 M U X 8 0 i3 D ire ct add ressing Figure 4.7: Indexed addressing with a register offset 4.2.5.5 Indexed addressing with Post-modification of the Index Data Memory access : DM(ix) Page 36 XX-XE88LC01/03/05, Data Book Index Update : Particular case : 4 Central processing unit ix <- ix+offset:7 offset:7 = 1 The 16-bit Data Memory address DMAddr[15:0] is given directly by the value of one of the 16-bit Index ix. The 16bit Index ix is updated by the addition of the 7-bit positive offset:7 field in the corresponding instruction. offset[6:0] r3 add r[7:0] M U X 7 16 + i0 M U X i1 i2 16 M U X DMAddr[7:0] M U X DMAddr[15:8] 16 8 M U X 0 i3 D irect a ddress in g Figure 4.8: Indexed addressing with post-modification of the Index 4.2.5.6 Indexed addressing with Pre-modification of the Index Data Memory access : DM(ix-offset:7) Index Update : Particular case : ix <- ix-offset:7 offset:7 = 1 The 16-bit Data Memory address DMAddr[15:0] is calculated by the subtraction of the 7-bit positive offset:7 from the 16-bit Index ix. The 16-bit Index ix is updated by the subtraction of the 7-bit positive offset:7 field in the corresponding instruction. 8 offset[6:0] r3 ad dr[7:0 ] M U X i0 i1 i2 M U X 7 16 - 16 M U X DMAddr[7:0] M U X DMAddr[15:8] 16 M U X 8 0 i3 D irect add ressing Figure 4.9: Indexed addressing with pre-modification of the index Page 37 Preliminary information 8 4 Central processing unit 4.2.5.7 XX-XE88LC01/03/05, Data Book Remark on the Indexed addressing In an Indexed Data Memory access, the Index used for the access may also be used as the destination register for the operation. Preliminary information In the case of Pre/Post Index modification, the Index ix is updated before the result of the operation is stored in ixl or ixh. 4.2.6 Flags Z, C & V The flag Z (zero) is modified by all ALU operations (including the MOVE into a register). Z = 1 only if the ALU Output (not the multiplier output) is equal to 0. The flags C (carry) and V (overflow) are only modified by arithmetic, comparison and shift operations. In shift operations, C always contains the "shifted out" bit. In arithmetic operations with unsigned numbers, C indicates whether an overflow or an underflow occurs (can be active either high or low depending on the operation). In arithmetic and shift operations with signed numbers, V indicates whether an overflow or an underflow occurs. V = 1 when overflow (or underflow). After the comparison instructions "CMP(A) d, s" : C = 0 if d > s 4.2.7 and V = C * NOT(Z) ALU output register: a The ALU Output Register (Figure 2.1) named a always contains the result of the last ALU operation. It is a temporary register that is always modified by ALU operations. It is addressed as a normal register in the register bank. It should be used for temporary results, as power-consumption is saved if this low-power accumulator is used instead of another data register. 4.2.8 Program counter The 16-bit program counter (PC) can address a Program Memory with up to 64K instructions. A hardware stack is provided for efficient subroutine and Interrupt support. When the hardware stack is full, Interrupt is disabled until one level of the stack becomes free again (RET or RETI). Additional subroutine levels are supported with no hardware cost through the use of the Software Call mechanism (CALLS instruction). 4.2.9 Branch conditions After a comparison instruction (CMP), 6 conditional branch instructions are possible depending on the comparison result, after the other ALU operations, 6 conditional branch instructions are possible depending on the value of the flags. The JEV branch instruction is executed if one (or more) of the Event bits of the Status register is active (equal to 1). Page 38 XX-XE88LC01/03/05, Data Book 4 Central processing unit The carry (C), the overflow (V) and the zero (Z) flags result from the "previous" ALU operation (which modified the flags!). Table 4.10 summarises the different Branch conditions available. Branch Test JCS C=1 JCC C=0 JVS V=1 JVC V=0 JZS Z=1 JZC Z=0 Branch on Event JEV (EV0 OR EV1) = 1 Branch on CMP result JEQ d=s JNE d <> s JGT d>s JGE d >= s JLT d<s JLE d <= s Table 4.10: Branch Conditions The Branch JEV is executed if one (or more) of the Event bits of the Status register is active (equal to 1). 4.2.10 Call, Branch and Link In most RISC microprocessors, only a Branch & Link mechanism is available. This mechanism saves the return address in a register. The programmer is responsible to save this address in the Data Memory before a new Software Call is used. CoolRISC provides both Hardware and Software Call mechanisms. The Software Call stores the return address in a particular register which is the two-byte Program Memory Index ip. Therefore, the programmer has to save ip (if it is used) before a Software Call (CALLS). 4.2.11 Events and Interrupts The 8-bit Status register (stat) contains the following booleans: bit0: Event nb 0 (EV0) bit1: Event nb 1 (EV1) bit2: Interrupt nb 0 (IN0) bit3: Interrupt nb 1 (IN1) bit4: Interrupt nb 2 (IN2) bit5: Enable bit for all Interrupts (GIE) bit6: Enable bit for IN1 (IE1) bit7: Enable bit for IN2 (IE2) Events and Interrupts are Boolean flags which can be either hardware or software modified. A negative pulse on one of the nEvent[1:0] or nInterrupt[2:0] pins will set the corresponding bit to 1. In addition, a write to the Status register can either set or reset any of these bits. Therefore Interrupts and Events can be forced by software (see next chapter: "Pipeline Exception"). Note however that a is modified when "Software Interrupt" are generated (by an ALU operation). Interrupts force a CALL to a fixed address (one specific address for each interrupt), save the Program counter (PC) on the stack (which will be restored by the RETI or RET instruction), and start the processor if it is in the HALT mode. Page 39 Preliminary information Branch on ALU result 4 Central processing unit XX-XE88LC01/03/05, Data Book Preliminary information The designer must save the accumulator a, the flag C and the working registers (which are used in the Interrupt routine) at the beginning of the Interrupt routine, and restore them at the end as follows : MOVE eaddr1, a SFLAG MOVE eaddr2, a MOVE eaddr3, ri .......................... MOVE ri, eaddr3 RFLAG eaddr2 MOVE a, eaddr1 ;save a & Z ;a ( C & V ;save C & V ;save ri ;restore ri ;restore C & V ;restore a & Z A disabled Interrupt (corresponding Enable bit at 0) cannot force a CALL, and cannot START the CPU if it is in the HALT mode. However, the request is taken into account and will be executed as soon as the corresponding Enable bit is set to 1, unless the interrupt bit has been successfully cleared by software in the meantime. The general Interrupt Enable bit GIE (stat[5]), if 0, disables any Interrupt with the same principle as above. When a CALL to an Interrupt routine is executed, GIE is automatically cleared in order to prevent the CPU executing another CALL to the same (or another) Interrupt. When the RETI instruction is executed, GIE is automatically set to 1 in order to allow Interrupts to occur again. In order to return from an Interrupt, RET must be used instead of RETI if the programmer does not want to change the value of GIE. The programmer may allow nested Interrupts by setting GIE to 1. But each time a new CALL to an Interrupt is executed, a new level of the hardware stack is used. When the hardware stack is full, Interrupts are disabled independently of the value of GIE. As soon as a level of the stack is freed (RET, RETI), a pending Interrupt can be executed. An action on the nEvent[1:0] pins restarts the processor if it is in the HALT mode. In contrast to the Interrupt, an Event does not force a call to a predefined address. It should be used as a handshake facility. The HALT instruction is only effective if all Event bits and all non-masked Interrupt bits are cleared. The nEvent and nInterrupt lines are active low, but a "short" negative pulse is sufficient to set the Event or Interrupt bit in the status register. Clearing an Event or an Interrupt bit is only possible if the corresponding input line is not active. This allows the execution of an Interrupt routine as long as the corresponding input line is active. In the Interrupt routine, it is recommended first to desactivate the Interrupt line (by commanding the corresponding peripheral to release the line), and then to clear the corresponding Interrupt bit. Thus, it will be possible to receive a new Interrupt (on the same input) as soon as the Interrupt bit is cleared. If several Interrupts are pending, they are executed in order of priority. Only GIE is reset by a hardware Reset. The other booleans must be initialised by the programmer. Table 4.11 shows the call addresses and the priorities of the Interrupts. Inter. nb. CALL ad. Priority Inter. nb 0 3 Highest Inter. nb 1 1 Medium Table 4.11: CALL addresses and priorities Page 40 XX-XE88LC01/03/05, Data Book 4 Central processing unit Inter. nb. CALL ad. Priority Inter. nb 2 2 Lowest Table 4.11: CALL addresses and priorities 4.2.12 Pipeline exception SETB stat, #4 MOVE a, #parameter ; trap ; a ( parameter If an Event bit is set by software, and a "JUMP on Event" (JEV) is the next instruction, the first instruction will be ignored by the second. These are the only delays caused by the CoolRISC(c) pipeline. 4.2.13 HALT mode The HALT instruction turns the processor into stand-by mode, in which power consumption is minimum. Only an Event, an Interrupt or a hardware Reset are able to wake up the microprocessor. The HALT instruction is only effective if all Event bits and all enabled Interrupt bits are inactive (low). When the processor stops because of a HALT instruction, the previous instruction is totally executed before the stand-by mode occurs. The next instruction will only begin when the processor restarts. 4.2.14 Hardware Reset When the nReset signal goes low, the general Interrupt Mask bit GIE is reset, the CPU restarts if it was in the HALT mode, the frequency division factor is set to 1x, the PC stack is emptied, and the Test mode is reset as well as the Program Memory Dump mode. Furthermore, at each rising edge of the external clock, a JUMP to address 0 is forced. The instruction located at address 0 will be executed when the nReset signal returns high. 4.2.15 Low frequency modes As explained in chapter 1.6, the processor internal frequency can be reduced by a factor of 2, 4, 8 or 16. The division factor is both hardware and software controlled. The FREQ instruction sets the basic division factor which is output on the FreqOut[3:0] bus. The instruction that follows FREQ is already executed with the new processor frequency. Page 41 Preliminary information If an interrupt bit is set by the software (write into stat) the pipeline causes the next instruction to be executed "before" the CPU executes the interrupt routine. This allows to supply a parameter to a "trap" as follows : Preliminary information 4 Central processing unit Page 42 XX-XE88LC01/03/05, Data Book XX-XE88LC01/03/05, Data Book 5 5 Memory Memory 5.1 Memory organisation Program memory Data address bus Program address bus Program memory is made in one page (program address bus is 16 bits wide). Data is made of several 256 bytes pages. RAM CPU Peripherals CPU Instruction pipeline registers 22 bits wide LP RAM 8 bits wide Figure 5.1: Memory organization 5.2 Program memory The program memory is implemented as Multiple Time Programmable (MTP) Flash memory or Read-Only Memory (ROM). The power consumption of MTP and ROM is linear with the access frequency (no static current). Memory sizes : * * Flash MTP: 8192 x 22 bits ROM : 8192 x 22 bits block size address ROM/MTP 8192 x 22 H0000 - H1FFF Table 5.1: Program addresses 5.3 Data memory The data memory is implemented as static Random-Access Memory (RAM). The RAM size is 512 x 8 bits, plus a 8 x 8 low memory registers (named LP RAM) that require very low current when addressed. Programs using these registers instead of regular RAM will spare current. Note: Note: The RAM content is not defined at power-up. The registers in Data memory (LP RAM) are not related to the CPU registers. Page 43 Preliminary information The MCU uses a Harvard architecture, so that memory is organised in two separated fields: program memory and data memory. As the memory is separated, the central processing unit can read/write data at the same time it loads an instruction. Peripherals and system control registers are mapped on data memory space. 5 Memory XX-XE88LC01/03/05, Data Book block size address LP RAM RAM 8x8 512 x 8 H0000 - H0007 H0080 - H027F Table 5.2: RAM addresses Preliminary information 5.4 Peripherals mapping block size address LP RAM Reserved System control Port A Port B Port C Port D MTP Event Interrupts control 8x8 8x8 16x8 8x8 8x8 4x8 4x8 4x8 4x8 8x8 H0000-H0007 H0008-H000F H0010-H001F H0020-H0027 H0028-H002F H0030-H0033 H0034-H0037 H0038-H003B H003C-H003F H0040-H0047 Page "System operating modes" on page 47 "Parallel IO ports" on page 69 "Memory" on page 43 (used only for MTP programming) "System operating modes" on page 47 Page 0 USRT 8x8 H0048-H004F UART 8x8 H0050-H0057 Counters ADC Reserved DACs Other (Vmult, VLD) RAM1 RAM2 RAM3 8x8 8x8 12x8 8x8 H0058-H005F H0060-H0067 H0068-H0073 H0074-H007B 4x8 H007C-H007F 128x8 256x8 128x8 H0080 - H00FF H0100 - H01FF H0200 - H027F Specific chapter "Memory" on page 43 (low power memory) "Universal Synchronous Receiver/Transmitter (USRT)" on page 101 "Universal Asynchronous Receiver/Transmitter (UART)" on page 79 "Counters/timers" on page 87 "Acquisition chain" on page 103 "Analog outputs" on page 111 "Power supply" on page 21 and "Voltage Level Detector" on page 99 Page 1 Page 2 Table 5.3: Peripherals addresses 5.5 Address pack A standardized peripheral address naming is provided to help developpers. The address pack is shown in XEMICS application note AN8000.01. 5.6 MTP Flash memory programmation 5.6.1 Introduction The programmation process uses the test interface of the CPU (the main clock of the processor, and its testin, testout and testck ports), a reset port (active high) and another clock (ptck). It requires that the XE88LC01/03/05 is in test mode (TEST/VPP above VDD), connecting internal signals to pins. More detailed information is given in XEMICS application note AN8000.02. Be aware that the XE88LC02/04/06 and above use another programming algorithm. Page 44 XX-XE88LC01/03/05, Data Book MTP Registers MTP memory 16 RegEEP1 16 instruction 8 RegEEP2MSB RegEEP2LSB RegEEP3MSB RegEEP3Mid 22 RegEEP3LSB Figure 5.2: MTP registers organisation register name address RegEEP RegEEP1 RegEEP2 RegEEP3 h0038 h0039 h003A h003B Table 5.4: MTP Registers Page 45 Preliminary information RegEEP address data bus address bus 5.6.2 5 Memory Preliminary information 5 Memory Page 46 XX-XE88LC01/03/05, Data Book XX-XE88LC01/03/05, Data Book 6 6 System operating modes System operating modes The system block controls resets, interrupts, events, clocks and operating modes. xtalPower ckXtal Xtal BitExtClk External clock ck125 BitColdRC BitSleep ResetPortA POR RCPower clocks ResetWD Peripherals Watchdog ResetWD ClearPre Reset Sources/ Synchronize BusError Reset Pin RC cold start ck1 Sleep mode CPU CPU clock selection Prescaler resetsleep PortA BitColdXtal ClearWD ResetSys ResetPad resetcold All signals enter left, top or bottom and output right of the boxes. Figure 6.1: System block 6.1 Operating modes The XE8000 system can operate in three different modes from which two are low-power dissipation modes (StandBy and Sleep). In addition to that, most peripherals also have several low power modes. * Active mode (normal operation) * StandBy mode (CPU halt, oscillator on) * Sleep mode (oscillator off, RAM state maintained) 6.1.1 Start-up and Reset states These states can only be entered following reset (see Figure 6.3). A correct start-up of the whole microcontroller is ensured. 6.1.2 Active mode This is the running mode where all peripherals can work and the CPU executes instructions. 6.1.3 Standby mode Executing a HALT instruction puts the XE8000 into the StandBy mode. The voltage regulators, Oscillators, Watchdog timer, interrupts, events and counters can be operated. However, the CPU stops, since the clock related to instruction fetching and execution stops. Registers, RAM, and I/O pins retain their states prior to StandBy mode. StandBy is cancelled by a RESET (except BusError reset) or an Interrupt/Event request if enabled. Note: Unless disabled, watchdog timer is running in standby mode. Page 47 Preliminary information Xtal cold start ck1 ckRC RC addr decoder ckcpu xtalPower RCPower 6 System operating modes 6.1.4 XX-XE88LC01/03/05, Data Book Sleep mode This is a very low-power mode in which all peripherals are stopped. All internal registers and RAM keep the value before Sleep mode. This mode can be used when no time-keeping is necessary. Both oscillators are stopped. datain[7] ck_RegSysCtrl BitEnSleep resetcold datain[7] Preliminary information ck_RegSysClock BitSleep_tmp ckCpu BitSleep to CPU ResetPortA ResetPad Figure 6.2: sleep mode structure To put the XE8000 in Sleep mode first the SleepEn (sleep enable) bit in RegSysCtrl must be set to 1. The only Reset which clears this bit is the Power-On-Reset. It can be cleared at any time also by writing 0 to this location. Once the SleepEn bit is set to one, writing the Sleep bit in RegSysReset immediately puts the XE8000 in the Sleep mode. There are only three possible ways to wake-up from the Sleep mode : 1. In case of Power-Down followed by Power-On, the Power-On-Reset initializes the whole system. In this case, the peripheral register contents and the RAM information is lost. 2. RESET pad, no information loss. 3. PortA reset combination, no information loss. If the Reset pin or PortA reset is the Wake-Up condition, the SleepEn bit is not cleared and this therefore provides the information that the circuit was previously running and that the XE8000 should now wake up from Sleep mode. Note: Due to the pipelined architecture, the instruction following the writing of the Sleep Bit may be executed under certain conditions. Therefore, the writing of the Sleep bit must be followed by a NOP. Note: Watchdog timer is stopped in sleep mode. Page 48 XX-XE88LC01/03/05, Data Book 6 System operating modes START-UP start phase RC on XTAL off por after 8 RC clock cycles por por padreset portA reset RESET CPU halted clocks active padreset portA reset watchdog reset buserror reset after 4 CPU clock cycles padreset portA reset watchdog reset halt instruction ACTIVE CPU active clocks active interrupt / event STAND-BY SLEEP CPU halted clocks active RC off RC bias on or off XTAL off set bit Sleep low current active ultra low current time keeping no activity memory keeping Figure 6.3: System operating modes. Most peripherals also have several low power modes register name address (hex) comments RegSysCtrl RegSysReset RegSysClock RegSysMisc RegSysWd RegSysPre0 RegSysPre1 RegSysTest1 RegSysTest2 RegSysTest3 RegSysTestAna RegSysRCTrim1 RegSysRCTrim2 RegSysVIreg RegSysWarm H0010 H0011 H0012 H0013 H0014 H0015 H0016 H0017 H0018 H0019 H001A H001B H001C H001D H001E H001F System sleep and reset flags System sleep and reset enable Clock selection Special functions Watchdog Prescaler Reserved RC clock frequency select Internal regulator setting Reserved Reserved Table 6.1: System registers 6.2 Resets To initialize the XE8000, a system reset must be executed. Page 49 Preliminary information por 6 System operating modes XX-XE88LC01/03/05, Data Book This can be performed in 5 ways: Preliminary information * * * * * initial reset from the Power-On Reset (POR) external RESET from the RESET pin port A reset combination (programmable) watchdog timer reset (programmable enable) wrong data memory address reset = BusError reset Power-on reset is treated as a special case with an additional ColdStart delay on RC oscillator. This ColdStart delay guarantees a stable oscillator clock once it is finished (see Figure 6.3). The circuit always starts with the RC oscillator because its Start-Up time is very short compared to the Quartz oscillator. Once the RC ColdStart delay of several RC clock is finished, the oscillator selector detecting only the RC clock needs an additional RC period to switch to RC oscillator for System clock. From now on all Reset sources go via the Reset Synchronizer logic which prolongs any reset by 3 whole System clock periods and then releases the System reset on the falling edge of the System clock. The program counter for Instruction words is cleared to 0 and first Jump Main instruction is executed after the end of System Reset. VDD POR RC ck 1 2 3 4 . . . . . . . . . . 5-10 ms. CPU ck System reset ColdStartRC CPUAddr 0000 MAIN 14 15 0000 MAIN 14 15 0000 MAIN Figure 6.4: power-on reset start Reset source RC ck 1 2 3 4 5 6 7 8 9 10 11 12 13 CPU ck System reset ColdStartRC CPUAddr ???? Figure 6.5: wake from sleep (short reset) Reset source RC ck 1 2 3 4 5 6 7 8 9 10 11 12 13 CPU ck System reset ColdStartRC CPUAddr ???? Figure 6.6: wake from sleep (long reset) Page 50 XX-XE88LC01/03/05, Data Book 6 System operating modes Reset source CPUck System reset ColdStartRC/Xtal ???? 0000 MAIN ???? ???? Figure 6.7: reset in active mode 6.2.1 Initial reset from the Power-On-Circuit At power-on the POR circuit supplied by the internal Voltage regulator (which also supplies the whole digital part ) generates a Reset until the regulated voltage is high enough for the IC to work. 6.2.2 External Reset from the RESET pin System reset can be activated by using the RESET pin. 6.2.3 PortA programmed Reset combination. As described in the PortA description a PortA reset can be programmed. When Input PortA status matches the programmed combination in RegPARes0 and RegPARes1 a reset is generated which lasts until Reset portA status is removed from PortA inputs. Direct non-debounced PortA status is used for this reset. 6.2.4 Watch-Dog timer Reset The Watchdog Timer will generate a RESET if it is not cleared on time. See chapter WATCHDOG TIMER for details. 6.2.5 BusError reset Address space is distributed as shown in Register mapping to different peripherals. If an unused address region was addressed, then the BusError reset is executed. 6.2.6 Reset Registers Two registers are dedicated for reset status and control, RegSysReset and RegSysCtrl. The bits Sleep and SleepEn are also located in those registers but have nothing to do with reset and are described in a dedicated chapter. RegSysReset gives reset source information. * * * * * ResBusError ResWD ResPortA ResPad ResPadSleep an undefined peripheral register was addressed. the Watchdog timer generated a reset. a PortA combination generated a reset. Reset pad was used . Reset pad was used during Sleep mode. RegSysCtrl enables reset sources * * * EnBusError EnResWD EnResPConf enables reset source from bus error enables reset source from watchdog has a special function. It is a reset source selection for Port Configuration reset. It can be activated either with power-on reset only or with a combination of power-on reset and any other reset source. EnResPConf resetpconf 1 0 any reset source por ONLY Table 6.2: EnResPConf Page 51 Preliminary information ???? CPUAddr 6 System operating modes Preliminary information bit name 7 Sleep 6 5 4 3 2 1 0 ResPor ResBusError ResWD ResPortA ResPad ResPadSleep XX-XE88LC01/03/05, Data Book reset resetpor or resetPortA or resetPad or resetCold 0 0 resetcold 0 resetcold 0 resetcold 0 resetcold 0 resetcold 0 rw description w Sleep flag (read value is 0) rt rc rc rc rc rc r Por status in test mode reset source is BusError reset source is Watchdog reset source is PortA combination reset source is debounced pad reset reset source is pad reset (in sleep mode) reserved Table 6.3: RegSysReset bit name reset rw description 7 6 5 SleepEn EnResPConf EnBusError 0 resetpor 0 resetcold 0 resetcold rw rw rw 4 EnResWD 0 resetcold rw 3-0 -- 0000 r enable Sleep flag enable reset port config when resetsystem enable reset from BusError enable reset from Watchdog this bit can not be set to 0 by software unused Table 6.4: RegSysCtrl 6.2.7 Oscillators and prescaler control This is described in the Oscillators chapter. 6.2.8 Other features * RCOnPA0 * * * DebFast OutputCKXtal OutputCKCpu if set to one, an event (or interrupt) on pad PA[0] will start the RC oscillator by setting EnableRC debouncer clock selection. This clock is used for all digital debouncer in the XE8000 output Xtal clock on portPB[3] output CpuCkout clock on portPB[2]. DebFast debouncer frequency 1 0 8KHz 256Hz Table 6.5: Debouncer frequency bit name reset rw description 7 6-4 3 2 1 0 DisResPad -RCOnPA0 DebFast OutputCkXtal OutputCkCpu 0 testpad 000 0 resetsleep 0 resetsleep 0 resetsleep 0 resetsleep r wt r rw rw rw rw disable resetpad in test mode unused Start RC on PA[0] debouncer clock speed (0=slow) output CkXtal on pad PB[3] output CKOutCpu on pad PB[2] Table 6.6: RegSysMisc 6.3 Interrupt 6.3.1 Features The XE8000 support 16 interrupt sources, namely: Page 52 XX-XE88LC01/03/05, Data Book * * * * * 6 System operating modes 8 external inputs from PortA 4 from the internal Counters A,B,C and D 2 from the internal Prescaler (128Hz and 1Hz ) 1 from internal Voltage Level Detector 1 from Acquisition chain These interrupts have 3 levels of priority. Overview The interrupts are divided into 3 categories with different priorities. The priorities are fixed and are described below : * * * High: acquisition chain, counterA, counterC, prescaler 128Hz, UartTx, UartRx Mid: PortA[0,1,4,5], prescaler 1Hz, VLD Low: PortA[2,3,6,7], counterB, counterD. There is an interrupt flag register associated with each priority. The interrupt flag registers are RegIrqHig, RegIrqMid and RegIrqLow. The rising edge of the interrupt (IRQ) source sets the Interrupt flag if it is enabled. The Interrupt flag is automatically cleared following system Resets and can be cleared by software. This is achieved by writing the corresponding Flag in the RegIrqXXX register to 1. For definitively clearing the interrupt, one has to disable the corresponding bit in the CoolRISC status register . For example if an interrupt is generated by the pad 0 of port A: move clrb RegIrqMid, #0x01 stat,#3 Each interrupt (IRQ) source can be enabled or disabled by software with the help of the Interrupt enable registers RegIrqEnHig, RegIrqEnMid and RegIrqEnLow. There is a bit within each of these registers corresponding to the list above. For example, within RegIrqEnHig, there is a bit corresponding to each of CounterA, CounterC, Prescaler 128Hz, UartTx and UartRx that enables/disables the associated interrupt accordingly. 6.3.3 PortA interrupts It is possible to use each pin of PortA (8 pins) as an independent edge triggered IRQ input. Bitwise configuration (debounced or non-debounced / falling or rising edge) is performed using reserved registers in portA. The debouncer frequency can be either 256Hz (slow debouncer clock) or 8KHz (fast-debouncer clock). The debounce clock is common for all 8 PortA inputs (and also for the RESET pad). When debounced, the signal on portA has to be stable for one to two periods of selected internal debounce clock to ensure that the new logical value is accepted. 6.3.4 Counters A, B, C and D interrupts Counters generate Interrupts only when they work as normal counters (as opposed to PWMs). Loops Counters generate interrupts regularly, depending on their mode of operation (up/down counting). If more interrupts arrive from the same counter before its interrupt is served, second and subsequent interrupts are ignored. This can be the case when interrupts arrive too quickly or the interrupt service routine is currently serving some higher priority interrupts. 6.3.5 Prescaler interrupts Two interrupts are available from the Prescaler, 128Hz and 1Hz. Both are generated by the low 15-stage divider.This means that they can be accurate at 128Hz and 1Hz only when the Xtal 32768 Quartz oscillator is enabled. If the Xtal is not enabled, they are derived from the RC oscillator frequency. The Prescaler can be resynchronized at any time by resetting it. Page 53 Preliminary information 6.3.2 6 System operating modes 6.3.6 XX-XE88LC01/03/05, Data Book Voltage Level Detector interrupt The Voltage Level Detector generates an interrupt following supply voltage comparison in response to a comparison request. The interrupt indicates the comparison is complete. 6.3.7 Acquisition chain interrupt Preliminary information The Acquisition chain generates an interrupt when the acquisition is completed. 6.3.8 Interrupt priorities Two registers have been provided to facilitate the writing of interrupt service software namely : * * RegIrqPriority RegIrqIrq The first, RegIrqPriority, contains the ID-code of the highest Priority interrupt. The table below shows these priorities which correspond to organization of interrupts in the registers above and their ID-code. RegIrqPriority Irq on CPU (priority) highest priority interrupt set HFF H17 H16 H14 H13 H11 H10 H0F H0E H0D H0C H0B H0A H09 H08 H07 H06 H05 H04 H03 H02 none IN0 (high) IN0 (high) IN0 (high) IN0 (high) IN0 (high) IN0 (high) IN1 (mid) IN1 (mid) IN1 (mid) IN1 (mid) IN1 (mid) IN1 (mid) IN1 (mid) IN1 (mid) IN2 (low) IN2 (low) IN2 (low) IN2 (low) IN2 (low) IN2 (low) no interrupt IrqAc IrqPre1 IrqCntA IrqCntC IrqUartTx IrqUartRx reserved reserved IrqPA[5] IrqPA[4] IIrqPre2 IrqVLD IrqPA[1] IrqPA[0] IrqPA[7] IrqPA[6] IrqCntB IrqCntD IrqPA[3] IrqPA[2] Table 6.7: all interrupts and their priorities ID-codes H15, H12, H11, H10, H1, and H0 are not used in this product. Code H17 is only used in some products. After any system Reset the RegIrqPriority value is HFF indicating no interrupt request has been issued subsequently to the Reset. The second, RegIrqIrq, indicates the priority levels of the current IRQs. The three levels of interrupts map directly to those supported by the CoolRISC (IN0, IN1 & IN2). For more information, see the documentation about the CoolRISC816 core. register name address (hex) RegIrqHig H0040 Table 6.8: Interrupt registers Page 54 XX-XE88LC01/03/05, Data Book register name address (hex) RegIrqMid RegIrqLow RegIrqEnHig RegIrqEnMid RegIrqEnLow RegIrqPriority RegIrqIrq H0041 H0042 H0043 H0044 H0045 H0046 H0047 6 System operating modes bit name reset rw description 7 6 5 4 3 2 1 0 IrqAc IrqPre1 -IrqCntA IrqCntC -IrqUartTx IrqUartRx 0 resetsystem 0 resetsystem 0 0 resetsystem 0 resetsystem 0 0 resetsystem 0 resetsystem r c1 r c1 r r c1 r c1 r r c1 r c1 interrupt from acquisition chain (when available) interrupt from prescaler (128 Hz) unused interrupt from CounterA interrupt from CounterC unused interrupt from Uart Transmitter interrupt from Uart Receiver Table 6.9: RegIrqHig bit name reset rw description 7 6 5 4 3 2 1 0 reserved reserved IrqPA[5] IrqPA[4] IrqPre2 IrqVld IrqPA[1] IrqPA[0] 0 resetsystem 0 resetsystem 0 resetsystem 0 resetsystem 0 resetsystem 0 resetsystem 0 resetsystem 0 resetsystem r c1 r c1 r c1 r c1 r c1 r c1 r c1 r c1 interrupt from Pad PA[5] interrupt from Pad PA[4] interrupt from prescaler (1 Hz) interrupt from Voltage Level Detector interrupt form Pad PA[1] interrupt form Pad PA[0] Table 6.10: RegIrqMid bit name reset rw description 7 6 5 4 3 2 1 0 IrqPA[7] IrqPA[6] IrqCntB IrqCntD IrqPA[3] IrqPA[2] --- 0 resetsystem 0 resetsystem 0 resetsystem 0 resetsystem 0 resetsystem 0 resetsystem 0 0 r c1 r c1 r c1 r c1 r c1 r c1 r r interrupt from Pad PA[7] interrupt from Pad PA[6] interrupt from CounterB interrupt from CounterD interrupt from Pad PA[3] interrupt from Pad PA[2] unused unused Table 6.11: RegIrqLow bit name reset rw 7 IrqEnAc 0 resetsystem rw 6 5 4 3 2 1 0 IrqEnPre1 -IrqEnCntA IrqEnCntC -IrqEnUartTx IrqEnUartRx 0 resetsystem 0 0 resetsystem 0 resetsystem 0 0 resetsystem 0 resetsystem rw r rw rw r rw rw description enable interrupt from acquisition chain (when available) enable interrupt from prescaler (128 Hz) unused enable interrupt from CounterA enable interrupt from CounterC unused enable interrupt from Uart Transmitter enable interrupt from Uart Receiver Table 6.12: RegIrqEnHig Page 55 Preliminary information Table 6.8: Interrupt registers Preliminary information 6 System operating modes XX-XE88LC01/03/05, Data Book bit name reset rw description 7 6 5 4 3 2 1 0 reserved reserved IrqEnPA[5] IrqEnPA[4] IrqEnPre2 IrqEnVld IrqEnPA[1] IrqEnPA[0] 0 resetsystem 0 resetsystem 0 resetsystem 0 resetsystem 0 resetsystem 0 resetsystem 0 resetsystem 0 resetsystem rw rw rw rw rw rw rw rw bit should not be used bit should not be used enable interrupt from Pad PA[5] enable interrupt from Pad PA[4] enable interrupt from prescaler (1 Hz) enable interrupt from Voltage Level Detector enable interrupt from Pad PA[1] enable interrupt from Pad PA[0] Table 6.13: RegIrqEnMid bit name reset rw description 7 6 5 4 3 2 1 0 IrqEnPA[7] IrqEnPA[6] IrqEnCntB IrqEnCntD IrqEnPA[3] IrqEnPA[2] --- 0 resetsystem 0 resetsystem 0 resetsystem 0 resetsystem 0 resetsystem 0 resetsystem 0 0 rw rw rw rw rw rw r r enable interrupt from Pad PA[7] enable interrupt from Pad PA[6] enable interrupt from CounterB enable interrupt from CounterD enable interrupt from Pad PA[3] enable interrupt from Pad PA[2] unused unused Table 6.14: RegIrqEnLow bit name reset rw description 7-0 IrqPriority HFF resetsystem r code of highest priority set interrupt Table 6.15: RegIrqPriority bit name reset rw description 7-3 2 1 0 -IrqHig IrqMid IrqLow 0 0 resetsystem 0 resetsystem 0 resetsystem r r r r unused one (or more) high priority interrupt is set one (or more) middle priority interrupt is set one (or more) low priority interrupt is set Table 6.16: RegIrqIrq bit name reset rw description 7-0 IrqTest 00000000 resetsystem wt for test only Table 6.17: RegIrqTest 6.4 Events 6.4.1 Features The XE8000 support 8 event sources, namely: * * * 2 external inputs from PortA 4 from the internal Counters A,B,C and D 2 from the internal Prescaler (128Hz and 1Hz ) Events are used to restart the CPU after a HALT instruction, without having to handle a complete interrupt cycle. These events display 2 levels of priority. Page 56 XX-XE88LC01/03/05, Data Book 6.4.2 6 System operating modes Overview The events are divided into 2 categories with different priorities. The priorities are fixed and are described below : * * High: counterA, counterC, prescaler 128Hz & pad PA[1] Low: CounterB, CounterD, prescaler 1Hz & pad PA[0] There is an event flag register associated with each priority. The event flag register is RegEvn. The event flag is automatically cleared following system Resets and can be cleared by software. This is achieved by writing the corresponding Flag in the RegEvn register to 1 (the CoolRISC events are active low). For clearing definitively the event, one has to disable the corresponding bit in the CoolRISC status register. For example if a event is generated by the pad 0 of port A: move clrb RegEvn, #0x01 stat,#1 Each Event (EVN) source can be enabled or disabled by software with the help of the Event enable registers RegEvnEn. 6.4.3 PortA events It is possible to use pin PA[0] & PA[1] of PortA as an independent edge triggered EVN input. Bitwise configuration (debounced or non-debounced / falling or rising edge) is performed using reserved registers in portA. The debouncer frequency can be either 256Hz (slow debouncer clock) or 8KHz (fast-debouncer clock). The debounce clock is common for all 8 PortA inputs (and also for the RESET pad). When debounced, the signal on portA has to be stable for one to two periods of selected internal debounce clock to ensure that the new logical value is accepted. 6.4.4 Counters A, B, C and D events Counters generate Events only when they work as normal counters (not when set to PWM). Loop Counters generate events regularly, depending on their mode of operation (up/down counting). It is for the software programmer to handle the processing of events. 6.4.5 Prescaler events Two events are available from the Prescaler, 128Hz and 1Hz. Both are generated by the low 15-stage divider.This means that they can be accurate at 128Hz and 1Hz only when the Xtal 32768 Quartz oscillator is enabled. If the Xtal is not enabled, they are derived from the RC oscillator frequency. The Prescaler can be resynchronized at any time by resetting it. 6.4.6 Event priorities Two registers have been provided to facilitate the writing of software used for handling events, namely : * * RegEvnPriority RegEvnEvn The first, RegEvnPriority, contains the ID-code of the highest activated Priority event. The table below shows these priorities which correspond to organization of event in the registers above and their ID-code. Page 57 Preliminary information The rising edge of the event (EVN) source sets the event flag if it is enabled. Preliminary information 6 System operating modes XX-XE88LC01/03/05, Data Book RegEvnPriority Event priority (on CPU) highest priority event set HFF H07 H06 H05 H04 H03 H02 H01 H00 none EV0 (high) EV0 (high) EV0 (high) EV0 (high) EV1 (low) EV1 (low) EV1 (low) EV1 (low) no event EvnCntA EvnCntC EvnPre1 EvnPA[1] EvnCntB EvnCntD EvnPre2 EvnPA[0] Table 6.18: all events and their priorities After any system Reset the RegEvnPriority value is HFF indicating no event request has been issued subsequent to the Reset. The second, RegEvnEvn, indicates the priority levels of the current events. The two levels of events map directly to those supported by the CoolRISC (EV0 & EV1). For more information, see the documentation about the CoolRISC816 core. register name address (hex) RegEvn RegEvnEn RegEvnPriority RegEvnEvn H003C H003D H003E H003F Table 6.19: Event registers bit name reset rw description 7 6 5 4 3 2 1 0 EvnCntA EvnCntC EvnPre1 EvnPA[1] EvnCntB EvnCntD EvnPre2 EvnPA[0] 0 resetsystem 0 resetsystem 0 resetsystem 0 resetsystem 0 resetsystem 0 resetsystem 0 resetsystem 0 resetsystem rc1 rc1 rc1 rc1 rc1 rc1 rc1 rc1 event from Counter A event from Counter C event from prescaler (128 Hz) event from Pad PA[1] event from Counter B event from Counter D event from prescaler (1 Hz) event from Pad PA[0] Table 6.20: RegEvn bit name reset rw description 7 6 5 4 3 2 1 0 EvnEnCntA EvnEnCntC IrqREnPre1 EvnEnPA[1] EvnEnCntB EvnEnCntD IrqREnPre1 EvnEnPA[0] 0 resetsystem 0 resetsystem 0 resetsystem 0 resetsystem 0 resetsystem 0 resetsystem 0 resetsystem 0 resetsystem rw rw rw rw rw rw rw rw enable event from CounterA enable event from CounterC enable event from prescaler (128 Hz) enable event from Pad PA[1] enable event from CounterB enable event from CounterD enable event from prescaler (1 Hz) enable event from Pad PA[0] Table 6.21: RegEvnEn bit name reset rw description 7-0 EvnPriority HFF resetsystem r code of highest priority set interrupt Table 6.22: RegEvnPriority Page 58 XX-XE88LC01/03/05, Data Book 6 System operating modes bit name reset rw description 7-2 1 0 -EvnHig EvnLow 000000 0 resetsystem 0 resetsystem r r r unused one (or more) high priority event is set one (or more) low priority event is set bit name reset rw description 7-0 EvnTest 00000000 resetsystem wt for test only Table 6.24: RegEvnTest 6.5 Miscellaneous 6.5.1 Port configuration reset Port configuration (pins in input or output mode) is controlled by registers described in the Ports chapters. These registers are initialized by signal ResetPConf that the user can configure as active or inactive during system reset with bit EnResPConf in register RegSysCtrl. The user can also choose if these registers are initialized for each reset or only on power-on reset. BitEnResPConf Port config reset 1 0 reset with any reset source reset with resetcold only (power-on reset) Table 6.25: Port config reset Reset Synchronizer ResetSys PortA datain[6] ck_RegSysMisc EnResPConf ResetPConf resetcold Figure 6.8: Port configuration reset 6.5.2 Prescaler interrupt synchronization Prescaler generates two interrupts at frequencies 128 Hz and 1 Hz. Interrupt signal is generated on negative slope so that 1Hz interrupt is generated one second after prescaler initialization, and then subsequently each second. ck128 Prescaler resetDivXtal irq(Pre0) ck1 Prescaler irq(Pre1) resetDivXtal Figure 6.9: Prescaler interrupt synchronization Page 59 Preliminary information Table 6.23: RegEvnEvn 6 System operating modes 6.6 XX-XE88LC01/03/05, Data Book Digital debouncer A digital debouncer can be used to filter input pins of PortA. Period of the debouncer is set by bit DebFast in register RegSysMisc. 6.6.1 Description Preliminary information At power-on, signal resetcold is activated by power-on reset block. DebFast is initialized at 0 (ckdeb = 4 ms) digital filter is initialized at 0 (not active). Debouncer period can be set to 125 us or 4 ms with bit DebFast. DebFast debouncer period 1 0 125 us 3.9 ms Table 6.26: Debouncer frequency Input signal must be stable during the complete debouncer period to be transmitted. Note: Note: Debouncer clock is taken from the prescaler, and so may vary with actual RC frequency. Debouncer delay varies with the respective phases of the input signal and the debouncer clock. 6.7 System peripheral addresses register addresses RegSysCtrl RegSysReset RegSysClock RegSysMisc RegSysWD RegSysPre0 RegSysPre1 reserved reserved reserved reserved RegSysRCTrim1 RegSysRCTrim2 RegSysVIreg reserved RegSysWarm h0010 h0011 h0012 h0013 h0014 h0015 h0016 h0017 h0018 h0019 h001A h001B h001C h001D h001E h001F Table 6.27: system address ranges Page 60 XX-XE88LC01/03/05, Data Book 7 7 Oscillators Oscillators There are two oscillators: one fast programmable RC oscillator, and a precise crystal oscillator. Registers for controlling the oscillators are described in the SYSTEM chapter. 7.1.1 RC Oscillator RC oscillator principle The RC Oscillator is always turned on at power-on reset and can be turned off after the optional Xtal oscillator has been started. The RC oscillator has two frequency ranges: sub-MHz (100KHz to 1MHz) and above-MHz (1MHz to 10MHz). Inside a range, the frequency can be tuned by software for coarse and fine adjustment. Programmable oscillator 80 kHz 800 kHz range 1 coarse 16 0.6 fine 1.5 Figure 7.1: RC programming principle No external components are required as both the resistor and the capacitor are on chip. The RC oscillator can be in 3 modes. In mode 1(RC on), the RC oscillator and its bias are on. In mode 2 (RC ready), the RC oscillator is off and the bias is on. In mode 3 (RC off), the RC oscillator and the bias are off. RC ready mode is a compromise between power consumption and start-up time. Figure 7.2: RC frequencies programming example for low range (typical values) Page 61 Preliminary information 7.1 7 Oscillators symbol description min typ max unit Fst frequency at start-up 50 80 110 kHz comments range range selection 1 10 multiplies Fst mult[3:0] coarse tuning range 1 16 4 bits, multiplies Fst * range fine tuning range 0.65 tune[5:0] Preliminary information XX-XE88LC01/03/05, Data Book 6 bits, multiplies Fst * range * mult 1.5 fine tuning step 1.4 2 % 30 50 s 50 % bias current is off (RC off) 5 s bias current is on (RC ready) % bias current is on (RC ready) Tst start-up time Ost overshoot at start-up Twu wakeup time Owu overshoot at wakeup jit jitter rms 3 50 2 o bias current is off (RC off) /oo Table 7.1: RC specifications 7.1.2 RC divider cold start During RC oscillator start-up, the coldstart structure masks the first system clock cycles. Two bits EnableRC and ColdRC in register RegSysClock control this coldstart structure. At power-on, resetcold signal initialize EnableRC and ColdRC to 1 (selects RC oscillator). RC oscillator starts and some cycles later bit ColdRC is reset and the clock is made available to the system after one additionnal clock cycle delay. RC oscillator can be stopped by the user by resetting bit EnableRC. In this case, bit ColdRC goes immediately to 1. By setting bit EnableRC, one restarts the RC oscillator. Eight cycles later, bit ColdRC is reset and clock is made available to the system after one additionnal clock cycle delay. When user sets sleep mode, signal Sleep is set together with bits EnableRC and ColdRC. Signal rcPower is masked to maintain oscillator stopped. When coming out of sleep mode, usual start-up happens. RC oscillator starts on Port A event if ResOnPA0 is set in RegSysMisc. Note: Prescaler is initialized by signal BitSleep. Note: RC oscillator bias is set by bit BitBiasRC in RegSysClock. bit name reset rw description 7-6 5 4 3 2 1 0 -EnRCRext RCFreqRange RCFreqCoarse[3] RCFreqCoarse[2] RCFreqCoarse[1] RCFreqCoarse[0] 00 0 resetcold 0 resetcold 0 resetcold 0 resetcold 0 resetcold 0 resetcold r rw rw rw rw rw rw unused enable external resistor for trimming low- / high-frequency RC (0=low) RC frequency coarse trimming bit 3 RC frequency coarse trimming bit 2 RC frequency coarse trimming bit 1 RC frequency coarse trimming bit 0 Table 7.2: RegSysRCTrim1 bit name reset rw description 7-6 5 4 3 2 1 0 -RCFreqFine[5] RCFreqFine[4] RCFreqFine[3] RCFreqFine[2] RCFreqFine[1] RCFreqFine[0] 00 1 resetcold 0 resetcold 0 resetcold 0 resetcold 0 resetcold 0 resetcold r rw rw rw rw rw rw unused RC frequency fine trimming bit 5 RC frequency fine trimming bit 4 RC frequency fine trimming bit 3 RC frequency fine trimming bit 2 RC frequency fine trimming bit 1 RC frequency fine trimming bit 0 Table 7.3: RegSysRCTrim2 Page 62 XX-XE88LC01/03/05, Data Book 7.2 7 Oscillators Xtal Oscillator 7.2.1 General description The Xtal Oscillator operates with an external crystal of 32'768 Hz. description nominal frequency oscillator start-up time duty cycle on the digital output relative frequency deviation from nominal, for a crystal with CL=8.2 pF and temperature between -40 and +85C fstab_1 min typ 30 32768 1 50 -100 max unit 2 70 Hz s % +300 ppm comments not included: crystal frequency tolerance and aging crystal frequency - temperature dependence Table 7.4: Xtal oscillator specifications. Note: Board layout recommendations for safer crystal oscillation and lower current consumption: * Keep lines xtal_in and xtal_out short and insert a VSS line between them. * Connect package of the crystal to VSS. * No noisy or digital lines near xtal_in and xtal_out. * Insert guards at VSS where needed. 7.2.2 Typical external component The crystal oscillator needs a 32'768 Hz crystal with specifications as in Table 7.5 (normal watch crystal). Attention has to be made when designing the board, especially to the parameters given in Table 7.6. symbol description Fs CL Rm Cm C0 Q Resonance frequency CL for nominal frequency motional resistance motional capacitance shunt capacitance quality factor min typ 1.8 0.7 40k 32768 8.2 40 2.5 1.1 80k max unit 100 3.2 2.0 400k Hz pF k fF pF - comments Table 7.5: External crystal specifications. 32 kHz Xtal outside these specifications will must probably delivers correct frequency, but some precision specifications will be released. symbol description external board parasitic rh_xin resistance xtal_in - VSS external board parasitic rh_xout resistance xtal_out - VSS external board parasitic rh_xin_xout resistance xtal_in - xtal_out external board parasitic cp_xin capacitance on xtal_in - VSS external board parasitic cp_xout capacitance on xtal_out - VSS external board parasitic cp_xin-xout capacitance xtal_in - xtal_out min typ max unit 10 M 10 M 50 M 0.5 3.0 pF 0.5 3.0 pF 0.2 1.0 pF Table 7.6: Board design specifications 7.2.3 Xtal divider cold start During Xtal oscillator start-up, a cold start structure masks the first 32768 clock cycles. The two bits EnableXtal and BitColdXtal in register RegSysClock control this structure. 7.2.4 Description At power-on, signal resetcold resets EnableXtal and sets ColdXtal (Xtal oscillator is not selected at start-up). Page 63 Preliminary information symbol f_clk32k st_x32k duty_clk32k 7 Oscillators XX-XE88LC01/03/05, Data Book Xtal oscillator can be started by the user by setting EnableXtal. Bit EnExtClk should be reset first to disable external clock detection. If an external clock is already detected, Xtal oscillator can not be started anymore (blocked by ExtClk). When Xtal oscillator starts, bit ColdXtal is reset after 32768 cycles and clock is made available to the system. Xtal oscillator can be stopped by user by resetting bit EnableXtal. In this case, bit ColdXtal is immediately set. Preliminary information When the user chooses sleep mode, signal Sleep going to 1 resets EnableXtal and sets ColdXtal. When going out of sleep mode the oscillator is stopped until being started by the user. Note: Prescaler is initialised by signal Sleep. 7.3 External clock An external clock can be provided by the user instead of the Xtal oscillator. The clock is input through the pin OSCIN. If the external clock is present, it is detected after 4 cycles (ExtClk set) and the Xtal oscillator is disabled (not possible to set EnableXtal). Note: After power-up, the external clock detection is disabled (EnExtClk is off). If the user wants to use the external oscillator, the bit EnExtClk has to be set to 1. ExtClk can be reset by power-on reset only. 7.4 Oscillators control Note: Both RC and Xtal oscillators can be controlled by changing the states of selected bits with RegSysClock. After power-on reset, only the RC oscillator is running. 7.4.1 CPU clock As there are three different clock sources available for the CPU clock, it is possible to select one of them. The RC clock is always selected after power-up or after Sleep mode. The CPU clock selection is done with the bit CpuSel in RegSysClock (0=RC clock, 1 = Xtal clock or external clock). Note: If a clock is selected but its oscillator is in cold start phase, the CPU clock is stopped during that time. Note: Switching from RC clock to Xtal clock and stopping the RC must be performed using 2 MOVE instructions to RegSysClock. First select the Xtal clock and then stop the RC. When switching form Xtal to RC clock, first select the RC clock and then stop the Xtal. Note: If only one clock is active (RC or Xtal), that clock is selected per default. At power-on, or when going to sleep mode, signal resetsleep (resetcold OR BitSleep) resets CpuSel, RC oscillator is chosen. CpuSel ColdRC ColdXtal BitExtClk sel ckcpu X 0 1 0 0 1 1 1 0 0 1 1 X X 1 X 1 0 1 0 1 0 X 0 X 1 X 1 0 0 0 1 1 1 1 0 ckRC ckRC ckXtal extClk ckXtal extClk Table 7.7: CPU clock selection Page 64 XX-XE88LC01/03/05, Data Book 7 Oscillators Selection of clock is made without glitches thanks to a specific block (see Figure 7.3). Note: crRC ckXtal sel Figure 7.3: CPU clock selection 7.4.2 * * * * * Oscillator register BiasRC ColdXtal ColdRC EnableXtal EnableRC enables the RC oscillator bias current for a fast start-up this bit is set during the cold start of the Xtal oscillator. The delay is 32'768 clock cycles this bit is set during the cold start of the RC oscillator. The delay is 8 clock cycles enables the Xtal oscillator. This bit is set after power-on. enables the RC oscillator bit name reset rw description 7 6 5 4 3 2 CpuSel ExtClk EnExtClk BiasRC ColdXtal ColdRC 0 resetsleep 0 resetcold 0 resetcold 1 resetcold 1 resetsleep 1 resetsleep rw r rw rw r r 1 EnableXtal 0 resetsleep rw 0 EnableRC 1 resetsleep rw CkCpu selection (0=RC) external clock detected enable Oscin to be driven from ext. enable RC bias when EnableRC = 0 Xtal in starting phase for 32768 cycles RC in starting phase for 8 cycles enable Xtal oscillator (cannot be set if EnExtClk=1 or ExtClk=1) enable RC oscillator Table 7.8: RegSysClock, address h0012 Note: If the ExtClk bit is one, then the EnExtClk bit must not be set to 0. 7.5 Prescaler The prescaler is a divider chain providing frequencies down to 1Hz based on the RC oscillator or based on the Xtal oscillator. Two registers RegSysPre0 and RegSysPre1 control the prescaler. The prescaler is made of one asynchronous 8 stage divider and one asynchronous 15 stage divider, all chained, and of one initialization structure. 7.5.1 * * * * * * * Features basic 15 stage divider in case of 32768Hz -> 1Hz low 15 stages can be reset with a reset prescaler command all 15 divided clocks are outputs which can be used in other blocks like timer/counter, debouncer, EOL logic, Oscillation detector, WD, used outputs from 15 stage dividers are 32kHz, 1024Hz, 256Hz, 128Hz, 1Hz RC oscillator itself has a divider by 32 to accept 1MHz clock and output for other peripherals 1MHz, 250 kHz and 31 kHz clocks Prescaler as divider chain and clock selector can be tested separately. (this means independent of other blocks) with test register we can read state of the divider chain after each 4 dividers, (after 2 dividers for hi-frequency RC clock) Prescaler has a Reset input to reset the whole divider chain. This can be the sum of POR and Reset pad Page 65 Preliminary information ckcpu 7 Oscillators 7.5.2 XX-XE88LC01/03/05, Data Book Description The 8 stages divider is directly connected to the RC oscillator. The 15 stages dividers is clocked by the Xtal oscillator when it is on, or by a frequency near to 32 kHz taken from the first divider based on the RC oscillator trimming. See examples below (Figure 7.4, Table 7.9). Additionnal circuitry, not shown on the figure, prevents unwanted transitions on ck32k when switching the RC oscillator frequency. ck16 ck8 ck4 ck2 ck1 divider 8 stages ckRC ck512 ck256 ck128 ck64 ck32 RC oscillator ck16k ck8k ck4k ck2k ck1k ck32k Preliminary information ck500k ck250k ck125k ck62k RCTrimm + glue divider 5 stages divider 5 stages divider 5 stages 0 1 WD ckXtal Xtal oscillator resetDivRC resetDivXtal ClearPre ColdXtal Sleep prescaler synchronise and control EnableXtal resetcold Figure 7.4: prescaler principle freq name coarse (3:0) fine (5:0) ckRC ck500k ck250k ck125k ck62k ckXtal ck64k to ck32k divider ck32k ck16k ck8k ck4k ck2k ck1k ck512 ck256 ck128 ck64 ck32 ck16 ck8 ck4 ck2 ck1 watchdog clocks 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -- RC@4MHz, Xtal off 0100b 100001b 4'000'000 2'000'000 1'000'000 500'000 250'000 OFF RC@2.5MHz, Xtal off RC@1MHz, Xtal off 2'457'600 1'228'800 614'400 307'200 153'600 OFF 1'040'000 520'000 260'000 130'000 65'000 OFF RC@1MHz, Xtal on RC off, Xtal on 1'040'000 520'000 260'000 130'000 65'000 32'768 N/A N/A OFF OFF OFF OFF OFF 32'768 8 4 2 N/A N/A 31'250 15'625 7813 3'906 1'953 977 488 244 122 61 31 15.3 7.63 3.81 1.91 0.95 4.19 seconds 38'400 19'200 9600 4800 2400 1200 600 300 150 75 37.5 18.8 9.38 4.69 2.34 1.17 3.41 seconds 32'500 16'250 8125 4062 2031 1016 508 254 127 63.5 31.7 15.9 7.93 3.97 1.98 0.992 4.03 seconds 32'768 16'384 8192 4096 2048 1024 512 256 128 64 32 16 8 4 2 1 4 seconds 32'768 16'384 8192 4096 2048 1024 512 256 128 64 32 16 8 4 2 1 4 seconds Table 7.9: frequency examples, typical values for RC setting, range is set to 1 Signal resetcold initializes all dividers at power-on. The 8-bits divider and the remaining 5-bits dividers use different initialization signals. The 3 low frequency dividers can be reset simultaneously by writing bXXXXXXX1 in register RegSysPre0. These dividers are also initialized at Page 66 XX-XE88LC01/03/05, Data Book 7 Oscillators Note: Dividers are initialised in mode `Sleep'. Note: Low frequency part of prescaler is not initialised by the reset Synchronizer (ClearPre) when Xtal oscillator is in coldstart so that the coldstart delay is not disturbed. Note: Low frequency part of prescaler is always set after the high frequency part (connected to RC) when external clock is selected. RC Trimming EnXtal 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RC frequency RegSysRC- RegSysRC- RegSysRCRange Coarse Trim2 = 00 Trim2 = 20 Trim2 = 3F X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 XXXX 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0000 0001 0010 0011 0100 0101 0110 X 56560 113120 169680 226240 282800 339360 395920 452480 509040 565600 622160 678720 735280 791840 848400 904960 565600 1131200 1696800 2262400 2828000 3393600 3959200 X 80000 160000 240000 320000 400000 480000 560000 640000 720000 800000 880000 960000 1040000 1120000 1200000 1280000 800000 1600000 2400000 3200000 4000000 4800000 5600000 X 112800 225600 338400 451200 564000 676800 789600 902400 1015200 1128000 1240800 1353600 1466400 1579200 1692000 1804800 1128000 2256000 3384000 4512000 5640000 6768000 7896000 division factor X 2 4 8 8 16 16 16 16 16 32 32 32 32 32 32 32 32 64 64 128 128 128 128 Low Prescaler input freq RegSysRC- RegSysRC- RegSysRCTrim2 = 00 Trim2 = 20 Trim2 = 3F 28280 28280 21210 28280 17675 21210 24745 28280 31815 17675 19443 21210 22978 24745 26513 28280 17675 17675 26513 17675 22094 26513 30931 32768 40000 40000 30000 40000 25000 30000 35000 40000 45000 25000 27500 30000 32500 35000 37500 40000 25000 25000 37500 25000 31250 37500 43750 56400 56400 42300 56400 35250 42300 49350 56400 63450 35250 38775 42300 45825 49350 52875 56400 35250 35250 52875 35250 44063 52875 61688 Table 7.10: automatic input frequency selection, typical values. Values in italic are not allowed and may result in unpredictable CPU behaviour. Note: UNLESS ck32k IS TAKEN FROM THE Xtal OSCILLATOR, ITS FREQUENCY CAN SIGNIFICANTLY DIFFER FROM ITS NOMINAL VALUE. 7.5.3 Registers The RegSysPre0 controls some of the prescaler functions. The bits within the registers define the following: * * internal CPU clock in internal test mode only When 1 is written at this address only the low 15 stage "Xtal" divider is reset to 0. This reset takes one Xtal clock period CpuClk ResPre bit name reset rw description 7-2 1 0 -CpuClk ResPre 000000 0 0 resetcold r r w unused CpuClk in test mode reset the Xtal Prescaler when written to 1 Table 7.11: RegSysPre0 Page 67 Preliminary information Xtal oscillator start (writing bXXXXXXX1X in register RegSysClock). Initialization signal is synchronized to the low frequency clock in order to ensure correct divider initialization. Preliminary information 7 Oscillators Page 68 XX-XE88LC01/03/05, Data Book XX-XE88LC01/03/05, Data Book Parallel IO ports 8.1 Port A 8.1.1 * * * * * * * * Features input port, 8 bits wide RegPAin read the input status after the debouncer option each bit can be set individually for debounced or direct input each bit can be set individually for pullup or not each bit is an interrupt request source and can be set on rising or falling edge a system reset can be generated on a port configuration, each bit as direct input, inverted input, zero or one PA[0] and PA[1] can generate two events for the cpu, individually maskable PA[0] to PA[3] can be used as clock inputs for the counters 8.1.2 Overview Port A is a general purpose 8 bit wide input port, with interrupt capability. It can be debounced or not. internal bus Internal Pull-Up resistors can be connected to its inputs. It can be used to connect external clock sources for the internal counters (also event counter capability). Rising or falling edge for interrupt generation can be selected, PA[0] and PA[1] can generate events for the CPU. Port A RegPAPullup p_in[7:0] RegPADebounce Debounce 8x 1 RegPAIn 0 RegPATest RegPAEdge 1 0 8x 1 resetPA 8 8 4 8 interrupts 11 10 8 RegPARes0 8 01 0 00 RegPARes1 8 Figure 8.1: Port A 8.1.3 Port A configuration The PortA input status can be read from RegPAin. Each bit of PortA can be set individually to be a debounced or a direct input using register RegPADebounce (Input is debounced if 1 is written in). Following reset, this register is 0. Page 69 Preliminary information 8 8 Parallel IO ports 8 Parallel IO ports XX-XE88LC01/03/05, Data Book Depending on the status of an EnResPConf bit in RegSysCtrl, RegPADebounce can be reset by any of the possible system resets or only with power-on reset (POR). Note: Each PortA input is an interrupt request source and can be set on rising or falling edge with a RegPAEdge. Following reset, the rising edge is selected for Interrupt generation by default. Care must be taken when modifying RegPAEdge because this register performs a selection, the dynamic result of which may be interpreted incorrectly as a transition. It is therefore better to remove the corresponding PortA IrqMask in RegIrqEnMid and RegIrqEnLow when changing RegPAEdge. Interrupt flag is set only when its corresponding IrqMask bit is set to 1. Preliminary information Note: Each bit can be set individually for pullup or not using Register RegPAPullup. Input is Pulled-Up when its corresponding bit in this register is set to 1. Default status after reset is 0 what means no Pull_Up. Depending on the status of an EnResPConf bit in RegSysCtrl, RegPAEdge can be reset by any of the possible system resets or only with PowerOnReset (POR). See Table 8.1. Note: PortA can be used to generate a system reset by placing a predetermined word on PortA externally. The precise code that will cause a system reset can be set with the aid of table 8.1. PARes1[x] PARes0[x] PARes[x] 1 1 0 0 1 0 1 0 1 NOT PA[x] PA[x] 0 Table 8.1: reset selection for each pin Two registers RegPARes0 and RegPARes1 (bit as direct input, inverted input, zero or one) can select one of four possibilities shown in this table. The Logical AND combination of all 8 input lines with their selection (shown in the column PARes[x]) can give a resetportA as one of system reset sources. resetportA = PARes[7] AND PARes[6] AND PARes[5] AND ... AND PARes[0] Note: a reset via Port A can be inhibited by placing a 0 on both PARes1[x] and PARes0[x] (for a particular x). PA[0] to PA[3] can be used as clock input for the counters, A, B, C & D respectively. In this case counters can be used as event counters of PA[0]..PA[3]. PortA input external clock for counter PA[0] PA[1] PA[2] PA[3] CounterA CounterB CounterC CounterD Table 8.2: clock inputs for counters Counter inputs can be debounced or not, depending on RegPADebounce. Additionally, the counting edge (falling or Rising) can be selected using RegPAEdge. input ckdeb 1 1 1 1 2 1 debounced Figure 8.2: digital debouncer Page 70 2 XX-XE88LC01/03/05, Data Book 8.1.4 8 Parallel IO ports PortA registers register name address (hex) RegPAIn RegPADebounce RegPAEdge RegPAPullup RegPARes0 RegPARes1 RegPATest H0020 H0021 H0022 H0023 H0024 H0025 H0027 bit name reset rw description 7-0 PAIn[7-0] xxxxxxxx r pad PA[7-0] input status Preliminary information Table 8.3: Port A registers Table 8.4: Register RegPAIn bit 7-0 name reset PADeb[7] 00000000 resetpconf rw description rw debounce for PA[7-0] (1=debounce) Table 8.5: Register RegPADebounce bit 7-0 name reset PAEdge[7-0] 00000000 resetsystem rw description rw edge selection for IrqPA[7-0] (0=rise) Table 8.6: Register RegPAEdge bit 7-0 name reset rw description PAPullup[7-0] 00000000 resetpconf rw pullup for pad PA[7-0] (1=active) rw description Table 8.7: Register RegPAPullup bit 7-0 name reset PARes0[7-0] 00000000 resetsynch rw reset selection bit 0 for pad PA[7-0] Table 8.8: RegPARes0 bit name reset 7-0 PARes1[7-0] 0 resetsynch rw description rw reset selection bit 1 for pad PA[7-0] Table 8.9: RegPARes1 bit name reset rw description 7-4 3 2 1 0 -PATest[3] PATest[2] PATest[1] PATest[0] 0000 0 resetsystem 0 resetsystem 0 resetsystem 0 resetsystem r r rw rw rw unused resetportA PATest = Irqbus in test mode 8 bits of Irqbus in test mode Irqbus = 8 x PATest1 in test mode Table 8.10: RegPATest Page 71 8 Parallel IO ports 8.2 XX-XE88LC01/03/05, Data Book Port B Port B 4 vdd internal bus PortB internal analog bus Preliminary information RegPBAna 4 RegPBPullup RegPBOpen 8 8 1 p_out[7:0] 0 RegPBOut p_enable[7:0] RegPBDir p_in[7:0] RegPBIn 8 8 8 Figure 8.3: Port B 8.2.1 * * * * * * * * * * * Features input / output / analog port, 8 bits wide each bit can be set individually for input or output each bit can be set individually for open-drain or push-pull each bit can be set individually for pullup or not four pairs of pads which can be connected individually to four internal analog lines (4 line analog bus) pullup is not active when corresponding pad is set to zero two PWM can be output on pads PB[0] and PB[1] two internal freq (Xtal and cpu) can be output on PB[2] and PB[3] the synchronous serial interface uses pads PB[5], PB[4] and PB[3] for SIN, SCL and SOU PB[0] is used in test mode for cpu test output the UART interface uses pads PB[6] and PB[7] for Tx and Rx 8.2.2 Overview PortB is a multi-purpose 8 bit Input/output port. In addition to digital behaviour, all pins can be used for analog signals. Each port terminal can be individually selected as digital input or output or in pairs as analog for sharing one of four possible analog lines. 8.2.3 Port B digital capabilities When used as logic outputs, each can be individually set as an N-channel open-drain or a push-pull (conventional) output. Each pin can be individually set to use internal pull-ups. Page 72 XX-XE88LC01/03/05, Data Book 8 Parallel IO ports Data is stored in RegPBOut prior to output at PortB.This occurs provided that PBDir[x] has been set high (1), accordingly. Its default following reset is low (0). The direction of each bit within PortB (input or output) can be individually set using the RegPBDir register. If PBDir[x] = 1, the corresponding PortB pin becomes an output. Following reset PortB is in input mode (PBDir[x] are reset to 0). When a pin is in output mode (its PBDir[x] is set to 1), the output can be conventional CMOS (Push-Pull) or N-channel Open-drain. driving the output only Low. By default, after POR the PBOpen[x] in RegPBOpen is cleared to 0 (push-pull). If PBOpen[x] in RegPBOpen is set to 1 then the internal P transistor in the output buffer is electrically removed and the output can only be driven low. When the output should be high the pin becomes high Impedance. The internal pull-up or external pull-up resistor can be used to drive to pin high if required. Note: Because the P transistor actually exists (this not a real Open-drain output) the pull-up range is limited to avoid forward bias the P transistor / diode (VDD + 0.2V). Each bit can be set individually for pullup or not using Register RegPBPullup. Input is Pulled-Up when its corresponding bit in this register is set to 1. Default status after reset is 0 which means no Pull_Up. To conserve power, pull-ups are only enabled when the associated pin is either a digital input or on an N-channel open-drain output. When the counters are used to implement a PWM function, the PB[0] and PB[1] terminals are declared as outputs and override other values written in RegPBout. PBDir(0) and PBDir(1) must be set to 1. If OutputCkXtal is set in RegSysMisc the Xtal frequency is output on PB[3]. This overrides the value contained in RegPBOut. Similarly, if OutputCkCpu is set in RegSysMisc, the CPU frequency is output on PB[2]. This overrides the value contained in RegPBOut. PBDir(2) and PBDir(3) must be set to 1. Pins PB[5] and PB[4] can be used for Serial Data (SIN) and Serial Clock (SCL) when the EnableUSRT bit is set in USRTctrl. When EnableUSRT is set the PB[5] and PB[4] bidirectional become open-drain (RegPBopen is not changed). If there is no external Pull-Up resistor on these pins, this must be set to be pull-ups in RegPBPullup. When used as output and in synchronous serial mode, outputs take the value of USRTSIN and USRTScl bits from their respective registers RegUSRTSIN and RegUSRTSCL. When EnTx in RegUartCtrl is set, PB[6] is output signal Tx. When EnRx in RegUartCtrl is set, PB[7] is input signal Rx. Port B name PB[7] PB[6] PB[5] PB[4] PB[3] PB[2] PB[1] PB[0] high utilisation (priority) medium analog usart Rx usart Tx analog synchronous serial analog analog clock 32KHz clock CPU PWM1 Counter C (C+D) PWM0 Counter A (A+B) low I/O I/O I/O I/O I/O I/O I/O I/O Table 8.11: different PortB functions Page 73 Preliminary information The status of PortB is available in RegPBIn (read only). Reading is always direct - there is no debounce function associated with PortB. In case of possible noise on input signals, a software debouncer with pooling must be realized. 8 Parallel IO ports 8.2.4 XX-XE88LC01/03/05, Data Book Port B analog capability PortB terminals can be attached to 4 line analog bus in pairs by setting the PBAna[x] bits in RegPBAna register. With other registers we can program sharing of this 4 analog lines between different pads of PortB. This can be used to implement simple LCD driver or A/D converters. Analog switching is available only when the circuit is powered with sufficient voltage. Preliminary information When PBAna[x] is set to 1, changing one pair of the PortB terminals from digital I/O mode to analog, the corresponding RegPBPullup, RegPBOut and RegPBdir change their functions. Example: When PBAna[0] is set to 1 then the interpretation of two LSBs (bit0 and Bit1) in RegPBOut and RegPBdir change. PB[0] and PB[1] become analog pins. The other PortB pins (PB[7]..PB[2]) stay digital. The selection is performed with RegPBout and RegPBDir. The analog line to which the appropriate signal is connected is determined by the codes placed on RegPBout and RegPBDir according to the following table. Selection bits from PB[x] selection on RegPBDir or RegPBou 0 0 1 1 0 1 0 1 analog line 0 analog line 1 analog line 2 analog line 3 Table 8.12: selection for analog lines with RegPBDir (pads B0, B2, B4 and B6) or RegPBout (pads B1, B3, B5 and B7) In the context of the example where PBAna[0] is set to 1: to connect PB[0] to analog line 3 and PB[1] to analog line 2 would require that f(RegPBDir[1], RegPBDir[0]) = (1,1) and that f(RegPBOut[1], RegPBOut[0]) = (1,0). RegPBTest is used for internal test purposes.It can not be influenced by user outside test mode. In normal mode it is always read as 0. Note: Depending on the status of an EnResPConf bit in RegSysCtrl, some registers can be reset by any of the possible system resets or only with PowerOnReset (POR). register name address (hex) RegPBOut RegPBIn RegPBDir RegPBOpen RegPBPullup RegPBAna H0028 H0029 H002A H002B H002C H002D H002E H002F reserved Table 8.13: Port B registers bit name reset rw description 7-0 PBIn[7-0] x r pad PB[7-0] input status Table 8.14: RegPBIn bit name reset rw description 7-0 PBOpen[7-0] 0 resetpconf rw pad PB[7-0] opendrain (1=opendrain) Table 8.15: RegPBOpen Page 74 XX-XE88LC01/03/05, Data Book 8 Parallel IO ports bit name reset rw description 7-4 3 2 1 0 -PBAna[3] PBAna[2] PBAna[1] PBAna[0] 0000 0 resetpconf 0 resetpconf 0 resetpconf 0 resetpconf r rw rw rw rw used set PB[7] and PB[6] in analog mode set PB[5] and PB[4] in analog mode set PB[3] and PB[2] in analog mode set PB[1] and PB[0] in analog mode bit name reset rw description in digital mode descriptionin analog mode 7-0 PBPullup[7-0] 0 resetpconf rw pullup for pad PB[7-0] (1=active) connect pad PB[7-0] on selected ana bus Table 8.17: RegPBPullup bit name reset rw description in digital mode description in analog mode 7 6 5 4 3 2 1 0 PBOut[7] PBOut[6] PBOut[5] PBOut[4] PBOut[3] PBOut[2] PBOut[1] PBOut[0] 0 resetpconf 0 resetpconf 0 resetpconf 0 resetpconf 0 resetpconf 0 resetpconf 0 resetpconf 0 resetpconf rw rw rw rw rw rw rw rw pad PB[7] output value pad PB[6] output value pad PB[5] output value pad PB[4] output value pad PB[3] output value pad PB[2] output value pad PB[1] output value pad PB[0] output value analog bus selection bit 1 for pad PB[7] analog bus selection bit 0 for pad PB[7] analog bus selection bit 1 for pad PB[5] analog bus selection bit 0 for pad PB[5] analog bus selection bit 1 for pad PB[3] analog bus selection bit 0 for pad PB[3] analog bus selection bit 1 for pad PB[1] analog bus selection bit 0 for pad PB[1] Table 8.18: RegPBOut bit name reset rw description in digital mode description in analog mode 7 6 5 4 3 2 1 0 PBDir[7] PBDir[6] PBDir[5] PBDir[4] PBDir[3] PBDir[2] PBDir[1] PBDir[0] 0 resetpconf 0 resetpconf 0 resetpconf 0 resetpconf 0 resetpconf 0 resetpconf 0 resetpconf 0 resetpconf rw rw rw rw rw rw rw rw pad PB[7] direction (0=input) pad PB[6] direction (0=input) pad PB[5] direction (0=input) pad PB[4] direction (0=input) pad PB[3] direction (0=input) pad PB[2] direction (0=input) pad PB[1] direction (0=input) pad PB[0] direction (0=input) analog bus selection bit 1 for pad PB[6] analog bus selection bit 0 for pad PB[6] analog bus selection bit 1 for pad PB[4] analog bus selection bit 0 for pad PB[4] analog bus selection bit 1 for pad PB[2] analog bus selection bit 0 for pad PB[2] analog bus selection bit 1 for pad PB[0] analog bus selection bit 0 for pad PB[0] Table 8.19: RegPBDir 8.3 8.3.1 * * * Port C Features input / output port, 8 bits wide each bit can be set individually for input or output push-pull output only 8.3.2 Overview PortC is a general purpose 8 bit Input/output port. Data is stored in RegPCOut prior to output at PortC. This occurs provided that PCDir[x] has been set high (1), accordingly. Its default following reset is low (0). The status of PortC is available in RegPCIn (read only). Reading is always direct - there is no digital debounce function associated with PortC. In case of possible noise of input signals, a software debouncer with pooling must be realized. Page 75 Preliminary information Table 8.16: RegPBAna 8 Parallel IO ports XX-XE88LC01/03/05, Data Book The direction of each bit within PortC (input or output) can be individually set using the RegPCDir register. If PCDir[x] = 1, the corresponding PortC pin becomes an output. Following reset PortC is in input mode (PCDir[x] are reset to 0). Depending on the status of an EnResPConf bit in RegSysCtrl, this register can be reset by any of the possible system resets or only with PowerOnReset (POR). See table Table 8.1. internal bus Preliminary information Note: Port C p_out[7:0] RegPCOut p_enable[7:0] RegPCDir p_in[7:0] RegPCIn 8 8 8 Figure 8.4: Port C register name address (hex) RegPCOut RegPCIn RegPCDir reserved H0030 H0031 H0032 H0033 Table 8.20: Port C registers bit name reset rw description 7 6 5 4 3 2 1 0 PCOut[7] PCOut[6] PCOut[5] PCOut[4] PCOut[3] PCOut[2] PCOut[1] PCOut[0] 0 resetpconf 0 resetpconf 0 resetpconf 0 resetpconf 0 resetpconf 0 resetpconf 0 resetpconf 0 resetpconf rw rw rw rw rw rw rw rw pad PC[7] output value pad PC[6] output value pad PC[5] output value pad PC[4] output value pad PC[3] output value pad PC[2] output value pad PC[1] output value pad PC[0] output value Table 8.21: RegPCOut bit name reset rw description 7 6 5 4 3 2 1 PCIn[7] PCIn[6] PCIn[5] PCIn[4] PCIn[3] PCIn[2] PCIn[1] x x x x x x x r r r r r r r pad PC[7] input status pad PC[6] input status pad PC[5] input status pad PC[4] input status pad PC[3] input status pad PC[2] input status pad PC[1] input status Table 8.22: RegPCIn Page 76 XX-XE88LC01/03/05, Data Book 8 Parallel IO ports bit name reset rw description 0 PCIn[0] x r pad PC[0] input status bit name reset rw description 7 6 5 4 3 2 1 0 PCDir[7] PCDir[6] PCDir[5] PCDir[4] PCDir[3] PCDir[2] PCDir[1] PCDir[0] 0 resetpconf 0 resetpconf 0 resetpconf 0 resetpconf 0 resetpconf 0 resetpconf 0 resetpconf 0 resetpconf rw rw rw rw rw rw rw rw pad PC[7] direction (0=input) pad PC[6] direction (0=input) pad PC[5] direction (0=input) pad PC[4] direction (0=input) pad PC[3] direction (0=input) pad PC[2] direction (0=input) pad PC[1] direction (0=input) pad PC[0] direction (0=input) Table 8.23: RegPCDir 8.3.3 Port D Is identical to port C. Page 77 Preliminary information Table 8.22: RegPCIn Preliminary information 8 Parallel IO ports Page 78 XX-XE88LC01/03/05, Data Book XX-XE88LC01/03/05, Data Book 9 Universal Asynchronous Receiver/Transmitter (UART) Features Full duplex operation with buffered receiver and transmitter. Internal baudrate generator with 8 programmable baudrate (300 - 38400). 7 or 8 bits word length. Even, odd, or no-parity bit generation and detection 1 stop bit error receive detection : Start, Parity, Frame and Overrun Receiver echo mode 2 interrupts (receive full and transmit empty) Enable receive and/or transmit invert pad Rx and/or Tx 9.2 Overview The Uart hardware is tied to PB[7] which is used as Rx - receive and PB[6] as Tx - transmit. 9.3 Uart Prescaler In order to have correct baudrates, the Uart interface has to fed with a stable and trimmed clock source. It can be issued by the Xtal oscillator or by the RC oscillator (bit SelXtal in RegUartCmd). The following RC frequencies are suitable for correct Uart protocols. rc freq [Hz] 9'830'400 4'915'200 2'457'600 1'228'800 614'400 Table 9.1: RC frequencies for Uart The internal prescaler of the Uart has to be set according to the RC frequency : UartRcSel[2:0] prescaler division rc freq [Hz] 111 110 101 100 011 010 001 000 reserved reserved reserved : 16 :8 :4 :2 no division 9'830'400 4'915'200 2'457'600 1'228'800 614'400 Table 9.2: uart internal prescaler Note: the bit UartRcSel[2:0] in RegUartCmd only sets the internal prescaler of the Uart. It has no influence on the RC oscillator trimming or on the CPU prescaler. 9.4 Function description The bit UartTxFull in RegUartTxSta goes to 0 when the uart transfers data from the RegUartTx register to the transmitter shift register, and goes to 1 when the processor writes new data onto the RegUartTx. An interrupt is generated when there is a falling edge of the UartTxFull bit. Page 79 Preliminary information 9.1 * * * * * * * * * * 9 Universal Asynchronous Receiver/Transmitter (UART) 9 Universal Asynchronous Receiver/Transmitter (UART) XX-XE88LC01/03/05, Data Book The bit UartTxBusy in RegUartTxSta shows that the transmitter has transmitted data. The bit UartRxFull in RegUartRxSta goes to 1 when the uart transfers data from the receiver shift register to RegUartRx, and goes to a 0 when the processor reads the RegUartRx. An interrupt is generated when there is a rising edge of the UartRxFull bit. Preliminary information The bit UartRxBusy in RegUartRxSta shows that the receiver has received data. The bit UartRxSErr in RegUartRxSta shows that a start error has been detected. The bit UartRxPErr in RegUartRxSta shows that a parity error has been detected. The received parity is not equal to the calculated parity with the received data. The bit UartRxFErr in RegUartRxSta shows that a frame error has been detected. There is no stop bit. The bit UartRxOErr in RegUartRxSta shows that an overrun error has been detected. The reception buffer is not empty when a new data is received. This bit is cleared by all reset conditions and by writing any data to its address. The bit UartEcho in RegUartCtrl is used to return the Rx signal on the Tx signal. Tx = Rx XOR UartXRx XOR UartXTx. UartEnRx (register RegUartCtrl bit 6) must be zero if the reception of data in echo mode is not wanted. The bits UartEnRx and UartEnTx in RegUartCtrl are used to enable or disable the reception and transmission. The bits UartXRx and UartXTx in RegUartCtrl are used to enable or disable the reversal on the Rx and Tx signal. The bits UartBR in RegUartCtrl are used to select the internal baudrate. The RegUartCmd register is used to select the word length (7-8 data bit) UartWL, the enable or disable parity UartPE and the parity mode (odd or even) UartPM. 9.5 Interrupt or polling There are two possibilities for transmit or receive a message. First by interrupt, when the RegUartRx is full an interrupt is generated, the UartRx register must be read. And when the RegUartTx is empty an interrupt is generated too, the UartTx register can be load. Second by polling, reading and checking the UartRxFull bit and when it is at 1 the RegUartRx register must be read. Also, reading and checking the UartTxdFull bit and when it is 0 the RegUartTx register can be load. 9.6 Software hints Example of programme for a transmission with polling: 1. The RegUartCmd register and the RegUartCtrl register are initialized (for example: 8 bit WordLen, Odd Parity, 9600 baud, enable Uart Transmission). 2. Write a byte in RegUartTx. 3. Wait on the UartTxFull bit in RegUartTxSta register equal 0. 4. jump to 2 for writing the next byte if the message is not finished. 5. End of transmission. Example of program for a transmission with interrupt: 1. The RegUartCmd register and the RegUartCtrl register are initialized (for example: 8 bit WordLen, Odd Parity, 9600 baud, enable Uart Transmission). 2. Write a byte in RegUartTx. 3. When there is an interrupt, if the message is not finished then write the next byte in RegUartTx else End of transmission. Example of program for a reception with polling: 1. The RegUartCmd register and the RegUartCtrl register are initialized (for example: 8 bit WordLen, Odd Par- Page 80 XX-XE88LC01/03/05, Data Book ity, 9600 baud, enable Uart Reception). Wait on the UartRxFull bit in RegUartRxSta register equal 1. Reading the RegUartRxSta and checking if there is no error. Read data in RegUartRx. If data is not equal at End-Of-Line then jump to 5. End of reception. Example of program for a reception with interrupt: 1. The RegUartCmd register and the RegUartCtrl register are initialized (for example: 8 bit WordLen, Odd Parity, 9600 baud, enable Uart Reception). 2. When there is an interrupt jump to 3 3. Reading the RegUartRxSta and checking if there is no error. 4. Read data in RegUartRx. 5. If data is not equal at End-Of-Line then jump to 2. 6. End of reception. Rx / Tx start bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 parity stop start bit 0 bit 1 bit 2 clock/16 Figure 9.1: example of UART messages UartBR[2-0] baud rate, RC input baud rate, Xtal input 111 110 101 100 011 010 001 000 38400 19200 9600 4800 2400 1200 600 300 2400 1200 600 300 Table 9.3: baud rate selection UartWL word length 1 0 8 bits 7 bits Table 9.4: word length UartPM parity mode 1 0 even odd Table 9.5: parity mode UartPE parity enable 1 0 with parity no parity Table 9.6: parity enable Page 81 bit 2 Preliminary information 2. 3. 4. 5. 6. 9 Universal Asynchronous Receiver/Transmitter (UART) 9 Universal Asynchronous Receiver/Transmitter (UART) register name address (hex) RegUartCtrl RegUartCmd RegUartTx RegUartTxSta RegUartRx RegUartRxSta H0050 H0051 H0052 H0053 H0054 H0055 XX-XE88LC01/03/05, Data Book Preliminary information Table 9.7: UART registers UartEcho echo 1 0 echo Rx -> Tx no echo Table 9.8: echo modes bit name reset rw description 7 6 5-3 2 1 0 SelXtal UartWakeup UartRcSel[2:0] UartPM UartPE UartWL 0 resetsystem 0 resetsystem 000 resetsystem 0 resetsystem 0 resetsystem 1 resetsystem rw rw rw rw rw rw Select input clock; 0->RC, 1->Xtal Uart reception enabled on falling on Rx Rc prescaler selection select parity mode enable parity select word length Table 9.9: RegUartCmd bit name reset rw description 7 6 5 4 3 2-0 UartEcho UartEnRx UartEnTx UartXRx UartXTx UartBR[2-0] 0 resetsystem 0 resetsystem 0 resetsystem 0 resetsystem 0 resetsystem 101 resetsystem rw rw rw rw rw rw enable Echo Mode enable Uart reception enable Uart Transmission invert pad Rx invert pad Tx select baud rate Table 9.10: RegUartCtrl bit name reset rw description 7-0 UartRx xxxxxxxx r data received Table 9.11: RegUartRx bit name reset rw description 7-6 5 4 3 -UartRxSErr UartRxPErr UartRxFErr 00 x x x r r r r unused start error parity error frame error overrun error cleared by writing RegUartRxSta Uart is busy receiving RegUartRx is Full (irq on full) cleared by reading RegUartRx 2 UartRxOErr 0 resetsystem c 1 UartRxBusy 0 resetsystem r 0 UartRxFull 0 resetsystem r Table 9.12: RegUartRxSta bit name reset rw description 7-0 UartTx 00000000 resetsystem rw data to send Table 9.13: RegUartTx Page 82 XX-XE88LC01/03/05, Data Book 9 Universal Asynchronous Receiver/Transmitter (UART) bit name reset rw description 7-2 1 -UartTxBusy 000000 0 resetsystem r r 0 UartTxFull 0 resetsystem r unused Uart is busy transmitting RegUartTx is full (irq on empty) set by wrinting RegUartTx Preliminary information Table 9.14: RegUartTxSta Page 83 Preliminary information 9 Universal Asynchronous Receiver/Transmitter (UART) Page 84 XX-XE88LC01/03/05, Data Book XX-XE88LC01/03/05, Data Book 10 Universal Synchronous Receiver/Transmitter (USRT) 10 Universal Synchronous Receiver/Transmitter (USRT) 10.1 Overview The serial transceiver hardware is connected to PB[5] (SIN: Synchronous INput), PB[3] (SOU: Synchronous OUtput) and PB[4] (SCL: Synchronous CLock). The register RegUSRTSIN can be used to read SIN when the serial interface is in Receive = Slave mode. It is advised to read the SIN when in Slave mode from the RegUSRTData register (data is stored on SCL rising edge in this register). The RegUSRTSCL register is used to read SCL when interface is in Receive mode or to drive SCL by writing it when in Transmit mode. 10.1.1 Enabling the serial interface The bit EnableUSRT in RegUSRTCtrl is used to enable the serial interface and controls the SIN and SCL lines. This bit puts these two PortB lines in open drain configuration. If no external SIN and SCL Pull-ups are added, the user has to add them by software by setting PBPullup[5] and PBPullup[4] in RegPBPullup (see chapter "Parallel IO ports" ). 10.1.2 Reading the serial interface The bit USRTData in RegUSRTData is the prefered way to read the SIN data line because this data is stored on the rising edge of the SCL and will change only on the next rising SCL edge. The bit USRTEdgeSCL in RegUSRTEdgeSCL is set to one on SCL rising edge and is cleared on any reset as well as by reading the data from the RegUSRTData. It is the prefered way of knowing if data has been stored. 10.2 Registers register name address (hex) RegUSRTSIN RegUSRTSCL RegUSRTCtrl Reserved Reserved RegUSRTData RegUSRTEdgeSCL Reserved H0060 H0061 H0062 H0063 H0064 H0065 H0066 H0067 Table 10.1: serial interface registers bit name reset rw description 7-1 0 Reserved USRTSIN 0000000 1 resetsystem r rw reserved Serial Data (SIN on pad PB[5]) Table 10.2: RegUSRTSIN Page 85 Preliminary information The XE8000 includes hardware to support the software implementation of several bidirectional synchronous serial interfaces, for Master and Slave modes. 10 Universal Synchronous Receiver/Transmitter (USRT) XX-XE88LC01/03/05, Data Book bit name reset rw description 7-1 0 Reserved USRTSCL 0000000 1 resetsystem r rw reserved Serial Clock (SCL on pad PB[4]) Preliminary information Table 10.3: RegUSRTSCL bit name reset rw description 7-3 2-1 0 Reserved Reserved USRTEnable 00000 00 0 resetsystem r rw rw reserved reserved, should always be set to 0 enable hardware and pads for USRT (0=disable) Table 10.4: RegUSRTCtrl bit name reset rw description 7-1 0 Reserved USRTData 0000000 x r r reserved last received data Table 10.5: RegUSRTData bit name reset rw description 7-1 Reserved 0000000 r 0 USRTEdgeSCL 0 resetsystem r reserved edge detection on SCL (1 = edge detected) cleared by reading RegUSRTData Table 10.6: RegUSRTEdgeSCL Page 86 XX-XE88LC01/03/05, Data Book 11 Counters/timers 11 Counters/timers 11.1 Introduction The watchdog is a counter that sends an interrupt when it is not correctly addressed within a given time. It is used to recover from abnormal situations, like endless software loops. The general purpose counters/timers are used for counting events, counting time, measuring frequency (capture function) and generating analog-like outputs (PWM). The prescaler (see "Prescaler" on page 65) is used to extract all necessary signals from the different clocks. 11.2 Watchdog Watchdog is a timer which has to be cleared at least every 4 seconds by the software to prevent program overrun. The watchdog can be enabled by software, and it is disabled at power-on. Once enabled, it cannot be disabled by software (only with power-on reset). See register RegSysCtrl (bit EnResWD). The watchdog is made of a 3 stage divider chain clocked by a 2 Hz signal from the prescaler and gives a system reset if not cleared within 4 seconds. The watchdog timer can be cleared by writing two successive WDKeys to RegSysWD register. This sequence must be respected. Only writing hxA followed by hx3 resets the WD. Example : move move AddrRegSysWD, #0x0A AddrRegSysWD, #0x03 If some other write instruction is done to RegSysWD between the hxA and hx3, the watchdog timer will not be reset. It is possible to read the status of the RegSysWD register. The watchdog timer doesn't perform a full range count for the 4 bits associated with it. The watchdog is a 4 bit counter, however the count range is 0 to 7 and following the count of 7, the system reset is generated concurrently with the setting of WDCount[3]. bit name reset rw description 7-4 -WDKey[3] WDCounter[3] WDKey[2] WDCounter[2] WDKey[1] WDCounter[1] WDKey[0] WDCounter[0] 0 r w r w r w r w r reserved Watchdog Key bit 3 Watchdog counter bit 3 (1/4 Hz) Watchdog Key bit 2 Watchdog counter bit 2 (1/2 Hz) Watchdog Key bit 1 Watchdog counter bit 1 (1 Hz) Watchdog Key bit 0 Watchdog counter bit 0 (2 Hz) 3 2 1 0 0 resetpor 0 resetpor 0 resetpor 0 resetpor Table 11.1: RegSysWD 11.3 11.3.1 Counters Overview There are four general purpose 8-bit wide Up/Down counters, CounterA, CounterB, CounterC & CounterD. Page 87 Preliminary information They are several types of counters in the XE8000: * Watchdog * 4 general purpose counters/timers * Prescaler 11 Counters/timers XX-XE88LC01/03/05, Data Book Each counter has four possible clock inputs. Three of them are internal clocks provided by the prescaler and the forth is a PortA pin. The clock input of PortA is set as a normal portA input (rising/falling, debounced/not debounced). CounterA and CounterB can be combined to form a 16-bit counter and similarly with CounterC and CounterD. When not in PWM mode, counters can generate an interrupt when reaching a predefined value. Preliminary information Counters can also be used to generate two PWM outputs on PB[1] and PB[0]. In PWM mode one can generate PWM functions on 8 to 16 bits width. Note: If PowerXtal is set when the counter is set to use one of the low frequency clocks (32kHz or lower), counter switches immediately on Xtal. The Xtal frequency takes time to stabilize. ColdXtal goes low when the Xtal is considered stable. Additionally, the low 15-stage divider of the Prescaler is cleared when PowerXtal is set. 11.3.2 * * * * * * * * Features four independent 8-bit up/down counters - each with 4 possible clock selections PA[3:0] can be used as clock inputs (debounced or direct) counters can be set in pairs to form blocks of 16-bit counters generate interrupts when used as normal counters PWM function on two simple (8-bit) or combined (16-bit) counters. PWM function on 8 / 10 / 12 / 14 / or 16 bit width Capture function (internal or external) PWM output on PB[1] and PB[0] 11.3.3 Block schematics ck128 ck250k ck1M PA(0) ck128 ck250k ck1M PA(1) ck128 ck1k ck32k PA(2) ck128 ck1k ck32k PA(3) counter A capture RegCntA counter B RegCntB counter C RegCntC counter D ck1k ck32k PA(2) PA(3) RegCntD Figure 11.1: Counters/timers block schematics 11.3.4 Counter Registers Counters are enabled by CntAEnable, CntBEnable, CntCEnable, CntDEnable in RegCntOn. Each counter has a corresponding 8 bit read/write register RegCntA, RegCntB, RegCntC, and RegCntD. These registers contain the counter value for the purposes of reading. When written by the user, they contain the comparison values. They can only be reliably modified when the counter is stopped. Page 88 XX-XE88LC01/03/05, Data Book 11 Counters/timers To stop the counter, CntXEnable must be reset. To start the counter, CntXEnable must be set. The only operation allowed when the counter is stopped is loading the counter with data. If no new data has been written, the counter remains unchanged. So the smallest sequence is a STOP/MODIFY/START. 11.3.5 Clock selection The clock source for each counter can be individually selected by writing the appropriate value in RegCntCtrlCk. Each value can be 1 of 4 (2 bits) : each represents one of the different clock options. Table 7.1, 7.2, 7.3 & 7.4 describe the code for each counter clock source combination. See chapter "Prescaler" on page 65, and Figure 7.4 for more explainations about the ck128, ck1k, ck32k, ck250k, and ck1M signals. CntACkSel[1:0] clock source 11 10 01 00 ck128 ck250k ck1M PA[0] Table 11.2: clock source for Counter A CntBCkSel[1:0] clock source 11 10 01 00 ck128 ck250k ck1M PA[1] Table 11.3: clock source for Counter B CntCCkSel[1:0] clock source 11 10 01 00 ck128 ck1k ck32k PA[2] Table 11.4: clock source for Counter C CntDCkSel[1:0] clock source 11 10 01 00 ck128 ck1k ck32k PA[3] Table 11.5: clock source for Counter D The clock source must be changed ONLY WHEN THE COUNTER IS STOPPED. Once the counter is restarted/ started, the circuit wait for a falling edge on the clock signal (internally generated clock or external source), to start counting. The counter is modified at the clock rising edge. Depending when the start of the counter related to its selected clock arrives, the first counter clock might not be counted because the first falling edge is used for synchronization and counter preparation. Page 89 Preliminary information It is possible to read any counter at any time, even when the counter is running. However, the value is only guaranteed correct when the counter is static. For precise counter acquisition, one should use the capture function (see below). 11 Counters/timers XX-XE88LC01/03/05, Data Book clock counter 0 1 2 enable the counter Preliminary information Figure 11.2: start synchronization When the counter arrives at IRQ condition (if count down when it change to 00), it does not give an IRQ at that moment but one half period of selected clock later. clock counter 1 0 N N-1 interrupt Figure 11.3: interrupt generation If corresponding CounterMask bits are set to 1, interrupts are generated on the clock's falling edge after the counter has reached the expected value. The counter is stopped immediately by setting start at 0. If a rising edge occurs exactly at this time, we cannot predict if the counter will be modified or not. For this reason, there is always a 1 lsb uncertainty on the counter value. Note: You can read the counter properly ONLY WHEN THE COUNTER IS STOPPED. Reading on run can give false values. This case is not advised, use only when the counter counts at least 8 times lower than CPU clock. In this case user can do a software filer of at least three readings to determine the counter value. Be careful to select the counter mode BEFORE writing any value in it. Value is not stored in the counter in the "UP-COUNT" mode. In "Down-COUNT" or "PWM" mode, the value is stored in the counter. When you write a value into the counter, the counter will be cleared if you are in UP-COUNT mode. Otherwise, the counter will be loaded with the value. If you do not write a value, the counter will not be modified, even if you are modifying the mode. 11.3.6 16 bit counters CascadeAB and CascadeCD in RegCntConfig1 are used to set the count ranges. When CascadeAB is set, the CounterA is connected to CounterB to form a 16-bit wide counter. In this case, CounterA is the LSB and CounterB is the MSB. When not cascaded (CascadeAB = 0), the counters are independent. CounterC and CounterD can be set similarly with CascadeCD. There is no default values, so these bits must be set before using any of the counters. CascadeAB counters 1 16 bits counter AB 8 bit counter A 8 bit counter B 0 Table 11.6: cascading counter A & B Page 90 XX-XE88LC01/03/05, Data Book CascadeCD counters 1 16 bits counter CD 8 bit counter C 8 bit counter D 0 11 Counters/timers Table 11.7: cascading counter C & D Only CounterA and CounterC IRQ are generated in 16 bit mode. Up/down counting The counters can be up- or down-counting. 11.3.7.1 Up-counting For 8 bits up-counting, we see the following behaviour: * Counter A: 0,1,2,...,ValueA-1,ValueA,0,1,....,ValueA-1,ValueA,... * Counter B: 0,1,2,...,ValueB-1,ValueB,0,1,....,ValueB-1,ValueB,... For 16 bits up-counting, we see the following behaviour: * Counter (B,A): (00, 00), (00, 01),..., (00, FF), (01, 00), (01, 01), .., (ValueB, ValueA), (00,00), ... In 16 bits mode, counter B is incremented only when counter A is FF IRQ generated when counter reaches VALUE. 11.3.7.2 Down-counting For 8 bits down-counting, we see the following behaviour: * Counter A: ValueA,...,2,1,0,ValueA,ValueA-1,....,2,1,0,ValueA,... * Counter B: ValueB,...,2,1,0,ValueB,ValueB-1,....,2,1,0,ValueB,... For 16 bits down-counting, we see the following behaviour: * Counter (B,A): (ValueB, ValueA), (ValueB, ValueA-1),..., (ValueB, 00), (ValueB-1, FF), .., (00,00), (ValueB, ValueA), ... IRQ generated when counter reaches 0. 11.3.7.3 Registers for up/down counting CntADownUp, CntBDownUp, CntCDownUp & CntDDownUp in RegCntConfig1 are used to individually set up and down counting for Counters A, B ,C & D. Note: There is no default values, so these bits must be set before using any of the Counters. CntXDownUp CounterX 1 0 up-counting down-counting Table 11.8: selection for up/down-counting An IRQ will be generated every "VALUE+1" clock cycles For example in 8 bits mode, if you load the counter with a value h5B, with a 4 MHz clock, an interrupt will be generated every 23 us; in 16 bits mode, if you load the counter will a value h5BA7, with a 4 MHz clock, an interrupt will be generated every 5866 us. Page 91 Preliminary information 11.3.7 11 Counters/timers XX-XE88LC01/03/05, Data Book clock up-counter 0 1 2 N-1 N 0 1 2 N-1 N 0 1 down-counter N N-1 N-2 1 0 N N-1 N-2 1 0 N N-1 PWM counter 0 FF FE N+1 N N-1 N-2 N-3 1 0 FF FE Preliminary information PWM Figure 11.4: counter examples 11.3.8 Capture functions 11.3.8.1 Overview The 16 bit capture register is provided to facilitate frequency measurements. It captures the data held in counters A and B and is split into CaptureA and CaptureB. The instant of capture for both CaptureA and CaptureB are user defined by selecting either internal sources derived from the prescaler or from a chip pin (PA[2] or PA[3]). Both registers use the same capture source. For all sources, rising edge sensitivity, falling edge sensitivity or both can be selected dynamically. This is especially useful for synchronizing with signals for which duty cycle measurements are required. The source of the capture signal and the edge sensitivity are determined in RegCntConfig2. When counters A or B are active, reads performed on their associated addresses come from the capture register. Figure 11.5 shows a representation of the capture block within the context of counter A. Counter A Irq Irq counter/capture A Counter A data out Counter/capture Block data A output Capture edge select Temp Copy of A CpuDomain copy of A Capture source select ck1k ck32k PA(3) PA(2) Edge Detector (1) Edge Detector (2) Counter A clock CPU clock Capture function Figure 11.5: Capture Architecture (counter A) Page 92 XX-XE88LC01/03/05, Data Book 11.3.8.2 11 Counters/timers Detailed implementation Several edge detectors and temporary registers are implemented to ensure proper operation of the capture function despite the asynchronous multiple clocks. Understanding of the detailed implementation is only required for very precise measurements. Other users may directly go to the registers chapter. * * Edge detector (1) Edge detector (2) Edge detector (1) generates the strobe pulse that captures the contents of the counter into the register marked Temp copy of A within Figure 11.5. This strobe signal is also used to communicate the availability of data within that register to the Edge detector (2) block which in turn generates the strobe signal that copies the data into the cpu clock domain. The architectures of Edge detector (1) and Edge detector (2) are represented in Figure 11.6 and Figure 11.7 respectively. Clock Enable Rising A B C Capture Latch Enable Enable Falling D Figure 11.6: Edge detector (1) principle The Edge detector (1) represented in Figure 11.6 may be divided into two sections that are associated with rising edge detection (top row of cells) and falling edge detection (bottom row of cells). To explain the circuit functionality the rising edge detection is used as an example. The state of Enable Rising is user defined. Assuming that it is disabled (set to 0) then no contribution is made to the Latch Enable output circuit. If the Enable Rising signal is active (set to 1), then the output of d-flip-flop A (subsequently referred to as A) becomes high within a flip-flop delay time of the rising edge of the capture signal. This signal remains until A is reset. Following the next falling edge of the Clock signal, the output of A is copied to B. The next rising edge of clock copies this further to C. The output of C causes A to be reset; only to become active following the detection of the next rising edge of the capture signal (if enabled). This structure is based on conventional techniques for exchanging data between different clock domains. Within the bottom row of cells, D is sensitive to the falling edge of Capture. Page 93 Preliminary information When in capture mode the capture block becomes the source of interrupts from the counter/capture block A. Additionally, the global data register address associated with the counter/capture block A becomes that labelled as CPUdomain copy of A within the figure. Within the Capture architecture there are two edge detector blocks, namely: 11 Counters/timers XX-XE88LC01/03/05, Data Book Clock `1' A Preliminary information Capture Latch Enable Figure 11.7: Edge detector (2) principle The behavior of the Edge Detector (2) is similar to that previously described, with the exception that it is always enabled and the output of cell A is always set following the rising edge of the flip flop generated by Edge Detector (1). In both circuits, the outputs of cells A and D can only be reset (during normal operation) as a result of acknowledgment of the request signal (A or D) by downstream cells. 11.3.8.3 Registers Table 11.9 and Table 11.10 describe the mapping between the codes placed on CapSel[1:0] (Capture source select) and CapFunc[1:0] (Capture Function) and their meanings. CapSel[1:0] source 11 10 01 00 ck1k (RC divider) ck32k (RC divider) PA[3] PA[2] Table 11.9: capture source CapFunc[1:0] selection 11 10 01 00 both edges falling edge rising edge disabled Table 11.10: capture function selection 11.3.9 11.3.9.1 PWM functions General The counters can generate PWM (pulse width modulation) PB(0) and PB(1) outputs. PWM mode override normal outputs settings on PB(0) and PB(1) (except analog mode). The counters can be used in 8 or 16 bits mode. Counters in PWM mode always count down, independently of CntXDownUp setting. Page 94 XX-XE88LC01/03/05, Data Book 11 Counters/timers Output is low as long as the value of the counter is bigger than the stored value, and high when the value of the counter is smaller or equal to the stored value. big stored value small stored value CntPWM1 and CntPWM0 in RegCntConfig1 are used to set PWM functions. These two bits are by default after any reset cleared to 0 disabling the PWM function. CntPWM1 PWM1 PB[1] 1 0 active stopped outputs PWM1 normal function Table 11.11: PWM1 CntPWM0 PWM0 PB[0] 1 0 active stopped outputs PWM0 normal function Table 11.12: PWM0 PWM resolution is always 8 bits when the counters are in 8 bits mode. PWM1Size and PWM0Size in RegCntConfig2 are used to set the PWM resolution when the counters are in 16 bits mode (CascadeAB or/and CascadeCD set). PWM1Size[1:0] Size of PWM1 11 10 01 00 16 bits 14 bits 12 bits 10 bits Table 11.13: PWM1 size selection PWM0Size[1:0] Size of PWM0 11 10 01 00 16 bits 14 bits 12 bits 10 bits Table 11.14: PWM0 size selection Note: Counters used for PWM do not generate any IRQ. 11.3.9.2 PWM in 8 bits mode With "Value" in the range from 0 - FF one selects the duty cycle of the output between 0 and 99.6%. h00 = 0%, h3F = 25%, h7F = 50%, hFF = 255/256. 11.3.9.3 PWM in 16 bits mode The counter counts from 0, MAX, MAX-1, ....., 2, 1, 0, MAX, MAX-1, ....... MAX is depending on the PWM size setting. It is hFFFF for 16 bits, h3FFF for 14 bits, h0FFF for 12 bits and h03FF for 12 bits. Page 95 Preliminary information Figure 11.8: PWM output examples 11 Counters/timers Preliminary information 11.3.10 XX-XE88LC01/03/05, Data Book Counter registers register name address (hex) RegCntA RegCntB RegCntC RegCntD RegCntCtrlCk RegCntConfig1 RegCntConfig2 RegCntOn H0058 H0059 H005A H005B H005C H005D H005E H005F Table 11.15: Counters registers bit name reset rw description 7-0 CounterA xxxxxxxx rw 8-bit Counter A Table 11.16: RegCntA bit name reset rw description 7-0 CounterB xxxxxxxx rw 8-bit Counter B Table 11.17: RegCntB bit name reset rw description 7-0 CounterC xxxxxxxx rw 8-bit Counter C Table 11.18: RegCntC bit name reset rw description 7-0 CounterD xxxxxxxx rw 8-bit Counter D Table 11.19: RegCntD bit name reset rw description 7-6 5-4 3-2 1-0 CntDCkSel[1:0] CntCCkSel[1:0] CntBCkSel[1:0] CntACkSel[1:0] xx xx xx xx rw rw rw rw CounterD clock selection CounterC clock selection CounterB clock selection CounterA clock selection Table 11.20: RegCntCtrlCk bit name reset rw description 7 6 5 4 3 2 1 0 CntDDownUp CntCDownUp CntBDownUp CntADownUp CascadeCD CascadeAB CntPWM1 CntPWM0 x x x x x x 0 resetsystem 0 resetsystem rw rw rw rw rw rw rw rw CounterD down- or up-counting (0=down) CounterC down- or up-counting (0=down) CounterB down- or up-counting (0=down) CounterA down- or up-counting (0=down) cascade Counter C & Counter D (1=cascade) cascade Counter A & Counter B (1=cascade) activate PWM1 on Counter C or C+D (PB[1]) activate PWM0 on Counter A or A+B (PB[0]) Table 11.21: RegCntConfig1 bit name 7-6 5-4 CapSel[1:0] CapFunc[1:0] reset Table 11.22: RegCntConfig2 Page 96 rw 00 resetsystem r w 00 resetsystem r w description capture source selection capture function XX-XE88LC01/03/05, Data Book 11 Counters/timers bit name reset rw description 3-2 1-0 PWM1Size[1:0] PWM0Size[1:0] xx xx rw rw PWM1 size selection PWM0 size selection bit name reset rw description 7-4 3 2 1 0 -CntDEnable CntCEnable CntBEnable CntAEnable 0000 0 resetsystem 0 resetsystem 0 resetsystem 0 resetsystem r rw rw rw rw reserved enable Counter D enable Counter C enable Counter B enable Counter A Preliminary information Table 11.22: RegCntConfig2 Table 11.23: RegCntOn Page 97 Preliminary information 11 Counters/timers Page 98 XX-XE88LC01/03/05, Data Book XX-XE88LC01/03/05, Data Book 12 Voltage Level Detector 12 Voltage Level Detector 12.1 can be switched off and on generates an interrupt if power supply is below a pre-determined level at end of measurement 12.2 Overview The Voltage level detector monitors the state of the system battery. It returns a logical value depending on the result. If the supplied voltage drops below a user defined value (Vsb) then an interrupt request (`1' on VldIrq) is generated. 12.3 VLD operation The VLD is controlled by VldMult, VldTune and VldEn. VldMult selects the voltage range applicable to the product, while VldTune is used to programme the reference voltage level. VldEn is used to enable (disable) the VLD with a 1(0) value respectively. The user tunes the Vsb level using the VldTune bits. In low and high range, 8 values of Vsb can be selected. symbol description min typ max unit comments Vsb threshold voltage for VLD_tune = h100 1.2 2.4 1.3 2.55 1.4 2.7 V V low range high range dVsb step size of tuning % tEOM duration of measurement relative to Vsb time between setting VldEn and rise of VldValid 6 2 ms Table 12.1: Voltage level detector operation To start the voltage level detection, the user sets bit VldEn. Analog part is powered and measurement is started. After the measurement, Bit VldValid is set to signal validity of VldIrq, a maskable interrupt request is sent if voltage level is below threshold. By reading bit VldIrq, the user knows the power supply status. Figure 12.1 describes the functionality of the VldValid and VldIrq signals with respect to the battery level (Vbat), the measurement made by the analog part of the vld (vld_out), the vld enable signal, the vld_valid signal and the vld_irq signal.The VLD is intended to be polled, namely: the user requests that a measurement be taken by VldEn. The bit VldValid becomes active indicating the validity of VldIrq. Once the VldIrq has been read, the user can disable the VLD by setting the VldEn to 0. Figure 12.1 shows that the VldValid signal rises to its active state with the sixteenth rising ck8k edge following the rise of VldEn. The intermediate time is required for the vld to stabilize. Digital filtering is used to filter the output signal. vbat ck8k VLD_out 1 2 3 4 5 6 7 1 2 3 4 5 6 7 1 2 3 4 5 6 7 1 2 3 4 5 6 7 1 VldEn VldValid VldIrq Figure 12.1: VLD timing Page 99 Preliminary information * * Features 12 Voltage Level Detector XX-XE88LC01/03/05, Data Book Figure 12.1 also shows that if the VLD remains in the enabled state, it continues to generate interrupt requests as appropriate. However, it should be noted that these are based on the existence of three consecutive agreeing measurements being made, and therefore the transitions occuring on VldIrq are not always equi-distant. 12.4 Registers Preliminary information The CPU interface comprises two 8 bit registers that are globally accessible, namely RegVldCtrl and RegVldStat. Table 12.2 shows the mapping of control bits and functionality of RegVldCtrl while Table 12.3 describes that for RegVldStat. bit name reset rw description 7-4 3 2-0 -VldMult VldTune[2:0] 0000 0 resetcold 000 resetcold r rw rw reserved VLD double level dectector VLD level tuning Table 12.2: RegVldCtrl bit name reset rw description 7-3 2 1 0 -VldIrq VldValid VldEn 00000 0 resetsystem 0 resetsystem 0 resetsystem r r r rw reserved VLD irq VLD valid result VLD enable Table 12.3: RegVldStat Page 100 XX-XE88LC01/03/05, Data Book 13 Power-on reset 13 Power-on reset The Power-on reset (POR) block fixes the conditions for the beginning of the power-on sequence (see SYSTEM chapter). VREG VT Vf POR trise tdrop ton Figure 13.1: reset conditions symbol description min ton reset duration 5 tdrop drop duration 10 start threshold voltage 0.7 VT Vdd_sl_M Vdd_sl_R voltage slope for activation of MTP versions voltage slope for activation of ROM versions typ max unit 20 ms 3 s Vf = 0.4 VREG V 1 20 V/ms 2 0.25 V/ms 2 1.1 comments Table 13.1: POR specifications Note: Note: Note: 1) Threshold voltage for the power-on reset does not imply that this voltage is sufficient for correct operation of the CPU. This has to be checked with the voltage level detector during operation of the device, and to be ensured by design for the start-up of the chip. 2) The Vdd_sl defines a minimum slope on Vreg. The power-on reset behaviour of the circuit is not guaranteed if this slope is too slow as system could start before program memory has sufficient voltage to insure correct behaviour. In such a case, a delay has to be built using the RESET pin. 3) The power-on sequence (see SYSTEM chapter) follows the reset duration. Page 101 Preliminary information At start-up of the circuit, the POR block generates a reset signal during ton. In normal mode if the voltage supply falls below a critical value, the reset signal is activated. Preliminary information 13 Power-on reset Page 102 XX-XE88LC01/03/05, Data Book XX-XE88LC01/03/05, Data Book 14 Acquisition chain 14 Acquisition chain Introduction The Acquisition Chain is made of an Analog Multiplexer (AMUX) entering a Programmable Gain Amplifier (PGA) followed by an Analog-to-Digital Converter (ADC). It is intended to sense a differential voltage at its input, which can be connected for instance to a Wheatstone-bridge type resistive sensor, and to deliver a signed 16 bits-wide word in 2's complement. A busy signaland a maskable interrupt inform the CPU about the state of the conversion. The PGA can provide both amplification and offset compensation. The ADC converter is oversampled and incremental, i.e. it uses several input samples to generate one output data and it is reset before each conversion. Its oversampling ratio can be programmed as a power of 2 to choose the appropriate trade-off between conversion duration and resolution. Input swiching is immediate when PGA is off, it requires a short delay when PGA is on. The block can be operated in two ways: "on request" upon a Start Conversion signal or "continuously running". 14.2 Block diagram AC_R(0) AC_R(1) AC_R(2) AC_R(3) AC_A(0) AC_A(1) AC_A(2) AC_A(3) AC_A(4) AC_A(5) AC_A(6) AC_A(7) reference selection ADC gain1 gain2 offset2 gain3 offset3 mode output code input selection zoom Figure 14.1: Acquisition channel block diagram with ZoomingADCTM Figure 14.1 shows the general block diagram of the peripheral. The PGA selects a combination of input signals, modulates the input voltage and amplifies it through 1 to 3 stages, 2 of these providing offset compensation. Each amplifier can be bypassed. The ADC delivers the output in 2's complement. The acquisition channel also includes a control block that manages all communication with the CPU, sets the configuration of the peripheral and implements the different test modes. 14.3 Input signal multiplexing There are 8 inputs named AC_A[0] to AC_A[7]. Inputs can be used either as four differential channels (Vin1=AC_A[1]-AC_A[0], ..., Vin4=AC_A[7]-AC_A[6]) or AC_A[0] can be used as a common reference, providing 7 signal paths (AC_A[1]-AC_A[0], ..., AC_A[7]-AC_A[0]), all referred to AC_A[0]. Default input is Vin1. Page 103 Preliminary information 14.1 14 Acquisition chain XX-XE88LC01/03/05, Data Book On top of these settings, inputs can be crossed or not. All multiplexing combinations are summarised in the following table (see Table 14.1) : uni/bi-polar AMUX(4) sign AMUX(3) AMUX(2) 0 unused 1 unused channel selection AMUX(1) AMUX(0) 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Preliminary information 0 0 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 selected differential input VINVIN+ A(0) A(2) A(4) A(6) A(1) A(3) A(5) A(7) A(0) A(0) A(0) A(0) A(0) A(0) A(0) A(0) A(0) A(1) A(2) A(3) A(4) A(5) A(6) A(7) A(1) A(3) A(5) A(7) A(0) A(2) A(4) A(6) A(0) A(1) A(2) A(3) A(4) A(5) A(6) A(7) A(0) A(0) A(0) A(0) A(0) A(0) A(0) A(0) Table 14.1: AMUX selection 14.4 Input reference multiplexing One must select one of two differential signal as reference signal (Vref1=AC_R[1]-AC_R[0], Vref2=AC_R[3]AC_R[2]). Default is Vref1. 14.5 Amplifier chain The 3 stages transfer functions are: VD3 = GD3.VD2 - GDoff3.Vref VD2 = GD2.VD1 - GDoff2.Vref VD1 = GD1.Vin where: Vin=Selected input voltage Vref=Selected reference voltage VD1=Differential voltage at the output of first amplifier VD2=Differential voltage at the output of second amplifier VD3=Differential voltage at the output of third amplifier GD1=Differential gain of stage 1 GD2=Differential gain of stage 2 GD3=Differential gain of stage 3 GDoff2= Offset gain of stage 2 GDoff3=Offset gain of stage 3 and therefore the whole transfer function is: Vout of PGA = VD3 = GD3.GD2.GD1.Vin - (GDoff3 + GDoff2.GD3).Vref Note: As the offset compensation is realized together with the amplification on the same summing node, the only voltages that have to stay within the supplies are Vref and the VDi . GDi . VDi-1 and GDoffi . Vref can be Page 104 XX-XE88LC01/03/05, Data Book Note: larger without any saturation. All stages use a fully differential architecture and all gain and offset settings are realized with ratios of capacitors. As the ADC also provides a gain (2 nominal), the total chain transfer function is: Data _ out = 2 GD3 GD2 GD1 Vin - 2 (GDoff 3 + GDoff 2 GD3) Vref Each stage is called PGAi. Features of these stages are: * Gain can be chosen between 1 and 10 (between 0 and 10 for PGA3) * Offset can be compensated for in PGA2 (a little) and in PGA3 (to a large extent) * Granularity of settings is rough for PGA1, medium for PGA2, fine for PGA3 * Zero, one, two or three of the PGA stages can be used. A functional example of one of the stages is given on Figure 14.2. Vref Vout Vin Figure 14.2: PGA stage principle implementation 14.5.1 PGA 1 symbol description min GD_preci GD_TC fs Zin1 Zin1p Precision on gain settings Temperature dependency of gain settings input sampling frequency Input impedance Input impedance for gain 1 -5 -5 5 150 1500 VN1 Input referred noise typ max unit +5 +5 512 % ppm/C kHz k k nV/ sqrt(Hz) 18 Comments 1 1 2 Table 14.2: PGA1 Performances Note: Note: 1) Measured with block connected to inputs through AMUX block. Normalized input sampling frequency for input impedance is 512 kHz. This figure has to be multiplied by 2 for fs = 256 kHz and 4 for fs = 128 kHz. 2) Input referred rms noise is 10 uV per input sample. This corresponds to 18 nV/sqrt(Hz) for fs = 512 kHz. 14.5.2 PGA2 sym description min GDoff2 GDoff2_step PGA2 Offset Gain GDoff2(code+1) - GDoff2(code) -1 0.18 typ max unit 0.2 1 0.22 FS - Comments Table 14.3: PGA2 Performances Page 105 Preliminary information Note: 14 Acquisition chain 14 Acquisition chain XX-XE88LC01/03/05, Data Book sym description min GD_preci GD_TC fs Zin2 Precision on gain settings Temperature dependency of gain settings Input sampling frequency Input impedance -5 -5 5 150 VN2 Input referred noise typ max unit Comments +5 +5 512 % ppm/C kHz k nV/ sqrt(Hz) valid for GD2 and GDoff2 36 1 2 Table 14.3: PGA2 Performances Preliminary information Note: Note: 1) Measured with block connected to inputs through AMUX block. Normalized input sampling frequency for input impedance is 512 kHz. This figure has to be multiplied by 2 for fs = 256 kHz and 4 for fs = 128 kHz. 2) Input referred rms noise is 26uV per sample.This corresponds to 36 nV/sqrt(Hz) max for fs = 512 kHz. 14.5.3 PGA3 sym description min GDoff3 GD3_step GDoff3_step GD_preci GD_TC fs PGA3 Offset Gain GD3(code+1) - GD3(code) GDoff2(code+1) - GDoff2(code) Precision on gain settings Temperature dependency of gain settings Input sampling frequency -5 0.075 0.075 -5 -5 5 Zin3 Input impedance 150 VN3 Input referred noise typ 0.08 0.08 max unit 5 0.085 0.085 +5 +5 512 FS % ppm/C kHz 36 Comments valid for GD3 and GDoff3 k 1 nV/ sqrt(Hz) 2 Table 14.4: PGA3 Performances Note: 1) Measured with block connected to inputs through AMUX block. Normalized input sampling frequency for input impedance is 512 kHz. This figure has to be multiplied by 2 for fs = 256 kHz and 4 for fs = 128 kHz. 2) Input referred rms noise is 26uV per sample. This corresponds to 36 nV/sqrt(Hz) max for fs = 512 kHz. 14.6 ADC Note: 14.6.1 Input-Output relation The ADC block is used to convert the differential input signal into a 16 bits 2's complement output format. The output code corresponds to the ratio: Output code = Vin Vref . smax + 1 smax smax being the number of samples used to generate one output sample per elementary conversion. smax is set by OSR on RegACCfg0. Vref can be selected up to the power supply rails and must be positive. The corresponding 2's complement output code is given in hexadecimal notation by 8000 (negative full scale) and 7FFF (positive full scale). Code outside the range are saturated to the closest full scale value. Note: The output code is normalized into a 16 bits format by shifting the result left or right accordingly. 14.6.2 Operation mode The mode can be either "on request" or "continuously running". In the "on request" mode, after a request, an initialization sequence is performed, then an algorithm is applied and an output code is produced. The converter is idle until the next request. Page 106 XX-XE88LC01/03/05, Data Book 14 Acquisition chain In the "continuously running" mode, an internal conversion request is generated each time a conversion is finished, so that the converter is never idle. The output code is updated at a fixed rate corresponding to 1/Tout, with Tout being the conversion time. 14.6.3 Conversion sequence 1 2 input sample smax 1 2 1st elementary conversion START conversion index smax 1 2 2nd elementary conversion 1 elementary conversion 2 smax elementary conversion NumConv-1 END NumConv Figure 14.3: Conversion sequence. smax is the oversampling rate. NumCONV elementary conversions are performed, each elementary conversion being made of smax+1 input samples. Note: NumConv = 2NELCONV smax = 8 * 2OSR During the elementary conversions, the operation of the converter is the same as in a sigma delta modulator. During one conversion sequence, the elementary conversions are alternatively performed with direct and crossed PGA-ADC differential inputs, so that when two elementary conversions or more are performed, the offset of the converter is cancelled. The sizing of the decimation filter puts some limits on the total number of conversions and it is not possible to combine the maximum number of elementary conversions with the maximum oversampling (see the Nelconv*smax specification). Note: Some additional clock cycles (NINIT+NEND) clock cycles are required to initiate and terminate the conversion properly. 14.6.4 Conversion duration The conversion time is given by : TOUT = (NumConv * Smax + NINIT + NEND) / fs 14.6.5 Resolution As far as it is not limited by thermal noise and internal registers width, the resolution is given by : Resolution (in bits) = 6 + 2 * OSR + NELCONV 14.6.6 ADC performances sym description min VINR Input range -0.5 typ max unit 0.5 Vref Comments Table 14.5: ADC Performances Page 107 Preliminary information The whole conversion sequence is basically made of an initialisation, a set of Numconv elementary incremental conversions and finally a termination phase (NumCONV is set by the 2 NELCONV bits on RegACCfg0). The result is a mean of the results of the elementary conversions. 14 Acquisition chain sym description min Resol NResol INL TC fs smax NUMCONV Resolution Numerical resolution Integral non-linearity Temperature dependency of sensitivity sampling frequency Oversampling Ratio 12 Number of elementary conversions typ max unit Comments 1 4 1,3, LSB at 12bits -5 10 8 16 4 +5 512 1024 bits bits LSB ppm/C kHz - 1 8 - 2 5 - 5 - Number of periods for incremental conversion initialization Number of periods for incremental conversion termination Ninit Preliminary information XX-XE88LC01/03/05, Data Book Nend 2 Table 14.5: ADC Performances Note: 1) Resolution specification also includes thermal noise and differential non-linearity (DNL) for a reference signal of 2.4 V. It is defined for default operating mode ( See "Default operation mode (not yet implemented)" on page 108.) 2) Only powers of 2 3) INL is defined as the deviation of the DC transfer curve from the best fit straight line. This specification holds over the full scale. 4) NResol is the maximal readable resolution of the digital filter. Input noise may be higher than NResol. 14.7 Control part Note: Note: Note: 14.7.1 Starting a convertion A conversion is started each time START or DEF is set. PGAs are reset after each writing operation to registers RegACCfg1-5. The ADCs must be started after a PGA common-mode stabilisation delay. This is done by writing bit START several cycles after PGA settings modification. Delay between PGA start and ADC start should be equivalent to smax number of cycles. (This delay does not apply to conversions made without the PGAs) 14.7.2 Clocks generation The clock of the acquisition path is derived from the RC oscillator clock. fs = psck/4 psck can be chosen among four prescaler clocks (bit FIN of RegACCfg2), see Table 14.7. 14.7.3 Default operation mode (not yet implemented) The DEF bit (RegACCfg5) allows the use of the ADC in a default mode without any gain nor offset adjustment (see values in the right column of Table 14.7). The only action to launch the ADC default conversion is to write a `b01AAAAAV' in RegACCfg5, AAAAA being the AMUX selection and V the VMUX selection. This default mode is used in specifications to define resolution and INL. 14.7.4 Registers Eight registers control this peripheral. Two registers are for the data output, six for peripheral general set-up. Registers are defined in Table 14.6 and Table 14.7. register RegACOutLSB RegACOutMSB RegACCfg0 RegACCfg1 RegACCfg2 RegACCfg3 RegACCfg4 data START IB_AMP_ADC FIN PGA1_ GAIN reserved ADC_OUT_L ADC_OUT_H OSR NELCONV IB_AMP_PGA PGA2_GAIN Table 14.6: Peripheral register memory map Page 108 PGA3_GAIN PGA3_OFF CONT ENABLE PGA2_OFF reserved XX-XE88LC01/03/05, Data Book 14 Acquisition chain register RegACCfg5 data BUSY DEF AMUX VMUX Name Register rm description Default (reset and DEF mode) ADC_OUT(15:0) RegACOutLSB RegACOutMSB r data output data is shifted left for having the MSB on the MSB of RegACOutMSB for any resolution. Therefore LSBs may be fixed at 0 ifdigital resolution is below 16 bits. 0000h AMUX(4:0) RegACCfg5 wr Selection of PGA inputs 00000 (reset only) BUSY RegACCfg5 CONT RegACCfg0 DEF RegACCfg5 ENABLE(3:0) RegACCfg1 FIN(1:0) RegACCfg2 IB_AMP_PGA(1:0) RegACCfg1 IB_AMP_ADC(1:0) RegACCfg1 NELCONV(1:0) RegACCfg0 OSR(2:0) RegACCfg0 wr PGA1_GAIN RegACCfg3 wr PGA2_GAIN(1:0) RegACCfg2 wr PGA2_OFF(3:0) RegACCfg2 wr PGA3_GAIN(6:0) RegACCfg3 wr PGA3_OFF(6:0) RegACCfg4 wr START TEST RegACCfg0 RegACCfg0 wr0 VMUX RegACCfg5 wr `1' : conversion is in progress `0' : data is available `1' : continuous operation. wr `0' : one shot mode Default Operation bit (not yet implemented) wr0 `1': All registers but VMUX and AMUX are reset and default values are used `0': Normal operation bit3 : PGA3, bit2 : PGA2, bit1 : PGA1, bit 0 : ADC If a bit is `1', the block is powered. If not, the block is switched off and all internal wr digital signals are reset. Concerning the PGAs, ENABLE=0 means also that inputs and outputs are wired together and that the acquisition chain is not perturbed by the block. `00' : RC is used as master clock (psck) `01' : RC / 2 is used as master clock (psck) wr `10' : RC / 8 is used as master clock (psck) `11' : RC / 32 is used as master clock (psck) Rem: do not select a clock that results in fs faster than 512 kHz. PGA amplifiers biasing current reduction factor `00' : current = 0.25 nominal current wr `01' : current = 0.5 nominal current `10' : current = 0.75 nominal current `11' : current = nominal current ADC amplifiers biasing current reduction factor. wr Tuning identical to IB_AMP_PGA Number of elementary conversions setting wr `00' : 1 conversion, `01' : 2 conversions `10' : 4 conversions, `11' : 8 conversions 0 r OverSampling Ratio setting. Defined as fs/fout. smax = 8*2OSR(2:0). `000' : oversampling = 8, ..., `111' : oversampling = 1024 signal gain of first PGA stage (GD1) `1' : nominal gain is 10. `0' : nominal gain is 1 signal gain of second PGA stage (GD2) `11' : nominal gain is 10 `10' : nominal gain is 5 `01' : nominal gain is 2 `00' : nominal gain is 1 offset gain of second PGA stage (GDoff2) bit 3: offset sign (`0' : GDoff2 > 0, `1' : GDoff2 < 0) bits (2:0) : offset amplitude `01x1' : GDoff2 = 1.0 nominal, `0100' : GDoff2 = 0.8 nominal, `0011' : GDoff2 = 0.6 nominal, ..., `0000' : GDoff2 = 0.0 nominal, `1001'' : GDoff2 = -0.2 nominal, ..., `11x1' : GDoff2 = -1.0 nominal signal gain of third stage (GD3) GD3 = 0.08*PGA3_GAIN(6:0) Nominal values : 0 (`000 0000'), ..., 10 (`111 1000') offset gain of third stage (GDoff3) bit 6: offset sign (`0' : GDoff3 > 0, `1' : GDoff3 < 0) GDoff3 = 0.08*PGA3_OFF(5:0), maximum = 5.04 Nominal values : -5.04 (`111 1111'), 0 (`x00 0000'), +5.04 (`011 1111') writing a "1" in START bit restarts the ADC. It does not affect the PGAs. reserved VREF selection multiplexer `0' : VREF0 is used, `1' : VREF1 is used 0 N/A 0000 (reset) 0001 (DEF mode) 00 11 11 01 010 0 00 0000 000 1100 000 0000 0 0 0 (reset only) Table 14.7: Peripheral register memory map, bits description Page 109 Preliminary information Table 14.6: Peripheral register memory map 14 Acquisition chain 14.8 XX-XE88LC01/03/05, Data Book Acquisition of a sample Preliminary information use default mode no yes use PGA AND modifiy PGA yes write in RegACCfg5 write in RegACCfg1-5 wait for PGA stable start ADC by writing RegACCfg0 wait for ADC ready read ADC results Figure 14.4: Acquisition flow Page 110 no XX-XE88LC01/03/05, Data Book 15 Analog outputs 15 Analog outputs The PWM DACs available in all XE8000 products are described in the TIMERS chapter. Please refer to XEMICS application note AN8000.03 for more hints on how to use the XE88LC05 DACs. 15.1 15.1.1 Signal DAC Application The DAC signal block described in this document converts a digital signal into an analog output signal (voltage output or 4-20mA loop). 15.1.2 Typical external components External components are needed for the filtering of the generic DAC output. These external components depend on the characteristics the customer wants to obtain. Some application examples are shown in the application note AN8000.03. 15.1.3 Block diagram Figure 15.1: General block diagram Figure 15.1 shows the general block diagram of the peripheral. It consists of a control block that manages all communication with the CPU, sets the configuration of the peripheral and implements the different test modes. The DAC converts the digital data in a PWM output signal. A completely independent amplifier is added. This allows the user to build a low impedance voltage output after the (external, probably passive) filter. It also allows to build a 4-20mA loop. (See amplifier section below for examples) Page 111 Preliminary information The XE88LC05 has two additional digital to analog converters (DAC)s: a signal DAC able to pass a 4 kHz signal with 10 bits precision (16 bits resolution at low frequency), and a bias DAC able to output 10 mA to bias a resistive bridge sensor on 8 bits resolution. Both are DACs formed from a generic DAC and an amplifier. This makes possible current and voltage drive and lets full freedom for the user to choose the preferred filtering scheme. 15 Analog outputs 15.1.4 XX-XE88LC01/03/05, Data Book The generic DAC Preliminary information The generic DAC block consists of two major parts: the noise shaper (sigma-delta modulator) and the PWM modulator as shown in Figure 15.2. Figure 15.2: The DAC signal structure The DAC word width at the input is 16 bit. If the word is narrower, 0's have to be added after the LSB to fill the 16 bits. To maintain maximum flexibility, the order of the noise shaper and the resolution of the PWM modulation are programmable by writing the codes code_lmax and ns_order to the configuration register. The possible noise shaper order is 0, 1 or 2. With noise shaper order 0, the generic DAC is a conventional PWM DAC which resolution can be set between 4 and 11 bits. Higher resolutions are reached with higher orders of the noise shaper. The role of the sigma-delta modulator is to vary the code sent to the PWM modulator, so that its mean value is exactly equal to the code set in the DAC input. Regular way of using the DAC is to set code_lmax for 4 bits (000) and ns_order to 2 (10). DACs and filter settings are explained in application note AN8000.03 "XE88LC05 DACs usage". 15.1.5 The amplifier The amplifier can be used in several configurations. Therefore, it is not connected internally. sym description min gain GBW0 cl0 GBW1 cl1 fm rl SR CMR OR voff CMRR noise PSRR ibias ioff gain at DC gain bandwidth product capacitive load gain bandwidth product capacitive load phase margin resistive load slew rate common mode input range output range offset common mode rejection integrated input noise power supply rejection ratio quiescent bias current off current 80 25 typ max 5 125 200 55 5 10 vss-0.2 vss+0.2 vdd-1.2 vdd-0.2 5 60 100 20 200 500 1 unit Comments dB kHz nF kHz pF kohm kV/s V V mV dB uVrms dB uA uA 1 7 7 8 8 9 6 10 2 3 4 Table 15.1: DAC signal amplifier performances Note: Note: Note: Note: Note: Note: Note: Note: 1. For the minimal resistive load and the maximal capacitive load 2. The amplifier common mode is vss in the 4-20mA loop (Figure 6). 3. At DC 4. At DC. Only a low rejection ratio is needed since the DAC output refers directly to the power supplies. 6. Short circuit protection at ~5mA. 7. GBW when the maximal load is cl0 and with the bit BW=0 8. GBW when the maximal load is cl1 and with the bit BW=1 9. In both cases BW=0 and BW=1 for the maximal capacitive load and the minimal resistive load. Page 112 XX-XE88LC01/03/05, Data Book 15 Analog outputs 10. For maximal load cl0, BW=0 and maximal resistive load rl 15.1.6 Signal DAC registers register name address (hex) comments RegDasInLsb RegDasInMsb RegDasCfg0 RegDasCfg1 H0068 H0069 H006A H006B input code (LSB) input code (MSB) DAC settings Table 15.2: Signal DAC registers bit name reset rw description 7-6 5-3 2-1 0 NsOrder CodeImax Enable Fin 0 resetsystem 0 resetsystem 0 resetsystem 0 resetsystem rw rw rw rw modulator order PWM resolution DAC and buffer enable input frequency selection Table 15.3: RegDasCfg0 bit name reset rw description 7-2 1 0 reserved BW Inv 0 resetsystem 0 resetsystem 0 resetsystem rw rw rw output bandwidth selection output polarity selection Table 15.4: RegDasCfg1 The CPU communicates with the peripheral through registers. Two registers are needed for the data input, two are needed for the set-up of the peripheral. The registers are defined in Table 15.2. The data in the set-up registers code for the noise shaper order (ns_order), the resolution of the PWM pulse modulation (code_lmax), the peripheral status (enable), clock input frequency (fin), if the PWM pulse is active low or high (inv) and the amplifier bandwidth. The input data will have to be resynchronized with respect to the peripheral clock. In order to guarantee the synchronization of the MSB and LSB part of the input data, a validity flag is reset when the CPU is writing in the LSB register and set again when the CPU is writing to the MSB register. The contents of the registers is not copied to the DAC while the validity flag is reset. This means that the CPU always has to write the LSB register before writing the MSB register. The different set-up words (set-up register definition in Table 15.2) are coded as indicated in the tables below. ns_order(1:0) Noise shaping order 00 01 1x 0 (PWM operation) 1 2 Table 15.5: Noise shaping setting code_lmax m (PWM resolution in bits) 000 001 010 011 100 101 110 111 4 5 6 7 8 9 10 11 Table 15.6: PWM setting enable(1:0) Peripheral status 00 DAC: switched off; Amplifier switched off Table 15.7: DAC status Page 113 Preliminary information Note: 15 Analog outputs XX-XE88LC01/03/05, Data Book enable(1:0) Peripheral status 01 10 11 DAC: normal operation; Amplifier: switched off DAC: switched off; Amplifier: normal operation normal operation Table 15.7: DAC status Preliminary information The Fin bit allows the choice between two clock inputs that can be connected in two different places of the prescaler of the XE8000. The control logic has to guarantee correct switching from one to the other. fin used clock input 0 1 RC clock RC clock div 2 Table 15.8: Clock setting Finally, the inv bit indicates if the PWM output pulse is active low or active high. This allows the use of the output amplifier in an inverting or not inverting configuration. inv PWM pulse 0 1 active high active low Table 15.9: PWM polarity Page 114 XX-XE88LC01/03/05, Data Book 15.2 15.2.1 15 Analog outputs Bias DAC Application The bias DAC block converts a digital signal into an analog output signal in DC. It can be used to bias resistive sensors. In some cases it could also be used to do a rough offset calibration of a resistive bridge. 15.2.2 Typical external components 15.2.3 Block diagram Figure 15.3: General block diagram of the bias DAC Figure 15.3 shows the general block diagram of the peripheral. It consists of a control block that manages all communication with the CPU, sets the configuration of the peripheral and implements the different test modes. The DAC converts the digital data in an analog output signal. An amplifier is added in order to be able to deliver large currents. 15.2.4 The DAC The DAC convertor is a resistive divider connected between pads DAB_R_m and DAB_R_p. sym description wda tstep range number of input bits step response DAC output range min typ max unit 8 100 DAB_R_p DAB_R_m Comments bits ms 1 2 Table 15.10: DAC performances Note: Note: 15.2.5 1) Time to reach the final value within 5%. 2) In most cases DAB_R_m will be connected to vss and DAB_R_p to vdd. The amplifier The amplifier can be used in several configurations as for biasing a bridge in voltage or current. Application examples are given in application note AN8000.03. sym description min gain GBW gain at DC gain bandwidth product 60 100 typ max unit Comments dB Hz 1 1 Table 15.11: Amplifier performances Page 115 Preliminary information No other external devices are needed in case of voltage controlled bridge bias. An additional resistor is needed for current controlled bridge bias. Preliminary information 15 Analog outputs XX-XE88LC01/03/05, Data Book sym description min fm rl cl CMR OR outp vr voff noise isourc PSRR ibias ioff phase margin resistive load capacitive load common mode input range output range outp pin voltage range offset integrated input noise max source current power supply rejection ratio quiescent bias current off current 60 300 typ max 100000 1 vdd vdd-0.2 vdd 10 100 10 vss vss+0.2 vss+2.3 40 2 5 1 unit Comments ohm nF V V V mV uVrms mA dB uA uA 1 5,6 3,4 5 2 6 Table 15.11: Amplifier performances Note: Note: Note: Note: Note: Note: 1) For all possible combinations of resistive load and capacitive load. 2) At DC. 3) For voltage controlled bias control. For current controlled operation the voltage drop on the pMOS output transistor has to be less than 200mV at maximum current. 4) Special analog output pads without series resistor will be needed in order to get the specification. Care has to be taken with the layout so that ESD and latchup specifications can be met. 5) Short circuit protection at ~80mA. 6) This amplifier must be loaded for correct operation. Ibias is without load current. 15.2.6 Bias DAC registers register name address (hex) comments RegDab1In RegDab1Cfg H006C H006D input code DAC settings Table 15.12: Bias DAC registers enable(1:0) Peripheral status 00 01 10 11 DAC disabled, amplifier disabled DAC: normal operation; Amplifier: switched off DAC: switched off; Amplifier: normal operation DAC: enabled; Amplifier: enabled Table 15.13: RegDab1Cfg Page 116 XX-XE88LC01/03/05, Data Book 16 Pin-out, package and electrical specifications 16 Pin-out, package and electrical specifications All chips of the XE8000 family are available either as bare die or packaged. 16.1 XE88LC01 pin-out 1 2 3 4 40 38 36 XEMICS Preliminary information device type 42 34 32 31 XE88LC01MI 30 5 N9K1444 7 9920 29 8 26 9 25 6 28 27 production lot identification packaging date 24 10 12 14 18 16 20 22 Pinout of the XE88LC01 in TQFP44 package Pin Position in TQFP44 Function name 1 2 3 4 5 6 7 8 9 10 11 PA(5) PA(6) PA(7) PC(0) PC(1) PC(2) PC(3) PC(4) PC(5) PC(6) PC(7) 12 PB(0) 13 PB(1) Input/Output/Analog 14 PB(2) Input/Output/Analog 15 PB(3) SOU Input/Output/Analog 16 PB(4) SCL Input/Output/Analog 17 PB(5) SIN Input/Output/Analog 18 PB(6) Tx Input/Output/Analog 19 PB(7) Rx Input/Output/Analog 20 VPP/TEST Vhigh Special 21 AC_R(3) Analog 22 AC_R(2) Analog 23 AC_A(7) Analog Second function name Type Input Input Input Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output testout Input/Output/Analog Description Input of Port A Input of Port A Input of Port A Input-Output of Port C Input-Output of Port C Input-Output of Port C Input-Output of Port C Input-Output of Port C Input-Output of Port C Input-Output of Port C Input-Output of Port C Input-Output-Analog of Port B/ Data output for test and MTP programing/ PWM output Input-Output-Analog of Port B/ PWM output Input-Output-Analog of Port B Input-Output-Analog of Port B, Output pin of USRT Input-Output-Analog of Port B/ Clock pin of USRT Input-Output-Analog of Port B/ Data input or input-output pin of USRT Input-Output-Analog of Port B/ Emission pin of UART Input-Output-Analog of Port B/ Reception pin of UART Test mode/High voltage for MTP programing Highest potential node for 2nd reference of ADC Lowest potential node for 2nd reference of ADC ADC input node Pin-out of the XX-XE88LC01 in TQFP44 Page 117 16 Pin-out, package and electrical specifications XX-XE88LC01/03/05, Data Book Preliminary information Pin Position in TQFP44 Function name 24 25 26 27 28 29 30 AC_A(6) AC_A(5) AC_A(4) AC_A(3) AC_A(2) AC_A(1) AC_A(0) Analog Analog Analog Analog Analog Analog Analog 31 AC_R(1) Analog 32 AC_R(0) Analog Second function name Type 33 VSS Power 34 35 36 37 Vbat Vreg RESET Vmult Power Analog Input Analog 38 OscIn ck_cr Analog/Input 39 OscOut ptck Analog/Input 40 PA(0) testin Input 41 PA(1) testck Input 42 PA(2) Input 43 PA(3) Input 44 PA(4) Input Pin-out of the XX-XE88LC01 in TQFP44 Page 118 Description ADC input node ADC input node ADC input node ADC input node ADC input node ADC input node ADC input node Highest potential node for 1st reference of ADC Lowest potential node for 1st reference of ADC Negative power supply, connected to substrate Positive power supply Regulated supply Reset pin (active high) Pad for optional voltage multiplier capacitor Connection to Xtal/ CoolRISC clock for test and MTP programing Connection to Xtal/ Peripheral clock for test and MTP programing Input of Port A/ Data input for test and MTP programing/ Counter A input Input of Port A/ Data clock for test and MTP programing/ Counter B input Input of Port A/ Counter C input/ Counter capture input Input of Port A/ Counter D input/ Counter capture input Input of Port A XX-XE88LC01/03/05, Data Book XE88LC03 pin-out 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 RCRes RESET PB[7] PB[6] PB[5] PB[4] PB[3] PB[2] PB[1] PB[0] PC[3] PC[2] PC[1] PC[0] 30 1 2 3 4 26 24 XEMICS 22 XX88LC03MI 5 N9K1444 6 7 9920 8 Pinout of the XX-XE88LC03 in SOP28 package 10 12 14 20 device type production lot identification packaging date 18 16 Pinout of the XX-XE88LC03 in TQFP32 Pin Second function name Position in SO28 Position in TQFP32 Function name 1 2 13 14 Vbat Vreg 3 15 TEST/Vhigh Vhigh Special 4 16 OscOut ptck Analog/Input 5 17 OscIn ck_cr Analog/Input 6 18 Vss 7 19 PA(0) testin Input 8 20 PA(1) testck Input 9 21 PA(2) Input 10 22 PA(3) Input 11 12 13 14 15 16 17 18 23 24 25 26 27 28 29 30 31 32 1 2 PA(4) PA(5) PA(6) PA(7) PC(0) PC(1) PC(2) PC(3) PC(4) PC(5) PC(6) PC(7) Input Input Input Input Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output 19 3 PB(0) 20 4 PB(1) Type Power Analog Power testout 28 Input/Output/Analog Input/Output/Analog 21 5 PB(2) 22 6 PB(3) SOU Input/Output/Analog Input/Output/Analog 23 7 PB(4) SCL Input/Output/Analog Description Positive power supply Regulated supply Test mode/High voltage for MTP programing Connection to Xtal/ Peripheral clock for test and MTP programing Connection to Xtal/ CoolRISC clock for test and MTP programing Negative power supply, connected to substrate Input of Port A/ Data input for test and MTP programing/ Counter A input Input of Port A/ Data clock for test and MTP programing/ Counter B input Input of Port A/ Counter C input/ Counter capture input Input of Port A/ Counter D input/ Counter capture input Input of Port A Input of Port A Input of Port A Input of Port A Input-Output of Port C Input-Output of Port C Input-Output of Port C Input-Output of Port C Input-Output of Port C Input-Output of Port C Input-Output of Port C Input-Output of Port C Input-Output-Analog of Port B/ Data output for test and MTP programing/ PWM output Input-Output-Analog of Port B/ PWM output Input-Output-Analog of Port B Input-Output-Analog of Port B, Output pin of USRT Input-Output-Analog of Port B/ Clock pin of USRT Pin-out of the XX-XE88LC03 in SO28 and TQFP32 Page 119 Preliminary information VBat VReg TEST/VHigh OSCout OSCin/FREQin Vgnd PA[0] PA[1] PA[2] PA[3] PA[4] PA[5] PA[6] PA[7] XEMICS XX88LC03xI015 9920 16.2 16 Pin-out, package and electrical specifications Preliminary information 16 Pin-out, package and electrical specifications XX-XE88LC01/03/05, Data Book Position in SO28 Position in TQFP32 Function name Pin Second function name 24 8 PB(5) SIN Input/Output/Analog 25 9 PB(6) Tx Input/Output/Analog 26 10 PB(7) Rx Input/Output/Analog 27 28 11 12 RESET RCRes Type Pin-out of the XX-XE88LC03 in SO28 and TQFP32 Page 120 Input Analog Description Input-Output-Analog of Port B/ Data input or input-output pin of USRT Input-Output-Analog of Port B/ Emission pin of UART Input-Output-Analog of Port B/ Reception pin of UART Reset pin (active high) Optional external resistor for RC oscillator XX-XE88LC01/03/05, Data Book 53 DAS_Out DAS_AI_p DAS_AI_m 55 DAS_AO 57 51 48 PA(0) 1 PA(1) 2 47 PA(2) 3 46 AC_R(0) PA(3) 4 45 AC_R(1) PA(4) 5 44 AC_A(0) PA(5) PA(6) 6 43 AC_A(1) 7 42 AC_A(2) PA(7) 8 41 AC_A(3) PC(0) 9 40 AC_A(4) PC(1) 10 39 AC_A(5) PC(2) 11 38 AC_A(6) PC(3) 12 37 AC_A(7) PC(4) 13 36 AC_R(2) PC(5) 14 35 AC_R(3) PC(6) 15 34 PC(7) 16 18 TEST DAB_AI_m DAB_Out DAB_AO_p 33 30 DAB_AI_p 28 DAB_AO_m 26 DAB_R_m DAB_R_p PB(4) PB(5) 24 PB(7) 22 PB(6) 20 PB(3) PB(2) PB(0) PB(1) XEMICS XE88LC05x028 Figure 16.1: Pinout of the XE88LC05 in TQFP64 package Position Function name Pin Second function name 1 PA(0) testin Input 2 PA(1) testck Input 3 PA(2) Input 4 PA(3) Input 5 6 7 8 9 10 11 12 13 14 15 16 PA(4) PA(5) PA(6) PA(7) PC(0) PC(1) PC(2) PC(3) PC(4) PC(5) PC(6) PC(7) Input Input Input Input Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output 17 PB(0) 18 PB(1) Input/Output/Analog 19 PB(2) Input/Output/Analog testout Type Input/Output/Analog Description Input of Port A/ Data input for test and MTP programing/ Counter A input Input of Port A/ Data clock for test and MTP programing/ Counter B input Input of Port A/ Counter C input/ Counter capture input Input of Port A/ Counter D input/ Counter capture input Input of Port A Input of Port A Input of Port A Input of Port A Input-Output of Port C Input-Output of Port C Input-Output of Port C Input-Output of Port C Input-Output of Port C Input-Output of Port C Input-Output of Port C Input-Output of Port C Input-Output-Analog of Port B/ Data output for test and MTP programing/ PWM output Input-Output-Analog of Port B/ PWM output Input-Output-Analog of Port B Table 16.1: Pin-out of the XE88LC05 in TQFP64 Page 121 Preliminary information 59 Vbat 61 Vss_Vreg Vss RESET Vmult 63 Vreg OscIn OscOut XE88LC05 pin-out RCRes 16.3 Preliminary information XX-XE88LC01/03/05, Data Book Position Function name Pin Second function name 20 PB(3) SOU Input/Output/Analog 21 PB(4) SCL Input/Output/Analog 22 PB(5) SIN Input/Output/Analog 23 PB(6) Tx Input/Output/Analog 24 PB(7) Rx Input/Output/Analog 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47-50 51 52 53 54 55 56 57 58 59 60 61 DAB_R_p DAB_R_m DAB_Out DAB_AO_p DAB_AO_m DAB_AI_p DAB_AI_m 62 OscOut ptck Analog/Input 63 OscIn ck_cr Analog/Input 64 RCRes TEST/Vhigh Vhigh AC_R(3) AC_R(2) AC_A(7) AC_A(6) AC_A(5) AC_A(4) AC_A(3) AC_A(2) AC_A(1) AC_A(0) AC_R(1) AC_R(0) DAS_Out DAS_AI_p DAS_AI_m DAS_AO Vbat/VDD Vss Vss_Reg Vreg Vmult RESET Type Analog Analog Analog Analog Analog Analog Analog Not connected Special Not connected Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Not connected Analog Analog Analog Analog Power Power Power Analog Not connected Analog Input Analog Table 16.1: Pin-out of the XE88LC05 in TQFP64 Page 122 Description Input-Output-Analog of Port B, Output pin of USRT Input-Output-Analog of Port B/ Clock pin of USRT Input-Output-Analog of Port B/ Data input or input-output pin of USRT Input-Output-Analog of Port B/ Emission pin of UART Input-Output-Analog of Port B/ Reception pin of UART Positive reference of bias DAC Negative reference of bias DAC Output of bias DAC Highest potential output of bias DAC buffer Lowest potential output of bias DAC buffer Positive input of bias DAC buffer Negative input of bias DAC buffer Spare pin to be connected to negative power supply Test mode/High voltage for MTP programing Spare pin to be connected to negative power supply Highest potential node for 2nd reference of ADC Lowest potential node for 2nd reference of ADC ADC input node ADC input node ADC input node ADC input node ADC input node ADC input node ADC input node ADC input node Highest potential node for 1st reference of ADC Lowest potential node for 1st reference of ADC Spare pins to be connected to negative power supply Output of signal DAC Positive input of signal DAC buffer Negative input of signal DAC buffer Output of signal DAC buffer Positive power supply Negative power supply, connected to substrate Digital negative power supply, must be equal to Vss Regulated supply Spare pin to be connected to negative power supply Pad for optional voltage multiplier capacitor Reset pin (active high) Connection to Xtal/ Peripheral clock for test and MTP programing Connection to Xtal/ CoolRISC clock for test and MTP programing Optional external resistor for RC oscillator XX-XE88LC01/03/05, Data Book 16.4.1 Electrical specifications Absolute maximum ratings name value Maximal voltage applied between any pin (but VPP/TEST) and VSS Voltage applied to any pin (but VPP/TEST) Storage temperature (no programmed) Storage temperature (programmed) 5.5 V VSS - 0.3 V to VDD + 0.3 V 150 C 85 C Table 16.2: Absolute maximum ratings 16.4.2 Operating conditions name value Voltage applied between VDD and VSS (ROM version, without ADC or DAC) Voltage applied between VDD and VSS (MTP version, or ROM version with ADC or DAC) Operating temperature (ROM) Operating temperature (MTP) 1.2 - 5.5 V 2.4 - 5.5 V -40 - 125C -40 - 85 C Table 16.3: Operating conditions 16.4.3 sym IO pins operation description Port A: low threshold limit Port A: high threshold limit output drop when sinking 1 mA output drop when sourcing 1 mA Port A: low threshold limit Port A: high threshold limit output drop when sinking 1 mA output drop when sinking 8 mA output drop when sourcing 1 mA output drop when sourcing 8 mA Port A: low threshold limit Port A: high threshold limit output drop when sinking 1 mA output drop when sinking 8 mA output drop when sourcing 1 mA output drop when sourcing 8 mA pull-up, pull-down resistor condition min typ Vbat = 1.2 V max 0.4 0.4 1 1.5 Vbat = 2.4 V 0.4 0.4 2 3 Vbat = 5.0 V 0.4 50 0.4 150 unit Comments V V V V V V V V V V V V V V V V kohm Table 16.4: IO pins performances Page 123 Preliminary information 16.4 Preliminary information XX-XE88LC01/03/05, Data Book Page 124 20000327 17 Index 17 Index Numerics 16 bit counters A Absolute Absolute maximum ratings Active mode ADC analog to digital converter Operation mode 90 123 123 47 103 103 C Capture functions Conventions CoolRISC 816 Architecture 816 core Instruction set Counters Current requirement 28 25 29 87 24 H Harvard 43 I input reference multiplexing input signal multiplexing Instruction Set L Low power 92 15 104 103 29 21, 24 M Mode Active 47 Sleep 47 Standby 47 MTP 17, 43 Multiple Time Programmable Flash memory 43 O Operating conditions 20000327 P pins operation Pipeline Power supply range Prescaler PWM 21 123 25 21 65 94, 95 R Resets 49 S Sleep mode StandBy mode 47 47 T Timers 87 V Voltage multiplier Voltage regulator VSS 23 22 15 W Watchdog 87 X XE8000 XE88LC01 XE88LC02 XE88LC03 XE88LC04 XE88LC05 17 17 17 17 18 18 Z zooming ADC 103 123 Page 125 Preliminary information XX-XE88LC01/03/05, Data Book Preliminary information 17 Index Page 126 XX-XE88LC01/03/05, Data Book XX-XE88LC01/03/05, Data Book 18 Contact 18 Contact One can contact XEMICS at info@xemics.com or on our web site at http://www.xemics.com. List of contacts, representatives and distributors can be found on the web at http://www.xemics.com/contact.html. XEMICS Headquarters is XEMICS SA Maladiere 71 2007 Neuchatel Switzerland Page 127 Preliminary information Application notes can be found on the web at http://www.xemics.com/downldata.html. XX-XE88LC01/03/05, Data Book Preliminary information 18 Contact Page 128 xxDB004-74