Supertex inc.
Supertex inc.
www.supertex.com
Doc.# DSFP-LP0701
B071513
LP0701
Absolute Maximum Ratings
Parameter Value
Drain-to-source voltage BVDSS
Drain-to-gate voltage BVDGS
Gate-to-source voltage ±10V
Operating and storage temperature -55°C to +150°C
Absolute Maximum Ratings are those values beyond which damage to the device may
occur. Functional operation under these conditions is not implied. Continuous operation
of the device at the absolute rating level may affect device reliability. All voltages are
referenced to device ground.
Pin Conguration
TO-928-Lead SOIC
D
D
D
D
G
S
NC
NC
Features
►Ultra-low threshold
►High input impedance
►Low input capacitance
►Fast switching speeds
►Low on-resistance
►Freedom from secondary breakdown
►Low input and output leakage
Applications
►Logic level interfaces
►Solid state relays
►Battery operated systems
►Photo voltaic drives
►Analog switches
►General purpose line drivers
P-Channel Enhancement-Mode
Lateral MOSFET
General Description
These enhancement-mode (normally-off) transistors utilize
a lateral MOS structure and Supertex’s well-proven silicon-
gate manufacturing process. This combination produces
devices with the power handling capabilities of bipolar
transistors and with the high input impedance and negative
temperature coefcient inherent in MOS devices.
Characteristic of all MOS structures, these devices are free
from thermal runaway and thermally induced secondary
breakdown. The low threshold voltage and low on-resistance
characteristics are ideally suited for hand held, battery
operated applications.
Product Marking
8-Lead SOIC
YY = Year Sealed
WW = Week Sealed
= “Green” Packaging
SiLP
0701
YYWW
TO-92
YY = Year Sealed
WW = Week Sealed
L = Lot Number
= “Green” Packaging
YYWW
P0701
LLLL
Package may or may not include the following marks: Si or
Package may or may not include the following marks: Si or
GATE
SOURCE
DRAIN
Product Summary
BVDSS/BVDGS RDS(ON) VGS(TH) ID(ON)
-16.5V 3.0kΩ -1.0V (max) 3.0mA (min)
-G denotes a lead (Pb)-free / RoHS compliant package
Refer to ‘P0xx’ Tape & Reel Specs for P002, P003, P005, P013, and P014
TO-92 Taping Specications and Winding Styles
Part Number Package Options Packing
LP0701LG-G 8-Lead SOIC 2500/Reel
LP0701N3-G TO-92 1000/Bag
LP0701N3-G P002 TO-92 2000/Reel
LP0701N3-G P003 TO-92 2000/Reel
LP0701N3-G P005 TO-92 2000/Reel
LP0701N3-G P013 TO-92 2000/Reel
LP0701N3-G P014 TO-92 2000/Reel
Ordering Information
2
Supertex inc.
www.supertex.com
Doc.# DSFP-LP0701
B071513
LP0701
Thermal Characteristics
Package
ID
(continuous)†
(mA)
ID
(pulsed)†
(A)
Power Dissipation
@TC = 25OC
(W)
θja
(OC/W)
IDR
(mA)
IDRM
†
(A)
8-Lead SOIC -700 -1.25 1.5‡101‡-700 -1.25
TO-92 -500 -1.25 1.0 132 -500 -1.25
Notes:
† ID (continuous) is limited by max rated Tj.
‡ Mounted on FR4 board, 25mm x 25mm x 1.57mm
Sym Parameter Min Typ Max Units Conditions
BVDSS Drain-to-source breakdown voltage -16.5 - - V VGS = 0V, ID = -1.0mA
VGS Gate threshold voltage -0.5 -0.7 -1.0 V VGS = VDS, ID = -1.0mA
ΔVGS(th) Change in VGS(th) with temperature - - -4.0 mV/OC VGS = VDS, ID = -1.0mA
IGSS Gate body leakage - - -100 nA VGS = ±10V, VDS = 0V
IDSS Zero gate voltage drain current
- - -100 nA VDS = -15V, VGS = 0V
- - -1.0 mA VDS = 0.8 Max Rating,
VGS = 0V, TA = 125OC
ID(ON) On-state drain current
- -0.4 -
A
VGS = VDS = -2.0V
-0.6 -1.0 - VGS = VDS = -3.0V
-1.25 -2.30 - VGS = VDS = -5.0V
RDS(ON)
Static drain-to-source on-state
resistance
- 2.0 4.0
Ω
VGS = -2.0V, ID = -50mA
- 1.7 2.0 VGS = -3.0V, ID = -150mA
- 1.3 1.5 VGS = -5.0V, ID = -300mA
ΔRDS(ON) Change in RDS(ON) with temperature - - 0.75 %/OC VGS = -5.0V, ID = -300mA
GFS Forward transconductance 500 700 - mmho VGS = -15V, ID = -1.0A
CISS Input capacitance - 120 250
pF
VGS = 0V,
VDS = -15V,
f = 1.0MHz
COSS Common source output capacitance - 100 125
CRSS Reverse transfer capacitance - 40 60
td(ON) Turn-on delay time - - 20
ns
VDD = -15V,
ID = -1.25A,
RGEN = 25Ω
trRise time - - 20
td(OFF) Turn-off delay time - - 30
tfFall time - - 30
VSD Diode forward voltage drop - -1.2 -1.5 V VGS = 0V, ISD = -500mA
Notes:
1. All D.C. parameters 100% tested at 25OC unless otherwise stated. (Pulse test: 300µs pulse, 2% duty cycle.)
2. All A.C. parameters sample tested.
Electrical Characteristics (TA = 25°C unless otherwise specied)
90%
10%
90% 90%
10%
10%
Pulse
Generator
VDD
R
L
OUTPUT
D.U.T.
t
(ON)
t
d(ON)
t
(OFF)
t
d(OFF)
t
f
t
r
INPUT
R
GEN
INPUT
OUTPUT
0V
VDD
0V
-10V
Switching Waveforms and Test Circuit
3
Supertex inc.
www.supertex.com
Doc.# DSFP-LP0701
B071513
LP0701
Typical Performance Curves
Saturation Characteristics
0-1-2-
3-
5-4
Maximum Rated Safe Operating Area
-0.1 -100-10-1.0
-0.1
-1.0
-10
-0.01
Thermal Response Characteristics
Thermal Resistance (normalized)
1.0
0.8
0.6
0.4
0.2
0.00
11
00.01 0.1 1.0
Transconductance vs. Drain Current
1.0
0.8
0.6
0.4
0.2
00-2.0
-1.0
Power Dissipation vs. Case Temperature
01
5010050
2
1
01257525
T
A
= -55
O
C
TO-92 (DC)
SO-8 (DC)
TO-92
TO-92/SO-8 (pulsed)
-4V
-3V
-2V
-1V
-2.5
-2.0
-1.5
-1.0
-0.5
0
0
Output Characteristics
-2.5
-2.0
-1.5
-1.0
-0.5
00-4-8-12 -16
V
GS
= -5.0V
-4V
-3V
-2V
-1V
I
D
(amperes)
V
DS
(volts)
G
FS
(seimens)
P
D
(watts)
T
C
(
O
C)
I
D
(amperes)
V
DS
(volts) t
p
(seconds)
TO-92
T
C
= 25V
P
D
= 1.0W
SO-8
I
D
(amperes)
V
DS
(volts)
I
D
(amperes)
V
GS
= -5.0V
V
DS
= -15V
T
A
= 25
O
C
T
A
= 125
O
C
T
C
= 25
O
C
4
Supertex inc.
www.supertex.com
Doc.# DSFP-LP0701
B071513
LP0701
Typical Performance Curves (cont.)
Gate Drive Dynamic Characteristics
Q
G
(nanocoulombs)
V
GS(th)
(normalized)
R
DS(ON)
(normalized)
V
(th)
and R
DS
Variation with Temperature
On-Resistance vs. Drain Current
BV
DSS
Variation with Temperature
BV
DSS
(normalized)
Transfer Characteristics
Capacitance vs. Drain-to-Source Voltage
200
C (picofarads)
0-5 -10 -15
100
0-1-2-3-4-5
-2
-1
-500 50 100150
1.1
10
8
6
4
2
00
-3
1.4
1.2
1.0
0.8
0.6
0.4
1.6
1.4
1.2
1.0
0.8
0.6
-10
-8
-6
-4
-2
0012345
-50 050 100 150
238pF
f = 1.0MHz
-1 -2
-20V
0
V
DS
= -15V
0.9
1.0
C
ISS
= 115pF
RDS(ON) @ -5V, -300mA
0
T
A
= 125
O
C
V
GS
= -2.0V
I
D
(amperes)
T
J
(
O
C)
R
DSS(ON)
(ohms)
I
D
(amperes)
V
GS (volts)
V
DS
= -10V
V
DS
(volts)
V
GS
(volts)
C
ISS
C
OSS
C
RSS
T
J
(
O
C)
V
GS
= -3.0V
V
GS
= -5.0V
T
A
= 25
O
C
T
A
= -55
O
C
V
(th)
@ -1.0mA
5
Supertex inc.
www.supertex.com
Doc.# DSFP-LP0701
B071513
LP0701
1
8
Seating
Plane
Gauge
Plane
L
L1
L2
EE1
D
eb
AA2
A1
Seating
Plane
A
A
Top View
Side View
View B View B
θ1
θ
Note 1
(Index Area
D/2 x E1/2)
View A-A
h
h
Note 1
Symbol A A1 A2 b D E E1 e h L L1 L2 θ θ1
Dimension
(mm)
MIN 1.35* 0.10 1.25 0.31 4.80* 5.80* 3.80*
1.27
BSC
0.25 0.40
1.04
REF
0.25
BSC
0O5O
NOM - - - - 4.90 6.00 3.90 - - - -
MAX 1.75 0.25 1.65* 0.51 5.00* 6.20* 4.00* 0.50 1.27 8O15O
JEDEC Registration MS-012, Variation AA, Issue E, Sept. 2005.
* This dimension is not specied in the JEDEC drawing.
Drawings are not to scale.
Supertex Doc. #: DSPD-8SOLGTG, Version I041309.
Note:
1. This chamfer feature is optional. A Pin 1 identier must be located in the index area indicated. The Pin 1 identier can be: a molded mark/identier;
an embedded metal marker; or a printed indicator.
8-Lead SOIC (Narrow Body) Package Outline (LG)
Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives
an adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liability
to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and
specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http//www.supertex.com)
©2013 Supertex inc. All rights reserved. Unauthorized use or reproduction is prohibited. Supertex inc.
1235 Bordeaux Drive, Sunnyvale, CA 94089
Tel: 408-222-8888
www.supertex.com
6
LP0701
(The package drawing(s) in this data sheet may not reect the most current specications. For the latest package outline
information go to http://www.supertex.com/packaging.html.)
Doc.# DSFP-LP0701
B071513
3-Lead TO-92 Package Outline (N3)
Symbol A b c D E E1 e e1 L
Dimensions
(inches)
MIN .170 .014†.014†.175 .125 .080 .095 .045 .500
NOM - - - - - - - - -
MAX .210 .022†.022†.205 .165 .105 .105 .055 .610*
JEDEC Registration TO-92.
* This dimension is not specied in the JEDEC drawing.
† This dimension differs from the JEDEC drawing.
Drawings not to scale.
Supertex Doc.#: DSPD-3TO92N3, Version E041009.
Seating
Plane
1
2
3
Front View Side View
Bottom View
E1 E
D
e1
L
e
c
1 2 3
b
A