SCES351I - JUNE 2001 - REVISED AUGUST 2003 D Available in the Texas Instruments D D D D D D D D DBV OR DCK PACKAGE (TOP VIEW) NanoStar and NanoFree Packages Supports 5-V VCC Operation Inputs Accept Voltages to 5.5 V Max tpd of 4.6 ns at 3.3 V Low Power Consumption, 10-A Max ICC 24-mA Output Drive at 3.3 V Ioff Supports Partial-Power-Down Mode Operation Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 - 2000-V Human-Body Model (A114-A) - 200-V Machine Model (A115-A) - 1000-V Charged-Device Model (C101) NC A GND 1 5 VCC 4 Y 2 3 NC - No internal connection YEA, YEP, YZA, OR YZP PACKAGE (BOTTOM VIEW) GND A DNU 3 4 Y 2 1 5 VCC DNU - Do not use description/ordering information This single Schmitt-trigger buffer is designed for 1.65-V to 5.5-V VCC operation. The SN74LVC1G17 contains one buffer and performs the Boolean function Y = A. The device functions as an independent buffer, but because of Schmitt action, it may have different input threshold levels for positive-going (VT+) and negative-going (VT-) signals. NanoStar and NanoFree package technology is a major breakthrough in IC packaging concepts, using the die as the package. ORDERING INFORMATION NanoStar - WCSP (DSBGA) 0.17-mm Small Bump - YEA SN74LVC1G17YEAR NanoFree - WCSP (DSBGA) 0.17-mm Small Bump - YZA (Pb-free) SN74LVC1G17YZAR NanoStar - WCSP (DSBGA) 0.23-mm Large Bump - YEP -40 C to 85C 85 C -40C ORDERABLE PART NUMBER PACKAGE TA Reel of 3000 SOT (SC-70) - DCK _ _ _C7_ SN74LV1G17YEPR NanoFree - WCSP (DSBGA) 0.23-mm Large Bump - YZP (Pb-free) SOT (SOT-23) - DBV TOP-SIDE MARKING SN74LV1G17YZPR Reel of 3000 SN74LVC1G17DBVR Reel of 250 SN74LVC1G17DBVT Reel of 3000 SN74LVC1G17DCKR Reel of 250 SN74LVC1G17DCKT C17_ C7_ Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site. YEA/YZA, YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, * = Pb-free). Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. NanoStar and NanoFree are trademarks of Texas Instruments. Copyright 2003, Texas Instruments Incorporated ! "#$ ! %#&'" ($) (#"! " !%$""! %$ *$ $! $+! !#$! !(( ,-) (#" %"$!!. ($! $"$!!'- "'#($ $!. '' %$$!) POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 SCES351I - JUNE 2001 - REVISED AUGUST 2003 description/ordering information (continued) This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. FUNCTION TABLE INPUT A OUTPUT Y H H L L logic diagram (positive logic) 2 4 A Y absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 6.5 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 6.5 V Voltage range applied to any output in the high-impedance or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 6.5 V Voltage range applied to any output in the high or low state, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA Package thermal impedance, JA (see Note 3): DBV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206C/W DCK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252C/W YEA/YZA package . . . . . . . . . . . . . . . . . . . . . . . . . . . 154C/W YEP/YZP package . . . . . . . . . . . . . . . . . . . . . . . . . . . 132C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The value of VCC is provided in the recommended operating conditions table. 3. The package thermal impedance is calculated in accordance with JESD 51-7. 2 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SCES351I - JUNE 2001 - REVISED AUGUST 2003 recommended operating conditions (see Note 4) Operating VCC Supply voltage VI VO Input voltage Data retention only Output voltage VCC = 1.65 V VCC = 2.3 V IOH MAX 1.65 5.5 VCC = 3 V VCC = 2.3 V 0 5.5 V 0 VCC -4 V -8 mA -24 -32 4 8 16 Low-level output current UNIT V 1.5 -16 High-level output current VCC = 4.5 V VCC = 1.65 V IOL MIN VCC = 3 V 24 VCC = 4.5 V 32 mA TA Operating free-air temperature -40 85 C NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 3 SCES351I - JUNE 2001 - REVISED AUGUST 2003 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VT+ Positive-going input threshold voltage VT- Negative-going input threshold voltage VT Hysteresis (VT+ - VT-) MIN 1.65 V 0.76 1.13 2.3 V 1.08 1.56 3V 1.48 1.92 2.19 2.74 5.5 V 2.65 3.33 1.65 V 0.35 0.59 2.3 V 0.56 0.88 3V 0.89 1.2 4.5 V 1.51 1.97 5.5 V 1.88 2.4 1.65 V 0.36 0.64 2.3 V 0.45 0.78 3V 0.51 0.83 4.5 V 0.58 0.93 0.69 1.04 1.65 V to 4.5 V IOH = -8 mA IOH = -16 mA VOH 1.9 0.1 1.65 V 0.45 2.3 V 0.3 0.4 5 A 10 A 1.65 V to 5.5 V 10 A 3 V to 5.5 V 500 mA 0 ICC One input at VCC - 0.6 V, IO = 0 Other inputs at VCC or GND V 0.55 0 to 5.5 V VI = 5.5 V or GND, V 0.55 4.5 V ICC V 3.8 3V VI = 5.5 V or GND VI or VO = 5.5 V V V 1.65 V to 4.5 V IOL = 24 mA IOL = 32 mA UNIT 2.3 4.5 V IOL = 8 mA IOL = 16 mA A input 2.3 V 2.4 IOL = 100 A IOL = 4 mA II Ioff 1.65 V VCC-0.1 1.2 3V IOH = -24 mA IOH = -32 mA VOL MAX 4.5 V 5.5 V IOH = -100 A IOH = -4 mA TYP VCC Ci VI = VCC or GND All typical values are at VCC = 3.3 V, TA = 25C. 3.3 V 4.5 pF switching characteristics over recommended operating free-air temperature range, CL = 15 pF (unless otherwise noted) (see Figure 1) PARAMETER tpd 4 FROM (INPUT) TO (OUTPUT) A Y POST OFFICE BOX 655303 VCC = 1.8 V 0.15 V VCC = 2.5 V 0.2 V VCC = 3.3 V 0.3 V VCC = 5 V 0.5 V MIN MAX MIN MAX MIN MAX MIN MAX 2.8 9.9 1.6 5.5 1.5 4.6 0.9 4.4 * DALLAS, TEXAS 75265 UNIT ns SCES351I - JUNE 2001 - REVISED AUGUST 2003 switching characteristics over recommended operating free-air temperature range, CL = 30 pF or 50 pF (unless otherwise noted) (see Figure 2) PARAMETER tpd FROM (INPUT) TO (OUTPUT) A Y VCC = 1.8 V 0.15 V VCC = 2.5 V 0.2 V VCC = 3.3 V 0.3 V VCC = 5 V 0.5 V MIN MAX MIN MAX MIN MAX MIN MAX 3.8 11 2 6.5 1.8 5.5 1.2 5 UNIT ns operating characteristics, TA = 25C PARAMETER Cpd Power dissipation capacitance TEST CONDITIONS f = 10 MHz POST OFFICE BOX 655303 VCC = 1.8 V TYP VCC = 2.5 V TYP 20 * DALLAS, TEXAS 75265 21 VCC = 3.3 V TYP 22 VCC = 5 V TYP 26 UNIT pF 5 SCES351I - JUNE 2001 - REVISED AUGUST 2003 PARAMETER MEASUREMENT INFORMATION RL From Output Under Test CL (see Note A) VLOAD Open S1 GND RL TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open VLOAD GND LOAD CIRCUIT INPUTS VCC 1.8 V 0.15 V 2.5 V 0.2 V 3.3 V 0.3 V 5 V 0.5 V VI tr/tf VCC VCC 3V VCC 2 ns 2 ns 2.5 ns 2.5 ns VM VLOAD CL RL V VCC/2 VCC/2 1.5 V VCC/2 2 x VCC 2 x VCC 6V 2 x VCC 15 pF 15 pF 15 pF 15 pF 1 M 1 M 1 M 1 M 0.15 V 0.15 V 0.3 V 0.3 V VI Timing Input VM 0V tw tsu VI Input VM VM th VI Data Input VM VM 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VI VM Input VM 0V tPLH tPHL VOH VM Output VM VOL tPHL Output Waveform 1 S1 at VLOAD (see Note B) tPLH VM VM VM 0V tPZL tPLZ VLOAD/2 VM tPZH VOH Output VI Output Control VM VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS Output Waveform 2 S1 at GND (see Note B) VOL + V VOL tPHZ VM VOH - V VOH 0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 . D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms 6 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SCES351I - JUNE 2001 - REVISED AUGUST 2003 PARAMETER MEASUREMENT INFORMATION RL From Output Under Test CL (see Note A) VLOAD Open S1 GND RL TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open VLOAD GND LOAD CIRCUIT INPUTS VCC 1.8 V 0.15 V 2.5 V 0.2 V 3.3 V 0.3 V 5 V 0.5 V VI tr/tf VCC VCC 3V VCC 2 ns 2 ns 2.5 ns 2.5 ns VM VLOAD CL RL V VCC/2 VCC/2 1.5 V VCC/2 2 x VCC 2 x VCC 6V 2 x VCC 30 pF 30 pF 50 pF 50 pF 1 k 500 500 500 0.15 V 0.15 V 0.3 V 0.3 V VI Timing Input VM 0V tw tsu VI Input VM VM th VI Data Input VM VM 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VI VM Input VM 0V tPLH tPHL VOH VM Output VM VOL tPHL Output Waveform 1 S1 at VLOAD (see Note B) tPLH VM VM VM 0V tPZL tPLZ VLOAD/2 VM tPZH VOH Output VI Output Control VM VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS Output Waveform 2 S1 at GND (see Note B) VOL + V VOL tPHZ VM VOH - V VOH 0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 . D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 2. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 7 MECHANICAL DATA MPDS018E - FEBRUARY 1996 - REVISED FEBRUARY 2002 DBV (R-PDSO-G5) PLASTIC SMALL-OUTLINE 0,95 5X 5 0,50 0,20 M 0,30 4 1,70 1,50 1 0,15 NOM 3,00 2,60 3 Gage Plane 3,00 2,80 0,25 0-8 0,55 0,35 Seating Plane 1,45 0,95 0,05 MIN 0,10 4073253-4/G 01/02 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion. Falls within JEDEC MO-178 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 MECHANICAL DATA MPDS025C - FEBRUARY 1997 - REVISED FEBRUARY 2002 DCK (R-PDSO-G5) PLASTIC SMALL-OUTLINE PACKAGE 0,30 0,15 0,65 5 0,10 M 4 1,40 1,10 1 0,13 NOM 2,40 1,80 3 Gage Plane 2,15 1,85 0,15 0-8 0,46 0,26 Seating Plane 1,10 0,80 0,10 0,00 0,10 4093553-2/D 01/02 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion. Falls within JEDEC MO-203 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. 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J) (sn74lvc1g17.pdf, 342 KB) 30 Nov 2004 Download - TI Cross Reference - Training LVC1G17-1.8 LVC1G17-2.5 LVC1G17-3.3 LVC1G17-5.0 Voltage Node (V) 1.8 2.5 3.3 5 Voltage Nodes (V) 1.8 2.5 3.3 5 Vcc min (V) 1.65 1.65 1.65 1.65 Vcc max (V) 5.5 5.5 5.5 5.5 IOH (mA) -4 -8 -24 -32 IOL (mA) 4 8 24 32 tpd max (ns) 11 6.5 5.5 5 ICC (uA) 10 10 10 10 Input Level 1.8V CMOS 2.5V CMOS LV TTL CMOS Output Level 1.8V CMOS 2.5V CMOS LV TTL CMOS No. of Gates 1 1 1 1 Performance Optimized Samples Not Available Samples Not Available Samples Not Available Samples Not Available Inventory Not Available Inventory Not Available Inventory Not Available Inventory Not Available Product Information Save this to your personal library Features Available in the Texas Instruments NanoStarTM and NanoFreeTM Packages Supports 5-V VCC Operation Inputs Accept Voltages to 5.5 V Max tpd of 4.6 ns at 3.3 V Support Low Power Consumption, 10-A Max ICC 24-mA Output Drive at 3.3 V Ioff Supports Partial-Power-Down Mode Operation Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 2000-V Human-Body Model (A114-A) 200-V Machine Model (A115-A) 1000-V Charged-Device Model (C101) NanoStar and NanoFree are trademarks of Texas Instruments. Description This single Schmitt-trigger buffer is designed for 1.65-V to 5.5-V VCC operation. The SN74LVC1G17 contains one buffer and performs the Boolean function Y = A. The device functions as http://focus.ti.com/docs/prod/folders/print/sn74lvc1g17.html (1 of 5) [1/4/2005 5:52:14 PM] - Part Marking Lookup - Part Number Nomenclature Product Folder : SN74LVC1G17 - Single Schmitt-Trigger Buffer an independent buffer, but because of Schmitt action, it may have different input threshold levels for positive-going (VT+) and negative-going (VT-) signals. NanoStarTM and NanoFreeTM package technology is a major breakthrough in IC packaging concepts, using the die as the package. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. Pricing/Packaging/Samples Price Device Packaging Samples Status Temp (oC) Budget Price ($US) | QTY Package Type | Pins Footprints STD Pack QTY Samples SN74LVC1G17DBVR ACTIVE -40 to 85 0.11 | 1KU SOT-23 (DBV) | 5 3000 Request Samples SN74LVC1G17DBVT ACTIVE -40 to 85 0.44 | 1KU SOT-23 (DBV) | 5 250 Not Available SN74LVC1G17DCKR ACTIVE -40 to 85 0.11 | 1KU SC70 (DCK) | 5 3000 Request Samples SN74LVC1G17DCKT ACTIVE -40 to 85 0.44 | 1KU SC70 (DCK) | 5 250 Not Available SN74LVC1G17YEAR ACTIVE -40 to 85 0.23 | 1KU WCSP (YEA) | 5 3000 Request Samples SN74LVC1G17YEPR ACTIVE -40 to 85 0.23 | 1KU WCSP (YEP) | 5 3000 Not Available SN74LVC1G17YZAR ACTIVE -40 to 85 0.23 | 1KU WCSP (YZA) | 5 3000 Request Samples SN74LVC1G17YZPR ACTIVE -40 to 85 0.23 | 1KU WCSP (YZP) | 5 3000 Request Samples Inventory TI Inventory Status SN74LVC1G17DBVR Reported Distributor Inventory As of 9:38 AM GMT, 4 Jan 2005 As of 9:38 AM GMT, 4 Jan 2005 In Stock In Progress QTY | Date Lead Time In Stock Distributor: Region | Company Purchase >10k* SN74LVC1G17DBVT >10k | 17 Jan 2 Weeks >1k Americas | Memec Insight >1k Americas | Arrow >1k Americas | Avnet >1k Europe | Rutronik >1k Americas | DigiKey >1k Europe | Arrow Northern Europe >1k Europe | EBV Elektronik >1k Americas | Newark Electronics As of 9:38 AM GMT, 4 Jan 2005 As of 9:38 AM GMT, 4 Jan 2005 In Stock In Progress QTY | Date Lead Time In Stock Distributor: Region | Company Purchase >10k* SN74LVC1G17DCKR >10k | 9 Feb 4 Weeks 705 Americas | Arrow 228 Europe | Spoerle 57 Asia | P&S As of 9:38 AM GMT, 4 Jan 2005 As of 9:38 AM GMT, 4 Jan 2005 In Stock In Progress QTY | Date Lead Time In Stock Distributor: Region | Company Purchase >10k* SN74LVC1G17DCKT >10k | 17 Jan 2 Weeks >1k Americas | DigiKey >1k Europe | Arrow Northern Europe >1k Americas | Arrow >1k Asia | P&S As of 9:38 AM GMT, 4 Jan 2005 As of 9:38 AM GMT, 4 Jan 2005 In Stock In Progress QTY | Date Lead Time In Stock Distributor: Region | Company Purchase >10k* SN74LVC1G17YEAR >10k | 9 Feb 4 Weeks 167 Asia | P&S As of 9:38 AM GMT, 4 Jan 2005 As of 9:38 AM GMT, 4 Jan 2005 In Stock In Progress QTY | Date Lead Time In Stock Distributor: Region | Company Purchase >10k* SN74LVC1G17YEPR >10k | 18 Feb 6 Weeks >1k Americas | DigiKey As of 9:38 AM GMT, 4 Jan 2005 As of 9:38 AM GMT, 4 Jan 2005 In Stock In Progress QTY | Date Lead Time In Stock Distributor: Region | Company Purchase 0* 6000 | 24 Feb 7 Weeks >1k Americas | Avnet >10k | 25 Feb SN74LVC1G17YZAR As of 9:38 AM GMT, 4 Jan 2005 http://focus.ti.com/docs/prod/folders/print/sn74lvc1g17.html (2 of 5) [1/4/2005 5:52:14 PM] As of 9:38 AM GMT, 4 Jan 2005 View all Distributors Choose a Region Product Folder : SN74LVC1G17 - Single Schmitt-Trigger Buffer In Stock In Progress QTY | Date Lead Time In Stock Distributor: Region | Company Purchase >10k* >10k | 25 Feb SN74LVC1G17YZPR 6 Weeks 215 Americas | DigiKey As of 9:38 AM GMT, 4 Jan 2005 As of 9:38 AM GMT, 4 Jan 2005 In Stock In Progress QTY | Date Lead Time In Stock Distributor: Region | Company Purchase 0* >10k | 14 Mar 10 Weeks >1k Americas | DigiKey * Our information is updated daily, so please check back with us soon if ** Lead time information is not available at this time. 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Quality & Lead (Pb)-Free Data Product Content MTBF/FIT Rate Device Eco Plan* Lead/Ball Finish MSL Rating/Peak Reflow Details Details SN74LVC1G17DBVR Pb-Free (RoHS) CU NIPDAU Level-1-260C-UNLIM View View SN74LVC1G17DBVT Pb-Free (RoHS) CU NIPDAU Level-1-260C-UNLIM View View SN74LVC1G17DCKR Pb-Free (RoHS) CU NIPDAU Level-1-260C-UNLIM View View SN74LVC1G17DCKT Pb-Free (RoHS) CU NIPDAU Level-1-260C-UNLIM View View SN74LVC1G17YEAR None SNPB Level-1-260C-UNLIM View View SN74LVC1G17YEPR None SNPB Level-1-260C-UNLIM View View SN74LVC1G17YZAR None Call TI Call TI View View SN74LVC1G17YZPR None Call TI Call TI View View * May not be currently available - please click on the Product Content Details "View" link in the table above for the latest availability information and additional product content details. If the information you are requesting is not available online at this time, contact one of our Product Information Centers regarding the availability of this information. TI Recommends Technical Documents Datasheets Keep track of what's new SN74LVC1G17 (Rev. J) (sn74lvc1g17.pdf,342 KB) 30 Nov 2004 Download Application Notes Semiconductor Packing Material Electrostatic Discharge (ESD) Protection (szza047.htm,12 KB) 08 Jul 2004 Abstract Selecting the Right Level Translation Solution (Rev. A) (scea035a.htm,12 KB) 22 Jun 2004 Abstract Shelf-Life Evaluation of Lead-Free Component Finishes (szza046.htm,12 KB) 24 May 2004 Abstract Use of the CMOS Unbuffered Inverter in Oscillator Circuits (szza043.htm,12 KB) 06 Nov 2003 Abstract Understanding and Interpreting Standard-Logic Data Sheets (Rev. B) (szza036b.htm,11 KB) 28 May 2003 Abstract Texas Instruments Little Logic Application Report (scea029.htm,12 KB) 01 Nov 2002 Abstract TI IBIS File Creation, Validation, and Distribution Processes (szza034.htm,12 KB) 29 Aug 2002 Abstract 16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B) (szza029b.htm,12 KB) 22 May 2002 Abstract Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices (szza033.htm,12 KB) 10 May 2002 Abstract http://focus.ti.com/docs/prod/folders/print/sn74lvc1g17.html (3 of 5) [1/4/2005 5:52:14 PM] Product Folder : SN74LVC1G17 - Single Schmitt-Trigger Buffer Selecting the Right Texas Instruments Signal Switch (szza030.htm,11 KB) 07 Sep 2001 Abstract Implications of Slow or Floating CMOS Inputs (Rev. C) (scba004c.htm,12 KB) 01 Feb 1998 Abstract Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) (scba012a.htm,12 KB) 01 Aug 1997 Abstract CMOS Power Consumption and CPD Calculation (Rev. B) (scaa035b.htm,12 KB) 01 Jun 1997 Abstract LVC Characterization Information (scba011.htm,11 KB) 01 Dec 1996 Abstract Live Insertion (sdya012.htm,11 KB) 01 Oct 1996 Abstract Input and Output Characteristics of Digital Integrated Circuits (sdya010.htm,12 KB) 01 Oct 1996 Abstract Understanding Advanced Bus-Interface Products Design Guide (scaa029.pdf,253 KB) 01 May 1996 Download View Application Notes for SINGLE-GATES User Guides Signal Switch Data Book (Rev. A) (scdd003a.pdf,19732 KB) 14 Nov 2003 Download LVC and LV Low-Voltage CMOS Logic Data Book (Rev. B) (scbd152b.pdf,13291 KB) 18 Dec 2002 Download LOGIC Pocket Data Book (scyd013.pdf,4835 KB) 05 Dec 2002 Download Simulation Models IBIS Model IBIS MODEL OF SN74LVC162244A (scem477.ibs,246 KB) 17 Dec 2004 ibis / zip IBIS Model of SN74LVC1G17 (Rev. A) (scem299a.ibs,243 KB) 14 Aug 2003 ibis / zip More Literature Design Summary for WCSP Little Logic (Rev. B) (scet007b.pdf,295 KB) 04 Nov 2004 Download Logic Selection Guide Second Half 2004 (Rev. V) (sdyu001v.pdf,5770 KB) 21 Sep 2004 Download Dual- Supply Translation Product Clip (scyb033.pdf,230 KB) 07 Sep 2004 Download Military Semiconductors Selection Guide 2004-2005 (Rev. D) (sgyc003d.pdf,964 KB) 10 Aug 2004 Download SN74LVC1G97 and SN74LVC1G98 Product Clip (Rev. A) (scyb010a.pdf,253 KB) 13 Jul 2004 Download Wireless Infrastructure Solutions Guide (4Q2003) (Rev. C) (sstc001c.pdf,957 KB) 19 Feb 2004 Download http://focus.ti.com/docs/prod/folders/print/sn74lvc1g17.html (4 of 5) [1/4/2005 5:52:14 PM] Product Folder : SN74LVC1G17 - Single Schmitt-Trigger Buffer Logic Cross-Reference (Rev. A) (scyb017a.pdf,2938 KB) 07 Oct 2003 Download SN74LVC1G3157 and SNS74LVC2G53 SPDT Analog Switches (scyb014.pdf,65 KB) 12 Jun 2003 Download Standard Linear & Logic for PCs, Servers & Motherboards (scyb005.pdf,3997 KB) 13 Jun 2002 Download STANDARD LINEAR AND LOGIC FOR DVD/VCD PLAYERS (scym001.pdf,5872 KB) 27 Mar 2002 Download Military Low Voltage Solutions (sgyn139.pdf,103 KB) 04 Apr 2001 Download Low-Voltage Logic (LVC) Designer's Guide (scba010.htm,11 KB) 01 Sep 1996 Abstract View More Literature for SINGLE-GATES Products | Applications | Support | Site Map (c) Copyright 1995-2004 Texas Instruments Incorporated. All rights reserved. Trademarks | Privacy Policy | Terms of Use http://focus.ti.com/docs/prod/folders/print/sn74lvc1g17.html (5 of 5) [1/4/2005 5:52:14 PM]