
  
SCES351I − JUNE 2001 − REVISED AUGUST 2003
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DAvailable in the Texas Instruments
NanoStarand NanoFreePackages
DSupports 5-V VCC Operation
DInputs Accept Voltages to 5.5 V
DMax tpd of 4.6 ns at 3.3 V
DLow Power Consumption, 10-µA Max ICC
D±24-mA Output Drive at 3.3 V
DIoff Supports Partial-Power-Down Mode
Operation
DLatch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
DESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
description/ordering information
This single Schmitt-trigger buffer is designed for 1.65-V to 5.5-V VCC operation.
The SN74LVC1G17 contains one buffer and performs the Boolean function Y = A. The device functions as an
independent b u ffer, bu t b e c a u s e o f S c h m i t t a c t i o n , i t may have different input threshold levels for positive-going
(VT+) and negative-going (VT−) signals.
NanoStarand NanoFreepackage technology is a major breakthrough in IC packaging concepts, using the
die as the package.
ORDERING INFORMATION
TAPACKAGE†ORDERABLE
PART NUMBER TOP-SIDE
MARKING‡
NanoStar − WCSP (DSBGA)
0.17-mm Small Bump − YEA SN74LVC1G17YEAR
NanoFree − WCSP (DSBGA)
0.17-mm Small Bump − YZA (Pb-free)
Reel of 3000
SN74LVC1G17YZAR
_ _ _C7_
−40 C to 85 C
NanoStar − WCSP (DSBGA)
0.23-mm Large Bump − YEP
Reel of 3000 SN74LV1G17YEPR _ _ _C7_
−40°C to 85°CNanoFree − WCSP (DSBGA)
0.23-mm Large Bump − YZP (Pb-free) SN74LV1G17YZPR
SOT (SOT-23) − DBV
Reel of 3000 SN74LVC1G17DBVR
C17_
SOT (SOT-23) − DBV Reel of 250 SN74LVC1G17DBVT C17_
SOT (SC-70) − DCK
Reel of 3000 SN74LVC1G17DCKR
C7_
SOT (SC-70) − DCK
Reel of 250 SN74LVC1G17DCKT
C7_
†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
‡DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site.
YEA/YZA, YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code,
and one following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition
(1 = SnPb, •= Pb-free).
Copyright 2003, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoStar and NanoFree are trademarks of Texas Instruments.
DBV OR DCK PACKAGE
(TOP VIEW)
1
2
3
5
4
NC
A
GND
VCC
Y
DNU − Do not use
3
2
1
4
5
GND
A
DNU
Y
VCC
YEA, YEP, YZA, OR YZP PACKAGE
(BOTTOM VIEW)
NC − No internal connection
   ! "#$ !  %#&'" ($)
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SCES351I − JUNE 2001 − REVISED AUGUST 2003
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description/ordering information (continued)
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
FUNCTION TABLE
INPUT
AOUTPUT
Y
H H
L L
logic diagram (positive logic)
AY
24
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC −0.5 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1) −0.5 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high-impedance or power-off state, VO
(see Note 1) −0.5 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high or low state, VO
(see Notes 1 and 2) −0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0) −50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0) −50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, IO ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through VCC or GND ±100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Note 3): DBV package 206°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DCK package 252°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
YEA/YZA package 154°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . .
YEP/YZP package 132°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The value of VCC is provided in the recommended operating conditions table.
3. The package thermal impedance is calculated in accordance with JESD 51-7.

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recommended operating conditions (see Note 4)
MIN MAX UNIT
VCC
Supply voltage
Operating 1.65 5.5
V
VCC Supply voltage Data retention only 1.5 V
VIInput voltage 0 5.5 V
VOOutput voltage 0 VCC V
VCC = 1.65 V −4
VCC = 2.3 V −8
I
OH
High-level output current
VCC = 3 V
−16 mA
IOH
High-level output current
VCC = 3 V −24
mA
VCC = 4.5 V −32
VCC = 1.65 V 4
VCC = 2.3 V 8
I
OL
Low-level output current
VCC = 3 V
16 mA
IOL
Low-level output current
VCC = 3 V 24
mA
VCC = 4.5 V 32
TAOperating free-air temperature −40 85 °C
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

  
SCES351I − JUNE 2001 − REVISED AUGUST 2003
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electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP†MAX UNIT
1.65 V 0.76 1.13
2.3 V 1.08 1.56
Positive-going input
3 V 1.48 1.92 V
threshold voltage 4.5 V 2.19 2.74
V
5.5 V 2.65 3.33
1.65 V 0.35 0.59
2.3 V 0.56 0.88
Negative-going input
3 V 0.89 1.2 V
threshold voltage 4.5 V 1.51 1.97
V
5.5 V 1.88 2.4
1.65 V 0.36 0.64
2.3 V 0.45 0.78
Hysteresis
3 V 0.51 0.83 V
(VT+ − VT−)4.5 V 0.58 0.93
V
5.5 V 0.69 1.04
IOH = −100 µA1.65 V to 4.5 V VCC−0.1
IOH = −4 mA 1.65 V 1.2
IOH = −8 mA 2.3 V 1.9
V
VOH IOH = −16 mA
3 V
2.4 V
IOH = −24 mA 3 V 2.3
IOH = −32 mA 4.5 V 3.8
IOL = 100 µA1.65 V to 4.5 V 0.1
IOL = 4 mA 1.65 V 0.45
IOL = 8 mA 2.3 V 0.3
V
VOL IOL = 16 mA
3 V
0.4 V
IOL = 24 mA 3 V 0.55
IOL = 32 mA 4.5 V 0.55
IIA input VI = 5.5 V or GND 0 to 5.5 V ±5µA
Ioff VI or VO = 5.5 V 0±10 µA
ICC VI = 5.5 V or GND, IO = 0 1.65 V to 5.5 V 10 µA
∆ICC One input at VCC − 0.6 V, Other inputs at VCC or
GND 3 V to 5.5 V 500 mA
CiVI = VCC or GND 3.3 V 4.5 pF
†All typical values are at VCC = 3.3 V, TA = 25°C.
switching characteristics over recommended operating free-air temperature range, CL = 15 pF
(unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 1.8 V
± 0.15 V VCC = 2.5 V
± 0.2 V VCC = 3.3 V
± 0.3 V VCC = 5 V
± 0.5 V
UNIT
PARAMETER
(INPUT)
(OUTPUT)
MIN MAX MIN MAX MIN MAX MIN MAX
UNIT
tpd AY2.8 9.9 1.6 5.5 1.5 4.6 0.9 4.4 ns
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  
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switching characteristics over recommended operating free-air temperature range, CL = 30 pF or
50 pF (unless otherwise noted) (see Figure 2)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 1.8 V
± 0.15 V VCC = 2.5 V
± 0.2 V VCC = 3.3 V
± 0.3 V VCC = 5 V
± 0.5 V
UNIT
PARAMETER
(INPUT)
(OUTPUT)
MIN MAX MIN MAX MIN MAX MIN MAX
UNIT
tpd AY3.8 11 2 6.5 1.8 5.5 1.2 5 ns
operating characteristics, TA = 25°C
PARAMETER
TEST CONDITIONS
VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 5 V
UNIT
PARAMETER
TEST CONDITIONS
TYP TYP TYP TYP
UNIT
Cpd Power dissipation capacitance f = 10 MHz 20 21 22 26 pF

  
SCES351I − JUNE 2001 − REVISED AUGUST 2003
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
VM
th
tsu
From Output
Under Test
CL
(see Note A)
LOAD CIRCUIT
S1
V
LOAD
Open
GND
RL
RL
Data Input
Timing Input VI
0 V
VI
0 V
0 V
tw
Input
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
PULSE DURATION
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
VI
0 V
Input
Output
Waveform 1
S1 at VLOAD
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
VLOAD/
2
0 V
VOL + V∆
VOH − V∆
≈0 V
VI
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
Output
Output
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
VLOAD
GND
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. W aveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Output
Control
VMVM
VMVM
VMVM
VM
VMVM
VM
VM
VM
VI
VM
VM
1.8 V ±0.15 V
2.5 V ±0.2 V
3.3 V ±0.3 V
5 V ±0.5 V
1 MΩ
1 MΩ
1 MΩ
1 MΩ
VCC RL
2 × VCC
2 × VCC
6 V
2 × VCC
VLOAD CL
15 pF
15 pF
15 pF
15 pF
0.15 V
0.15 V
0.3 V
0.3 V
V∆
VCC
VCC
3 V
VCC
VI
VCC/2
VCC/2
1.5 V
VCC/2
VM
tr/tf
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
INPUTS
Figure 1. Load Circuit and Voltage Waveforms

  
SCES351I − JUNE 2001 − REVISED AUGUST 2003
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
VM
th
tsu
From Output
Under Test
CL
(see Note A)
LOAD CIRCUIT
S1
V
LOAD
Open
GND
RL
RL
Data Input
Timing Input VI
0 V
VI
0 V
0 V
tw
Input
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
PULSE DURATION
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
VI
0 V
Input
Output
Waveform 1
S1 at VLOAD
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
VLOAD/
2
0 V
VOL + V∆
VOH − V∆
≈0 V
VI
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
Output
Output
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
VLOAD
GND
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. W aveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Output
Control
VMVM
VMVM
VMVM
VM
VMVM
VM
VM
VM
VI
VM
VM
1.8 V ±0.15 V
2.5 V ±0.2 V
3.3 V ±0.3 V
5 V ±0.5 V
1 kΩ
500 Ω
500 Ω
500 Ω
VCC RL
2 × VCC
2 × VCC
6 V
2 × VCC
VLOAD CL
30 pF
30 pF
50 pF
50 pF
0.15 V
0.15 V
0.3 V
0.3 V
V∆
VCC
VCC
3 V
VCC
VI
VCC/2
VCC/2
1.5 V
VCC/2
VM
tr/tf
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
INPUTS
Figure 2. Load Circuit and Voltage Waveforms
MECHANICAL DATA
MPDS018E – FEBRUAR Y 1996 – REVISED FEBRUAR Y 2002
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DBV (R-PDSO-G5) PLASTIC SMALL-OUTLINE
0,10
M
0,20
0,95
0°–8°
0,25
0,35
0,55
Gage Plane
0,15 NOM
4073253-4/G 01/02
2,60
3,00
0,50
0,30
1,50
1,70
45
31
2,80
3,00
0,95
1,45 0,05 MIN
Seating Plane
5X
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion.
D. Falls within JEDEC MO-178
MECHANICAL DATA
MPDS025C – FEBRUAR Y 1997 – REVISED FEBRUAR Y 2002
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DCK (R-PDSO-G5) PLASTIC SMALL-OUTLINE PACKAGE
0,10
M
0,10
0,65
0°–8°0,46
0,26
0,13 NOM
4093553-2/D 01/02
0,15
0,30
1,40
1,10 2,40
1,80
45
2,15
1,85
1 3
1,10
0,80 0,10
0,00
Seating Plane
0,15
Gage Plane
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion.
D. Falls within JEDEC MO-203
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Datasheet
SN74LVC1G17 (Rev. J) (sn74lvc1g17.pdf, 342 KB)
30 Nov 2004 Download
LVC1G17-1.8 LVC1G17-2.5 LVC1G17-3.3 LVC1G17-5.0
Voltage Node (V) 1.8 2.5 3.3 5
Voltage Nodes (V) 1.8 2.5 3.3 5
Performance Optimized
Vcc min (V) 1.65 1.65 1.65 1.65
Vcc max (V) 5.5 5.5 5.5 5.5
IOH (mA) -4 -8 -24 -32
IOL (mA) 4 8 24 32
tpd max (ns) 11 6.5 5.5 5
ICC (uA) 10 10 10 10
Input Level 1.8V CMOS 2.5V CMOS LV TTL CMOS
Output Level 1.8V CMOS 2.5V CMOS LV TTL CMOS
No. of Gates 1 1 1 1
Samples Not Available Samples Not Available Samples Not Available Samples Not Available
Inventory Not
Available Inventory Not
Available Inventory Not
Available Inventory Not
Available
Product Information
Features Save this to your personal library
● Available in the Texas Instruments NanoStar™ and NanoFree™ Packages
● Supports 5-V VCC Operation
● Inputs Accept Voltages to 5.5 V
● Max tpd of 4.6 ns at 3.3 V
● Low Power Consumption, 10-µA Max ICC
● ±24-mA Output Drive at 3.3 V
● Ioff Supports Partial-Power-Down Mode Operation
● Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
● ESD Protection Exceeds JESD 22
❍ 2000-V Human-Body Model (A114-A)
❍ 200-V Machine Model (A115-A)
❍ 1000-V Charged-Device Model (C101)
NanoStar and NanoFree are trademarks of Texas Instruments.
Description
This single Schmitt-trigger buffer is designed for 1.65-V to 5.5-V VCC operation.
The SN74LVC1G17 contains one buffer and performs the Boolean function Y = A. The device functions as
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Product Folder : SN74LVC1G17 - Single Schmitt-Trigger Buffer
an independent buffer, but because of Schmitt action, it may have different input threshold levels for
positive-going (VT+) and negative-going (VT–) signals.
NanoStar™ and NanoFree™ package technology is a major breakthrough in IC packaging concepts, using
the die as the package.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the
outputs, preventing damaging current backflow through the device when it is powered down.
Pricing/Packaging/Samples
Price Packaging Samples
Device Status Temp (oC) Budget Price ($US) | QTY Package Type | Pins Footprints STD Pack QTY Samples
SN74LVC1G17DBVR ACTIVE -40 to 85 0.11 | 1KU SOT-23 (DBV) | 5 3000 Request Samples
SN74LVC1G17DBVT ACTIVE -40 to 85 0.44 | 1KU SOT-23 (DBV) | 5 250 Not Available
SN74LVC1G17DCKR ACTIVE -40 to 85 0.11 | 1KU SC70 (DCK) | 5 3000 Request Samples
SN74LVC1G17DCKT ACTIVE -40 to 85 0.44 | 1KU SC70 (DCK) | 5 250 Not Available
SN74LVC1G17YEAR ACTIVE -40 to 85 0.23 | 1KU WCSP (YEA) | 5 3000 Request Samples
SN74LVC1G17YEPR ACTIVE -40 to 85 0.23 | 1KU WCSP (YEP) | 5 3000 Not Available
SN74LVC1G17YZAR ACTIVE -40 to 85 0.23 | 1KU WCSP (YZA) | 5 3000 Request Samples
SN74LVC1G17YZPR ACTIVE -40 to 85 0.23 | 1KU WCSP (YZP) | 5 3000 Request Samples
Inventory
TI Inventory Status Reported Distributor Inventory
SN74LVC1G17DBVR As of 9:38 AM GMT, 4 Jan 2005 As of 9:38 AM GMT, 4 Jan 2005
In Stock In Progress QTY | Date Lead Time In Stock Distributor: Region | Company Purchase
>10k* >10k | 17 Jan 2 Weeks >1k Americas | Memec Insight
>1k Americas | Arrow
>1k Americas | Avnet
>1k Europe | Rutronik
>1k Americas | DigiKey
>1k Europe | Arrow Northern Europe
>1k Europe | EBV Elektronik
>1k Americas | Newark Electronics
SN74LVC1G17DBVT As of 9:38 AM GMT, 4 Jan 2005 As of 9:38 AM GMT, 4 Jan 2005
In Stock In Progress QTY | Date Lead Time In Stock Distributor: Region | Company Purchase
>10k* >10k | 9 Feb 4 Weeks 705 Americas | Arrow
228 Europe | Spoerle
57 Asia | P&S
SN74LVC1G17DCKR As of 9:38 AM GMT, 4 Jan 2005 As of 9:38 AM GMT, 4 Jan 2005
In Stock In Progress QTY | Date Lead Time In Stock Distributor: Region | Company Purchase
>10k* >10k | 17 Jan 2 Weeks >1k Americas | DigiKey
>1k Europe | Arrow Northern Europe
>1k Americas | Arrow
>1k Asia | P&S
SN74LVC1G17DCKT As of 9:38 AM GMT, 4 Jan 2005 As of 9:38 AM GMT, 4 Jan 2005
In Stock In Progress QTY | Date Lead Time In Stock Distributor: Region | Company Purchase
>10k* >10k | 9 Feb 4 Weeks 167 Asia | P&S
SN74LVC1G17YEAR As of 9:38 AM GMT, 4 Jan 2005 As of 9:38 AM GMT, 4 Jan 2005
In Stock In Progress QTY | Date Lead Time In Stock Distributor: Region | Company Purchase
>10k* >10k | 18 Feb 6 Weeks >1k Americas | DigiKey
SN74LVC1G17YEPR As of 9:38 AM GMT, 4 Jan 2005 As of 9:38 AM GMT, 4 Jan 2005
In Stock In Progress QTY | Date Lead Time In Stock Distributor: Region | Company Purchase
0* 6000 | 24 Feb 7 Weeks >1k Americas | Avnet
>10k | 25 Feb
SN74LVC1G17YZAR As of 9:38 AM GMT, 4 Jan 2005 As of 9:38 AM GMT, 4 Jan 2005
View all Distributors
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Product Folder : SN74LVC1G17 - Single Schmitt-Trigger Buffer
In Stock In Progress QTY | Date Lead Time In Stock Distributor: Region | Company Purchase
>10k* >10k | 25 Feb 6 Weeks 215 Americas | DigiKey
SN74LVC1G17YZPR As of 9:38 AM GMT, 4 Jan 2005 As of 9:38 AM GMT, 4 Jan 2005
In Stock In Progress QTY | Date Lead Time In Stock Distributor: Region | Company Purchase
0* >10k | 14 Mar 10 Weeks >1k Americas | DigiKey
* Our information is updated daily, so please check back with us soon if
this does not meet your needs. You may also contact your TI Authorized
Distributor, including those listed above, for real time stock information.
** Lead time information is not available at this time. However, our
information is updated daily so please check back with us soon. Please
contact your preferred TI Authorized Distributor for additional
information.
Quality & Lead (Pb)-Free Data
Product Content MTBF/FIT Rate
Device Eco Plan* Lead/Ball Finish MSL Rating/Peak Reflow Details Details
SN74LVC1G17DBVR Pb-Free (RoHS) CU NIPDAU Level-1-260C-UNLIM View View
SN74LVC1G17DBVT Pb-Free (RoHS) CU NIPDAU Level-1-260C-UNLIM View View
SN74LVC1G17DCKR Pb-Free (RoHS) CU NIPDAU Level-1-260C-UNLIM View View
SN74LVC1G17DCKT Pb-Free (RoHS) CU NIPDAU Level-1-260C-UNLIM View View
SN74LVC1G17YEAR None SNPB Level-1-260C-UNLIM View View
SN74LVC1G17YEPR None SNPB Level-1-260C-UNLIM View View
SN74LVC1G17YZAR None Call TI Call TI View View
SN74LVC1G17YZPR None Call TI Call TI View View
* May not be currently available - please click on the Product Content
Details "View" link in the table above for the latest availability
information and additional product content details.
If the information you are requesting is not available online at this
time, contact one of our Product Information Centers regarding the
availability of this information.
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Product Folder : SN74LVC1G17 - Single Schmitt-Trigger Buffer
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Product Folder : SN74LVC1G17 - Single Schmitt-Trigger Buffer
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