CBOOT
Q1
VDC
OUTPUT
VDD
IN
Undervoltage
GND
Q2
−
+
VDD
Level Shift
OUTL
OUTH
SD
VBBM
BOOT
D1
VS
Si9912
Vishay Siliconix
Document Number: 71311
S-40134—Rev. B, 16-Feb-04
www.vishay.com
1
Half-Bridge MOSFET Driver for Switching Power Supplies
FEATURES APPLICATIONS
D4.5- to 5.5-V Operation
DUndervoltage Lockout
D250-kHz to 1-MHz Switching Frequency
DShutdown Quiescent Current <5 mA
DOne Input PWM Signal Generates Both Drive
DBootstrapped High-Side Drive
DOperates from 4.5- to 30-V Supply
DTTL/CMOS Compatible Input Levels
D1-A Peak Drive Current
DBreak-Before-Make Circuit
DMultiphase Desktop CPU Supplies
DSingle-Supply Synchronous Buck Converters
DMobile Computing CPU Core Power Converters
DStandard-Synchronous Converters
DHigh Frequency Switching Converters
DESCRIPTION
The Si9912 is a dual MOSFET high-speed driver with
break-before-make. It is designed to operate in high frequency
dc-dc switchmode power supplies. The high-side driver is
bootstrapped to handle the high voltage slew rate associated
with “floating” high-side gate drivers. Each driver is capable of
switching a 3000-pF load with 60-ns propogation delay and
25-ns transition time. The Si9912 comes with an internal
break-before-make feature to prevent shoot-through current in
the external MOSFETs. A shutdown pin is used to enable the
driver. When disabled, the quiescent current of the driver is
less than 5 mA.
The Si9912 is available in both standard and lead (Pb)-free, 8-pin
SOIC packages for operation over the industrial operation range
(−40_C to 85_C).
FUNCTIONAL BLOCK DIAGRAM AND TRUTH TABLE
TRUTH TABLE
VSSD IN VOUTL VOUTH
L L L L L
L L H L L
L H L H L
L H H L H
H L L L L
H L H L L
H H L L L
H H H L H
Si9912
Vishay Siliconix
www.vishay.com
2
Document Number: 71311
S-40134—Rev. B, 16-Feb-04
ABSOLUTE MAXIMUM RATINGS (TA = 25_C UNLESS OTHERWISE NOTED)
Parameter Symbol Limit Unit
Low Side Driver Supply Voltage VDD 7.0
Input Voltage on IN VIN −0.3 to VDD +0.3
Shutdown Pin Voltage VSD −0.3 to VDD +0.3 V
Bootstrap Voltage VBOOT 35.0
High Side Driver (Bootstrap) Supply Voltage VBOOT − VS7.0
Operating Junction Temperature Range TJ−40 to 125
_
C
Storage Temperature Range Tstg −40 to 150
_C
Power Dissipation (Note a and b) PD830 mW
Thermal Impedance qJA 125 °C/W
Lead Temperature (soldering 10 Sec) 300 °C
Notes
a. Device mounted with all leads soldered to P.C. Board
b. Derate 8.3 W/_C above 25_C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only , and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Parameter Symbol Limit Unit
Bootstrap Voltage (High-Side Drain Voltage) VBOOT 4.5 to 30
V
Logic Supply VDD 4.5 to 5.5 V
Bootstrap Capacitor CBOOT 100 n to 1 mF
Ambient Temperature TA−40 to 85 _C
SPECIFICATIONS
Test Conditions Unless Specified Limits
Parameter Symbol VDD = 4.5 to 5.5 V
VBOOT = 4.5 to 30 V, TA = −40 to 85_CMinaTypbMaxaUnit
Power Supplies
VDD Supply VDD 4.5
IDD Supply IDD1(en) SD = H, IN = H, VS = 0 V 1000
IDD Supply IDD2(en) SD = H, IN = L, VS = 0 V 500
mA
IDD Supply IDD3(dis) SD = L, IN = X, VS = 0 V 5mA
IDD Supply IDD4(en) SD = H, IN = X, VS = 25 V, VBOOT = 30 V 200
IDD Supply IDD5(dis) SD = L, IN = X, VS = 25 V, VBOOT = 30 V 5
IDD Supply
IDD(en) FIN = 300 kHz, SD = High, Driving Si4412DY 9 mA
IDD Supply IDD(dis) FIN = 300 kHz, SD = Low, Driving Si4412DY 3mA
Boot Strap Current IBOOT VBOOT = 30 V, VS = 25 V, VOUTH = High 0.9 3 mA
Reference Voltage
Break-Before-Make Reference Voltage VBBM 1.1 3 V
Logic Inputs (SD, IN)
Input High VIH 0.7 VDD VDD + 0.3
V
Input Low VIL −0.3 0.3 VDD
V
Undervoltage Lockout
VDD Undervoltage VUVL VDD Rising 3.7 4.3
V
VDD Undervoltage Hysteresis VHYST 0.4 V
Si9912
Vishay Siliconix
Document Number: 71311
S-40134—Rev. B, 16-Feb-04
www.vishay.com
3
SPECIFICATIONS
Test Conditions Unless Specified Limits
Parameter Symbol VDD = 4.5 to 5.5 V
VBOOT = 4.5 to 30 V, TA = −40 to 85_CMinaTypbMaxaUnit
Bootstrap Diode
Diode Forward Voltage VFD1 Forward Current = 100 mA 0.8 1 V
Output Drive Current
OUTH Source Current IOUT(H+) VBOOT − VS = 3.7 V, VOUTH − VS = 2 V −0.4
OUTH Sink Current IOUT(H−) VBOOT − VS = 3.7 V, VOUTH − VS = 1 V 0.4
A
OUTL Source Current IOUT(L+) VDD = 4.5 V, VOUTL = 2 V −0.4
A
OUTL Sink Current IOUT(L−) VDD = 4.5 V, VOUTL = 1 V 0.6
Timing (CLOAD = 3 nF)
OUTL Off Propagation Delay tpdl(OUTL)
VDD = 4 5 V
30
OUTL On Propagation Delay tpdh(OUTL)
V
DD
=
4.5
V
20
OUTH Off Propagation Delay tpdl(OUTH)
VBOOT VS = 4 5 V
30
OUTH On Propagation Delay tpdh(OUTH)
VBOOT − VS = 4.5 V 20
ns
OUTL Turn On Time tr(OUTL) OUTL = 10 to 90% 25 ns
OUTL Turn Off Time tf(OUTL) OUTL = 90 to 10% 25
OUTH Turn On Time tr(OUTH) OUTH − VS = 10 to 90% 30
OUTH Turn Off Time tf(OUTH) OUTH − VS = 90 to 10% 20
Notes
a. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
b. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
TIMING WAVEFORMS
OUTH
10% 10%
90% 90%
VS
OUTL
IN 50% 50%
tpdh(OUTL)
tf(OUTL)
tpdh(OUTH)
90%
10%
tr(OUTH)
tpdl(OUTH)
tf(OUTH)
tpdl(OUTL)
tr(OUTL)
10%
90%
Si9912
Vishay Siliconix
www.vishay.com
4
Document Number: 71311
S-40134—Rev. B, 16-Feb-04
PIN CONFIGURATION
GND
SO-8
5
6
7
8
Top View
2
3
4
1
OUTHVS
IN
BOOT
VDD
SD OUTL
PIN DESCRIPTION
Pin Number Name Function
1 OUTHOutput drive for upper MOSFET.
2 GND Ground supply
3 IN CMOS level input signal. Controls both output drives.
4 SD Shutdown pin
5 OUTLOutput drive for lower MOSFET.
6 VDD Input power supply
7 BOOT Floating bootstrap supply for the upper MOSFET
8 VSFloating GND for the upper MOSFET. VS is connected to the buck switching node and the source side of the upper MOSFET.
ORDERING INFORMATION
Part Number Temperature Range Package
Si9912DY Bulk
Si9912DY-T1 −40 to 85_C
Tape and Reel
Si9912DY-T1—E3 (Lead (Pb)-Free) Tape and Reel
Eval Kit Temperature Range Board Type
Si9912DB −40 to 85_CSurface Mount
TYPICAL WAVEFORMS
Driver On Switch Delay
Si9912 tr, tf, tpd
Driver Off Switch Delay
VS
OUTH
OUTL
IN
VS
OUTH
OUTL
IN
Si9912 tr, tf, tpd
CL = Si4412DY CL = Si4412DY
See Figure 1 See Figure 1
Si9912
Vishay Siliconix
Document Number: 71311
S-40134—Rev. B, 16-Feb-04
www.vishay.com
5
TYPICAL CHARACTERISTICS (25_C UNLESS NOTED)
1
1
100
30
100010
Current (mA)
Frequency (kHz)
10
0.3 101
Rise and Fall times (ns)
Load Capacitance (nF)
tr(OUTH)
tr(OUTL)
tf(OUTH)
Rise and Fall Time vs. CLOAD
3
50
40
30
20
10
0
0
1
2
3
4
5
3.0 3.5 4.0 4.5 5.0 5.5 6.0
−5
−4
−3
−2
−1
0
3.0 3.5 4.0 4.5 5.0 5.5 6.0
Output Voltage Drop (V)
VOUT(H+) vs. Supply
Supply Voltage (V) Supply Voltage (V)
0.0
0.5
1.0
1.5
2.0
2.5
4.0 4.5 5.0 5.5 6.0
−6
−5
−4
−3
−2
−1
0
4.0 4.5 5.0 5.5 6.0
VOUT(H−) vs. Supply
VOUT(L+) vs. Supply VOUT(L−) vs. Supply
Supply Voltage (V) Supply Voltage (V)
Output Voltage Drop (V)
Output Voltage Drop (V)Output Voltage Drop (V)
0.5 A
1 A
1.5 A
0.5 A
1 A
1.5 A
2 A
0.5 A
1 A
1.5 A
2 A
0.5 A
1 A
1.5 A
2 A
tf(OUTL)
IDD Supply Current vs. Frequency
See Figure 1
See Figure 3
See Figure 2
See Figure 3
See Figure 3
See Figure 3
Si9912
Vishay Siliconix
www.vishay.com
6
Document Number: 71311
S-40134—Rev. B, 16-Feb-04
TYPICAL CHARACTERISTICS (25_C UNLESS NOTED)
0
1
2
3
4
5
−50 −25 0 25 50 75 100
−5
−4
−3
−2
−1
0
−50 −25 0 25 50 75 100
Output Voltage Drop (V)
VOUT(H+) vs. Temperature
Temperature (_C)
0.0
0.5
1.0
1.5
2.0
−50 −25 0 25 50 75 100
−5
−4
−3
−2
−1
0
−50 −25 0 25 50 75 100
VOUT(H−) vs. Temperature
VOUT(L+) vs. Temperature VOUT(L−) vs. Temperature
Output Voltage Drop (V)
Output Voltage Drop (V)Output Voltage Drop (V)
0.5 A
1 A
0.5 A
1 A
1.5 A
2 A
0.5 A
1 A
1.5 A
2 A
0.5 A
1 A
1.5 A
2 A
Temperature (_C)
Temperature (_C) Temperature (_C)
See Figure 3
See Figure 3
See Figure 3
See Figure 3
THEORY OF OPERATION
Break-Before-Make Function
The Si9912 has an internal break-before-make function to
ensure that both high-side and low-side MOSFETs are not
turned on at the same time. The high-side drive (OUTH) will not
turn on until the low-side gate drive voltage (measured at the
OUTL pin) is less than VBBM, thus ensuring that the low-side
MOSFET is turned off. The low-side drive (OUTL) will not turn
on until the voltage at the MOSFET half-bridge output
(measured at the VS pin) is less than VBBM, thus ensuring that
the high-side MOSFET is turned off.
Under Voltage Lockout Function
The Si9912 has an internal under-voltage lockout feature to
prevent driving the MOSFET gates when the supply voltage (at
VDD) is less than the under-voltage lockout specification
(VUVL). This prevents the output MOSFETs from being turned
on without sufficient gate voltage to ensure they are fully on.
There is hysteresis included in this feature to prevent lockout
from cycling on and off.
Si9912
Vishay Siliconix
Document Number: 71311
S-40134—Rev. B, 16-Feb-04
www.vishay.com
7
Bootstrap Supply Operation
(see Functional Block Diagram)
The power to drive the high-side MOSFET (Q2) gate comes
from the bootstrap capacitor (CBOOT). This capacitor charges
through D1 during the time when the low-side MOSFET is on
(VS is at GND potential), and then provides the necessary
charge to turn on the high-side MOSFET. CBOOT should be
sized to be greater than ten times the high-side MOSFET gate
capacitance, and large enough to supply the bootstrap current
(IBOOT) during the high-side on time, without significant voltage
droop.
Shutdown (SD)
(shutdown input, active low)
When this pin is high, the IC operates normally. When this pin
is low, both high- and low-side MOSFETs are turned off .
Layout Considerations
There are a few critical layout considerations for these parts.
Firstly, the IC must be decoupled as closely as possible to the
power pins. Secondly the IC should be placed physically close
to the high- and low-side MOSFETs it is driving. The major
consideration is that the MOSFET gates must be charged or
discharged in a few nanoseconds, and the peak current to do
this is of the order of 1 A. This current must flow from the
decoupling and bootstrap capacitors to the IC, and from the
output driver pin to the MOSFET gate, returning from the
MOSFET source to the IC. The aim of the layout is to reduce
the parasitic inductance of these current paths as much as
possible. This is accomplished by making these traces as
short as possible, and also running trace and its current return
path adjacent to each other.
APPLICATIONS
FIGURE 1. Typical Applications Schematic Circuit Used to Obtain Typical Rising and Falling Switching Waveforms
8
6
7
5
1
3
2
4
OUTH
GND
IN
SD
VS
BOOT
VDD
OUTL
U1
Si9912
+5 V
C2
0.1 mF
PWM IN
GND
1 mF
C5
C1
0.1 mF
Enable
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
Q1
Si4412
Q2
Si4412
+VDC
L1
15 mH
0.1 mF
C3
15 mF
C4
GND
+
GND
RLOAD
Si9912
Vishay Siliconix
www.vishay.com
8
Document Number: 71311
S-40134—Rev. B, 16-Feb-04
FIGURE 2. Capacitive Load Test Circuit Used to Measure
Rise and Fall Times vs. Capacitance
FIGURE 3. Load Test Schematic Circuit Used to
Measure Driver Output Impedance
8
6
7
5
1
3
2
4
OUTH
GND
IN
SD
VS
BOOT
VDD
OUTL
U1
Si9912
+5 V
C2
0.1 mF
ISRC
ISRC
Input
GND
8
6
7
5
1
3
2
4
OUTH
GND
IN
SD
VS
BOOT
VDD
OUTL
U1
Si9912
+5 V
C2
0.1 mF
PWM IN
GND
CLOAD
C8
CLOAD
C9
Document Number: 91000 www.vishay.com
Revision: 18-Jul-08 1
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All product specifications and data are subject to change without notice.
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