5962-9682101VDA - Texas Instruments High-Performance Analog

SN54AHCT08, SN74AHCT08

QUADRUPLE 2-INPUT POSITIVE-AND GATES

SCLS237L − OCTOBER 1995 − REVISED JULY 2003

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

DInputs Are TTL-Voltage Compatible

DLatch-Up Performance Exceeds 250 mA Per

JESD 17

DESD Protection Exceeds JESD 22

− 2000-V Human-Body Model (A114-A)

− 200-V Machine Model (A115-A)

− 1000-V Charged-Device Model (C101)

GND

VCC

SN54AHCT08 ...J OR W PACKAGE

SN74AHCT08 ...D, DB, DGV, N, NS,

OR PW PACKAGE

(TOP VIEW)

3212019

910111213

GND

SN54AHCT08 . . . FK PACKAGE

(TOP VIEW)

NC − No internal connection

SN74AHCT08 . . . RGY PACKAGE

(TOP VIEW)

114

3Y V

GND

description/ordering information

The ’AHCT08 devices are quadruple 2-input positive-AND gates. These devices perform the Boolean function

Y+A•BorY+A)B in positive logic.

ORDERING INFORMATION

TAPACKAGE†ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

QFN − RGY Tape and reel SN74AHCT08RGYR HB08

PDIP − N Tube SN74AHCT08N SN74AHCT08N

SOIC D

Tube SN74AHCT08D

AHCT08

SOIC − D Tape and reel SN74AHCT08DR AHCT08

−40°C to 85°CSOP − NS Tape and reel SN74AHCT08NSR AHCT08

SSOP − DB Tape and reel SN74AHCT08DBR HB08

TSSOP PW

Tube SN74AHCT08PW

HB08

TSSOP − PW Tape and reel SN74AHCT08PWR HB08

TVSOP − DGV Tape and reel SN74AHCT08DGVR HB08

CDIP − J Tube SNJ54AHCT08J SNJ54AHCT08J

−55°C to 125°CCFP − W Tube SNJ54AHCT08W SNJ54AHCT08W

55 C

125 C

LCCC − FK Tube SNJ54AHCT08FK SNJ54AHCT08FK

†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines

are available at www.ti.com/sc/package.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

On products compliant to MIL-PRF-38535, all parameters are tested

unless otherwise noted. On all other products, production

processing does not necessarily include testing of all parameters.

SN54AHCT08, SN74AHCT08

QUADRUPLE 2-INPUT POSITIVE-AND GATES

SCLS237L − OCTOBER 1995 − REVISED JULY 2003

2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

FUNCTION TABLE

(each gate)

INPUTS OUTPUT

A B

OUTPUT

H H H

LXL

X L L

logic diagram, each gate (positive logic)

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†

Supply voltage range, VCC −0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, VI (see Note 1) −0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output voltage range, VO (see Note 1) −0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input clamp current, IIK (VI < 0) −20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output clamp current, IOK (VO < 0 or VO > VCC) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous output current, IO (VO = 0 to VCC) ±25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous current through VCC or GND ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Package thermal impedance, θJA (see Note 2): D package 86°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

(see Note 2): DB package 96°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

(see Note 2): DGV package 127°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

(see Note 2): N package 80°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

(see Note 2): NS package 76°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

(see Note 2): PW package 113°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

(see Note 3): RGY package 47°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, Tstg −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

2. The package thermal impedance is calculated in accordance with JESD 51-7.

3. The package thermal impedance is calculated in accordance with JESD 51-5.

SN54AHCT08, SN74AHCT08

QUADRUPLE 2-INPUT POSITIVE-AND GATES

SCLS237L − OCTOBER 1995 − REVISED JULY 2003

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

recommended operating conditions (see Note 4)

SN54AHCT08 SN74AHCT08

UNIT

MIN MAX MIN MAX UNIT

VCC Supply voltage 4.5 5.5 4.5 5.5 V

VIH High-level input voltage 2 2 V

VIL Low-level input voltage 0.8 0.8 V

VIInput voltage 0 5.5 0 5.5 V

VOOutput voltage 0 VCC 0 VCC V

IOH High-level output current −8 −8 mA

IOL Low-level output current 8 8 mA

Δt/ΔvInput transition rise or fall rate 20 20 ns/V

TAOperating free-air temperature −55 125 −40 85 °C

NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,

Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

PARAMETER

TEST CONDITIONS

TA = 25°C SN54AHCT08 SN74AHCT08

UNIT

PARAMETER TEST CONDITIONS VCC MIN TYP MAX MIN MAX MIN MAX UNIT

IOH = −50 mA

45V

4.4 4.5 4.4 4.4

VOH IOH = −8 mA 4.5 V 3.94 3.8 3.8 V

IOL = 50 mA

45V

0.1 0.1 0.1

VOL IOL = 8 mA 4.5 V 0.36 0.44 0.44 V

IIVI = 5.5 V or GND 0 V to 5.5 V ±0.1 ±1* ±1mA

ICC VI = VCC or GND, IO = 0 5.5 V 2 20 20 mA

ΔICC†One input at 3.4 V,

Other inputs at VCC or GND 5.5 V 1.35 1.5 1.5 mA

CiVI = VCC or GND 5 V 4 10 10 pF

* On products compliant to MIL-PRF-38535, this parameter is not production tested at VCC = 0 V.

†This is the increase in supply current for each input at one of the specified TTL voltage levels, rather than 0 V or VCC.

switching characteristics over recommended operating free-air temperature range,

VCC = 5 V ±0.5 V (unless otherwise noted) (see Figure 1)

PARAMETER

FROM TO LOAD TA = 25°C SN54AHCT08 SN74AHCT08

UNIT

PARAMETER

FROM

(INPUT)

(OUTPUT)

LOAD

CAPACITANCE MIN TYP MAX MIN MAX MIN MAX UNIT

tPLH

AorB

C15 pF

5** 6.9** 1** 8** 1 8

tPHL

A or B Y CL = 15 pF 5** 6.9** 1** 8** 1 8 ns

tPLH

AorB

C=50pF

5.5 7.9 1 9 1 9

tPHL

A or B Y CL = 50 pF 5.5 7.9 1 9 1 9 ns

** On products compliant to MIL-PRF-38535, this parameter is not production tested.

SN54AHCT08, SN74AHCT08

QUADRUPLE 2-INPUT POSITIVE-AND GATES

SCLS237L − OCTOBER 1995 − REVISED JULY 2003

4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

noise characteristics, VCC = 5 V, CL = 50 pF, TA = 25°C (see Note 5)

PARAMETER

SN74AHCT08

UNIT

PARAMETER MIN TYP MAX UNIT

VOL(P) Quiet output, maximum dynamic VOL 0.4 0.8 V

VOL(V) Quiet output, minimum dynamic VOL −0.4 −0.8 V

VOH(V) Quiet output, minimum dynamic VOH 4.4 V

VIH(D) High-level dynamic input voltage 2 V

VIL(D) Low-level dynamic input voltage 0.8 V

NOTE 5: Characteristics are for surface-mount packages only.

operating characteristics, VCC = 5 V, TA = 25°C

PARAMETER TEST CONDITIONS TYP UNIT

Cpd Power dissipation capacitance No load, f = 1 MHz 18 pF

SN54AHCT08, SN74AHCT08

QUADRUPLE 2-INPUT POSITIVE-AND GATES

SCLS237L − OCTOBER 1995 − REVISED JULY 2003

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

50% VCC

3 V

0 V

tsu

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

Data Input

tPLH

tPHL

tPLH

VOH

VOL

3 V

0 V

50% VCC

Input

Out-of-Phase

Output

In-Phase

Output

Timing Input

50% VCC

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

INVERTING AND NONINVERTING OUTPUTS

Output

Control

Output

Waveform 1

S1 at VCC

(see Note B)

Output

Waveform 2

S1 at GND

(see Note B)

VOL

VOH

tPZL

tPZH

tPLZ

tPHZ

≈VCC

0 V

50% VCC VOL + 0.3 V

50% VCC

≈0 V

3 V

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

LOW- AND HIGH-LEVEL ENABLING

tPLH/tPHL

tPLZ/tPZL

tPHZ/tPZH

Open Drain

Open

VCC

GND

VCC

TEST S1

3 V

0 V

VOLTAGE WAVEFORMS

PULSE DURATION

Input

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤3 ns, tf ≤ 3 ns.

D. The outputs are measured one at a time with one input transition per measurement.

E. All parameters and waveforms are not applicable to all devices.

From Output

Under Test

(see Note A)

LOAD CIRCUIT FOR

3-STATE AND OPEN-DRAIN OUTPUTS

VCC

RL = 1 kΩ

GND

From Output

Under Test

(see Note A)

Test

Point

LOAD CIRCUIT FOR

TOTEM-POLE OUTPUTS

Open

VOH − 0.3 V

1.5 V 1.5 V

1.5 V

1.5 V 1.5 V

1.5 V 1.5 V1.5 V 1.5 V

Figure 1. Load Circuit and Voltage Waveforms

PACKAGE OPTION ADDENDUM

www.ti.com 18-Oct-2013

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead/Ball Finish

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

5962-9682101Q2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962-

9682101Q2A

SNJ54AHCT

08FK

5962-9682101QCA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 5962-9682101QC

SNJ54AHCT08J

5962-9682101QDA ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 5962-9682101QD

SNJ54AHCT08W

5962-9682101VCA ACTIVE CDIP J 14 25 TBD A42 N / A for Pkg Type -55 to 125 5962-9682101VC

SNV54AHCT08J

5962-9682101VDA ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 5962-9682101VD

SNV54AHCT08W

SN74AHCT08D ACTIVE SOIC D 14 50 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 AHCT08

SN74AHCT08DBLE OBSOLETE SSOP DB 14 TBD Call TI Call TI -40 to 85

SN74AHCT08DBR ACTIVE SSOP DB 14 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HB08

SN74AHCT08DBRE4 ACTIVE SSOP DB 14 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HB08

SN74AHCT08DBRG4 ACTIVE SSOP DB 14 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HB08

SN74AHCT08DE4 ACTIVE SOIC D 14 50 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 AHCT08

SN74AHCT08DG4 ACTIVE SOIC D 14 50 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 AHCT08

SN74AHCT08DGVR ACTIVE TVSOP DGV 14 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HB08

SN74AHCT08DGVRE4 ACTIVE TVSOP DGV 14 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HB08

SN74AHCT08DGVRG4 ACTIVE TVSOP DGV 14 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HB08

PACKAGE OPTION ADDENDUM

www.ti.com 18-Oct-2013

Addendum-Page 2

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead/Ball Finish

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

SN74AHCT08DR ACTIVE SOIC D 14 2500 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 AHCT08

SN74AHCT08DRE4 ACTIVE SOIC D 14 2500 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 AHCT08

SN74AHCT08DRG4 ACTIVE SOIC D 14 2500 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 AHCT08

SN74AHCT08N ACTIVE PDIP N 14 25 Pb-Free

(RoHS) CU NIPDAU N / A for Pkg Type -40 to 85 SN74AHCT08N

SN74AHCT08NE4 ACTIVE PDIP N 14 25 Pb-Free

(RoHS) CU NIPDAU N / A for Pkg Type -40 to 85 SN74AHCT08N

SN74AHCT08NSR ACTIVE SO NS 14 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 AHCT08

SN74AHCT08NSRG4 ACTIVE SO NS 14 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 AHCT08

SN74AHCT08PW ACTIVE TSSOP PW 14 90 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HB08

SN74AHCT08PWE4 ACTIVE TSSOP PW 14 90 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HB08

SN74AHCT08PWG4 ACTIVE TSSOP PW 14 90 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HB08

SN74AHCT08PWLE OBSOLETE TSSOP PW 14 TBD Call TI Call TI -40 to 85

SN74AHCT08PWR ACTIVE TSSOP PW 14 2000 Green (RoHS

& no Sb/Br) CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 85 HB08

SN74AHCT08PWRE4 ACTIVE TSSOP PW 14 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HB08

SN74AHCT08PWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HB08

SN74AHCT08RGYR ACTIVE VQFN RGY 14 3000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 HB08

SN74AHCT08RGYRG4 ACTIVE VQFN RGY 14 3000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 HB08

SNJ54AHCT08FK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962-

9682101Q2A

SNJ54AHCT

08FK

SNJ54AHCT08J ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 5962-9682101QC

PACKAGE OPTION ADDENDUM

www.ti.com 18-Oct-2013

Addendum-Page 3

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead/Ball Finish

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

SNJ54AHCT08J

SNJ54AHCT08W ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 5962-9682101QD

SNJ54AHCT08W

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish

value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

PACKAGE OPTION ADDENDUM

www.ti.com 18-Oct-2013

Addendum-Page 4

OTHER QUALIFIED VERSIONS OF SN54AHCT08, SN54AHCT08-SP, SN74AHCT08 :

•Catalog: SN74AHCT08, SN54AHCT08

•Enhanced Product: SN74AHCT08-EP, SN74AHCT08-EP

•Military: SN54AHCT08

•Space: SN54AHCT08-SP

NOTE: Qualified Version Definitions:

•Catalog - TI's standard catalog product

•Enhanced Product - Supports Defense, Aerospace and Medical Applications

•Military - QML certified for Military and Defense Applications

•Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

SN74AHCT08DBR SSOP DB 14 2000 330.0 16.4 8.2 6.6 2.5 12.0 16.0 Q1

SN74AHCT08DGVR TVSOP DGV 14 2000 330.0 12.4 6.8 4.0 1.6 8.0 12.0 Q1

SN74AHCT08DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1

SN74AHCT08NSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1

SN74AHCT08PWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1

SN74AHCT08PWRG4 TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1

SN74AHCT08RGYR VQFN RGY 14 3000 330.0 12.4 3.75 3.75 1.15 8.0 12.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 23-Oct-2013

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

SN74AHCT08DBR SSOP DB 14 2000 367.0 367.0 38.0

SN74AHCT08DGVR TVSOP DGV 14 2000 367.0 367.0 35.0

SN74AHCT08DR SOIC D 14 2500 333.2 345.9 28.6

SN74AHCT08DR SOIC D 14 2500 367.0 367.0 38.0

SN74AHCT08NSR SO NS 14 2000 367.0 367.0 38.0

SN74AHCT08PWR TSSOP PW 14 2000 367.0 367.0 35.0

SN74AHCT08PWRG4 TSSOP PW 14 2000 367.0 367.0 35.0

SN74AHCT08RGYR VQFN RGY 14 3000 367.0 367.0 35.0

PACKAGE MATERIALS INFORMATION

www.ti.com 23-Oct-2013

Pack Materials-Page 2

MECHANICAL DATA

MPDS006C – FEBRUAR Y 1996 – REVISED AUGUST 2000

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE

24 PINS SHOWN

3,70

3,50 4,90

5,10

DIM

PINS **

4073251/E 08/00

1,20 MAX

Seating Plane

0,05

0,15

0,25

0,50

0,75

0,23

0,13

112

24 13

4,30

4,50

0,16 NOM

Gage Plane

7,90

7,70

382416

4,90

5,103,70

3,50

A MAX

A MIN

6,60

6,20

11,20

11,40

9,60

9,80

0,08

0,07

0,40

0°–8°

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.

D. Falls within JEDEC: 24/48 Pins – MO-153

14/16/20/56 Pins – MO-194