ANALOG DEVICES AN-397 APPLICATION NOTE ONE TECHNOLOGY WAY e P.O. BOX 9106 e NORWOOD, MASSACHUSETTS 02062-9106 @ 617/329-4700 Electrically Induced Damage to Standard Linear Integrated Circuits: The Most Common Causes and the Associated Fixes to Prevent Reoccurrence by Niall Lyne INTRODUCTION The sensitivity of electronic components to transient electrical overstress events is a well-known problem, exacerbated by the continuing evolution of integrated circuits. Smaller geometries, increased circuit densities, and the limited area allotted to on-chip protection all tend to increase this sensitivity. In an effort to minimize costs in each particular segment of system implementa- tion, the burden of transient protection is often shifted to other, less efficient means. Techniques for protection from zapping depend on the stage of manufacture. During the manufacturing of integrated circuits and assembly of electronic equip- ment, protection is achieved through the use of well- known measures such as static dissipative table tops, wrist straps, ionized air blowers, antistatic shipping tubes, etc. These methods will be discussed only briefly here in relation to Electrostatic Discharge (ESD) protec- tion. Likewise this application note is not addressed to precautionary measures employed during shipping, in- stallation, or repair of equipment. Rather, the main thrust will be limited to protection aspects called upon during printed circuit board assembly, normal operation of the equipment (often by operating personnel who are untrained in preventative measures), and in service con- ditions where the transient environment may not be well characterized. The transient environment varies widely. There are sub- stantial differences among those experienced by, say, automotive systems, airborne or shipborne equipment, space systems, industrial equipment or consumer prod- ucts. All types of electronic components can be destroyed or degraded.' Even capacitors, relays, con- nectors, printed circuit boards, etc., are susceptible, although their threshold levels are much higher than integrated circuits. Microwave diodes and transistors are among the most sensitive components. However, this application note will be restricted to standard linear integrated circuits because of their wide usage, and to limit the scope of coverage. This application note will first review the nature of the threat to integrated circuits in an operating environ- ment, and then briefly discuss overall device protection from the following: (1) ESD events caused by human handling, automatic board insertion equipment, etc., (2) LATCH-UP generated from power-up/down sequencing errors, floating ground(s) due to a loose edge connec- tors, etc., and finally, (3) HIGH VOLTAGE TRANSIENTS generated from a power supply, a defective circuit board, during circuit board troubleshooting, etc. Electrostatic Discharge Electrostatic discharge is a single, fast, high current transfer of electrostatic charge that results from: * Direct contact transfer between two objects at differ- ent potentials, or * A high electrostatic field between two objects when they are in close proximity. The prime sources of static electricity are mostly insula- tors and are typically synthetic materials, e.g., vinyl or plastic work surfaces, insulated shoes, finished wood chairs, Scotch tape, bubble pack, soldering irons with ungrounded tips, etc. Voltage levels generated by these sources can be extremely high since their charge is not readily distributed over their surfaces or conducted to other objects. The generation of static electricity caused by rubbing two substances together is called the triboelectric effect. Examples of sources of triboelectric electrostatic charge generation in a high RH (~60%) environment include: Walking across a carpet = 1000 V-1500 V generated. Walking across a vinyl floor = 150 V-250 V generated. * Handling material protected by clear plastic covers => 400 V-600 V generated. Handling polyethylene bags => 1000 V-1200 V generated. e Pouring polyurethane foam into a box => 1200 V- 1500 V generated.e ICs sliding down an open antistatic shipping tube > 25 V-250 V generated. Note: For low RH (<30%) environments, generated volt- ages can be >10x those listed above. ESD Models To evaluate the susceptibility of devices to simulated stress environments a host of test waveforms have been developed. The three most prominent of these wave- forms currently in general use for simulating ESD events in semiconductor or discrete devices are: The Human Body Model (HBM), the Machine Model (MM), and the Charged Device Model (CDM). The test circuits and cur- rent waveform characteristics for these three models are shown in Figures 1 to 3. Each of these models repre- sents a fundamentally different ESD event. Conse- quently, correlation between the test results for these models is minimal. Human Body Model. Simulates the discharge event that occurs when a per- son charged to either a positive or negative potential touches an IC at a different potential. RLC = 1.5 kQ, ~0 nH, 100 pF. I 10OMQ S41 OH 1.5kQ Gor Lo : Figure 1. Human Body Model Machine Model: Japanese model based on a worst-case HBM. RLC = 0, 500 nH, 200 pF. 1 500NH Ok? 10MQ Si Figure 2. Machine Model Charged Device Model: Simulates the discharge that occurs when a pin on an IC charged to either a positive or negative potential con- tacts a conductive surface at a different (usually ground) potential. RLC = 09, ~0 nH, 1 pF-20 pF. I 1GQ 1Q CHARGE| < > | DISCHARGE (wv) DIELECTRIC GROUND PLANE Figure 3. Charged Device Model Comparison of HBM, MM, and CDM Waveforms Figure 4 shows 400 V HBM, MM, and CDM discharge waveforms on the same current vs. time scale. These waveforms are of great use in predicting what failure mechanism may result on a particular device type due to ESD events simulated by one of these three models. The rise time for the HBM waveform is <10 ns (typically 6 ns-9 ns), and this waveform decays exponentially to- wards OV with a fall time of >150ns. MIL-STD-883 Method 3015 Electrostatic Discharge Sensitivity Classifi- cation requires a rise time of <10 ns and a delay time of 150 + 20 ns (Method 3015 defines delay time as the time for the waveform to drop from 90% of the peak current to 36.8% of the peak current). The peak current for the HBM waveform is ~400 V/1500 Q or 0.267A. Although this peak current is much lower than that for 400 V CDM and MM events, the relatively long duration of the total HBM event results in a discharge of relatively high energy. 2-7 2 HBM = = 2 T T T T T 7 Tv 20ns/DIV t 64 44 2_ MM o aN = 0 t T a 1 < 20ns/DIV t 2-4 4 2 = 77 cDM < T qT T qT T qT T qT T T 20ns/DIV t Figure 4. Relative Comparison of 400 V HBM, MM, and CDM Discharges The MM waveform consists of both positive-going and negative-going sinusoidal peaks with peak magnitudes that decay exponentially. The initial MM peak has a rise time of =14 ns, i.e., only slightly greater than that of the single HBM peak. The total duration of the MM wave- form is comparable to that for the HBM waveform. How- ever, the peak current for the first peak of the 400 V MM event is =5.8 A, which is the highest of the three models. The next four peaks, though decreasing in current, still all have magnitudes of >1 A. These multiple high current peaks of substantial duration result in an overall dis- charge energy that is by far the highest of the three models because there is no current limiting; R = 0. The CDM waveform corresponds to the shortest known real-world ESD event. The socketed CDM waveform has a rise time of 400 ps, with the total duration of the CDM event of =2 ns. The CDM waveform is essentially unipo- lar, although some slight ringing occurs at the end of the CDM event that results in some negative-going peaks.With a 400V charging voltage, a socketed CDM dis- charge will have a peak current of 2.1 A. However, the very short duration of the overall CDM event results in an overall discharge of relatively low energy. Summary of ESD Models Table | is a reference table that compares the most important characteristics of the three ESD simulation models. Table I. Model HBM MM Socketed CDM Simulate Human Body | Machine Charged Device Origin US Military Japan 1976 AT&T 1974 Late 1960s Real World Yes Generally No | Yes RC 1.5kQ, 100 pF] 0, 200 pF 1.Q, 1 pF-20 pF Rise Time <10 ns 14 ns* 400 ps** IpEak at 400 V 0.27A 5.8 A* 2.1 A** Package Dependent | No No Yes Leakage Recovery No No Yes Standard MIL-STD-883 | ESD Assoc. ESD Assoc. Draft Method 3015 | Standard $5.2; EIAJ Standard ED-4701, Method C-111 Standard DS5.3 * These values are per ESD Association Standard $5.2. ElAJs stan- dard ED-4701 Method C-111 includes no waveform specifications. **These values are for the direct charging (socketed) method. Prevention When auditing a facility in which ESD protective mea- sures will be taken, the following should be considered:* e There must be a grounded workbench on which to handle static sensitive devices incorporating: a) Personal ground strap (wrist strap) b) Conductive trays or shunts, etc. c) Conductive work surface d) Conductive floor or mat e) Acommon ground point e All steel shelving or cabinets used to store devices must be grounded. The relative humidity should be controlled; the desir- able range is 40 to 60 percent. Where high relative humidity levels cannot be maintained, the use of ion- ized air should be used to dissipate electrostatic charges. e All electrical equipment used in the area must be grounded. e Prohibit the use of prime static generators, e.g., Scotch tape. e Follow up with ESD audits at a minimum of three month intervals. e Training: Keep in mind, the key to an effective ESD control program is TRAINING. Training should be given to all personnel who come in contact with inte- grated circuits and should be documented for certifi- cation purposes, e.g., ISO 9000 audits. Determining whether a device failed as a result of ESD or Electrical Overstress (EOS) can be difficult and is of- ten best left to Failure Analysis Engineers. Typically ESD damage is less obvious than that of EOS when elec- trical analysis and internal visual analysis are performed. In the case of ESD, events of 1 kV or more (depending on the ESD rating of the device) can rupture oxides (inter layer dielectric of the die) and damage junctions in less than 10 ns (see Figure 6). Alternately, EOS conditions leading to 1 to 3 amps of current for a duration of =1ms can cause sufficient self-heating of bond wires to fuse them. Such conditions can occur as a result of latch-up. Lower currents can cause rapid melt- ing of chip metallization and other interconnect layers (see Figure 5). Figure 5. Scanning Electron Microscope View of a Fused Metallization Site, as a Result of Electrical Overstress Figure 6. Scanning Electron Microscope Cross- Sectional View of a CDM ESD Site. This subsurface site could not be viewed from the surface with an optical microscope.A quick analysis can be performed on site to evaluate ifa device may have been overstressed or may have been subjected to an ESD event. In order to perform this analysis, to compare the pin-to-pin I/V results of the sus- pect device to those of a known good device, a curve tracer or similar equipment should be used. A typical set of I/V traces for a short circuit, open circuit or ESD leakage on a digital input pin (with reference to the Vss supply pin) of a 12-bit DAC is shown in Figure 7. woe dee ee ee. i * SHORT CIRCUIT. = | ne | ne i m@) =] =) ]| 5101011 Sa Figure 7. Example of an Unpowered Curve Trace Analysis of a Digital Pin versus a Supply Pin (Vss) LATCH-UP Latch-up is a potentially destructive situation in which a parasitic active device is triggered, shorting the positive and negative supplies together. If current flow is not limited, electrical overstress will occur. The classic case of latch-up occurs in CMOS output devices, in which the driver transistors and wells form a pnpn SCR structure when one of the two parasitic base-emitter junctions is momentarily forward biased during an overvoltage event. The SCR turns on and essentially causes a short between Vpp and ground. Triggering Mechanisms There are two main triggering mechanisms. First, if the input/output (I/O) pin voltage is raised above the posi- tive supply, or lowered below the negative supply, one of the parasitic transistors is turned on. The current re- turning to the supply through the collector causes a volt- age drop across the base-emitter of the second parasitic transistor. In turn, the collector current of the second transistor maintains a forward bias on the base-emitter of the first transistor. If the product of the two transistor gains is greater than unity, the condition may be self- sustaining and can persist even after the external volt- age is removed. Yoo S$ RWELL > 3 ap E OUTPUT ON OUTPUT r < >sup GND Figure 8. Parasitic SCR. The Diffusions ina CMOS output form a parasitic SCR. The resistors are labeled for an n-well process. This triggering mechanism can occur if excessive volt- age overshoot is present at the I/O pin, or if the signal arrives at the input before the power supplies are ap- plied to the device, or due to electrostatic discharge. This latch-up is usually limited to the devices directly connected to the pin. GND OUTPUT Yop I1 CY GND OUTPUT pt Lo+ | n+ Let] Let] Lot] AA a! | p-sub a n-well Voo Figure 9a. Output Overvoltage Triggering. Initial hole current flows when the output voltage is raised above Vpp. This current causes a voltage rise in the substrate under the NMOS device. GND OUTPUT Ypo _f1 Ct ctr GND OUTPUT Ne | Ne n-well pub Reus Figure 9b. Current Multiplication. The substrate voltage rise actively biases the second parasitic transistor into conduction. The electron current subsequently causes a voltage drop in the n-well, further turning on the first transistor. If the product of the current gains is larger than one, the final current flow between the supplies can be self-sustaining, limited only by internal resistances, i.e., an SCR. Although triggering is by an overvoltage event (typically m of only a diode drop above or below the power sup- plies), the industry practice is to classify the I/O suscepti- bility in terms of the amount of excess current the pin can source or sink in this overvoltage condition before the internal parasitic resistance's develop enough volt- age drop to sustain the latch-up condition. A value of 100 mA is generally considered adequate, with 200 mA considered immune to latch-up. The second triggering mechanism occurs if a supply voltage is raised enough to break down an internal junc- tion, injecting current into the SCR previously described. This triggering mechanism can occur due to supply tran- sients, or electrostatic discharges shunted to a supply rail. Unlike the case of 1/O triggering, latch-up can occur anywhere on the die and is not limited to the vicinity of the external power connections or I/O pins. The susceptibility to power supply overvoltage is usu- ally limited by the fabrication process on which the de- vice is manufactured, and can be found in the data sheet under the Absolute Maximum Rating specification. If this rating is exceeded, permanent EOS damage may occur. Operating a device near the maximum ratings may degrade the long term reliability of the device. Also the electrical specifications are applicable only at the =, supply specified on the data sheet and will not be guar- anteed above these ratings.Design Rules The following is a set of rules to be followed for all de- signers using CMOS and Bipolar-CMOS ICs:5 1. Digital inputs and outputs should not be allowed to exceed Vpp by more than 0.3 volts at any time. This includes a power-down situation when Vpp = 0 volts. 2. Digital inputs and outputs should also not be allowed to go below DGND by more than -0.3 volts. 3. For mixed signal devices, DGND should not be al- lowed to exceed AGND by 0.3 volts. 4. For a CMOS or Bipolar-CMOS DAC, lgyr should, in general, not be allowed to drop below AGND by more than 0.3 volts. Some DACs can tolerate significant lout current flow, however, without any danger of latch-up. Latch-Up Prevention Techniques The following recommendations should be imple- mented in general, for all applications with CMOS and Bipolar-CMOS ICs that violate one or more of the previ- ously discussed rules: 1. If the digital inputs or outputs of a device can go be- yond Vpp at any time, a diode (such as a 1N914) con- nected in series with Vpp will prevent SCR action and subsequent latch-up. This works because the diode prevents the base current of the parasitic lateral-PNP transistor from flowing out the Vpp pin, thus prevent- ing SCR triggering. This is shown in Figure 10. Diodes are also a reliable solution if power-up se- quencing is identified as the failure mechanism. In such a case, the insertion of a Schottky diode be- tween the logic inputs and the Vpp supply rail (the anode of the diode connected to the logic inputs), will ensure that the logic inputs do not exceed the Vpp supply by more than 0.3 volts, thus preventing latch- up of the device. +5V ov 9 G inote 4 lbp = 9 Vop | IC POWERED UP IC POWERED DOWN Yop 4 Bs Ic#1 IcK2 ly =O Tt) Rour foutpuT = |in= INPUT Asus WW > Ib=0 45 y DGND AA, x DGND COMMON GAOUND lbenn = 9 + IF Figure 10. Adding an inexpensive silicon diode in series with the Vpp pin of the unpowered IC effec- tively prevents the parasitic lateral-PNP transistors base current from flowing and inhibits SCR action. However, the one exception to this rule is when the input range of a device exceeds the supply voltage range of the device, e.g., by design the AD7893-10 12- bit A/D subsystem, the input range is +10 V and the supply is +5 V. 2. If the digital inputs and outputs of a device can go below DGND at any time, a Schottky diode (such as an HP5082-2835) connected from those inputs or out- puts to DGND will effectively clamp negative excur- sions at -0.3 volts to 0.4 volts. This prevents the emitter-base junction of the parasitic NPN transistor from being turned on, and also prevents SCR triggering. Figure 11 shows the connections for the Schottky diodes. ~\ INPUT CLAMPED | +5V AND DAMPED 1N914 0.3-- | Yop 7 Yo) |. _ IC#2 4 ic#H1 > . Rout | Apampinc Loup sus mw OUTPUT P O 45 PARASITIC TRACE INDUCTANCE DGND HP5082- A ! ho HP5082- oe Cn ou 4 2635 DGND COMMON GROUND Figure 11. Adding Schottky diodes from the inputs and outputs of a CMOS IC to DGND protects against undervoltages causing conduction of the parasitic NPN, thus inhibiting SCR action. The series damp- ing resistor makes ringing due to long PC board traces die out more quickly. 3. If the DGND potential can occasionally exceed AGND by more than 0.3 volts, a Schottky diode placed be- tween the two pins of the device will prevent conduc- tion of the associated parasitic NPN transistor. This provides additional protection against latch-up as shown in Figure 12. An extra diode connected in in- verse parallel with the one just mentioned provides clamping of DGND to AGND in the other direction and will help to minimize digital noise from being in- jected into the IC. To identify over- and under-voltage events as described in points (2) and (3) above, the use of a storage oscillo- scope is suggested, set at the maximum ratings specifi- cation for each pin. Set the Time/Div. to the minimum setting on the oscilloscope (preferably in the ns range). This test should be conducted over a long period of time, e.g., overnight. 4. In circuits where the Ioyr pin of a CMOS IC can be pulled below AGND, another Schottky diode clamp between these two terminals will prevent sensitive+5V 9 . LATERAL < PNP =m b > 2 2 R2 Rs VERTICAL J} ] NPN a Raz o\$__ _ | Hp 5082-2835 f | SCHOTTKY DIODES DGND AGND Figure 12. Connecting Schottky diodes between DGND and AGND prevents conduction of the parasitic NPN transistor, and helps to minimize injected noise from DGND to the analog output. ICs from latching up. This condition sometimes oc- curs with high speed bipolar operational amplifiers that are used as current-to-voltage converters follow- ing a DAC. During power-up or power-down transi- tions, the op amps inverting input presents a low impedance from Igur to the negative supply rail. An unprotected DAC may fail without the recommended Schottky diode clamp to AGND. 5. In designs that have long digital PC board traces be- tween components and are therefore prone to induc- tive ringing problems, a series damping resistor of 10 Q-100 will be beneficial. This resistor increases the damping factor of the equivalent series RLC net- work and causes the ringing to decay more quickly. This will help to prevent conduction of the input or output protection diodes. High Voltage Transients If power supply overvoltaging is identified as the failure mechanism, a reliable solution is the insertion of a TransZorb* transient voltage suppressor (TVS). What is a TVS and how does it work? Transient voltage suppressors (TVSs) are devices used to protect vulnerable circuits from electrical overstress such as that caused by ESD, inductive load switching and lightning-induced line transients. Within the TVS, damaging voltage spikes are limited by clamping or ava- lanche action of a rugged silicon pn junction which re- duces the amplitude of the transient to a nondestructive level. In a circuit, the TVS should be invisible until a transient appears. Electrical parameters such as break- down voltage (Vga), standby (leakage) current (Ip), and capacitance should have no effect on normal circuit performance. To limit standby current and to allow for variations in Ver caused by the temperature coefficient of the TVS, the TVS breakdown voltage is usually 10% above the *TransZorb is a registered trademark of General Semiconductor Industries, Inc. reverse standoff voltage (Vp), which approximates the circuit absolute maximum operating voltage. When a transient occurs, the TVS clamps instantly to limit the spike voltage to a safe level, called the clamping voltage (Vc), while conducting potentially damaging current away from the protected component. A TRANSIENT PEAK I\ I \ i +30V } \ X \ TVS CLAMPING +20V VOLTAGE (V,) +12V NORMAL OPERATING VOLTAGE tC FAILURE THRESHOLD TIME Figure 13. Transients of several thousand volts can be clamped to a safe level by the TVS. TVSs are designed, specified and tested for transient voltage protection, while a Zener diode is designed and specified for voltage regulation. Therefore, for transient protection the TVS should be selected over the Zener. The surge power and surge current capability of the TVS are proportional to its junction area. Surge ratings for silicon TVS families are normally specified in kilo- watts of peak pulse power (Pp) during a given waveform. Early devices were specified with a 10/1000 us wave- form (10 ps rise to peak and 1000 ps exponential decay to one half peak), while more recent devices are rated for an 8/20 Us test waveform. Power ratings range from 5 kW for 10/1000 us, down to 400 W for 8/20 us. This power is derived from the product of the peak voltage across the TVS and the peak current conducted through the device. TVSs have circuit operating voltages available in incre- ments from 5 V up to 376 V for some families. Because of the broad range of voltages and power ratings avail- able (as well as the universal presence of transient volt- ages), TVSs are used in a wide variety of circuits and applications. As an example, consider a pressure transducer which operates at 28 V, placed in an environment in which it encounters a transient voltage of 140 V peak, having a source impedance of 2.Q and a duration of 10/1000 ps. The failure threshold of the transducer is 40 V, therefore the TVS must clamp at 40 V or less. The current deliv- ered by this transient is: l= (140 V-40 VV2Q =50A Note that the voltage clamping action of the TVS results in a voltage divider whereby the open circuit voltage of the transient appears across the combination of the source impedance and the TVS device. Thus the TVSclamping voltage is subtracted from the transient volt- age leaving a net source voltage of 100 V. When the clamping voltage is high compared to the transient peak voltage, the current is significantly reduced. This circuit can be protected with a 5 kW rated TransZorb TVS which will easily sustain the surge current. TRANSIENT VOLTAGE CLAMPED TRANSIENT AAA VY 7 2av | y ay LOAD ) Figure 14. A5 kW TVS is required to handle the surge current. An alternate and more economical approach is to add a series resistor to effectively increase the source imped- ance thus limiting surge current as illustrated in Figure 15. Since the current drawn by the transducer under normal operation is small (<20 mA typical), perfor- mance is not adversely affected by a reduction in supply current. For a small load current, 10 mA, the voltage drop across the added resistance is minimal, about 250 mV for a 25 ohm resistor. Adding this resistor reduces the surge current to: [= (140 V - 40 V)(2Q + 26Q) =3.7A This is less than one-tenth the surge current without the resistor. A TVS with lower power rating is able to handle the resulting current. In this case a 500 W sup- pressor replaces the 5 kW device, saving board space and cost. 20 250 | 25 T 2BV *K ow LoaD Figure 15. The series resistor reduces transient current allowing a much smaller TVS to be used. Carbon composition resistors are recommended for this application because of their energy dissipation capabil- ity. Steady state power dissipated by the resistor (VxI) is 2.5 mW requiring the lowest rated resistor available for adequate margin. TYPICAL TVS APPLICATIONS DC Line Applications TransZorb TVSs on power lines prevent IC failures caused by transients, power supply reversals or during switching of the power supply between on and off (Figure 16). Figure 16. For power sources utilizing the TransZorb TVS, the TransZorb TVS is chosen such that the reverse stand-off voltage is equal to or greater than the dc output voltage. For certain applications it may be more desirable to re- place the series resistor (R) with an inductor (Figure 17). R R +0~\\-9 O W-e0 15V : To AC RECTIFIER TO INPUT Loap INPUT NETWORK EK oa o_4 0 =e) Figure 17. Signal Line Applications Input pins are vulnerable to low energy, high voltage static discharges or crosstalk transmitted to the signal wires. Limited protection is provided by the clamp diode or an input network within the IC substrate (Figure 18). q .> bo x 5 >~o O OR O-~W 4 L Figure 18. Transients generated on the line can vary from a few mi- croseconds to several milliseconds in duration and up to 10,000 volts in magnitude. Excess current passing through the diode can cause an open circuit condition or a slow degradation of the circuit performance. TransZorb TVSs located on the signal line can absorb this excess energy (Figure 19). Figure 19. A further reference on the subject of using TransZorbs for circuit protection is Analog Devices Application Note AN-311, entitled How to Reliably Protect CMOS Circuits against Power Supply Overvoltaging.IN SUMMARY Designing an application with maximum protection of the integrated circuits is a challenging problem with a solution that depends on many factors. The following is a brief summary of the protection schemes discussed in this application note: 1. Personnel should be trained in the proper handling techniques for prevention of EOS/ESD damage. 2. A good facilities ground system including shielding of equipment and data lines should be implemented. 3. Use transient suppressors judiciously, i.e., check if there are spikes on the supply and the ground lines which may exceed the maximum ratings of those pins. 4. Review the proper power-up sequence of the device(s). The correct order should normally be: GND, Main supplies (if possible the substrate supply being first), Vcc, Vrer. and finally all other pins. 5. Review the data sheet, in particular the maximum rat- ings section. Remaining devices from a lot that may have been mistested or subjected to the same conditions as those of any failing devices should be evaluated to determine if latent damage may be present. This analysis should be performed due to the possibility that overstress con- ditions existed which did not cause immediate failure but induced subtle damage that could result in long- term reliability problems. Finally, the issue of input overvoltage protection for am- plifiers is not discussed in this application note. How- ever, it is exclusively discussed in two other Analog Devices publications; (1) Joe Buxton, "Simple Tech- niques Protect Amplifiers from Input Overvoltage, Ana- log Dialogue 28-3, 1994, and (2) Joe Buxton, "Input Overvoltage Protection, System Applications Guide, Analog Devices, 1993, pp 1-56 to 1-74. REFERENCES Henry Domingos, "Circuit Design for EOS/ESD Protec- tion, Proc. 1982 EOS/ESD Symp., pp. 1-17 to 1-21. 2John A. Schmidt, Manager of Technical Services IMCS Corporation, Santa Clara, CA, "CDM-The Newest ESD Test Model, 1991. 3MIL-STD-883 Method 3015, Electrostatic Discharge Sensitivity Classification, Military Standard Test Methods and Procedures for Microelectronics. ESD Prevention Manual, 1986. Norwood MA; Analog Devices Inc., pp 9-11. Contains additional references. Mark Alexander, "Understanding and Preventing Latch-Up in CMOS DACs, AN-109. Free from Analog Devices, PMI Division. General Instrument, Power Semiconductor Division Data Book/11th edition, pp. 633, 696-703. Contains ad- ditional references. Andrew Olney, Analog Devices, Inc., personal communication E2054-15-8/95 PRINTED IN U.S.A.A Guide to Applying and Measuring Operational Amplifier Specifications By Ray STATA, of Analog Devices Since there are no established standards for operational amplifier specifications we shall discuss the terms used to define operational amplifier characteristics as well as the limitations which must be observed in applying the published data to actual circuits. The test circuits used to measure these parameters are shown. Although these test circuits are applicable to a wide range of operational amplifiers, _ Special amplifiers such as FET, chopper- stabilized or ultra-fast response ampli- fiers may require changes in the recom: mended circuit values or in some cases different test methods to measure their specifications. As a general rule the power supply for these measurements should have line and load regulation of about 0.1% and ripple should be no more than a few millivolts. Figure 1 gives a simplified equivalent circuit for an operational amplifier show- ing many of the sources of error which are discussed in the text. The specifi- cations should be referenced to this diagram to predict their effect in a, closed loop circuit. For a single-ended amplifier you would assume that the plus or non- inverting input is grounded. Open Loop Gain Open loop gain, A, is defined as the ratio of output voltage to error voltage ec be- tween inputs as shown in Figure 1. Gain is usually specified only at d.c. (A,), but in many applications such as a.c. ampli- fiers the frequency dependence of gain is also important. For this reason the typical .open loop gain response is published for each amplifier. The open loop gain response of most amplifiers can be approximated by Figure 2. Open loop gain changes with load . impedance (R,), ambient temperature and supply voltage. As a rule, open loop gain will not change more than a factor of 10 between rated load and no load conditions. Most operational amplifiers have a positive gain temperature coef- ficient of about 0.5 to 1%/C and gain changes with supply voltage at about 2%/%. The manufacturer specifies all open loop gains at rated load, 25C and rated supply voltages. A practical circuit for measuring open loop gain over a range of frequencies is shown in Figure 3. The voitage divider on the negative input boosts the sensi- tivity of the error voltage by 100 times which makes it possible to measure gains up to one million. At low frequen- cies open loop gain is constant so that d.c. gain can be measured by a low frequency signal (about 5 Hz). The. voltage divider may not be necessary for .. low gain amplifiers (below 20000) and it is not recommended for measuring gain at high frequencies where open loop gain is less. At very best, noise pick-up is a problem for measuring high gains and care must be taken to adequately shield the test circuit. At high frequencies the _ amplitude of the output valtage must be reduced to avoid exceeding the slewing rate of the amplifier. For this reason the output voltage should be adjusted, so that e, (peak) < slew rate/@,, where w, is the test frequency. Significance of Open Loop Gain Operational amplifiers are rarely used open loop. Instead negative feedback is used around the amplifier to improve the accuracy of the circuit. This introduces a second term, closed loop gain (G), which is defined as the gain of the circuit with feedback. The simple in- verting amplifier in Figure 4 illustrates this point. Linearity, gain stability, output im- pedance and gain accuracy are all improved by the amount of feedback. Figure 5 graphically illustrates the rela- tion between open loop gain and closed loop gain. The excess of open loop gain over closed sop gain is called loop gain. (Subtraction of dB is equivalent to arithmetic division.) The improvenient of open loop performance due to feedback is directly proportional to loop gain. As a general rule for moderate accuracy, open loop gain should be 100 times greater than the closed loop gain at the frequen- cy, or frequencies, of interest (that is loop gain = 100). For higher accuracy, loop gain should be 1000 or more. To: illustrate, we recall that open loop gain stability for most operational amplifiers is about 1%/C. With loop gain of 100, closed loop gain stability would be 100 times better or 0.01%/C. Likewise, closed loop output impedance would be 100 times less than open loop output impedance with a loop gain of 100. Rated Output Voltage and Current Rated output voltage, E.. is the maximum peak output voltage which can be obtained at rated output current beforeA Guide to Applying and Measuring Operational Amplifier Specifications = LOOP. GAIN OPEN LOOP GAIN CLOSED LOOP GAIN a | t+ 4 *N eg as __ et Fig. 5 & ecm = e*/CMR e,ze - at . S805 4e 40s Xs" Egst(Ga )aT + ( ave 28) avg +( a Jat BV@ 25C mweec BW % av/ony sip May SE REQUIRED : . TO AVOID PEAKING WITH ip? Ip + (2 Py at * Cw 5) as +(42 P) at SOME AMPLIFIERS. nA@ 25C = nAs*C nhs % nA/DAY Fig. 1 4 ook a 8 sok z 6db/OCTAVE = 60F a Ao 5 40- a & 1g. oO 20 f, 1 1 J 1 i i iP 10% 103 10% 105 18 107 Fig. 2 FREQUENCY IN. Hz o ft R, = Re OO Re=Eg/Ig R; (OK) Ry (IOK) (*:) & IL tT - -_8 20-l00pf a. 8, PEAK 7 7 ee Fig. 8 100 p= mort LR ER po Lg Ro= Eo 2 tEg-- - - -- - -- re = = = oT = 90% mee A=IOl Dex /de o QUTPUT SLEWS BETWEEN 0% . y 5 AND 90% LEVELS AT SLE Fig. 3 e RATE Sf AV/AT = l AMPLIFIER COMES OUT OF [Te 2 -| SATURATION WN OveRLoaD 2 We 5 ote PERIOD 7 pte oyTPuT ' =Ege- fa = /SatGRaten By ee 1 we ne |, OVERDRIVE C) OPEN LOOP GAIN (ars FD v 415 LARGE AMPLITUDE INPUT DRIVES be AMPLIFIER INTO SATURATION = + CLOSED LOOP GAIN (G)= 482 TIME = = i Fig. 4 Fig. 9 Fig. 1 Fig. 5 Operational amplifier equivalent circuit. Fig. 2 Typical open loop gain response. Fig. 3 Open loop gain test circuit. Fig. 4 Closed loop circuit. Determination of loop gain. Fig. 6 Inverting circuit for measuring fi. fy. S, T. Fig. 7 Non-inverting circuit for measuring f. fy. S, T, Eo, Fig. 8 Measuring full power response. Fig. 9 Overload recovery and slew rate illustration. clipping or excessive non-linearity oc- curs. This measurement is made at rated power supply voltage; at other supply voltages the output will swing to within about 4 volts of the supply voltage. Also the output voltage swing will increase somewhat at lower load current. Rated output current, Ij, is the minimum guaranteed value of current at the rated output voltage. Load impedance less than E,/l, can be used but E, will decrease, distortion may increase and open loop gain will be reduced. Driving large capacitance loads at high frequen- cies will present a low load impedance which may then exceed the rated output current. Any convenient circuit such as Figure 3 or Figure 6 can be used to measure E, and I.. Unity Gain Small Signal Response Unity gain small signal response, f,, is the frequency at which the open loop gain becomes unity or zero dB (see Figure 2). Small signal indicates that in general it is not possible to obtain large output voltage swing at high frequencies because of distortion due to slew rate limiting. Therefore in both mea- suring f, and using the amplifier at high frequencies, the output voltage swing must be restricted to avoid slew rate limiting. This implies that the peak output voltage, e,, for a sinusoidal signal at the unity gain frequency, f,, must be less than S/2nf,, where S is the slew rate. For amplifiers with symmetrical re- sponse on each input, f, may be measured by either the inverting circuit of Figure 6 or the non-inverting circuit of Figure 7. Some units such as chopper-stabilized amplifiers or wideband amplifiers with feed forward design have fast response only on the negative input which restricts testing and use to the inverting circuit. Remember that the closed loop unity gain response of Figure 6 will be about half the open loop unity gain response due to the loading of the feedback net- work. Moreover, large values of feedback resistance when coupled with stray capacitance may reduce the closed loop response and therefore the smallest possible value of R, should be used, the limit being set by output current capa- bility I,. Sometimes f, is called unity gain- bandwidth product which implies that open loop gain at other frequencies can be predicted from this number. However, gain-bandwidth product is constant only ~for amplifiers with 6 dB/octave roll off! For fast roll-off amplifiers, gain-band- width product increases with gain and thus we publish the open loop response curve to give typical gain at each frequency. Full Power Response The large signal and small signal re- sponse characteristics of operational amplifiers differ substantially due to dynamic non-linearities or transient satur- ation. An amplifier will not respond to large signal changes as fast as the small signal bandwidth characteristics would predict. The most prominent contributor to large signal response limitations is slew rate limiting in the output stages. Circuit and transistor capacitances can be charged and discharged only so fast due to the limited dynamic range of the driving circuits. Transient saturation can also occur in the input stages of the amplifier due to overloading the input stage or due to common mode voltage slew rate limiting, but this is rarely a problem as cor.pared with saturation of the output stages. Full power response, f. is the maxi- mum frequency measured at unity closed loop gain, for which rated output voltage, +E, can be obtained for a sinusoidal signal at rated load without distortion due to slew rate limiting. Note that this specification does not relate to re- sponse in the sense of gain reduction with frequency. Instead it refers only to distortion in the output signal caused by slew rate limiting. For a sinusoidal signal, the maximum slope or rate of voltage change occurs at zero crossing and is proportional to the peak amplitude and the frequency. Thus we see that to a first approximation slew rate, S, and full power response, t, are related by equation 1. de, =2nfE = dt max Moro As the voltage swing is reduced below rated output, E., the operating frequency can be proportionally increased without exceeding the slew rate, S. In the limit the operating frequency approaches the unity gain bandwidth, f,, and the corre- sponding voltage signal defines the maximum peak amplitude for small signal unity gain response. The circuits of Figure 6 or Figure 7 can be used to measure full power response depending on whether inverting or non-inverting A Guide to Applying and Measuring Operational Amplifier Specifications parameters are measured. Where dynamic saturation of the output stages is the primary cause for slew rate limiting either test circuit will give equivalent results. For very fast response amplifiers, load capacitance and/or capacitance from the output to the negative input will cause apparent slew rate limiting and conse- quent degradation of full power re- sponse. This is due to saturation of amplifier output current in charging these capacitances and therefore such capaci- tances must be low. Output distortion can be measured either by a distortion meter on the output or by observing a Lissajous pattern on an oscilloscope. There is no industry-wide accepted value for the distortion level which determines the full power re- sponse limitation, but a number like 1% to 3% is a reasonable figure. One subtle point here is that closed loop output distortion depends on the amount of feedback or loop gain and therefore it depends on the closed loop gain of the measurement. Full power response is generally measured at unity gain where loop gain is the highest. At higher closed loop gains output distortion will increase for the same full power response frequency. In many applications the additional distortion which is caused by exceeding the full power response can be comfort- ably ignored. However, a far more serious effect, often overlooked, is that a d.c. offset voltage can be generated when the full power response is exceeded due to .rectification of the asymmetrical feedback waveform or due to over- loading the input stage with large distortion signals at the summing junc- tion. These more subtle points in measuring full power response as well as the attendant side effects suggest the circuit of Figure 8 as a more satisfactory test circuit. By viewing the error voltage at the summing junction on an oscilloscope, distortion signals are more easily de- tected, signal generator distortion is eliminated from the measurement and frequency dependent d.c. offset can be readily observed. Slewing Rate The origins of slewing rate limitations were discussed in the previous section. Slewing rate, S, usually expressed in volts/ sec, defines the maximum rate of change of output voltage for a large step change. Equation 1 suggests a convenient method to measure slewing rate by first measuring full power response, f,, and then calculating S$. Although this test method yields usable results for most amplifiers in most applications, the relationship of equation 1 does not apply under all conditions. First, slewing rate is a non-linear function of output voltage and equation 1 measures slewing rate only at zero volts output. This second-order effect can usually be safely ignored in most applications. However, for certain amplifiers, particularly fast response types, the slew rate may be higher than that predictable from f,. In these cases f, is limited by factors other than slew rate such as d.c. offset errors which are generated by the rectification of large high-frequency error voltages. A more direct method to measure slewing rate is to apply low-frequency square waves (about 100 Hz) to the input of Figure 6 or Figure 7 which cause full voltage swing at the output and to observe the rise time from 10 to 90% on an oscilloscope (see Figure 9). Small feedback resistors must be used to avoid degradation of slewing rate due to stray capacitance. In applying operational amplifiers re- member that repetitive input waveforms whose rise time exceeds the amplifiers slewing rate will generate voltage spikes at the summing junction. These spikes are usually asymmetrical and are also usually clipped asymmetrically by the input circuit of the amplifiereither or both of which effects will cause d.c. offsets at the output. Overload Recovery Overload recovery, 1, defines the time required for the output voltage to recover to the rated output voltage E, from a saturated condition. For this test the circuit of Figure 6 or 7 is used with an input square wave adjusted to be 50% greater than the voltage required to saturate the amplifier output. The square- wave frequency should be adjusted to about 100 Hz and the input-output signals should be compared on a dual trace oscilloscope as_ illustrated in Figure 9. in some amplifiers the overload re- covery will increase for large impedances (greater than 50 KQ) in the input circuit, either the summing impedance for Figure 6 or the source input for Figure 7. Published specifications apply for low| OVERLOAD RECOVERY | CIRCUIT IN4i4B IN4148 (N9S61B INSG6IB Ble <To-T ASSUMING Rf >>R; AND Rs >> Rj S2 tot at [eos t Rs lig ig] ign ip-ig Parameter | Switch Position Out put S$} Se Voltage Re fos Closed| Closed e907 -(=*) eos i ix Rey. .- ip Open | Closed eor (2 -)Rsib . R ig Closed] Open eor-(a*) Reif I . R 'd Open | Open | eg* (F*)R sig i Set e, for 1 to 5 Hz, increase R, until opening S, increase e, by factor of 2. Then R= R, Ry Ry RyrxC, = Ry xCq TUNNEL NULL METERS GRI232A O+Vs Balance d.c. output reduce @; to smallest possible voltage and frequency Fig. 12 Fig. 10 External clamp circuit for +10 volts. Fig. 11 Test circuit for offset voltage, bias current and difference current. Fig. 12 Differential impedance test circuits. A Guide to Applying and Measuring Operational Amplifier Specifications impedances and assume that overload recovery is not degraded by stray capaci- tance in the feedback network. Normally, overloaded recovery time runs about one millisecond. For the inverting configuration an external clamp circuit can be added to improve overload recovery as illustrated in Figure 10. This circuit prevents the output from satu- rating and therefore circumvents any delays due to overload recovery. The only constraint for proper operation is that input current (e,/R;) shall be approximately less than the rated output current 1, minus the load current. The clamp circuit cannot be used with the non-inverting and differential configu- rations. Initial Offset Voltage Offset voltage, e,., is defined as the voltage required at the input from a zero source impedance to zero the output, at any temperature, supply voltage and time (see Figure 1). Initial offset voltage, E,., defines the offset voltage at 25C and rated supply voltages. In most amplifiers, provisions are made to adjust initial offset to zero with an external trim potentiometer. Some ampli- fiers are internally trimmed to guarantee some maximum limit on initial offset (usually +1mV) which means that in certain applications the external trim pot can be eliminated. On special order any amplifier from the manufacturer can be internally trimmed to +1mV initial offset orless. Initial offset can be measured with the circuit of Figure 11, where an appropriate fixed resistor is substituted for the external trim potentiometer. There is a warm-up drift of offset voltage following the application of power supply voltage and it is recommended that you let the amplifier stabilize for at least 15 minutes before making measurements. {nitial Bias Current Bias current, i,, is defined as the current, at any temperature, supply voltage and time, required at either input from an infinite source impedance to zero the output assuming zero common mode voltage. For differential amplifiers bias current is designated by i,- for the negative input and by i,t for the positive input. For single-ended ampli- fiers, like chopper-stabilized units, bias current refers to the current at the negative input only. Initial bias current, |,, is the bias current at either input measured at 25C, rated supply voltages and zero common mode voltage. The designation (0,+) or (0,) indicates that no internal compensation is used to reduce initial bias current so that the polarity is always known. The sign tells to which power supply voltage an external compensating resistor should be connected to zero the initial bias current. The designation (+) indicates that internal compensation has been used to reduce initial bias current and that the residual bias current can be of either polarity. In general, compen- sating initial bias current has little effect on the bias current temperature coef- ficient. The circuit of Figure 11 is used to measure initial bias current. Initial Difference Current Difference current, previously called offset current, iy is defined as the difference between the bias currents at each input from an infinite source re- quired to zero the output assuming zero common mode voltage. The input cir- cuitry of differential amplifiers is gener- ally symmetrical so that bias current at each tends to be equal and tends to track with changes in temperature and supply voltage. Usually difference current is 3 to 5 times less than bias current at either input, assuming that initial bias current is not compensated. If the impedance as seen from each input terminal to ground is balanced then offset and drift errors are proportional to difference current rather than to bias current. In most applications, if the external impedances at each input are balanced then there is no particular advantage in using an amplifier where initial bias current is internally com- pensated. Initial difference current, Vy the difference current measured at 25C and rated supply voltage, can be meas- ured by the circuit of Figure 11. Temperature Drift Offset voltage, bias current and difference current all change or drift from their initial values with temperature. By far this is the most important source of error in most applications. The temperature coefficients of these parameters, Ae,,/ AT, Ai,/AT and At,/AT are all defined as the average slope over a specified temper- ature range and are determined by sub- tracting the offset values at the endA Guide to Applying and Measuring points of the temperature range and Operational Amplifier Specifications | dividing by the temperature change. In general, drift is a non-linear function of temperature and the slopes are greater at the extremes of temperature than around normal room ambient. The tem- perature drift coefficients are measured by the circuit of Figure 11. The amplifier is used to boostits own low level input offset signal to a conveniently measur- able voltage at the output. Gain is established by the ratio of R,/R,. The current sampling resistors, R,, must be selected so that voltage drift is smail compared with the drift due to difference current; that is R,* Ai,/AT > > Ae, /AT. Alternatively, voltage drift must be sub- tracted from the data for current drift. One problem in using published voltage drift specifications is that these data apply only to static temperature condi- tions where the temperature of the module is assumed to be uniform. Voltage offset of most differential amplifiers is quite sensitive to thermal gradients, since drift performance depends on the can- cellation of large offset in each transistor of the input differential pair. Therefore in environments where thermal gradients are present voltage offset may exceed that predictable from the drift coefficients. In this case where low drift over a narrow temperature range is critical, it is good practice to insulate or shield the amplifier to assure a uniform temperature. Bias current is not noticeably affected by thermal gradients and difference current, while affected, is far less sensitive to gradients than voltage offset. Bias current and difference current for FET and varactor bridge amplifiers double each 10C and therefore a linearized drift coefficient has littie meaning except over a harrow operating temperature range. Supply Voltage Sensitivity Offset voltage, bias current and differ- ence current will also change when supply voltage is varied. Usually errors due to this effect are negligible com- pared with temperature drift. Static or d.c. supply voltage coefficients, Ae,,/ AV, Ai,/ AV,, Ai,/ AV, are measured with the circuit in Figure 11 by varying supply voltages individually by + 1 volt. There is a common misconception that tracking power supplies whose plus and minus voltages change by the same amounts will improve supply voltage coupling. In general tracking supplies are of no benefit since the positive supply voltage coefficient is usually much larger than the negative supply voltage coef- ficient. Rejection of a.c. noise and ripple on the power supplies is not as good as Static or d.c. rejection, but for almost all amplifiers a.c. rejection will be better than 1 mV/V or 60 dB over a wide range of frequencies. Drift vs Time Offset voltage, bias current and difference current change with time as components age. Static data over long time periods are difficult to obtain because of the in- herent time delays involved. But it is safe to say that the published time drift for amplifiers does not accumulate linearly. For exampie, voltage drift for a chopper- stabilized amplifier (which by the way is by far the best amplifier type for long- term stability) is usually quoted as 1 pV/day whereas cumulative drift over 30 days will usually not exceed 5 pV nor 15 yV in a year. Long-term voltage drift in differential input type amplifiers depends primarily on the aging of collector resistors in the input differential pair. The aging coef- ficient referred to the input is about 300 11V/% change of collector resistance. It is not unlikely that carbon composition resistors will age by 1 or 2% over a year resulting in an offset voltage change of 300 to 600 LV. The use of metal film resistors for the collector resistors will greatly improve long-term stability to the point where base-to-emitter voltage aging is the determining factor. With metal film resistors, drift of offset voltage for transistor amplifiers is about 100 pV/year while FET amplifiers will age somewhat more. Long-term bias current stability in differential input amplifiers again de- pends on resistor stability when internal initial current compensation is employed. In this case, multi-megohm carbon com- position resistors are used (since large value metal film resistors are not avail- able) to supply about 90% of the base bias current. If these resistors change by 1%, the specified initial bias current will change by about 9% which can be a substantial drift. Therefore one can con- clude that amplifiers without internal initial current compensation will exhibit more stable bias current. Under these conditions long-term bias current stabi- lity depends primarily on the stability of the transistor or FET devices which may be better than 1%.x Rs INCREASE Rg TO REDUCE @9 BY 10% THEN Rem? 9R5 &0 Fig. 14 ACTUAL CMR |S NONLINEAR SPECIFICATIONS LIST CMR AS AVERAGE CMR AT HIGH VOLTAGE EXCEEOS SPECIFIED (AVERAGE) VALUE CM ERROR 100K Fig. 13 Common mode impedance test circuit. Fig. 14 llustration of common mode voltage. Fig. 15 CM error vs CM voltage. Fig. 16 CMR test circuit. A Guide to Applying and Measuring Operational Amplifier Specifications Input Impedance Differential input impedance, R,. is de- fined as the impedance between the two input terminals, measured at 25C, as- suming that the error voltage, es, is nulled or very near zero volts (see Figure 1). For a single-ended amplifier, R,, is the input impedance since the plus input is grounded. To a first approxi- mation, dynamic impedance can be represented by a capacitor, C,. in parallel with R,. Differential input impedance is among the most difficult parameters to measure particularly for a high gain, high im- pedance type amplifier. In general this measurement can only be made under laboratory conditions by an experienced engineer with special fixtures to shield against noise pick-up. For this reason most Companies rarely measure this para- meter on a production line basis. Fortu- nately a precise knowledge of R, is not required, since for most circuits, so long as R, is large compared with the external feedback impedance, its value has little bearing on closed loop performance. The circuits of Figure 12 show in principle how R, can be measured with enough attention to reducing noise. These circuits actually measure R, in parallel with the negative input commen mode impedance. However, common mode impedance is usually 10 to 100 times greater than R, so that the error is negligible. Common mode impedance, R,,, is defined as the impedance between each input and ground or power supply common and is specified at 25C. (See Figure 1.) For most circuits common mode impedance on the negative input, Ron has little significance except for the capacitance which it adds to the summing junction. However, common mode impedance on the plus input, R.,,+. sets the upper limit on closed loop input impedance for the non-inverting configuration. Dynamic impedance can be represented by a capacitor, Coy in parallel with R.. which usually runs from 5 to 25 pF on the plus input. The circuit of Figure 13 can be used to measure R..+ up to about 500 M- ohms. Use an oscillator frequency of 1 to 5 Hz and adjust R, for 10% reduction at the output. Then R,,+ = 9 R.. Above this impedance it is advisable to sub- stitute a picoameter for the resistor R, and to measure d.c. bias current as a function of common mode voltage. Common mode impedance is a non- linear function of both temperature and common mode voltage. For FET ampli- fiers common mode impedance is re- duced by a factor of two for each 10C temperature rise. As a function of common mode voltage, R . is defined as average impedance for a common mode voltage change from zero to +E__, that is, maximum common mode voltage. Incremental Rim about some large common mode voltage may be considerably less than the specified average R._, especially for FET input amplifiers. Maximum Voltage between Inputs Under most operating conditions, feed- back maintains the error voltage, es, be- tween inputs very near to zero volts. However, in some applications, such as voltage comparators, or where the input voltage exceeds the level required to saturate the output, the voltage be- tween inputs can become large. E, defines the maximum voltage which can be applied between inputs without caus- ing permanent damage to the amplifier. Placing parallel back-to-back diodes across the input terminals is one way to provide added protection for the ampli- fier. Maximum Common Mode Voltage For differential input amplifiers, the volt- age at both inputs can be raised above ground potential. Common mode voltage, .m IS defined as the voltage above ground at each input when both inputs are at the same voltage. E__ is defined as the maximum peak common mode voltage at the input before clipping or excessive non-linearity is seen at the output. E. establishes the maximum input voltage for the voltage follower connection. (See Figure 7.) E.m ' Measured with the circuit of Figure 7 by increasing the peak input voltage (sinusoidal waveform) until dis- tortion is seen on the scope (about 1 to 3%). The input signal frequency must be well below the full power response frequency, f,, for the non- inverting input. Common Mode Rejection An ideal operational amplifier responds only to the difference voltage between inputs (e+ e~) and produces nooutput for a common mode voltagethat is when both inputs are at the same potential. However, due to slightly differ- ent gains between the plus and minus inputs, common mode input voltages are not entirely subtracted at the output. lf we refer the output common mode error voltage to the input (dividing by gain) and call this the input common mode error voltage, ee.,,, then common mode rejection (CMR) is defined as the ratio of common mode voltage to common mode error voltage. That is CMR = e,,,/ee,,, CMR is sometimes expressed in dB in which case you take 20 times the log (base 10) of the ratio. Errors due to common mode rejection can be represented in the equivalent circuit of Figure 1 by a voltage generator, ,,,- in series with the input. Note that common mode error goes to zero when either input is grounded. Therefore the inverting configuration does not exhibit a common mode error since the plus input is grounded. Thus CMR is only a problem in the non-inverting and differ- ential configurations where common mode voltage varies in direct proportion to the input signal. In this case @e,,, is a basic measuring error which affects the over-all circuit. accuracy. For example, if a 10-volt signal, e., were applied to the input of the circuit in Figure 14, common mode voitage, Cum: 'S equal to the input voltage, e,. This would cause a common mode error voltage, ec,,,, of 2mV for an amplifier with 5000 or 74 dB CMR and thus a 0.2% measuring error. Precisely specifying CMR is compli- cated by the fact that common voltage error, e.,,, Can be a highly non-linear function of common mode voltage and it also varies with temperature. This is particularly true for FET input amplifiers. As illustrated by Figure 15, CMR pub- lished by the manufacturer are average figures assuming an end-point measure- ment at maximum common mode volt- age, +E... But the incremental CMR about some large common mode voltage may be less than the average CMR which is specified. In fact, if common mode error were a linear function of common mode voltage and if CMR were not strongly influenced by temperature then this source of error would be of little consequence. This follows since a linear CMR error can be viewed as a gain error which could be compensated for by adjusting the closed loop gain. Therefore linearity of common mode error, Cfo vs common mode voltage is actually A Guide to Applying and Measuring Operational Amplifier Specifications more important for many applications than CMR itself. The circuit in Figure 16 provides a unique method to instrument CMR meas- urements as well as to measure the non- linearity of common mode errors. The oscilloscope display will duplicate the pattern of Figure 15. A floated power supply allows a_ single-ended oscil- loscope to be used and almost any regulated power supply has floated out- puts with sufficient isolation. Published CMR specifications apply only to d.c. input signals so that this measurement should be made with a signal frequency of 5 Hz or less. CMR at higher frequen- cies, although not guaranteed by the specifications, can also be measured with this circuit. It is further assumed that the external circuit impedances of both the test circuit and the application are small compared with the common mode impedance to avoid additional common mode errors due to impedance un- balance. /nput Noise Input voltage and current noise charac- teristics can be in principle measured, specified and analysed very much like offset voltage and bias current charac- teristics. In fact, offset voltage and bias current drift can be considered noise which occurs at very low frequencies. For this purpose in both the equivalent circuit of Figure 1 and the test circuit of Figure 11, replace e,, by e,, an equivalent voltage noise generator, and replace i,- and i,+ by iy and iy+, equivalent current noise generators. The primary difference in measuring and specifying noise as opposed to d.c. drift is that bandwidth must be considered. At low frequencies, 100 Hz or less, 1/f noise prevails, which means that the noise per root cycle increases inversely with fre- quency. At the mid-band frequencies noise per root cycle is constant or white. To measure noise a sharp cutoff band- pass filter is added to the output of the circuit of Figure 11. Furthermore the impedance, gain and capacitors must be adjusted to assure that neither the ampli- fier nor the external feedback com- ponents limit the noise bandwidth of the measurement. For very low current noise, it becomes very difficult to make wide- band measurements because of the inter- action of stray capacitance and the large sampling resistor values needed to boost sensitivity. Usually two noise measurements are taken. Low frequency noise in a band- pass of 0.01 to 1 Hz is measured ona strip chart recorder and is specified as peak to peak with a 36 uncertainty, meaning that 99% of the observed peak-to-peak ex- clusions will fall within the specified limits. Wideband. noise in a bandpass of 5 Hz to 50 kHz is measured on a VTVM, preferably a true RMS type, and is specified as rms. Of course, shielding becomes very critical in these measure- ments to avoid power line frequency and radio frequency pick-up.