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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
features
DFour 8-Bit D/A Converters
DMicroprocessor Compatible
DTTL/CMOS Compatible
DSingle Supply Operation Possible
DCMOS Technology
applications
DProcess Control
DAutomatic Test Equipment
DAutomatic Calibration of Large System
Parameters, e.g. Gain/Offset
description
The TLC7226C, TLC7226I, and TLC7226M
consist of four 8-bit voltage-output digital-to-
analog converters (DACs) with output buffer
amplifiers and interface logic on a single
monolithic chip.
Separate on-chip latches are provided for each o f
the four DACs. Data is transferred into one of
these data latches through a common 8-bit
TTL/CMOS-compatible 5-V input port. Control
inputs A0 and A1 determine which DAC is loaded
when WR goes low. The control logic is speed
compatible with most 8-bit microprocessors.
Each DAC includes an output buffer amplifier
capable of sourcing up to 5 mA of output current.
The TLC7226 performance is specified for input reference voltages from 2 V to VDD − 4 V with dual supplies.
The voltage mode configuration of the DACs allows the TLC7226 to be operated from a single power supply
rail at a reference of 10 V.
The TLC7226 is fabricated in a LinBiCMOS process that has been specifically developed to allow high-speed
digital logic circuits and precision analog circuits to be integrated on the same chip. The TLC7226 has a common
8-bit data bus with individual DAC latches. This provides a versatile control architecture for simple interface to
microprocessors. All latch-enable signals are level triggered.
Combining four DACs, four operational amplifiers, and interface logic into either a 0.3-inch wide, 20-terminal
dual-in-line IC (DIP) or a small 20-terminal small-outline IC (SOIC) allows a dramatic reduction in board space
requirements and of fers increased reliability in systems using multiple converters. The Leadless Ceramic Chip
Carrier (LCCC) package provides for operation at military temperature range. The pinout is aimed at optimizing
board layout with all of the analog inputs and outputs at one end of the package and all of the digital inputs at
the other.
Copyright 2009, Texas Instruments Incorporated
!" # $%&" !# '%()$!" *!"&+
*%$"# $ " #'&$$!"# '& ",& "&# &-!# #"%&"#
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"&#"0 !)) '!!&"&#+
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
LinBiCMOS is a trademark of Texas Instruments.
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
OUTB
OUTA
VSS
REF
AGND
DGND
DB7
DB6
DB5
DB4
OUTC
OUTD
VDD
A0
A1
WR
DB0
DB1
DB2
DB3
DW OR N PACKAGE
(TOP VIEW)
1920132
17
18
16
15
14
1312119 10
5
4
6
7
8
VDD
A0
A1
WR
DB0
REF
AGND
DGND
DB7
DB6
V
OUTA
OUTB
OUTC
OUTD
D
B4
D
B3
D
B2
D
B1
D
B5
FK PACKAGE
(TOP VIEW)
SS
LinBiCMOS is a trademark of Texas Instruments.
SLAS060F − JANUARY 1995 − REVISED APRIL 2009
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description (continued)
The TLC7226C is characterized for operation from 0°C to 70°C. The TLC7226I is characterized for operation
from −30°C to 85°C. The TLC7226M is characterized for operation from −55°C to 125°C.
AVAILABLE OPTIONS
PACKAGE
TASMALL OUTLINE
(DW) PLASTIC DIP
(N) LCCC
(FK)
0°C to 70°C TLC7226CDW TLC7226CN —
−30°C to 85°C TLC7226IDW TLC7226IN —
−55°C to 125°C — — TLC7226MFKB
functional block diagram
_
+
DAC A
Latch
A
8
_
+
DAC B
Latch
B
8
_
+
DAC C
Latch
C
8
_
+
DAC D
Latch
D
8
Control
Logic
8
4
7−14
15
17
16
REF
DB0−DB7
WR
A0
A1
2
1
20
19
OUTA
OUTB
OUTC
OUTD
8
8
8
8
schematic of outputs
Output
450 µA
VDD
VSS
EQUIVALENT ANALOG OUTPUT
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME NO.†
I/O
DESCRIPTION
AGND 5 Analog ground. AGND is the reference and return terminal for the analog signals and supply.
A0, A1 17, 16 IDAC select inputs. The combination of high or low levels select either DACA, DACB, DACC, or DACD.
DGND 6 Digital ground. DGND is the reference and return terminal for the digital signals and supply.
DB0−DB7 14−7 I Digital DAC data inputs. DB0−DB7 are the input digital data used for conversion.
OUTA 2 O DACA output. OUTA is the analog output of DACA.
OUTB 1 O DACB output. OUTB is the analog output of DACB.
OUTC 20 O DACC output. OUTC is the analog output of DACC.
OUTD 19 O DACD output. OUTD is the analog output of DACD.
REF 4 I Voltage reference input. The voltage level on REF determines the full scale analog output.
VDD 18 Positive supply voltage input terminal
VSS 3Negative supply voltage input terminal
WR 15 I Write input. WR selects DAC transparency or latch mode. The selected input latch is transparent when WR
is low.
†Terminal numbers shown are for the DW, N, and FK packages.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VDD: AGND or DGND −0.3 V to 17 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VSS‡ −0.3 V to 24 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Supply voltage range, VSS: AGND or DGND −7 V to 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range between AGND and DGND −17 V to 17 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (to DGND) −0.3 V to VDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference voltage range: Vref (to AGND) −0.3 V to VDD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Vref (to VSS) −0.3 V to 20 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, VO (to AGND) (see Note 1) VSS to VDD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous total power dissipation at (or below) TA = 25°C (see Note 2) 500 mW. . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, TA: C suffix 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
E suffix −30°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
M suffix −55°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Case temperature for 10 seconds: FK package 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
‡The VSS terminal is connected to the substrate and must be tied to the most negative supply voltage applied to the device.
NOTES: 1. Output voltages may be shorted to AGND provided that the power dissipation of the package is not exceeded. Typically short circuit
current to AGND is 60 mA.
2. For operation above TA = 75°C, derate linearly at the rate of 2 mW/°C.
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recommended operating conditions
MIN MAX UNIT
Supply voltage, VDD 11.4 16.5 V
Supply voltage, VSS −5.5 0 V
High-level input voltage, VIH 2 V
Low-level input voltage, VIL 0.8 V
Reference voltage, Vref 0 VDD−4 V
Load resistance, RL2 kΩ
Setup time, address valid before WR↓, tsu(AW) (see Figure 1) VDD = 11.4 V to 16.5 V *0 ns
Setup time, data valid before WR↑, tsu(DW) (see Figure 1) VDD = 11.4 V to 16.5 V *45 ns
Hold time, address valid after WR↑, th(AW) (see Figure 1) VDD = 11.4 V to 16.5 V *0 ns
Hold time, data valid after WR↑, th(DW) (see Figure 1) VDD = 11.4 V to 16.5 V *10 ns
Pulse duration, WR low, tw (see Figure 1) VDD = 11.4 V to 16.5 V *50 ns
C suffix 0 70
Operating free-air temperature, T
A
I suffix −25 85 °C
Operating free-air temperature, TA
M suffix −55 125
C
* This parameter is not tested for M suffix devices.
electrical characteristics over recommended operating free-air temperature range
dual power supply over recommended power supply and reference voltage ranges, AGND = DGND = 0 V
(unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IIInput current, digital VI = 0 V or VDD ±1µA
I(DD) Supply current VI = 0.8 V or 2.4 V,
VSS = − 5 V, VDD = 16.5 V,
No load 6 16 mA
I(SS) Supply current VI = 0.8 V or 2.4 V, No load 4 10 mA
ri(ref) Reference input resistance 2 4 kΩ
Power supply sensitivity ∆VDD = ±5% 0.01 %/%
All 0s loaded
C and I suffix 65
REF input All 0s loaded M suffix *30
C
i
Input capacitance
REF input
All 1s loaded *300 pF
Ci
Input capacitance
Digital inputs
C and I suffix 8
pF
Digital inputs M suffix *12
* This parameter is not tested for M suffix devices.
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
operating characteristics over recommended operating free-air temperature range
dual power supply over recommended power supply and reference voltage ranges, AGND = DGND = 0 V
(unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Slew rate *2.5 V•µs
Settling time to 1/2 LSB
Positive full scale
Vref = 10 V
*5
s
Settling time to 1/2 LSB Negative full scale Vref = 10 V *7 µs
Resolution 8 bits
Total unadjusted error ±2 LSB
Linearity error Differential/integral
VDD = 15 V ±5%,
Vref = 10 V
±1 LSB
Full-scale error VDD = 15 V ±5%, Vref = 10 V ±2 LSB
Gain error ±0.25 LSB
Temperature coefficient of gain
Full scale VDD = 14 V to 16.5 V, Vref = 10 V ±20 ppm/°C
Temperature coefficient of gain Zero-code error ±50 µV/°C
Zero-code error ±20 ±80 mV
Digital crosstalk glitch impulse area Vref = 0 50 nV•s
* This parameter is not tested for M suffix devices.
single power supply, VDD = 14.25 V to 15.75 V, VSS = AGND = DGND = 0 V, V ref = 10 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Supply current, IDD VI = 0.8 V or 2.4 V, No load 5 13 mA
Slew rate *2 V•µs
Settling time to 1/2 LSB
Positive full scale *5
s
Settling time to 1/2 LSB Negative full scale *20 µs
Resolution 8 bits
Total unadjusted error ±2 LSB
Full-scale error ±2 LSB
Temperature coefficient of gain
Full scale VDD = 14 V to 16.5 V, Vref = 10 V ±20 ppm/°C
Temperature coefficient of gain Zero-code error ±50 µV/°C
Linearity error Differential ±1 LSB
Digital crosstalk-glitch impulse area 50 nV•s
* This parameter is not tested for M suffix devices.
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6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
VDD
0 V
VDD
0 V
VDD
0 V
Data
Address
WR
tsu(DW)
th(DW)
th(AW)
tw
tsu(AW)
NOTES: A. tr = tf = 20 ns over VDD range.
B. The timing measurement reference level is equal to VIH + VIL
divided by 2.
C. The selected input latch is transparent while WR is low. Invalid
data during this time can cause erroneous outputs.
Figure 1. Write-Cycle Voltage Waveforms
TYPICAL CHARACTERISTICS
Figure 2
− Output Current − mA
OUTPUT CURRENT
vs
OUTPUT VOLTAGE
200
150
100
50
0
−0.1
−0.2
−0.3
−0.4−2 −1 0 1 2
VO − Output Voltage − V
IO
Source Current
Short-Circuit
Limiting
Sinking
Current Source
TA = 25°C
VSS = −5 V
Digital In = 0 V
VDD = 15 V
Figure 3
200
100
600
00123456
400
300
500
OUTPUT CURRENT (SINK)
vs
OUTPUT VOLTAGE
700
78910
TA = 25°C
VDD = 15 V
VSS = −5 V
VSS = 0
IOAµ
VO − Output Voltage − V
− Output Current (Sink) −
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
AGND bias for direct bipolar output operation
The TLC7226 can be used in bipolar operation without adding more external operational amplifiers as shown
in Figure 4 by biasing AGND to VSS. This configuration provides an excellent method for providing a direct
bipolar output with no additional components. The transfer values are shown in Table 1.
_
+
DAC A
AGND
DGND
TLC7226‡
REF (Vref = 5 V)
OUT
4 18
2
63
VDD
5
VSS
−5 V
Output range
(5 V to −5 V)
‡Digital inputs omitted for clarity.
Figure 4. AGND Bias for Direct Bipolar Operation
LSBMSB
DAC LATCH CONTENTS ANALOG OUTPUT
)Vref ǒ127
128Ǔ
1111 1111
)Vref ǒ1
128Ǔ
1000 0001
1000 0000
–Vref ǒ128
128Ǔ+*Vref
0111 1111
0000 0001 *Vref ǒ127
128Ǔ
0000 0000
0 V
Table 1. Bipolar (Offset Binary) Code
*Vref ǒ1
128Ǔ
AGND bias for positive output offset
The TLC7226 AGND terminal can be biased above or below the system ground terminal, DGND, to provide an
offset analog output voltage level. Figure 5 shows a circuit configuration to achieve this for channel A of the
TLC7226. The output voltage, VO, at OUTA can be expressed as:
VO+VBIAS )DAǒVIǓ
where DA is a fractional representation of the digital input word (0 ≤ D ≤ 255/256).
(1)
Increasing AGND above system GND reduces the output range. VDD − Vref must be at least 4 V to ensure
specified operation. Since the AGND terminal is common to all four DACs, this method biases up the output
voltages of all the DACs in the TLC7226. Supply voltages VDD and VSS for the TLC7226 should be referenced
to DGND.
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8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
AGND bias for positive output offset (continued)
_
+
DAC A
AGND
DGND
TLC7226†
Vref
OUTA
4 18
2
63
VDD
5
VSS
VI
Vbias
†Digital inputs omitted for clarity.
Figure 5. AGND Bias Circuit
interface logic information
Address lines A0 and A1 select which DAC accepts data from the input port. Table 2 shows the operations of
the four DACs. Figure 6 shows the input control logic. When the WR signal is low, the input latches of the
selected DAC are transparent and the output responds to activity on the data bus. The data is latched into the
addressed DAC latch on the rising edge of WR. While WR is high, the analog outputs remain at the value
corresponding to the data held in their respective latches.
Table 2. Function Table
CONTROL INPUTS
OPERATION
WR A1 A0
OPERATION
H
L
↑
L
↑
L
↑
L
↑
X
L
L
L
L
H
H
H
H
X
L
L
H
H
L
L
H
H
No operation
Device not selected
DAC A transparent
DAC A latched
DAC B transparent
DAC B latched
DAC C transparent
DAC C latched
DAC D transparent
DAC D latched
L = low, H = high, X = irrelevant
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PRINCIPLES OF OPERATION
interface logic information (continued)
17
16
15
A0
A1
WR
To Latch A
To Latch B
To Latch C
To Latch D
Figure 6. Input Control Logic
unipolar output operation
The unipolar output operation is the basic mode of operation for each channel of the TLC7226, with the output
voltages having the same positive polarity as Vref. The TLC7226 can be operated with a single power supply
(VSS = AGND) or with positive/negative power supplies. The voltage at V ref must never be negative with respect
to AGND to prevent parasitic transistor turnon. Connections for the unipolar output operation are shown in
Figure 7. Transfer values are shown in Table 3.
_
+
DAC A
_
+
DAC B
_
+
DAC C
_
+
DAC D
4
REF
2
1
20
19
OUTA
OUTB
OUTC
OUTD
Figure 7. Unipolar Output Circuit
LSBMSB
DAC LATCH CONTENTS ANALOG OUTPUT
)Vref ǒ255
256Ǔ
1111 1111
)Vref ǒ129
256Ǔ
1000 0001
1000 0000 )Vref ǒ128
256Ǔ+)Vref
2
0111 1111 )Vref ǒ127
256Ǔ
0000 0001 )Vref ǒ1
256Ǔ
0000 0000 0 V
NOTE A. 1 LSB +ǒVref 2–8Ǔ+Vref ǒ1
256Ǔ
Table 3. Unipolar Code
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10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
linearity, offset, and gain error using single-ended power supplies
When an amplifier is operated from a single power supply, the voltage offset can still be either positive or
negative. With a positive o ffset, the output voltage changes on the first code change. With a negative offset the
output voltage may not change with the first code depending on the magnitude of the offset voltage.
The output amplifier, with a negative voltage offset, attempts to drive the output to a negative voltage. However,
because the most negative supply rail is ground, the output cannot be driven to a negative voltage.
So when the output offset voltage is negative, the output voltage remains at zero volts until the input code value
produces a sufficient output voltage to overcome the inherent negative offset voltage, resulting in a transfer
function shown in Figure 8.
DAC Code
Output
Voltage
0 V
Negative
Offset
Figure 8. Effect of Negative Offset (Single Power Supply)
This negative offset error, not the linearity error, produces the breakpoint. The transfer function would have
followed the dotted line if the output buffer could be driven to a negative voltage.
For a DAC, linearity is measured between zero input code (all inputs 0) and full scale code (all inputs 1) after
offset and full scale are adjusted out or accounted for in some way. However , single power supply operation does
not allow for adjustment when the offset is negative due to the breakpoint in the transfer function. So the linearity
in the unipolar mode is measured between full scale code and the lowest code which produces a positive output
voltage.
The code is calculated from the maximum specification for the negative offset.
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
bipolar output operation using external amplifier
Each of the DACs of the TLC7226 can also be individually configured to provide bipolar output operation, using
an external amplifier and two resistors per channel. Figure 9 shows a circuit used to implement offset binary
coding (bipolar operation) with DAC A of the TLC7226. In this case:
VO+1)R2
R1 ǒDA VrefǓ*R2
R1 ǒVrefǓ
with R1 +R2
VO+ǒ2DA*1Ǔ Vref
where DAis a fractional representation of the digital word in latch A.
(2)
Mismatch between R1 and R2 causes gain and offset errors. Therefore, these resistors must match and track
over temperature. The TLC7226 can be operated with a single power supply or from positive and negative
power supplies.
15 V
_
+
DAC A
TLC7226
2
4R2†
R1†
VO
REF
†R1 = R2 = 10 kΩ ±0.1%
_
+
−15 V
Figure 9. Bipolar Output Circuit
staircase window comparator
In many test systems, it is important to be able to determine whether some parameter lies within defined limits.
The staircase window comparator shown in Figure 10 is a circuit that can be used to measure the VOH and VOL
thresholds of a TTL device under test. Upper and lower limits on both VOH and VOL can be programmed using
the TLC7226. Each adjacent pair of comparators forms a window of programmable size (see Figure 11). When
the test voltage (Vtest) is within a window, then the output for that window is higher. With a reference of 2.56 V
applied to the REF input, the minimum window size is 10 mV.
SLAS060F − JANUARY 1995 − REVISED APRIL 2009
12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
staircase window comparator (continued)
_
+
_
+
10 kΩ
5 V
_
+
_
+
10 kΩ
5 V
_
+
_
+
10 kΩ
5 V
_
+
_
+
10 kΩ
5 V
_
+
_
+
10 kΩ
5 V
2
1
20
19
VOH
VOH
VOL
VOL
REF
AGND
OUTA
OUTB
OUTC
OUTD
TLC7226
Window 1
Window 2
Window 3
Window 4
Window 5
Vtest
From DUT
5
4
Reference Voltage
Figure 10. Logic Level Measurement
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
staircase window comparator (continued)
REF
OUTA
OUTB
OUTC
OUTD
AGND
Window 1
Window 2
Window 3
Window 4
Window 5
Figure 11. Adjacent Window Structure
The circuit can easily be adapted as shown in Figure 12 to allow for overlapping of windows. When the three
outputs from this circuit are decoded, five different nonoverlapping programmable window possibilities can
again be defined (see Figure 13).
_
+
_
+
10 kΩ
5 V
_
+
_
+
10 kΩ
5 V
_
+
_
+
10 kΩ
5 V
2
1
20
19
REF
AGND
OUTA
OUTB
OUTC
OUTD
TLC7226
Window 1
Window 2
Window 3
Vtest
From DUT
5
4
Reference Voltage
Figure 12. Overlapping Window Circuit
SLAS060F − JANUARY 1995 − REVISED APRIL 2009
14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
staircase window comparator (continued)
REF
OUTB
OUTA
OUTD
OUTC
AGND
Window 1
Window 2
Window 3
Windows 1 and 2
Windows 2 and 3
Figure 13. Overlapping Window Structure
output buffer amplifier
The unity-gain output amplifier is capable of sourcing 5 mA into a 2-kΩ load and can drive a 3300-pF capacitor.
The output can be shorted to AGND indefinitely or it can be shorted to any voltage between VSS and VDD
consistent with the maximum device power dissipation.
multiplying DAC
The TLC7226 can be used as a multiplying DAC when the reference signal is maintained between 2 V and
VDD − 4 V. When this configuration is used, VDD should be 14.25 V to 15.75 V. A low output-impedance buffer
should be used so that the input signal is not loaded by the resistor ladder. Figure 14 shows the general
schematic.
_
+
_
+
DAC
AGND DGND
56
1/4 TLC7226
4
15 V Vref
OP07
15 V
R1
R2
AC Reference
Input Signal
VO
Figure 14. AC Signal Input Scheme
PACKAGE OPTION ADDENDUM
www.ti.com 25-Sep-2013
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
5962-87802012A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962-
87802012A
TLC7226
MFKB
5962-87802012C ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962-
87802012C
TLC7226CDW ACTIVE SOIC DW 20 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 TLC7226C
TLC7226CDWG4 ACTIVE SOIC DW 20 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 TLC7226C
TLC7226CDWR ACTIVE SOIC DW 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 TLC7226C
TLC7226CDWRG4 ACTIVE SOIC DW 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 TLC7226C
TLC7226CN ACTIVE PDIP N 20 20 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 TLC7226CN
TLC7226CNE4 ACTIVE PDIP N 20 20 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 TLC7226CN
TLC7226IDW ACTIVE SOIC DW 20 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 TLC7226I
TLC7226IDWG4 ACTIVE SOIC DW 20 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 TLC7226I
TLC7226IDWR ACTIVE SOIC DW 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 TLC7226I
TLC7226IDWRG4 ACTIVE SOIC DW 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 TLC7226I
TLC7226IN ACTIVE PDIP N 20 20 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type -40 to 85 TLC7226IN
TLC7226INE4 ACTIVE PDIP N 20 20 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type -40 to 85 TLC7226IN
TLC7226MFKB ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962-
87802012A
TLC7226
MFKB
PACKAGE OPTION ADDENDUM
www.ti.com 25-Sep-2013
Addendum-Page 2
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TLC7226, TLC7226M :
•Catalog: TLC7226
•Military: TLC7226M
NOTE: Qualified Version Definitions:
PACKAGE OPTION ADDENDUM
www.ti.com 25-Sep-2013
Addendum-Page 3
•Catalog - TI's standard catalog product
•Military - QML certified for Military and Defense Applications
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TLC7226CDWR SOIC DW 20 2000 330.0 24.4 10.8 13.3 2.7 12.0 24.0 Q1
TLC7226IDWR SOIC DW 20 2000 330.0 24.4 10.8 13.3 2.7 12.0 24.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 3-Jan-2013
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TLC7226CDWR SOIC DW 20 2000 367.0 367.0 45.0
TLC7226IDWR SOIC DW 20 2000 367.0 367.0 45.0
PACKAGE MATERIALS INFORMATION
www.ti.com 3-Jan-2013
Pack Materials-Page 2
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