PRELIMINARY ICS874002-02 PCI EXPRESS/JITTER ATTENUATOR GENERAL DESCRIPTION FEATURES The ICS874002-02 is a high perfor mance ICS Differential-to-LVDS Jitter Attenuator designed for HiPerClockSTM use in PCI Express systems. In some PCI Express systems, such as those found in desktop PCs, the PCI Express clocks are generated from a low bandwidth, high phase noise PLL frequency synthesizer. In these systems, a jitter attenuator may be required to attenuate high frequency random and deterministic jitter components from the PLL synthesizer and from the system board. The ICS874002-02 has 2 PLL bandwidth modes: 2.2MHz and 3MHz. The 2.2MHz mode will provide maximum jitter attenuation, but with higher PLL tracking skew and spread spectrum modulation from the motherboard synthesizer may be attenuated. The 3MHz bandwidth provides the best tracking skew and will pass most spread profiles, but the jitter attenuation will not be as good as the lower bandwidth modes. The 874002-02 can be set for differential modes using the F_SELx pins as shown in Table 3C. * Two differential LVDS output pair The ICS874002-02 uses IDT's 3 rd Generation FemtoClock TM PLL technology to achieve the lowest possible phase noise. The device is packaged in a 20 Lead TSSOP package, making it ideal for use in space constrained applications such as PCI Express add-in cards. PLL BANDWIDTH (TYPICAL) * One differential clock input * CLK and nCLK supports the following input types: LVPECL, LVDS, LVHSTL, SSTL, HCSL * Output frequency range: 98MHz - 640MHz * Input frequency range: 98MHz - 128MHz * VCO range: 490MHz - 640MHz * Cycle-to-cycle jitter: 50ps (maximum) design target * 3.3V operating supply * Two bandwidth modes allow the system designer to make jitter attenuation/tracking skew design trade-offs * 0C to 70C ambient operating temperature * Available in both standard (RoHS 5) and lead-free (RoHS 6) packages BW_SEL 0 = PLL Bandwidth: 2.2MHz (default) 1 = PLL Bandwidth: 3MHz PIN ASSIGNMENT BLOCK DIAGRAM OE Pullup F_SEL[1:0] Pullup:Pulldown 2 BW_SEL Pulldown 0 = 2.2MHz 1 = 3MHz CLK Pulldown nCLK Pullup Phase Detector VCO Output Divider 0 0 /5 0 1 /4 1 0 /2 (default) 1 1 /1 Q0 nQ0 nQ0 VDDO FB_OUT nFB_OUT MR BW_SEL F_SEL1 VDDA F_SEL0 VDD 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 Q0 VDDO Q1 nQ1 nFB_IN FB_IN GND nCLK CLK OE ICS874002-02 490 - 640 MHz 20-Lead TSSOP Q1 nQ1 FB_IN Pulldown 6.5mm x 4.4mm x 0.92mm package body G Package Top View nFB_IN Pullup /5 (fixed) FB_OUT nFB_OUT MR Pulldown The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization and/or qualification. Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice. IDT TM / ICSTM PCI EXPRESS/JITTER ATTENUATOR 1 ICS874002AG-02 REV. A JANUARY 3, 2007 ICS874002-02 PCI EXPRESS/JITTER ATTENUATOR PRELIMINARY TABLE 1. PIN DESCRIPTIONS Number Name Type Description 1, 20 nQ0, Q0 Output Differential output pair. LVDS interface levels. 2, 19 3, 4 VDDO FB_OUT, nFB_OUT Power Output supply pins. Output Differential feedback output pair. LVDS interface levels. Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs (Qx, FB_OUT) to go low and the Pulldown inver ted outputs (nQx, nFB_OUT) to go high. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS/LVTTL interface levels. PLL Bandwidth select input. LVCMOS/LVTTL interface levels. Pulldown See Table 3B. Pullup Frequency select pin. LVCMOS/LVTTL interface levels. See Table 3C. 5 MR Input 6 BW_SEL Input 7 F_SEL1 Input 8 VDDA Power 9 F_SEL0 Input Pulldown Frequency select pin. LVCMOS/LVTTL interface levels. See Table 3C. 10 VDD Power 11 OE Input 12 CLK Input Core supply pin. Output enable pin. When HIGH, the outputs are active. When LOW, the Pullup outputs are in a high impedance state. LVCMOS/LVTTL interface levels. See Table 3A. Pulldown Non-inver ting differential clock input. 13 nCLK Input 14 GND Power 15 FB_IN Input Analog supply pin. Pullup Inver ting differential clock input. Power supply ground. Pulldown Non-inver ting differential feedback input. 16 nFB_IN Input 17, 18 nQ1, Q1 Output Pullup Inver ting differential feedback input. Differential output pair. LVDS interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter Test Conditions Minimum Typical Maximum Units CIN Input Capacitance 4 pF RPULLUP Input Pullup Resistor 51 k RPULLDOWN Input Pulldown Resistor 51 k TABLE 3A. OUTPUT ENABLE FUNCTION TABLE Input OE TABLE 3B. PLL BANDWIDTH CONTROL TABLE Outputs Q[0:1] / nQ[0:1] Input FB_OUT/nFB_OUT 0 HiZ Enabled BW_SEL 0 1 Enabled Enabled 1 PLL Bandwidth 2.2MHz (default) 3MHz TABLE 3C. F_SELX FUNCTION TABLE Inputs Input Frequency (MHz) 100 F_SEL1 0 F_SEL0 0 Divider 5 Output Frequency (MHz) 100 100 0 1 4 125 100 1 0 2 250 (default) 100 1 1 1 50 0 IDT TM / ICSTM PCI EXPRESS/JITTER ATTENUATOR 2 ICS874002AG-02 REV. A JANUARY 3, 2007 ICS874002-02 PCI EXPRESS/JITTER ATTENUATOR PRELIMINARY ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5 V Outputs, VO -0.5V to VDDO + 0.5V NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Package Thermal Impedance, JA 73.2C/W (0 lfpm) Storage Temperature, TSTG -65C to 150C TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V5%, TA = 0C TO 70C Symbol Parameter VDD Core Supply Voltage Test Conditions Minimum Typical Maximum Units 3.135 3.3 3.465 V VDDA Analog Supply Voltage VDD - 0.10 3.3 VDD V VDDO Output Supply Voltage 3.135 3.3 3.465 V IDD Power Supply Current 65 mA IDDA Analog Supply Current 10 mA IDDO Output Supply Current 60 mA TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V5%, TA = 0C TO 70C Symbol Parameter VIH Input High Voltage VIL Input Low Voltage VIM Input Mid Voltage IIH Input High Current IIL Input Low Current Test Conditions F_SEL, OE, MR Minimum Typical 2 Units VDD + 0.3 V VDD - 0.4 BW_SEL F_SEL, OE, MR V -0.3 0.8 V VDD + 0.4 V VDD/2 +0.1 V VDD = VIN = 3.465V 5 A VDD = VIN = 3.465V 150 A BW_SEL BW_SEL OE, F_SEL1 BW_SEL, F_SEL0, MR OE, F_SEL1 BW_SEL, F_SEL0, MR Maximum VDD/2 - 0.1 VDD = 3.465V, VIN = 0V -150 A VDD = 3.465V, VIN = 0V -5 A TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V5%, TA = 0C TO 70C Symbol Parameter Test Conditions IIH Input High Current IIL Input Low Current VPP Peak-to-Peak Input Voltage CLK, FB_IN VDD = VIN = 3.465V nCLK, nFB_IN VDD = VIN = 3.465V CLK, FB_IN VDD = VIN = 3.465V nCLK, nFB_IN VDD = VIN = 3.465V Minimum Typical Maximum Units 15 0 A 5 A 15 0 -150 0.15 A 1.3 VCMR Common Mode Input Voltage; NOTE 1, 2 GND + 0.5 VDD - 0.85 NOTE 1: Common mode voltage is defined as VIH. NOTE 2: For single ended applications, the maximum input voltage for CLK, nCLK and FB_IN, nFB_IN is VDD + 0.3V. IDT TM / ICSTM PCI EXPRESS/JITTER ATTENUATOR 3 A V V ICS874002AG-02 REV. A JANUARY 3, 2007 ICS874002-02 PCI EXPRESS/JITTER ATTENUATOR PRELIMINARY TABLE 4D. LVDS DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V5%, TA = 0C TO 70C Symbol Parameter VOD Differential Output Voltage VOD VOD Magnitude Change VOS Offset Voltage VOS VOS Magnitude Change Test Conditions Minimum Typical Maximum Units 420 mV 50 mV 1.35 V 50 mV TABLE 5. AC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V5%, TA = 0C TO 70C Symbol Parameter fMAX Output Frequency tjit(cc) Cycle-to-Cycle Jitter; NOTE 1 tsk(o) Output Skew; NOTE 2, 3 tsk(O) Static Phase Offset; NOTE 4 t R / tF Output Rise/Fall Time Test Conditions Minimum Typical 98 20% to 80% Maximum Units 640 MHz 50 ps TBD ps TBD ps 350 ps odc Output Duty Cycle 50 % Minimum and maximum values are design target specs. NOTE 1: This parameter is defined in accordance with JEDEC Standard 65. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. NOTE 4: Defined as the time difference between the input reference clock and the average feedback input signal when the PLL is locked and the input reference frequency is stable. IDT TM / ICSTM PCI EXPRESS/JITTER ATTENUATOR 4 ICS874002AG-02 REV. A JANUARY 3, 2007 ICS874002-02 PCI EXPRESS/JITTER ATTENUATOR PRELIMINARY PARAMETER MEASUREMENT INFORMATION VDD SCOPE VDD, VDDO 3.3V5% POWER SUPPLY + Float GND - nCLK, nFB_IN Qx VDDA V V Cross Points PP LVDS CMR CLK, FB_IN nQx GND DIFFERENTIAL INPUT LEVEL nQx nQ0, nQ1 Qx Q0, Q1 nQy 3.3V LVDS OUTPUT LOAD AC TEST CIRCUIT ttcycle cycle n ttcycle cycle n+1 n+1 t jit(cc) = t cycle n - t cycle n+1 1000 Cycles Qy t sk(o) OUTPUT SKEW CYCLE-TO-CYCLE JITTER nCLK VOH nQ0, nQ1 CLK VOL Q0, Q1 nFB_IN VOH t PW t VOL FB_IN t (O) odc = PERIOD t PW x 100% t PERIOD t (O) mean = Static Phase Offset (where t (O) is any random sample, and t (O) mean is the average of the sampled cycles measured on controlled edges) STATIC PHASE OFFSET IDT TM / ICSTM PCI EXPRESS/JITTER ATTENUATOR OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD 5 ICS874002AG-02 REV. A JANUARY 3, 2007 ICS874002-02 PCI EXPRESS/JITTER ATTENUATOR PRELIMINARY VDD out 80% DC Input VOD Clock Outputs LVDS 80% 20% 20% out tF tR VOS/ VOS OUTPUT RISE/FALL TIME OFFSET VOLTAGE SETUP VDD LVDS 100 VOD/ VOD out DC Input out DIFFERENTIAL OUTPUT VOLTAGE SETUP IDT TM / ICSTM PCI EXPRESS/JITTER ATTENUATOR 6 ICS874002AG-02 REV. A JANUARY 3, 2007 ICS874002-02 PCI EXPRESS/JITTER ATTENUATOR PRELIMINARY APPLICATION INFORMATION POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS874002-02 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD, VDDA, and VDDO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10 resistor along with a 10F and a .01F bypass capacitor should be connected to each VDDA pin. 3.3V VDD .01F 10 VDDA .01F 10F FIGURE 1. POWER SUPPLY FILTERING WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS Figure 2 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609. VDD R1 1K Single Ended Clock Input CLK V_REF nCLK C1 0.1u R2 1K FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT IDT TM / ICSTM PCI EXPRESS/JITTER ATTENUATOR 7 ICS874002AG-02 REV. A JANUARY 3, 2007 ICS874002-02 PCI EXPRESS/JITTER ATTENUATOR PRELIMINARY DIFFERENTIAL CLOCK INPUT INTERFACE The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 3A to 3D show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 3A, the input termination applies for IDT HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation. 3.3V 3.3V 3.3V 1.8V Zo = 50 Ohm CLK Zo = 50 Ohm CLK Zo = 50 Ohm nCLK Zo = 50 Ohm LVPECL nCLK HiPerClockS Input LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 R1 50 HiPerClockS Input R2 50 R2 50 R3 50 FIGURE 3A. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY IDT HIPERCLOCKS LVHSTL DRIVER FIGURE 3B. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER 3.3V 3.3V 3.3V 3.3V 3.3V R3 125 BY R4 125 Zo = 50 Ohm LVDS_Driv er Zo = 50 Ohm CLK CLK R1 100 Zo = 50 Ohm nCLK LVPECL R1 84 HiPerClockS Input nCLK Receiv er Zo = 50 Ohm R2 84 FIGURE 3C. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY 3.3V LVPECL DRIVER FIGURE 3D. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVDS DRIVER BY RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS: OUTPUTS: LVCMOS CONTROL PINS: All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1k resistor can be used. LVDS All unused LVDS output pairs can be either left floating or terminated with 100 across. If they are left floating, there should be no trace attached. IDT TM / ICSTM PCI EXPRESS/JITTER ATTENUATOR 8 ICS874002AG-02 REV. A JANUARY 3, 2007 ICS874002-02 PCI EXPRESS/JITTER ATTENUATOR PRELIMINARY 3.3V LVDS DRIVER TERMINATION A general LVDS interface is shown in Figure 4. In a 100 differential transmission line environment, LVDS drivers require a matched load termination of 100 across near the receiver input. For a multiple LVDS outputs buffer, if only partial outputs are used, it is recommended to terminate the unused outputs. 3.3V 3.3V LVDS_Driv er + R1 100 - 100 Ohm Differiential Transmission Line FIGURE 4. TYPICAL LVDS DRIVER TERMINATION IDT TM / ICSTM PCI EXPRESS/JITTER ATTENUATOR 9 ICS874002AG-02 REV. A JANUARY 3, 2007 ICS874002-02 PCI EXPRESS/JITTER ATTENUATOR PRELIMINARY POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS874002-02. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS874002-02 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. * * Power (core)MAX = VDD_MAX * (IDD_MAX + IDDA_MAX) = 3.465V * (65mA + 10mA) = 259.9mW Power (outputs)MAX = VDDO_MAX * IDDO_MAX = 3.465V * 60mA = 207.9mW Total Power_MAX = 259.9mW + 207.9mW = 467.8mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6C/W per Table 6 below. Therefore, Tj for an ambient temperature of 70C with all outputs switching is: 70C + 0.468W * 66.6C/W = 101.2C. This is well below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). TABLE 6. THERMAL RESISTANCE JA FOR 20-LEAD TSSOP, FORCED CONVECTION JA by Velocity (Linear Feet per Minute) Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 114.5C/W 73.2C/W 98.0C/W 66.6C/W 88.0C/W 63.5C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. IDT TM / ICSTM PCI EXPRESS/JITTER ATTENUATOR 10 ICS874002AG-02 REV. A JANUARY 3, 2007 ICS874002-02 PCI EXPRESS/JITTER ATTENUATOR PRELIMINARY RELIABILITY INFORMATION TABLE 7. JAVS. AIR FLOW TABLE FOR 20 LEAD TSSOP JA by Velocity (Linear Feet per Minute) Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 114.5C/W 73.2C/W 98.0C/W 66.6C/W 88.0C/W 63.5C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for ICS874002-02 is: 1608 IDT TM / ICSTM PCI EXPRESS/JITTER ATTENUATOR 11 ICS874002AG-02 REV. A JANUARY 3, 2007 ICS874002-02 PCI EXPRESS/JITTER ATTENUATOR PRELIMINARY PACKAGE OUTLINE - G SUFFIX FOR 20 LEAD TSSOP TABLE 7. PACKAGE DIMENSIONS Millimeters SYMBOL MIN N MAX 20 A -- 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 6.40 6.60 E E1 6.40 BASIC 4.30 e 4.50 0.65 BASIC L 0.45 0.75 0 8 aaa -- 0.10 Reference Document: JEDEC Publication 95, MO-153 IDT TM / ICSTM PCI EXPRESS/JITTER ATTENUATOR 12 ICS874002AG-02 REV. A JANUARY 3, 2007 ICS874002-02 PCI EXPRESS/JITTER ATTENUATOR PRELIMINARY TABLE 8. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature ICS874002AG-02 TBD 20 Lead TSSOP tube 0C to 70C ICS874002AG-02T TBD 20 Lead TSSSOP 2500 tape & reel 0C to 70C ICS874002AG-02LF ICS74002A02L 20 Lead "Lead-Free" TSSOP tube 0C to 70C ICS874002AG-02LFT ICS74002A02L 20 Lead "Lead-Free" TSSOP 2500 tape & reel 0C to 70C NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. IDT TM / ICSTM PCI EXPRESS/JITTER ATTENUATOR 13 ICS874002AG-02 REV. A JANUARY 3, 2007 ICS874002-02 PCI EXPRESS/JITTER ATTENUATOR PRELIMINARY Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales For Tech Support 800-345-7015 408-284-8200 Fax: 408-284-2775 netcom@idt.com 480-763-2056 Corporate Headquarters Asia Pacific and Japan Europe Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 345 7015 +408 284 8200 (outside U.S.) Integrated Device Technology Singapore (1997) Pte. Ltd. Reg. No. 199707558G 435 Orchard Road #20-03 Wisma Atria Singapore 238877 +65 6 887 5505 IDT Europe, Limited 321 Kingston Road Leatherhead, Surrey KT22 7TU England +44 (0) 1372 363 339 Fax: +44 (0) 1372 378851 (c) 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA