PCI EXPRESS/JITTER ATTENUATOR ICS874002-02
IDT™ / ICS™ PCI EXPRESS/JITTER ATTENUATOR 1 ICS874002AG-02 REV. A JANUARY 3, 2007
PRELIMINARY
GENERAL DESCRIPTION
The ICS874002-02 is a high performance
Differential-to-LVDS Jitter Attenuator designed for
use in PCI Express systems. In some PCI Express
systems, such as those found in desktop PCs, the
PCI Express clocks are generated from a low
bandwidth, high phase noise PLL frequency synthesizer. In
these systems, a jitter attenuator may be required to attenuate
high frequency random and deterministic jitter components from
the PLL synthesizer and from the system board. The
ICS874002-02 has 2 PLL bandwidth modes: 2.2MHz and
3MHz. The 2.2MHz mode will provide maximum jitter
attenuation, but with higher PLL tracking skew and spread
spectrum modulation from the motherboard synthesizer may
be attenuated. The 3MHz bandwidth provides the best track-
ing skew and will pass most spread profiles, but the jitter
attenuation will not be as good as the lower bandwidth modes.
The 874002-02 can be set for differential modes using the
F_SELx pins as shown in Table 3C.
The ICS874002-02 uses IDT’s 3rd Generation FemtoClockTM
PLL technology to achieve the lowest possible phase noise.
The device is packaged in a 20 Lead TSSOP package, making
it ideal for use in space constrained applications such as PCI
Express add-in cards.
FEATURES
•Two differential LVDS output pair
•One differential clock input
•CLK and nCLK supports the following input types:
LVPECL, LVDS, LVHSTL, SSTL, HCSL
•Output frequency range: 98MHz - 640MHz
•Input frequency range: 98MHz - 128MHz
•VCO range: 490MHz - 640MHz
•Cycle-to-cycle jitter: 50ps (maximum) design target
•3.3V operating supply
•Two bandwidth modes allow the system designer to make
jitter attenuation/tracking skew design trade-offs
•0°C to 70°C ambient operating temperature
•Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
HiPerClockS™
ICS
BLOCK DIAGRAM
BW_SEL
0 = PLL Bandwidth: 2.2MHz (default)
1 = PLL Bandwidth: 3MHz
PLL BANDWIDTH (TYPICAL)
÷5 (fixed)
VCO
490 - 640 MHz
Phase
Detector
Output Divider
0 0 ÷5
0 1 ÷4
1 0 ÷2 (default)
1 1 ÷1
Q0
nQ0
Q1
nQ1
FB_OUT
nFB_OUT
BW_SEL
0 = 2.2MHz
1 = 3MHz
CLK
nCLK
FB_IN
nFB_IN
F_SEL[1:0]
MR
OE
Pulldown
Pullup:Pulldown
Pulldown
Pullup
Pullup
Pulldown
2
Pullup
Pulldown
PIN ASSIGNMENT
ICS874002-02
20-Lead TSSOP
6.5mm x 4.4mm x 0.92mm
package body
G Package
Top View
nQ0
VDDO
FB_OUT
nFB_OUT
MR
BW_SEL
F_SEL1
VDDA
F_SEL0
VDD
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
Q0
VDDO
Q1
nQ1
nFB_IN
FB_IN
GND
nCLK
CLK
OE
The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization
and/or qualification. Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.
IDT™ / ICS™ PCI EXPRESS/JITTER ATTENUATOR 2 ICS874002AG-02 REV. A JANUARY 3, 2007
ICS874002-02
PCI EXPRESS/JITTER ATTENUATOR PRELIMINARY
TABLE 2. PIN CHARACTERISTICS
TABLE 1. PIN DESCRIPTIONS
TABLE 3A. OUTPUT ENABLE FUNCTION TABLE TABLE 3B. PLL BANDWIDTH CONTROL TABLE
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R
PULLUP
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R
NWODLLUP
rotsiseRnwodlluPtupnI 15kΩ
tupnI
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0)tluafed(zHM2.2
1zHM3
TABLE 3C. F_SELX FUNCTION TABLE
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4
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.slevelecafretniLTTVL/SOMCVL
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:ETON
pulluP
dna
nwodlluP
.seulavlacipytrof,scitsiretcarahCniP,2elbaTeeS.srotsisertupnilanretniotrefer
IDT™ / ICS™ PCI EXPRESS/JITTER ATTENUATOR 3 ICS874002AG-02 REV. A JANUARY 3, 2007
ICS874002-02
PCI EXPRESS/JITTER ATTENUATOR PRELIMINARY
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V
DD 4.6V
Inputs, VI-0.5V to VDD + 0.5 V
Outputs, VO-0.5V to VDDO + 0.5V
Package Thermal Impedance, θJA 73.2°C/W (0 lfpm)
Storage Temperature, T
STG -65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional op-
eration of product at these conditions or any conditions beyond
those listed in the
DC Characteristics
or
AC Characteristics
is not
implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect product reliability.
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = 0°C TO 70°C
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V
DD
egatloVylppuSeroC 531.33.3564.3V
V
ADD
egatloVylppuSgolanAV
DD
01.0–3.3V
DD
V
V
ODD
egatloVylppuStuptuO 531.33.3564.3V
I
DD
tnerruCylppuSrewoP 56Am
I
ADD
tnerruCylppuSgolanA 01Am
I
ODD
tnerruCylppuStuptuO 06Am
TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = 0°C TO 70°C
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = 0°C TO 70°C
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
I
HI
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DD
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NI
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NI_BFn,KLCnV
DD
V=
NI
V564.3=5 Aµ
I
LI
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DD
V=
NI
V564.3=051Aµ
NI_BFn,KLCnV
DD
V=
NI
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V
PP
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DD
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V
HI
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DD
3.0+V
LES_WBV
DD
4.0-V
V
LI
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LES_WB V
DD
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V
MI
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DD
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DD
1.0+2/V
I
HI
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DD
V=
NI
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DD
V=
NI
V564.3=051Aµ
I
LI
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DD
V,V564.3=
NI
V0=051-Aµ
,LES_WB
RM,0LES_F V
DD
V,V564.3=
NI
V0=5-Aµ
IDT™ / ICS™ PCI EXPRESS/JITTER ATTENUATOR 4 ICS874002AG-02 REV. A JANUARY 3, 2007
ICS874002-02
PCI EXPRESS/JITTER ATTENUATOR PRELIMINARY
TABLE 4D. LVDS DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = 0°C TO 70°C
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V
DO
egatloVtuptuOlaitnereffiD 024Vm
∆V
DO
V
DO
egnahCedutingaM 05Vm
V
SO
egatloVtesffO 53.1V
∆V
SO
V
SO
egnahCedutingaM 05Vm
TABLE 5. AC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = 0°C TO 70°C
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
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.elbatssiycneuqerfecnerefertupniehtdnadekcolsiLLP
IDT™ / ICS™ PCI EXPRESS/JITTER ATTENUATOR 5 ICS874002AG-02 REV. A JANUARY 3, 2007
ICS874002-02
PCI EXPRESS/JITTER ATTENUATOR PRELIMINARY
PARAMETER MEASUREMENT INFORMATION
OUTPUT SKEW
DIFFERENTIAL INPUT LEVEL3.3V LVDS OUTPUT LOAD AC TEST CIRCUIT
CYCLE-TO-CYCLE JITTER
V
CMR
Cross Points
V
PP
GND
CLK,
FB_IN
nCLK,
nFB_IN
VDD
t
PW
tPERIOD
t
PW
t
PERIOD
odc = x 100%
Q0, Q1
nQ0, nQ1
➤
➤
➤
➤
t
cycle n
t
cycle n+1
t
jit(cc) =
t
cycle n –
t
cycle n+1
1000 Cycles
Q0, Q1
nQ0, nQ1
t
cycle n
t
cycle n+1
SCOPE
Qx
nQx
3.3V±5%
POWER SUPPLY
+–
Float GND
LVDS
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIODSTATIC PHASE OFFSET
VDD,
VDDO VDDA
t
sk(o)
nQx
nQy
Qx
Qy
➤
➤
t
(Ø)
V
OH
V
OL
V
OH
V
OL
(where
t
(Ø) is any random sample, and
t
(Ø) mean is the average
of the sampled cycles measured on controlled edges)
t
(Ø) mean = Static Phase Offset
nCLK
FB_IN
CLK
nFB_IN
IDT™ / ICS™ PCI EXPRESS/JITTER ATTENUATOR 6 ICS874002AG-02 REV. A JANUARY 3, 2007
ICS874002-02
PCI EXPRESS/JITTER ATTENUATOR PRELIMINARY
DIFFERENTIAL OUTPUT VOLTAGE SETUP
OFFSET VOLTAGE SETUPOUTPUT RISE/FALL TIME
Clock
Outputs 20%
80% 80%
20%
t
R
t
F
V
OD
➤
➤
➤
100
out
out
LVDS
DC Input VOD/∆ VOD
VDD
out
out
LVDS
DC Input
➤
➤
➤
V
OS
/∆ V
OS
V
DD
IDT™ / ICS™ PCI EXPRESS/JITTER ATTENUATOR 7 ICS874002AG-02 REV. A JANUARY 3, 2007
ICS874002-02
PCI EXPRESS/JITTER ATTENUATOR PRELIMINARY
APPLICATION INFORMATION
Figure 2
shows how the differential input can be wired
to accept single ended levels. The reference voltage
V_REF = VDD/2 is generated by the bias resistors R1, R2 and
C1. This bias circuit should be located as close as possible to
FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
the input pin. The ratio of R1 and R2 might need to be adjusted
to position the V_REF in the center of the input voltage swing.
For example, if the input clock swing is only 2.5V and VDD =
3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
V_REF
R1
1K
C1
0.1u R2
1K
Single Ended Clock Input
CLK
nCLK
VDD
POWER SUPPLY FILTERING T ECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS874002-02
provides separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. VDD, VDDA, and VDDO
should be individually connected to the power supply plane
through vias, and bypass capacitors should be used for each
pin. To achieve optimum jitter performance, power supply iso-
lation is required.
Figure 1
illustrates how a 10Ω resistor along
with a 10µF and a .01µF bypass capacitor should be con-
nected to each VDDA pin. FIGURE 1. POWER SUPPLY FILTERING
10Ω
VDDA
10µF
.01µF
3.3V
.01µF
VDD
IDT™ / ICS™ PCI EXPRESS/JITTER ATTENUATOR 8 ICS874002AG-02 REV. A JANUARY 3, 2007
ICS874002-02
PCI EXPRESS/JITTER ATTENUATOR PRELIMINARY
FIGURE 3C. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
FIGURE 3B. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
FIGURE 3D. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVDS DRIVER
3.3V
R1
50
R3
50
Zo = 50 Ohm
LVPECL
Zo = 50 Ohm
HiPerClockS
CLK
nCLK
3.3V
Input
R2
50
Zo = 50 Ohm
Input
HiPerClockS
CLK
nCLK
3.3V
R3
125
R2
84
Zo = 50 Ohm
3.3V
R4
125
LVPECL
R1
84
3.3V
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL
and other differential signals. Both VSWING and VOH must meet the
VPP and VCMR input requirements. Figures 3A to 3D show interface
examples for the HiPerClockS CLK/nCLK input driven by the
most common driver types. The input interfaces suggested here
FIGURE 3A. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
IDT HIPERCLOCKS LVHSTL DRIVER
are examples only. Please consult with the vendor of the driver
component to confirm the driver termination requirements. For
example in
Figure 3A,
the input termination applies for IDT
HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver
from another vendor, use their termination recommendation.
1.8V
R2
50
Input
LVHSTL Driver
ICS
HiPerClockS
R1
50
LVHSTL
3.3V
Zo = 50 Ohm
Zo = 50 Ohm
HiPerClockS
CLK
nCLK
Zo = 50 Ohm
R1
100
3.3V
LVDS_Driv er
Zo = 50 Ohm
Receiv er
CLK
nCLK
3.3V
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS:
LVCMOS CONTROL PINS:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
OUTPUTS:
LVDS
All unused LVDS output pairs can be either left floating or
terminated with 100Ω across. If they are left floating, there should
be no trace attached.
IDT™ / ICS™ PCI EXPRESS/JITTER ATTENUATOR 9 ICS874002AG-02 REV. A JANUARY 3, 2007
ICS874002-02
PCI EXPRESS/JITTER ATTENUATOR PRELIMINARY
3.3V LVDS DRIVER T ERMINATION
A general LVDS interface is shown in
Figure 4.
In a 100Ω
differential transmission line environment, LVDS drivers
require a matched load termination of 100Ω across near
FIGURE 4. TYPICAL LVDS DRIVER TERMINATION
the receiver input. For a multiple LVDS outputs buffer, if only
partial outputs are used, it is recommended to terminate the
unused outputs.
100 Ohm Differiential Transmission Line
R1
100
3.3V
+
-
LVDS_Driv er
3.3V
IDT™ / ICS™ PCI EXPRESS/JITTER ATTENUATOR 10 ICS874002AG-02 REV. A JANUARY 3, 2007
ICS874002-02
PCI EXPRESS/JITTER ATTENUATOR PRELIMINARY
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS874002-02.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS874002-02 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.
•Power (core)MAX = VDD_MAX * (IDD_MAX + IDDA_MAX) = 3.465V * (65mA + 10mA) = 259.9mW
•Power (outputs)MAX = VDDO_MAX * IDDO_MAX = 3.465V * 60mA = 207.9mW
Total Power_MAX = 259.9mW + 207.9mW = 467.8mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA
must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.468W * 66.6°C/W = 101.2°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and
the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE θθ
θθ
θJA FOR 20-LEAD TSSOP, FORCED CONVECTION
θθ
θθ
θJA by Velocity (Linear Feet per Minute)
0 200 500
Single-Layer PCB, JEDEC Standard Test Boards 114.5°C/W 98.0°C/W 88.0°C/W
Multi-Layer PCB, JEDEC Standard Test Boards 73.2°C/W 66.6°C/W 63.5°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
IDT™ / ICS™ PCI EXPRESS/JITTER ATTENUATOR 11 ICS874002AG-02 REV. A JANUARY 3, 2007
ICS874002-02
PCI EXPRESS/JITTER ATTENUATOR PRELIMINARY
RELIABILITY INFORMATION
TRANSISTOR COUNT
The transistor count for ICS874002-02 is: 1608
TABLE 7. θJAVS. AIR FLOW TABLE FOR 20 LEAD TSSOP
θθ
θθ
θJA by Velocity (Linear Feet per Minute)
0 200 500
Single-Layer PCB, JEDEC Standard Test Boards 114.5°C/W 98.0°C/W 88.0°C/W
Multi-Layer PCB, JEDEC Standard Test Boards 73.2°C/W 66.6°C/W 63.5°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
IDT™ / ICS™ PCI EXPRESS/JITTER ATTENUATOR 12 ICS874002AG-02 REV. A JANUARY 3, 2007
ICS874002-02
PCI EXPRESS/JITTER ATTENUATOR PRELIMINARY
TABLE 7. PACKAGE DIMENSIONS
PACKAGE OUTLINE - G SUFFIX FOR 20 LEAD TSSOP
LOBMYS sretemilliM
NIMXAM
N02
A--02.1
1A50.051.0
2A08.050.1
b91.003.0
c90.002.0
D04.606.6
ECISAB04.6
1E03.405.4
eCISAB56.0
L54.057.0
α°0°8
aaa--01.0
Reference Document: JEDEC Publication 95, MO-153
IDT™ / ICS™ PCI EXPRESS/JITTER ATTENUATOR 13 ICS874002AG-02 REV. A JANUARY 3, 2007
ICS874002-02
PCI EXPRESS/JITTER ATTENUATOR PRELIMINARY
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for
infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial
applications. Any other applications such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not recommended without additional
processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical
instruments.
TABLE 8. ORDERING INFORMATION
rebmuNredrO/traPgnikraMegakcaPgnigakcaPgnippihSerutarepmeT
20-GA200478SCIDBTPOSSTdaeL02ebutC°07otC°0
T20-GA200478SCIDBTPOSSSTdaeL02leer&epat0052C°07otC°0
FL20-GA200478SCIL20A20047SCIPOSST"eerF-daeL"daeL02ebutC°07otC°0
TFL20-GA200478SCIL20A20047SCIPOSST"eerF-daeL"daeL02leer&epat0052C°07otC°0
.tnailpmocSHoReradnanoitarugifnoceerF-bPehterarebmuntrapehtotxiffus"FL"nahtiwderedroeratahtstraP:ETON
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408-284-8200
Fax: 408-284-2775
For Tech Support
netcom@idt.com
480-763-2056
Corporate Headquarters
Integrated Device Technology, Inc.
6024 Silver Creek Valley Road
San Jose, CA 95138
United States
800 345 7015
+408 284 8200 (outside U.S.)
Asia Pacific and Japan
Integrated Device Technology
Singapore (1997) Pte. Ltd.
Reg. No. 199707558G
435 Orchard Road
#20-03 Wisma Atria
Singapore 238877
+65 6 887 5505
Europe
IDT Europe, Limited
321 Kingston Road
Leatherhead, Surrey
KT22 7TU
England
+44 (0) 1372 363 339
Fax: +44 (0) 1372 378851
© 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks
of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be
trademarks or registered trademarks used to identify products or services of their respective owners.
Printed in USA
ICS874002-02
PCI EXPRESS/JITTER ATTENUATOR PRELIMINARY
