PCI EXPRESS/JITTER ATTENUATOR ICS874002-02
IDT™ / ICS™ PCI EXPRESS/JITTER ATTENUATOR 1 ICS874002AG-02 REV. A JANUARY 3, 2007
PRELIMINARY
GENERAL DESCRIPTION
The ICS874002-02 is a high performance
Differential-to-LVDS Jitter Attenuator designed for
use in PCI Express systems. In some PCI Express
systems, such as those found in desktop PCs, the
PCI Express clocks are generated from a low
bandwidth, high phase noise PLL frequency synthesizer. In
these systems, a jitter attenuator may be required to attenuate
high frequency random and deterministic jitter components from
the PLL synthesizer and from the system board. The
ICS874002-02 has 2 PLL bandwidth modes: 2.2MHz and
3MHz. The 2.2MHz mode will provide maximum jitter
attenuation, but with higher PLL tracking skew and spread
spectrum modulation from the motherboard synthesizer may
be attenuated. The 3MHz bandwidth provides the best track-
ing skew and will pass most spread profiles, but the jitter
attenuation will not be as good as the lower bandwidth modes.
The 874002-02 can be set for differential modes using the
F_SELx pins as shown in Table 3C.
The ICS874002-02 uses IDT’s 3rd Generation FemtoClockTM
PLL technology to achieve the lowest possible phase noise.
The device is packaged in a 20 Lead TSSOP package, making
it ideal for use in space constrained applications such as PCI
Express add-in cards.
FEATURES
•Two differential LVDS output pair
•One differential clock input
•CLK and nCLK supports the following input types:
LVPECL, LVDS, LVHSTL, SSTL, HCSL
•Output frequency range: 98MHz - 640MHz
•Input frequency range: 98MHz - 128MHz
•VCO range: 490MHz - 640MHz
•Cycle-to-cycle jitter: 50ps (maximum) design target
•3.3V operating supply
•Two bandwidth modes allow the system designer to make
jitter attenuation/tracking skew design trade-offs
•0°C to 70°C ambient operating temperature
•Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
HiPerClockS™
ICS
BLOCK DIAGRAM
BW_SEL
0 = PLL Bandwidth: 2.2MHz (default)
1 = PLL Bandwidth: 3MHz
PLL BANDWIDTH (TYPICAL)
÷5 (fixed)
VCO
490 - 640 MHz
Phase
Detector
Output Divider
0 0 ÷5
0 1 ÷4
1 0 ÷2 (default)
1 1 ÷1
Q0
nQ0
Q1
nQ1
FB_OUT
nFB_OUT
BW_SEL
0 = 2.2MHz
1 = 3MHz
CLK
nCLK
FB_IN
nFB_IN
F_SEL[1:0]
MR
OE
Pulldown
Pullup:Pulldown
Pulldown
Pullup
Pullup
Pulldown
2
Pullup
Pulldown
PIN ASSIGNMENT
ICS874002-02
20-Lead TSSOP
6.5mm x 4.4mm x 0.92mm
package body
G Package
Top View
nQ0
VDDO
FB_OUT
nFB_OUT
MR
BW_SEL
F_SEL1
VDDA
F_SEL0
VDD
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
Q0
VDDO
Q1
nQ1
nFB_IN
FB_IN
GND
nCLK
CLK
OE
The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization
and/or qualification. Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.