Integrated Silicon Solution, Inc. — www.issi.com
1
Rev. B
03/04/2008
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability
arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any
published information and before placing orders for products.
IS61C5128AL/AS
IS64C5128AL/AS
FEATURES
HIGH SPEED: (IS61/64C5128AL)
• High-speed access time: 10ns, 12 ns
• Low Active Power: 150 mW (typical)
• Low Standby Power: 10 mW (typical)
CMOS standby
LOW POWER: (IS61/64C5128AS)
• High-speed access time: 25ns
• Low Active Power: 75 mW (typical)
• Low Standby Power: 1 mW (typical)
CMOS standby
• TTL compatible interface levels
• Single 5V ± 10% power supply
• Fully static operation: no clock or refresh
required
• Available in 36-pin SOJ (400-mil), 32-pin
sTSOP-I, 32-pin SOP, 44-pin TSOP-II and 32-
pin TSOP-II packages
• Commercial, Industrial and Automotive tempera-
ture ranges available
• Lead-free available
DESCRIPTION
The ISSI IS61C5128AL/AS and IS64C5128AL/AS are high-
speed, 4,194,304-bit static RAMs organized as 524,288
words by 8 bits. They are fabricated using ISSI's high-
performance CMOS technology. This highly reliable process
coupled with innovative circuit design techniques, yields
access times as fast as 12 ns with low power consumption.
When CE is HIGH (deselected), the device assumes a
standby mode at which the power dissipation can be reduced
down with CMOS input levels.
Easy memory expansion is provided by using Chip Enable
and Output Enable inputs, CE and OE. The active LOW Write
Enable (WE) controls both writing and reading of the memory.
A data byte allows Upper Byte (UB) and Lower Byte (LB)
access.
The IS61C5128AL/AS and IS64C5128AL/AS are packaged
in the JEDEC standard 36-pin SOJ (400-mil), 32-pin sTSOP-
I, 32-pin SOP, 44-pin TSOP-II and 32-pin TSOP-II packages
FUNCTIONAL BLOCK DIAGRAM
MARCH 2008
512K x 8 HIGH-SPEED CMOS STATIC RAM
A0-A18
CE
OE
WE
512K X 8
MEMORY ARRAY
DECODER
COLUMN I/O
CONTROL
CIRCUIT
GND
V
DD
I/O
DATA
CIRCUIT
I/O0-I/O7
2
Integrated Silicon Solution, Inc. — www.issi.com
Rev. B
03/04/2008
IS61C5128AL/AS IS64C5128AL/AS
PIN DESCRIPTIONS
A0-A18 Address Inputs
CE Chip Enable Input
OE Output Enable Input
WE Write Enable Input
I/O0-I/O7 Bidirectional Ports
VDD Power
GND Ground
NC No Connection
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
A0
A1
A2
A3
A4
CE
I/O0
I/O1
VDD
GND
I/O2
I/O3
WE
A5
A6
A7
A8
A9
NC
A18
A17
A16
A15
OE
I/O7
I/O6
GND
VDD
I/O5
I/O4
A14
A13
A12
A11
A10
NC
HIGH SPEED (IS61/64C5128AL) PIN CONFIGURATION
36-Pin SOJ (400-mil) 44-Pin TSOP (Type II)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
NC
NC
A0
A1
A2
A3
A4
CE
I/O0
I/O1
VDD
GND
I/O2
I/O3
WE
A5
A6
A7
A8
A9
NC
NC
NC
NC
NC
A18
A17
A16
A15
OE
I/O7
I/O6
GND
VDD
I/O5
I/O4
A14
A13
A12
A11
A10
NC
NC
NC
Integrated Silicon Solution, Inc. — www.issi.com
3
Rev. B
03/04/2008
IS61C5128AL/AS IS64C5128AL/AS
32-pin sTSOP (TYPE I) 32-pin SOP
32-pin TSOP (TYPE II)
PIN DESCRIPTIONS
A0-A18 Address Inputs
CE Chip Enable 1 Input
OE Output Enable Input
WE Write Enable Input
I/O0-I/O7 Input/Output
VDD Power
GND Ground
LOW POWER (IS61/64C5128AS) PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A11
A9
A8
A13
WE
A18
A15
V
DD
A17
A16
A14
A12
A7
A6
A5
A4
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
A3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A17
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
A15
A18
WE
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
V
DD
4
Integrated Silicon Solution, Inc. — www.issi.com
Rev. B
03/04/2008
IS61C5128AL/AS IS64C5128AL/AS
CAPACITANCE(1,2)
Symbol Parameter Conditions Max. Unit
CIN Input Capacitance VIN = 0V 5 pF
COUT Output Capacitance VOUT = 0V 7 pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25°C, f = 1 MHz, VDD = 5.0V.
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol Parameter Test Conditions Min. Max. Unit
VOH Output HIGH Voltage VDD = Min., IOH = –4.0 mA 2.4 — V
VOL Output LOW Voltage VDD = Min., IOL = 8.0 mA — 0.4 V
VIH Input HIGH Voltage 2.2 VDD + 0.5 V
VIL Input LOW Voltage(1) –0.3 0.8 V
ILI Input Leakage GND ≤ VIN ≤ VDD Com. –1 1 µA
Ind. –2 2
Auto. –5 5
ILO Output Leakage GND ≤ VOUT ≤ VDD Com. –1 1 µA
Outputs Disabled Ind. –2 2
Auto. –5 5
Note: 1. VIL = –3.0V for pulse width less than 10 ns.
TRUTH TABLE
I/O PIN
Mode WEWE
WEWE
WE CECE
CECE
CE OEOE
OEOE
OE I/O0-I/O7 VDD Current
Not Selected X H X High-Z ISB1, ISB2
Output Disabled H L H High-Z ICC1, ICC2
Read H L L DOUT ICC1, ICC2
Write L L X DIN ICC1, ICC2
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Parameter Value Unit
VTERM Terminal Voltage with Respect to GND –0.5 to +7.0 V
TSTG Storage Temperature –65 to +150 °C
PTPower Dissipation 1.5 W
IOUT DC Output Current (LOW) 20 mA
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Integrated Silicon Solution, Inc. — www.issi.com
5
Rev. B
03/04/2008
IS61C5128AL/AS IS64C5128AL/AS
OPERATING RANGE: LOW POWER OPTION (IS61/64C5128AS)
Range Ambient Temperature VDD Speed (ns)
Commercial 0°C to +70°C 5V ± 10% 25
Industrial -40°C to +85°C 5V ± 10% 25
Automotive -40°C to +125°C 5V ± 10% 25
OPERATING RANGE: HIGH SPEED OPTION (IS61/64C5128AL)
Range Ambient Temperature VDD Speed (ns)
Commercial 0°C to +70°C 5V ± 10% 10
Industrial -40°C to +85°C 5V ± 10% 10
Automotive -40°C to +125°C 5V ± 10% 12
6
Integrated Silicon Solution, Inc. — www.issi.com
Rev. B
03/04/2008
IS61C5128AL/AS IS64C5128AL/AS
HIGH SPEED OPTION (IS61/64C5128AL)
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-10 ns -12 ns
Symbol Parameter Test Conditions Min. Max. Min. Max. Unit
ICC1VDD Operating VDD = VDD MAX., CE = VIL
Com.
—45 —45 mA
Supply Current IOUT = 0 mA, f = 0
Ind.
—50 —50
Auto.
—55 —55
ICC2VDD Dynamic Operating VDD = VDD MAX., CE = VIL
Com.
—50 —45 mA
Supply Current IOUT = 0 mA, f = fMAX
Ind.
—55 —50
Auto.
—70 —60
typ.(2)
30 25
ISB1TTL Standby Current VDD = VDD MAX.,
Com.
—15 —15 mA
(TTL Inputs) VIN = VIH or VIL
Ind.
—20 —20
CE ≥ VIH, f = 0
Auto.
—30 —30
ISB2CMOS Standby VDD = VDD MAX.,
Com.
—8 —8 mA
Current (CMOS Inputs) CE
≤
VDD – 0.2V,
Ind.
—12 —12
VIN ≥ VDD – 0.2V, or
Auto.
—20 —20
VIN
≤
0.2V, f = 0
typ.(2)
2
Note:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
2. Typical values are measured at VDD = 5V, TA = 25% and not 100% tested.
LOW POWER OPTION (IS61/64C5128AS)
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-25 ns
Symbol Parameter Test Conditions Min. Max. Unit
ICC Average operating CE = VIL, VDD = Max. Com. — 10 mA
Current I OUT= 0 mA, f= 0 Ind. — 15
Auto. — 20
ICC1VDD Dynamic Operating VDD = Max., CE = VIL Com. — 25 mA
Supply Current IOUT = 0 mA, f = fMAX Ind. — 30
Auto. — 40
typ.
(2)
15
ISB1TTL Standby Current VDD = Max., Com. — 1 mA
(TTL Inputs) VIN = VIH or VIL, CE ≥ V IH, Ind. — 1.5
f = 0 Auto. — 2
ISB2CMOS Standby VDD = Max., Com. — 0.8 mA
Current (CMOS Inputs) CE ≥ V DD – 0.2V, Ind. — 0.9
VIN ≥ V DD – 0.2V, Auto. — 2
or VIN ≤ V SS + 0.2V, f = 0 typ. 0.2
Note:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
2. Typical values are measured at VDD = 5V, TA = 25% and not 100% tested.
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7
Rev. B
03/04/2008
IS61C5128AL/AS IS64C5128AL/AS
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
-10 -12 -25
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit
tRC Read Cycle Time 10 — 12 — 25 — ns
tAA Address Access Time — 10 — 12 — 25 ns
tOHA Output Hold Time 3 — 3 — 3 — ns
tACE CE Access Time — 10 — 12 — 25 ns
tDOE OE Access Time — 5 — 6 — 15 ns
tHZOE
(2)
OE to High-Z Output 0 5 0 6 0 8 ns
tLZOE
(2)
OE to Low-Z Output 0 — 0 — 2 — ns
tHZCE
(2)
CE to High-Z Output 0 5 0 6 0 8 ns
tLZCE
(2)
CE to Low-Z Output 2 — 2 — 2 — ns
AC TEST CONDITIONS
Parameter Unit
Input Pulse Level 0V to 3.0V
Input Rise and Fall Times 3 ns
Input and Output Timing 1.5V
and Reference Level
Output Load See Figures 1 and 2
480 Ω
30 pF
Including
jig and
scope
255 Ω
OUTPUT
5V
480 Ω
5 pF
Including
jig and
scope
255 Ω
OUTPUT
5V
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0
to 3.0V and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. Not 100% tested.
Figure 1 Figure 2
AC TEST LOADS
8
Integrated Silicon Solution, Inc. — www.issi.com
Rev. B
03/04/2008
IS61C5128AL/AS IS64C5128AL/AS
DATA VALID
READ1.eps
PREVIOUS DATA VALID
t
AA
t
OHA
t
OHA
t
RC
DOUT
ADDRESS
t
RC
t
OHA
t
AA
t
DOE
t
LZOE
t
ACS
t
LZCS
t
HZOE
HIGH-Z DATA VALID
CE_RD2.eps
ADDRESS
OE
CE
D
OUT
t
HZCS
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE = VIL.
3. Address is valid prior to or coincident with CE LOW transitions.
READ CYCLE NO. 2(1,3)
AC WAVEFORMS
READ CYCLE NO. 1(1,2)
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9
Rev. B
03/04/2008
IS61C5128AL/AS IS64C5128AL/AS
WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range)
-10 -12 -25
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit
tWC Write Cycle Time 10 — 12 — 25 — ns
tSCE CE to Write End 7 — 9 — 18 — ns
tAW Address Setup Time 7 — 9 — 18 — ns
to Write End
tHA Address Hold from Write End 0 — 0 — 0 — ns
tSA Address Setup Time 0 — 0 — 0 — ns
tPWE1WE Pulse Width (OE =High) 7 — 9 — 15 — ns
tPWE2WE Pulse Width (OE=Low) 7 — 9 — 15 — ns
tSD Data Setup to Write End 6 — 6 — 15 — ns
tHD Data Hold from Write End 0 — 0 — 0 — ns
tHZWE
(2)
WE LOW to High-Z Output — 6 — 6 — 15 ns
tLZWE
(2)
WE HIGH to Low-Z Output 3 — 3 — 5 — ns
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V
and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE LOW, and WE LOW. All signals must be in valid states to initiate a
Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or
falling edge of the signal that terminates the write.
10
Integrated Silicon Solution, Inc. — www.issi.com
Rev. B
03/04/2008
IS61C5128AL/AS IS64C5128AL/AS
AC WAVEFORMS
WRITE CYCLE NO. 1 (WEWE
WEWE
WE Controlled)(1,2)
DATA UNDEFINED
t WC
VALID ADDRESS
t SCS
t PWE1
t PWE2
t AW
t HA
HIGH-Z
t HD
t SA
t HZWE
ADDRESS
CE
WE
DOUT
DIN DATAIN VALID
t LZWE
t SD
CE_WR1.eps
Notes:
1. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the Write.
2. I/O will assume the High-Z state if OE
≥
VIH.
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11
Rev. B
03/04/2008
IS61C5128AL/AS IS64C5128AL/AS
WRITE CYCLE NO. 2
(OE is HIGH During Write Cycle)
(1,2)
WRITE CYCLE NO. 3
(OE is LOW During Write Cycle)
(1)
Notes:
1. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the Write.
2. I/O will assume the High-Z state if OE
≥
VIH.
DATA UNDEFINED
LOW
t
WC
VALID ADDRESS
t
PWE1
t
AW
t
HA
HIGH-Z
t
HD
t
SA
t
HZWE
ADDRESS
CE
WE
D
OUT
D
IN
OE
DATAIN VALID
t
LZWE
t
SD
CE_WR2.eps
DATA UNDEFINED
t
WC
VALID ADDRESS
LOW
LOW
t
PWE2
t
AW
t
HA
HIGH-Z
t
HD
t
SA
t
HZWE
ADDRESS
CE
WE
DOUT
DIN
OE
DATA
IN
VALID
t
LZWE
t
SD
CE_WR3.eps
12
Integrated Silicon Solution, Inc. — www.issi.com
Rev. B
03/04/2008
IS61C5128AL/AS IS64C5128AL/AS
DATA RETENTION WAVEFORM (CECE
CECE
CE Controlled)
VDD
CE ≥ VDD
- 0.2V
t
SDR
t
RDR
V
DR
CE
GND
4.5V
Data Retention Mode
DATA RETENTION SWITCHING CHARACTERISTICS (HIGH SPEED) (IS61/64C5128AL)
Symbol Parameter Test Condition Min. Max. Unit
VDR VDD for Data Retention See Data Retention Waveform 2.9 5.5 V
IDR Data Retention Current VDD = 2.9V, CE ≥ V DD – 0.2V Com. — 8 mA
VIN ≥ VDD – 0.2V, or VIN
≤
VSS + 0.2V
Ind. — 10
Auto. — 15
typ.
(1)
1
tSDR Data Retention Setup Time See Data Retention Waveform 0 — ns
tRDR Recovery Time See Data Retention Waveform tRC —ns
Note:
1. Typical Values are measured at V
DD
= 5V, T
A
= 25
o
C and not 100% tested.
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13
Rev. B
03/04/2008
IS61C5128AL/AS IS64C5128AL/AS
DATA RETENTION SWITCHING CHARACTERISTICS (LOW POWER) (IS61/64C5128AS)
Symbol Parameter Test Condition Min. Max. Unit
VDR VDD for Data Retention See Data Retention Waveform 2.9 5.5 V
IDR Data Retention Current VDD = 2.9V, CE ≥ V DD – 0.2V Com. — 0.8 mA
VIN ≥ VDD – 0.2V, or VIN
≤
VSS + 0.2V
Ind. — 0.9
Auto. — 2
typ.
(1)
0.2
tSDR Data Retention Setup Time See Data Retention Waveform 0 — ns
tRDR Recovery Time See Data Retention Waveform tRC —ns
Note:
1. Typical Values are measured at V
DD
= 5V, T
A
= 25
o
C and not 100% tested.
DATA RETENTION WAVEFORM (CECE
CECE
CE Controlled)
VDD
CE ≥ VDD
- 0.2V
t
SDR
t
RDR
V
DR
CE
GND
4.5V
Data Retention Mode
14
Integrated Silicon Solution, Inc. — www.issi.com
Rev. B
03/04/2008
IS61C5128AL/AS IS64C5128AL/AS
Automotive Range: –40°C to +125°C
Speed (ns) Order Part No. Package
12 IS64C5128AL-12KA3 400-mil Plastic SOJ
IS64C5128AL-12TA3 44-pin TSOP-II
IS64C5128AL-12TLA3 44-pin TSOP-II, Lead-free
HIGH SPEED (IS61/64C5128AL)
ORDERING INFORMATION
Industrial Range: –40°C to +85°C
Speed (ns) Order Part No. Package
10 IS61C5128AL-10KI 400-mil Plastic SOJ
IS61C5128AL-10KLI 400-mil Plastic SOJ, Lead-free
IS61C5128AL-10TI 44-pin TSOP-II
IS61C5128AL-10TLI 44-pin TSOP-II, Lead-free
LOW POWER (IS61/64C5128AS)
ORDERING INFORMATION
Industrial Range: –40°C to +85°C
Speed (ns) Order Part No. Package
25 IS61C5128AS-25QI 450-mil Plastic SOP
IS61C5128AS-25QLI 450-mil Plastic SOP, Lead-free
IS61C5128AS-25HI 32-pin STSOP-I
IS61C5128AS-25HLI 32-pin STSOP-I, Lead-free
IS61C5128AS-25TI 32-pin TSOP-II
IS61C5128AS-25TLI 32-pin TSOP-II, Lead-free
PACKAGING INFORMATION
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. C
06/13/03
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
450-mil Plastic SOP
Package Code: Q (32-pin)
D
SEATING PLANE
B
eC
1
N
E1
A1
A
E
Lα
S
MILLIMETERS INCHES
Symbol Min. Max. Min. Max.
No. Leads 32
A — 3.00 — 0.118
A1 0.10 — 0.004 —
B 0.36 0.51 0.014 0.020
C 0.15 0.30 0.006 0.012
D 20.14 20.75 0.793 0.817
E 13.87 14.38 0.546 0.566
E1 11.18 11.43 0.440 0.450
e 1.27 BSC 0.050 BSC
L 0.58 0.99 0.023 0.039
α0° 10° 0° 10°
S — 0.86 — 0.034
Notes:
1. Controlling dimension: inches, unless
otherwise specified.
2. BSC = Basic lead spacing between centers.
3. Dimensions D and E1 do not include mold
flash protrusions and should be measured
from the bottom of the package.
4. Formed leads shall be planar with respect to
one another within 0.004 inches at the
seating plane.
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. F
10/29/03
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
PACKAGING INFORMATION
400-mil Plastic SOJ
Package Code: K
Notes:
1. Controlling dimension:
millimeters.
2. BSC = Basic lead spacing
between centers.
3. Dimensions D and E1 do not
include mold flash protrusions
and should be measured from
the bottom of the package.
4. Reference document: JEDEC
MS-027.
SEATING PLANE
1
N
E1
D
E2
E
B
eA1
A
C
A2
b
N/2+1
N/2
Millimeters Inches Millimeters Inches Millimeters Inches
Symbol Min Max Min Max Min Max Min Max Min Max Min Max
No. Leads (N) 28 32 36
A 3.25 3.75 0.128 0.148 3.25 3.75 0.128 0.148 3.25 3.75 0.128 0.148
A1 0.64 — 0.025 — 0.64 — 0.025 — 0.64 — 0.025 —
A2 2.08 — 0.082 — 2.08 — 0.082 — 2.08 — 0.082 —
B 0.38 0.51 0.015 0.020 0.38 0.51 0.015 0.020 0.38 0.51 0.015 0.020
b 0.66 0.81 0.026 0.032 0.66 0.81 0.026 0.032 0.66 0.81 0.026 0.032
C 0.18 0.33 0.007 0.013 0.18 0.33 0.007 0.013 0.18 0.33 0.007 0.013
D 18.29 18.54 0.720 0.730 20.82 21.08 0.820 0.830 23.37 23.62 0.920 0.930
E 11.05 11.30 0.435 0.445 11.05 11.30 0.435 0.445 11.05 11.30 0.435 0.445
E1 10.03 10.29 0.395 0.405 10.03 10.29 0.395 0.405 10.03 10.29 0.395 0.405
E2 9.40 BSC 0.370 BSC 9.40 BSC 0.370 BSC 9.40 BSC 0.370 BSC
e 1.27 BSC 0.050 BSC 1.27 BSC 0.050 BSC 1.27 BSC 0.050 BSC
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
2
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. F
10/29/03
PACKAGING INFORMATION
Millimeters Inches Millimeters Inches Millimeters Inches
Symbol Min Max Min Max Min Max Min Max Min Max Min Max
No. Leads (N) 40 42 44
A 3.25 3.75 0.128 0.148 3.25 3.75 0.128 0.148 3.25 3.75 0.128 0.148
A1 0.64 — 0.025 — 0.64 — 0.025 — 0.64 — 0.025 —
A2 2.08 — 0.082 — 2.08 — 0.082 — 2.08 — 0.082 —
B 0.38 0.51 0.015 0.020 0.38 0.51 0.015 0.020 0.38 0.51 0.015 0.020
b 0.66 0.81 0.026 0.032 0.66 0.81 0.026 0.032 0.66 0.81 0.026 0.032
C 0.18 0.33 0.007 0.013 0.18 0.33 0.007 0.013 0.18 0.33 0.007 0.013
D 25.91 26.16 1.020 1.030 27.18 27.43 1.070 1.080 28.45 28.70 1.120 1.130
E 11.05 11.30 0.435 0.445 11.05 11.30 0.435 0.445 11.05 11.30 0.435 0.445
E1 10.03 10.29 0.395 0.405 10.03 10.29 0.395 0.405 10.03 10.29 0.395 0.405
E2 9.40 BSC 0.370 BSC 9.40 BSC 0.370 BSC 9.40 BSC 0.370 BSC
e 1.27 BSC 0.050 BSC 1.27 BSC 0.050 BSC 1.27 BSC 0.050 BSC
Integrated Silicon Solution, Inc.
PACKAGING INFORMATION
Plastic STSOP - 32 pins
Package Code: H (Type I)
Notes:
1. Controlling dimension: millimeters, unless otherwise
specified.
2. BSC = Basic lead spacing between centers.
3. Dimensions D1 and E do not include mold flash protru-
sions and
should be measured from the bottom of the package
.
4. Formed leads shall be planar with respect to one another
within 0.004 inches at the seating plane.
Plastic STSOP (H - Type I)
Millimeters Inches
Symbol Min Max Min Max
Ref. Std.
N 32
A — 1.25 — 0.049
A1 0.05 — 0.002 —
A2 0.95 1.05 0.037 0.041
b 0.17 0.23 0.007 0.009
C 0.14 0.16 0.0055 0.0063
D 13.20 13.60 0.520 0.535
D1 11.70 11.90 0.461 0.469
E 7.90 8.10 0.311 0.319
e 0.50 BSC 0.020 BSC
L 0.30 0.70 0.012 0.028
S 0.28 Typ. 0.011 Typ.
α0° 5° 0° 5°
PK13197H32 Rev. B 04/21/03
D1
SEATING PLANE
C
D
1N
e
S
b
A1
A
A2
E
Lα
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. F
06/18/03
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
PACKAGING INFORMATION
Plastic TSOP
Package Code: T (Type II)
D
SEATING PLANE
b
eC
1N/2
N/2+1N
E1
A1
A
E
Lα
ZD
.
Notes:
1. Controlling dimension: millimieters,
unless otherwise specified.
2. BSC = Basic lead spacing
between centers.
3. Dimensions D and E1 do not
include mold flash protrusions and
should be measured from the
bottom of the package.
4. Formed leads shall be planar with
respect to one another within
0.004 inches at the seating plane.
Plastic TSOP (T - Type II)
Millimeters Inches Millimeters Inches Millimeters Inches
Symbol Min Max Min Max Min Max Min Max Min Max Min Max
Ref. Std.
No. Leads (N) 32 44 50
A — 1.20 — 0.047 — 1.20 — 0.047 — 1.20 — 0.047
A1 0.05 0.15 0.002 0.006 0.05 0.15 0.002 0.006 0.05 0.15 0.002 0.006
b 0.30 0.52 0.012 0.020 0.30 0.45 0.012 0.018 0.30 0.45 0.012 0.018
C 0.12 0.21 0.005 0.008 0.12 0.21 0.005 0.008 0.12 0.21 0.005 0.008
D 20.82 21.08 0.820 0.830 18.31 18.52 0.721 0.729 20.82 21.08 0.820 0.830
E1 10.03 10.29 0.391 0.400 10.03 10.29 0.395 0.405 10.03 10.29 0.395 0.405
E 11.56 11.96 0.451 0.466 11.56 11.96 0.455 0.471 11.56 11.96 0.455 0.471
e 1.27 BSC 0.050 BSC 0.80 BSC 0.032 BSC 0.80 BSC 0.031 BSC
L 0.40 0.60 0.016 0.024 0.41 0.60 0.016 0.024 0.40 0.60 0.016 0.024
ZD 0.95 REF 0.037 REF 0.81 REF 0.032 REF 0.88 REF 0.035 REF
α0° 5° 0° 5° 0° 5° 0° 5° 0° 5° 0° 5°
