CS47048B-CQZ - Cirrus Logic, Inc.

CONFIDENTIAL DS787A7

CS47048 Data Sheet

Advance Product Information This document contains information for a new product.

Cirrus Logic reserves the right to modify this product without notice.

CONFIDENTIAL DRAFT

DELPHI

http://www.cirrus.com

FEATURES

Cost-effective, High-performance 32-bit DSP

— 300,000,000 MAC/S (multiply accumulates per second)

— Dual MAC cycles per clock

— 72-bit accumulators are the most accurate in the industry

— 32K x 32-bit SRAM with three 2K blocks assignable to either

Y data or program memory.

Integrated DAC & ADC Functionality

— 8 Channels of DAC output: 108dB DR, 98dB THD+N

— 4 Channels of ADC input: 105dB DR, 98dB THD+N

— Integrated 5:1 analog mux feeds one stereo ADC

Configurable Serial Audio Inpu ts/Output s

— Integrated 192 kHz S/PDIF Rx

— Integrated 192 kHz S/PDIF Tx

— Supports 32-bit Serial Data @ 192 kHz

— Supports 32-bit audio sample I/O between DSP chips

— TDM I/O modes (Up to 8 channels per line)

Supports Different Fs Sample Rates

— Three Integrated hardware SRC blocks

— Output can be master or slave

— Supports dual-domain Fs on inputs (S/PDIF Rx and I2S)

— Supports dual-domain Fs on outputs (S/PDIF Tx and I2S)

DSP Tool Set w/ Private Keys Protect Customer IP

Integrated Clock Manager/PLL

— Flexibility to operate from internal PLL, external crystal,

external oscillator

Input Fs Auto Detection w/ µC Acknowledgement

Host & Boot via SPI / I2C Serial Interface

Configurable GPIOs and External Interrupt Input

1.8V Core and a 3.3V I/O that is tolerant to 5V input

Low-power Mode: 620µW

The CS470 48 fam il y i s a ne w gen era tion of aud io system-o n-a -

chip (ASOC) processors targeted at high fidelity, cost sensitive

designs. Derived from the highly successful CS48500 32-bit

fixed point audio enhancement processor family, the CS47048

further simplifies system design and reduces total system cost

by integrati ng the S/PDIF Rx, S/PDIF Tx, ana lo g inp ut s , ana log

outputs, and SRCs to simplify system design. For example, a

hardware SRC ca n do wn-s am ple a 1 92k Hz S/PD IF stream to a

lower Fs to reduce memory and MIPS requirements for

processing. This integration effectively reduces the chip count

from 3 to 1 whic h allows small er , less expens ive board desi gns.

Target app lic ations are:

— Automotive Head Units & Outboard Amplifiers

— Automotive Processors & Automotive Integration Hubs

— Digita l TV

— MP3 Docking Stations

— AVR and DVD RX

— DSP Controlled Speakers (e.g. Subwoofers, Sound

Bars)

The CS47048 is programmed using the simple yet powerful

Cirrus proprietary DSP Composer™ GUI development and pre-

production tuning tool. Processing chains may be designed

using a drag-and-drop interface to place/utilize functional

macro audio DSP primitives and custom audio filtering blocks.

The end result is a software image that is downloaded to the

DSP via serial control port.

DSP programming could not be easier for the novice or small

engineering development group. DSP Composer provides the

programmer with faster time-to-market opportunities and the

ability to implement custom code.

The CS47048 is available in a 100-pin LQFP package with

exposed pad for better thermal characteristics. Both

Commercial (0°C to +70°C) and Automotive (-40°C to +85°C)

temperature grades.

Ordering Information:

See page 30 for ordering information

DAC0

text

Coyote32

32- b it D S P

DMA

SPI / I2C

Control

I2S /

TDM

ADC0/1

I2S / TDM

I2S / TDM /

SPDIF

PLL

ROM

Peripheral Bus

Clock

Manager Timers

RAM

GPIO

DAC1

DAC2

DAC3

DAC4

DAC5

DAC6

DAC7

MUX

1ROM

RAM

ROM

RAM PY

32K x 32-bit SRAM with three 2K blocks

Assignable to Program or Y Data memory

Memory Bus

I2S /

TDM /

SPDIF

Stereo Inputs

On Analog in

ADC2/3

DBC

(I2C Slave)

PIC

ADC’s & DAC’s operate

in Single ended or

Differential mo de

8ch

SRC3 has 8

independent Channels

for In or Out

4ch

CS47048 Data Sheet

Audio SOC Processor Family

CONFIDENTIAL DRAFT

DELPHI

Contacting Cirrus Logic Support

For all product questions and inquiries contact a Cirrus Logic Sales Representative.

To find the one nearest to you go to www.cirrus.com.

IMPORTANT NOTICE

“Advance” product in form at i on de scri bes products tha t are i n development and subj ect t o deve l opme nt chang es. Ci rrus Lo gi c, I nc. and its sub si di ari es (“Cirrus” ) be

lieve that the informati on contained i n this document i s accurate and reli able. However, t he information is subject to chan ge without no tice and is provi ded “AS IS

”

without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that infor

mation being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including

those pertaining to warranty, indemnification, and limitation of liability. No responsibility is a ssu med by C irrus for the u se o f th is in form ation , inc lud ing us e o f this infor

mation as the basi s for manufactu re or sal e of any items, or for i nfri ng emen t of pate nts or other ri gh t s of third parties. Thi s document is the property of Cirrus and by

furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectua

propert y rights. Cirrus owns the copyr i ghts asso ci at ed wi th the infor mati on cont ai ne d herein and gi ves conse nt for copies to be made of t he i n f orma ti on only for use

within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for genera

distribution, advertising or promotional purposes, or for creating any work for resale.

CERTAIN APP LICATIONS US ING SEMICOND UCTOR PROD UCTS M AY INVOLVE POTENTIAL RISKS OF DEATH, PE RSONAL INJURY, OR SEVE RE PROPE R

TY OR ENVIRONME NTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN

PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL

APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS

DISCLAIMS AND MAKES NO WAR RANT Y, EXPRESS , STATUTO RY OR IMP LIED, INCLUDIN G THE IMPLIED W ARRANT IES OF MERCH ANT ABILITY AND FIT

NESS FOR P ARTICULAR PURPOS E, WITH REG ARD TO ANY CIRRUS PRO DUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S

CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRO DUCT S IN CRITICAL APPLICATIONS, CUSTO MER AGREES, BY SU CH USE, T O FULLY INDEM

NIFY CIRRUS, ITS OFFICERS, DIREC TORS, EMPLOYEES , DISTRIBUTORS AN D OTHER AGEN TS FROM ANY AND ALL LIABILITY, INCLUDING ATTOR NEYS

FEES AND CO ST S, THAT MAY RESULT FRO M OR ARISE IN CONNECTION WITH THESE USES.

Cirrus Logic, Cirrus, the Cirrus Logic logo designs, DSP Composer, and Cirrus Framework are trademarks of Cirrus Logic, Inc. All other brand and product names in

this document may be trademarks or service marks of their respective owners.

SPI is a trademark of Motorola, Inc.

C is a regis tered tradema r k of Ph ilips Semico nd u c t o r.

CS47048 Data Sheet

Audio SOC Processor Family

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Table of Contents

FEATURES ......................................................................................................................... 1

1. Documentation S tr ategy ... ..... ..... .... ................................. .......................................................6

2. Overv iew .............................................................................................. .... ..... ..... ................... . ..6

2.1 Licensing ............................................................................................................................................... 6

3. Code Ove rlay s ................................................................................................... ......................7

4. Hardware Functional Desc ription ...... ................... ................................ ................................8

4.1 DSP Core .............................................................................................................................................. 8

4.2 DSP Memory ......................................................................................................................................... 9

4.2.1 DMA Controller .........................................................................................................................9

4.3 On-chip DSP Peripherals ...................................................................................................................... 9

4.3.1 Analog to Digital Converter Port (ADC) ....................................................................................9

4.3.2 Digital to Analog Converter Port (DAC) ....................................................................................9

4.3.3 Digital Audio Input Port (DAI) ..................................................................................................10

4.3.4 S/PDIF RX Input Port (DAI) ....................................................................................................10

4.3.5 Digital Audio Output Port (DAO) .............................................................................................10

4.3.6 S/PDIF TX Output Port (DAO) ................................................................................................10

4.3.7 Sample Rate Converters (SRC) .............................................................................................10

4.3.8 Serial Control Port (I2C® or SPI™) ......................... .......................... .......................... ............. 11

4.3.9 GPIO ....................................................................................................................................... 11

4.3.10 PLL-based Clock Generator ................................................................................................. 11

4.3.11 Hardware Watchdog Timer ................................................................................................... 11

4.4 DSP I/O Description .............................................................................................................................11

4.4.1 Multiplexed Pins ..................................................................................................................... 11

4.4.2 Termination Requirements ...................................................................................................... 11

4.4.3 Pads ....................................................................................................................................... 11

4.5 Application Code Security ................................................................................................................... 12

5. Character istic s a nd Specifications ............. .............. ..... ..... .... ............................................13

5.1 Absolute Maximum Ratings ................................................................................................................. 13

5.2 Recommended Operating Conditions ................................................................................................. 13

5.3 Digital DC Characteristics ................................................................................................................... 13

5.4 Power Supply Characteristics ............................................................................................................. 14

5.5 Thermal Data (100-Pin LQFP with Exposed Pad) ...............................................................................14

5.6 Digital Switching Characteristics— RESET ......................................................................................... 15

5.7 Digital Switching Characteristics — XTI .............................................................................................. 15

5.8 Digital Switching Characteristics — Internal Clock .............................................................................. 16

5.9 Digital Switching Characteristics — Serial Control Port - SPI Slave Mode ......................................... 17

5.10 Digital Switching Characteristics — Serial Control Port - SPI Master Mode ..................................... 18

5.11 Digital Switching Characteristics — Serial Control Port - I2C Slave Mode2 ............. ...... ....... ...... ....... 19

5.12 Digital Switching Characteristics — Serial Control Port - I2C Master Mode ...................................... 20

5.13 Digital Switching Characteristics — Digital Audio Slave Input Port ................................................... 21

5.14 Digital Switching Characteristics — Digital Audio Output Port .......................................................... 22

5.15 Digital Switching Characteristics — S/PDIF RX Port ........................................................................23

5.16 ADC Characteristics .......................................................................................................................... 24

5.16.1 Analog Input Characteristics (Commercial) ..........................................................................24

5.16.2 Analog Input Characteristics (Automotive) ...........................................................................25

5.16.3 ADC Digital Filter Characteristics .........................................................................................27

5.17 DAC Characteristics .......................................................................................................................... 27

5.17.1 Analog Output Characteristics (Commercial) .......................................................................27

CS47048 Data Sheet

Audio SOC Processor Family

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5.17.2 Analog Output Characteristics (Automotive) ........................................................................28

5.17.3 Combined DAC Interpolation & On-chip Analog Filter Response ........................................29

6. Ordering Informa ti on .................. .... ..... ............................................................. ............... .....30

7. Environmental, Manufacturing, & Handli ng Infor mation ................ .... ..... ................... ......30

8. Device Pi nout Diag ram ............... .... ........................................................................... ...........31

8.1 CS47048, 100-Pin LQFP Pinout Diagram ........................................................................................... 31

9. 100-pin LQ FP with E xpose d Pa d Pa cka ge Dra wing ......... .................. ................... ...........31

10. Paramete r Definitions .......... ......... .......... .... .......... ......... ......... .......... ......... ..... ......... ...........33

10.1 Dynamic Range ................................................................................................................................. 33

10.2 Total Harmonic Distortion + Noise ..................................................................................................... 33

10.3 Frequency Response ........................................................................................................................ 33

10.4 Interchannel Isolation ........................................................................................................................ 33

10.5 Interchann el Ga in Mis matc h ...... ....... ...... ....... ................... ...... ....... ................... ....... ...... .................... 33

10.6 Gain Error .......................................................................................................................................... 33

10.7 Gain Drift ........................................................................................................................................... 33

11. Revision History .............. ..... ..... .................................................................................... ..... .33

Figures

Figure 1. CS47048 Top-Level Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 2. RESET Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 3. XTI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Figure 4. Serial Control Port - SPI Slave Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 5. Serial Control Port - SPI Master Mode Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 6. Serial Control Port - I2C Slave Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 7. Serial Control Port - I2C Master Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 8. Digital Audio Input (DAI) Port Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 9. Digital Audio Output Port Timing, Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 10. Digital Audio Output Port Timing, Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 11. ADC Single-Ended Input Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 12. ADC Differential Input Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 13. DAC Single-Ended Output Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 14. DAC Differential Output Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 15. Maximum Loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 16. CS47048 Pinout Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 17. 100-Pin LQFP Package Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

CS47048 Data Sheet

Audio SOC Processor Family

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Tables

Table 1. CS47048 Related Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Table 2. Device Selection Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 3. Memory Configurations for CS47048 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 4. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 5. Environmental, Manufacturing, & Handling Information . . . . . . . . . . . . . . . . . . . . 30

CS47048 Data Sheet

Audio SOC Processor Family

CONFIDENTIAL DRAFT

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1. Documentation Strategy

The CS47048 Data Sheet describes the CS47048 audio processors. This document should be

used in conjunction with the following documents when evaluating or designing a system around

the CS47048 processor s

The scope of the CS47048 Data Sheet is primarily the hardware specifications of the CS47048

family of devices. This includes hardware functionality, characteristic data, pinout, and packaging

information.

The intended audience for the CS47048 Data Sheet is the system PCB designer, MCU

programmer, and the quality control engi neer.

2. Overvi ew

The CS47048 DSP is designed to provide high-performance post-processing and mixing of analog

and digi tal audio . The dual clock domain provided on the PCM inputs allows for the mixing of audio

streams with different sampling frequencies. The low-power standby preserves battery life for

applications which are always on, but not necessarily processing audio, such as automotive audio

systems.

The CS47048 utilizes voltage- out DACs and is capable of supporting dual inpu t clock domains and

dual output clock domains through the use of the internal SRCs. The CS47048 is available in a

100-pin LQFP package. Refer to Table 2 on page 7 for the input, output, and firmware

configur ations for the CS47048 DSP.

2.1 Licensing

Licenses are required for any 3rd party audio processing algorithms provided for the CS47048.

Please contact your local Cirrus Logic Sales representative for more information.

Table 1. CS47048 Related Documentation

Document Name Description

CS47048 Data Sheet This document

CS47048 System Designer’s Guide Includes detailed system design information

including Typical Connection Diagrams, Boot-

Procedures, Pin Descriptions, Etc.

AN333 - CS47048 Firmware User’s Manual Includes detailed firmware design information

including signal processing flow diagrams and

control API information

DSP Composer User’s Manual Includes detailed configuration and usage

information for the GUI development tool.

CS47048 Data Sheet

Audio SOC Processor Family

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DELPHI

3. Code Overlays

The suite of software available for the CS47048 family consists of an operating system (OS) and a

library of overlays. The overlays for the CS47048 are currently limited to post-processors. All

software components are defined below:

1. OS/Kernel - Encomp asses al l non-audi o processi ng t ask s, i ncludi ng loadi ng dat a from ext ernal

serial memory, processing host messages, calling audio-processing subroutines, error

concealment, etc.

2. Post-processors - Any module that processes audio I/O buffer PCM data. Examples are bass

management, audio manager, tone control, EQ, delay, customer-specific eff ects, and any post-

processing algorithms available for the CS485xx.

The bulk of st anda rd o verlays are st ored in ROM with in the CS4 7048, but a smal l image is re quired

to configure the overlays and boot the DSP. This small image can either be stored in an external

serial FLASH/EEPROM, or downloaded via a host controller through the SPI™/I2C® serial port.

The overlay structure reduces t he time required to reconfigure the DSP when a processing change

is requested. Each overlay can be reloaded independently without disturbing the other overlays.

For example, when a dif fer ent post- proce ssor is sele cted , the OS, does not need to be reloaded —

only the new post-processor.

Table 2 lists the different configuration options available. Please refer to the CS47048 Firmware

User’s Manual for the late st list ing of applica ti on codes and Cirrus Framework™ modules available.

Table 2. Device Selection Guide

Device Suggested

Application Channel Count

Input/Output Package

CS47048-CQZ

CS47048-DQZ

Automotive Head Units

Automotive Outboard Amplifiers

Automotive Processors

Automotive Integration Hubs

Digital TV

MP3 Docking Stations

AVR

DVD Rx

DSP Controlled Speakers

Up to 12 Channels Analog In (4 simultaneously)

Up to 10 Channels PCM In (Stand-Alone)

Up to 8 Channels PCM In (w/ Host)

Up to 40 Channels TDM In

Up to 8 Channels Analo g Out

Up to 8 Channels PCM Out

Up to 32 Channels TDM Out

100-pin

QFP

CS47048 Data Sheet

Audio SOC Processor Family

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DELPHI

4. Hardware Functional Description

The CS47048 is a true system-on-a-chip that combines a powerful 32-bit DSP engine with

analog/digital audio inputs and analog/digital audio outputs. It can be integrated into a complex

multi-DSP processing system, or stand alone in an audio product that requires analog-in and

analog-out. A top level block diagram is shown below in Figure 1.

Figure 1. CS47048 Top-Level Block Diagram

4.1 DSP Core

The CS47048 is a single-core DSP with separate X and Y data and P code memory spaces. The

DSP core is a high-performance, 32-bit, user-programmable, fixed-point DSP that is capable of

performing two multiply-and-accumulate (MAC) operations per clock cycle. The DSP core has

eight 72-bi t accumulators, four X-data and four Y-data registers, and 12 index register s.

The DSP core is coupled to a flexible 8-channel DMA engine. The DMA engine can move data

between perip herals suc h as the serial c ontrol port (SCP), digit al audio input (DAI ) and digita l audio

output (DAO), sample rate converters (SRC), analog-to-digital converters (ADC), digital-to-analog

converters (DAC), or any DSP core memory, all without the intervention of the DSP. The DMA

engine off-loads data move instructio ns from the DSP core, leaving more MIPS available for signal

processing instructions.

DAC0

text

Coyote32

32-bit DSP

DMA

SPI / I2C

Control

I2S /

TDM

ADC0/1

I2S / TDM

I2S / T D M /

SPDIF

PLL

ROM

Peripheral Bus

Clock

Manager Timers

RAM

GPIO

DAC1

DAC2

DAC3

DAC4

DAC5

DAC6

DAC7

MUX

1ROM

RAM

ROM

RAM PY

32K x 32-bit SRAM with three 2K b locks

Assign ab le to P rog ram o r Y Da ta m em o ry

Memory Bus

I2S /

TDM /

SPDIF

Stereo Inputs

On Analog in

ADC2/3

DBC

(I2C S lave)

PIC

ADC’s & DAC’s operate

in Single ended or

Differential mode

8ch

SRC3 has 8

independent Channels

for In or Out

4ch

CS47048 Data Sheet

Audio SOC Processor Family

CONFIDENTIAL DRAFT

DELPHI

CS47048 functionality is controlled by application codes that are stored in on-chip ROM or

downloaded to the CS47048 from a host controller or external serial FLASH/EEPROM.

Users can develop their applications using DSP ComposerTM to create the processing chain and

then compile the image into a series of commands that are sent to the CS47048 through the SCP.

The processing application can either load modules (post-processors) from the DSP’s on-chip

ROM, or custom firmware can be downloaded through the SCP.

The CS47048 is suit able for a var iety of audio post-pr ocessing applicat ions where sound quali ty via

sound enhancement and speaker/cabinet tuning is required to achieve the sound quality

consumers expect. Examples of such applications include automotive head-ends, automotive

amplifiers, docking st ations, sound bars, subwoofers, and boom boxes.

4.2 DSP Memory

The DSP core has its own on-chip data and program RAM and ROM and does not require external

memory for post-processing applications.

The Y-RAM and P-RAM share a single block of memory that includes three 2K word blocks (32

bits/word) that are assignable to either Y-RAM or P-RAM as shown in Table 3.

4.2.1 DMA Controller

The powerful 8-channel DMA controller can move data between 8 on-chip resources. Each

resource has its own arbiter: X, Y, and P RAMs/ROMs and the peripheral bus. Modulo and linear

addressing modes are supported, with flexible start address and increment controls. The service

intervals for each DMA channel, as well as up to 6 interr upt events, are programmable.

4.3 On-chip DSP Peripherals

4.3.1 Analog to Digital Converter Port (ADC)

The CS47048 features ADCs with dynamic range performance in excess of 100 dB, and they can

support up to 4 simultaneous channels of analog-to-digital conversion. Analog inputs AIN_1A and

AIN_1B are connected directly to one stereo ADC (ADC0-1). The analog input capability of the

second stereo ADC (ADC2-3) is expanded through a 5:1 analog stereo mux (analog inputs

AIN_2A/B through AIN_6A/B). This gives the CS47048 the ability to select from six stereo pairs of

analog input. A single programmable bit selects single-ended or differential mode signals for all

inputs.

The conversions are performed with either Fs=96 kHz or Fs=192 kHz.

4.3.2 Digital to Analog Converter Port (DAC)

The CS47048 can support up to 8 simultaneous channels of digital-to-analog conversion and

features DACs with dynamic range performance in excess of 100 dB. The DACs have voltage

mode outputs that can be connected either as singl e-ended or differential signals . The conversi ons

are performed with Fs=96 kHz.

Table 3. Memory Configurations for CS47048

P-RAM X-RAM Y-RAM

14K words 10K words 8K words

12K words 10K words 10K words

10K words 10K words 12K words

8K words 10K words 14K words

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Audio SOC Processor Family

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4.3.3 Digital Audio Input Port (DAI)

The input capabilities for each version of the CS47048 are summarized in Table 2 on page 7.

Up to five DAI ports are available. Two of the DAI ports can be programmed to implement other

functi ons. The S/PDI F Rx funct ion, i f used, t akes over the DAI_DATA3 pin. If the SPI mode is used ,

the DAI_DATA4 pin becomes the SCP_CS input.

The DAI port supports PCM format with word len gths up to 32 bits and sample rates as high as

192 kHz.

The DAI als o supp ort s a ti me divi sion mul tiplexed (TDM) one-l ine da ta mode t hat p acks PCM audi o

on a single data line. The total number possible depends on the ratio of SCLK to LRCLK. The

CS47048 hardware supports up to 40 channels in one line mode @ 48 kHz. There is also a

practical limitation set by the amount of processing required per channel.

The DAI port has two independent slave-only clock domains. The PCM inputs can be on one clock

domain, and the S/PDIF Rx on another. The output of the S/PDIF Rx can then be converted

through one of the internal SRC blocks to synchronize with the PCM input.

The sample rate of the input clock domains can be determined automatically by the DSP, off-

loading the task of monitoring the S/PDIF Rx from the host. A time-stamping feature provides the

ability to also sample-rate convert the input data via software.

4.3.4 S/PDIF RX Input Port (DAI)

One of the PCM pins of the DAI can also be used as a DC-coupled, TTL-level S/PDIF Rx input

capable of receiving and demodul ating bi-phase encoded S/PDIF signal s with Fs ≤ 192 kHz.

4.3.5 Digital Audio Output Port (DAO)

The output capabilities of the CS47048 are summarized in Table 2 on page 7.

DAO port supports PCM resolutions of up to 32-bits. The port supports sample rates (Fs) as high

as 192 kHz. The port can be configured as an independent clock domain mastered by the DSP, or

as a clock slave if an external MCLK or SCLK/LRCLK source is available.

The DAO also supports a time division multiplexed (TDM) one-line data mode, that packs multiple

channels of PCM audio on a single data line. The total number possible depends on the ratio of

SCLK to LRCLK and the version of chip. For example, the CS47048 hardware supports up to 32

channels in one line mode @ 48 kHz. There is also a practical limitation set by the amount of

processing required per channel.

4.3.6 S/PDIF TX Output Port (DAO)

Two of the serial audio pins can be re-configured as S/PDIF TX pins that drive a bi-phase encoded

S/PDIF signal (data with embedded clock on a single line). The S/PDIF engine can be driven by a

clock domain independent of the PCM output port by util izi ng one of the internal SRCs.

4.3.7 Sample Rate Converters (SRC)

The CS47048 has 3 internal SRC modules. Two of the SRC modules are capable of converting 8

Channels, and one SRC has 4-Channel capabili ty.

The ADCs are directly associated with a 4-Channel SRC which is used to transfer data from the

fixed 96/ 192 kHz Fs domain into an Fs appr opriat e for mixi ng with othe r audi o in the syst em. When

the Analog Inputs are not being used, this SRC can be used to convert digital data within the DSP

from the input Fs (Fsi) to the output Fs (Fso).

The DACs are directly associated with an 8-Channel SRC which is used to transfer data from the

Fs being processed by the DSP to a fixed 96 kHz Fs domain for conversion to analog. When the

Analog Outputs are not being used, this SRC can be used to convert digital data within the DSP

from Fsi to Fso.

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The second 8-Channel SRC is a stand-alone digital-to-digital conversion module. It can be used to

make independent in put clock domai ns synchronous ( dif f er ent Fs on PCM input and S/PDIF Rx) or

to drive the S/PDIF Tx at a different Fs than the PCM output of the DSP.

4.3.8 Serial Contr ol Port (I2C® or SPI™)

The on-chip serial control port is capable of operating as master or slave in either SPI™ or I2C®

modes. Master/Slave operation is chosen by mode select pins when the CS47048 comes out of

reset. The serial clock pin can support frequencies as high as 25 MHz in SPI mode (SPI clock

speed must always be ≤ (DSP Core Frequency/2)). The CS47048 serial control port also includes

a pin for flow control of the communications interface (SCP_BSY) and a pin to indicate when the

DSP has a message for the host (SCP_IRQ).

4.3.9 GPIO

Many of the CS47048 per ipheral pins are multi plexed with GPIO. Each GPIO can be configured as

an output, an input, or an input with interrupt. Each input-pin interrupt can be configured as rising

edge, falling edge, active -low, or active-high.

4.3.10 PLL-based Clock Generator

The low-ji tter PLL gener ates int eger or fra ctional multipl es of a refer ence f requency which are used

to clock the DSP core and peripherals. Through a second PLL divider chain, a dependent clock

domain can be output on the DAO port for driving audio converters. The CS47048 defaults to

running from the external reference frequency and is switched to use the PLL output after overlays

have been loaded and configured, either through master boot from an external FLASH or through

host control. A built-in crystal oscillator circuit with a buffered output is provided. The buffered

output frequency ratio is selectable between 1:1 (default) or 2:1.

4.3.11 Hardware Watchdog Timer

The CS47048 has an integrated watchdog timer that acts as a “health” monitor for the DSP. The

watchdog timer must be reset by the DSP before the counter expires, or the entire chip is reset.

This peri pheral e nsures th at the CS47048 will r eset it self in the event of a temporary system fai lure.

In stand-alone mode (i.e. no host MCU), the DSP will reboot from external FLASH. In slave mode

(i.e. host MCU present) a GPIO will be used to signal the host that the watchdog has expired and

the DSP should be rebooted and re-configured.

4.4 DSP I/O Description

4.4.1 Multiplexed Pins

Many of the CS47048 pins are multi-functional. For details on pin functionality please refer to the

CS47048 System Designer’s Guide.

4.4.2 Termination Requirements

Open-drain pins on the CS47048 must be pulled high for proper operation. Please refer to the

CS47048 System Designer’s Guide to identify which pins are open-drain and what value of pull-up

resistor is required fo r proper operation.

Mode select pins on the CS47048 are used to select the boot mode upon the rising edge from

reset. A detailed explanation of termination requirements for each communication mode select pin

can be found in the CS47048 System Designer’s Guide.

4.4.3 Pads

The CS47048 Digital I/Os operate from the 3.3 V supply and are 5 V tolerant.

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4.5 Application Code Security

The external program code may be encrypted by the programmer to protect any intellectual

property it may cont a in. A secret, custo mer-s pecific key is used to encrypt the program code t hat is

to be stored external to the device. Please contact your local Cirrus repr esentative for details.

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5. Characteristics and Specifications

Note: All data sheet minimum and maximum timing parameters are guaranteed over the rated voltage and

temperature. All data sheet typical parameters are measured under the following conditions: T = 25 °C,

VDD = 1.8 V, VDDIO = VDDA =3.3 V, GND = GNDIO = GNDA = 0 V.

5.1 Absolute Maximum Ratings

(GND = GNDIO = GNDA = 0 V; all voltages with respect to 0 V)

Caution: Operation at or beyond these li mits may result in perma nen t dama ge to th e dev ice. Nor m al op er ation is

not guaranteed at these extremes.

5.2 Recommended Operating Conditions

(GND = GNDIO = GNDA = 0 V; all voltages with respect to 0 V)

Note: It is recommended that the 3.3 V IO supply come up ahead of or simultaneously with the 1.8 V core supply.

5.3 Digital DC Characteristics

(Measurements performed under static conditions.)

Parameter Symbol Min Max Unit

DC power supplies: Core supply

Analog supply

I/O supply

|VDDA – VDDIO|

VDD

VDDA

VDDIO

–0.3

2.0

3.6

0.3

Input pin current, any pin except supplies Iin -+/- 10mA

Input voltage on PLL_REF_RES Vfilt -0.3 3.6 V

Input voltage on digital I/O pins Vinio -0.3 5.0 V

Analog Input Voltage Vin AGND - 0.7 VA + 0.7 V

Storage temperature Tstg –65 150 °C

Parameter Symbol Min Typ Max Unit

DC power supplies: Core supply

Analog supply

I/O supply

|VDDA – VDDIO|

VDD

VDDA

VDDIO

1.71

3.13

1.8

3.3

1.89

3.46

Ambient operating temperature Commercial - CQZ

Automotive - DQZ

TA0

- 40

-+ 70

+ 85

°C

Parameter Symbol Min Typ Max Unit

High-level input voltage VIH 2.0 - - V

Low-level input voltage, except XTI VIL --0.8V

Low-level input voltage, XTI VILXTI --0.6V

Input Hysteresis Vhys 0.4 V

High-level output voltage (IO = -2mA), except XTO VOH VDDIO * 0.9 - - V

Low-level out put voltage (IO = 2mA), except XTO VOL - - VDDIO * 0.1 V

Input leakage XTI ILXTI --5μA

Input leakage current (all digital pins with internal

pul l-up re si st or s enab led) ILEAK --70μA

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5.4 Power Supply Characteristics

Note:Measurements performed under operating conditions)

5.5 Thermal Data (100-Pin LQFP with Exposed Pad)

Parameter Min Typ Max Unit

Operational Power Supply Current:

VDD: Core and I/O operating1

VDDA: PLL operating current

VDDA: DAC operating current (all 8 channels enabled)

VDDA: ADC operating current (all 4 channels enabled)

VDDIO: With most ports operating

Total Operational Power Dissipation:

Standby Power Supply Current:

VDD: Core and I/O not clocked

VDDA: PLLs halted

VDDA: DAC disabled

VDDA: ADC disabled

VDDIO: All connected I/O pins 3-stated by other ICs in system

Total Standby Power Dissipation:

1. Dependent on application firmware and DSP clock speed.

325

1025

140

1.2

100

0.4

620

μA

μW

Parameter Symbol Min Typ Max Unit

Thermal Resistance (Junction to Ambient)Two-layer Board1

Four-layer Board2

1. To calculate the die temperature for a given power dissipation:

Τj = Ambient temperature + [ (Power Dissipation in Wat ts) * θja ]

2. To calculate the case temperature for a given power dissipation:

Τc = Τj - [ (Power Dissipation in Watts) * ψjt ]

Note:Two-layer board is specified as a 76 mm X 114 mm, 1.6 mm thick FR-4 material with 1-oz. copper covering 20%

of the top & bottom layers.

Note:Four-lay er boar d is sp eci fie d as a 76 mm X 114 mm, 1.6 mm thick FR-4 materi al with 1- oz . copper cov eri ng 20%

of the top & bottom layers and 0.5-oz. copper covering 90% of the internal power plane & ground plane layers.

θja -

-34

18 -

°C / Watt

Thermal Resistance (Junction to Top of Package)

Two-layer Board1

Four-layer Board2

ψjt -

-0.54

.28 -

°C / Watt

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5.6 Digital Switching Characteristics— RESET

Figure 2. RESET Timing

5.7 Digital Switching Characteristics — XTI

Figure 3. XTI Timing

Parameter Symbol Min Max Unit

RESET minimum pulse width low Trstl 1-μs

All bidirectional pins high-Z after RESET low Trst2z -100ns

Configuration pins setup before RESET high Trstsu 50 - ns

Configuration pins hold after RESET high Trsthld 20 - ns

Parameter Symbol Min Max Unit

External Crystal operating frequency1

1. Part characterized with the following crystal frequency values: 11.2896, 12.288, 18.432, 24.576, & 27 MH.z

Fxtal 11.2896 27 MHz

XTI period Tclki 37 89 ns

XTI high time Tclkih 13.3 - ns

XTI low time Tclkil 13.3 - ns

External Crystal Load Capacitance (parallel resonant)2

2. CL refers to the total load capacitance as specified by the crystal manufacturer. Crystals which require a CL outside

this range should be avoided. The crystal oscillator circuit design should follow the crystal manufacturer’s

recommendation for load capacitor selection.

CL10 18 pF

External Crystal Equivalent Series Resistance ESR 50 Ω

RESET

Trst2z

Trstl

Trstsu Trsthld

HS[3:0]

ll Bidirectional

Pins

tclkih tclkil

Tclki

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5.8 Digital Switching Characteristics — Internal Clock

Parameter Symbol Min Max Unit

Internal DSP_CLK frequency1

CS47048-CQZ

CS47048-DQZ

1. After in iti al po wer-on re set , Fdclk = Fxtal. A f ter in itia l ki ck st a r t co m m and s, the PLL i s loc ke d t o m ax F dclk and remains

locked until the next power-on reset.

Fdclk -

Fxtal2

Fxtal

2.See Section 5.7.

150

MHz

Internal DSP_CLK p eriod1

CS47048-CQZ

CS47048-DQZ

DCLKP -

6.7

6.7 1/Fxtal

1/Fxtal

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5.9 Digital Switching Characteristics — Serial Control Port - SPI Slave Mode

Figure 4. Serial Control Port - SPI Slave Mode Timing

Parameter Symbol Min Typical Max Units

SCP_CLK frequency1

1. fspisck indicates the maximum speed of the hardware. The system designer should be aware that the actual

maximum speed of the communication port may be limited by the firmware application. Flow control using the

SCP_BSY pin should be implemented to prevent overflow of the input data buffer. At boot the maximum speed is

Fxtal/3.

fspisck -25MHz

SCP_CS falling to SCP_CLK rising tspicss 24 - ns

SCP_CLK low time tspickl 20 - ns

SCP_CLK high time tspickh 20 - ns

Setup time SCP_MOSI input tspidsu 5-ns

Hold time SCP_MOSI input tspidh 5-ns

SCP_CLK low to SCP_MISO output valid tspidov -11ns

SCP_CLK falling to SCP_IRQ rising tspiirqh -20ns

SCP_CS rising to SCP_IRQ falling tspiirql 0ns

SCP_CLK low to SCP_CS rising tspicsh 24 - ns

SCP_CS rising to SCP_MISO output high-Z tspicsdz -20 ns

SCP_CLK rising to SCP_BSY falling tspicbsyl -3

*DCLKP+20 ns

SCP_BSY

SCP_CS

SCP_CLK

CP_MOSI

CP_MISO

SCP_IRQ

012670567

tspicss

tspickl

tspickh

tspidsu tspidh tspidov

A6 A5 A0 R/W MSB LSB

MSB LSB

tspicsh

tspibsyl

tspiirql

tspiirqh

fspisck

tspicsdz

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5.10 Digital Sw itching Cha racteristics — Serial Control Port - SPI Master Mode

Figure 5. Serial Control Port - SPI Master Mode Timing.

Parameter Symbol Min Typical Max Units

SCP_CLK frequency1

1. fspisck indicates the maximum speed of the hardware. The system designer should be aware that the actual

maximum speed of the communication port may be limited by the firmware application.

fspisck -F

xtal/22

2. See Section 5.7.

MHz

SCP_CS falling to SCP_CLK rising 3

3. SCP_CLK PERIOD refers to the period of SCP_CLK as being used in a given application. It does not refer to a

tested parameter

tspicss - 11*DCLKP +

(SCP_CLK PERIOD)/2 -ns

SCP_CLK low time tspickl 18 - ns

SCP_CLK high time tspickh 18 - ns

Setup time SCP_MISO input tspidsu 9-ns

Hold time SCP_MISO input tspidh 5-ns

SCP_CLK low to SCP_MOSI output valid tspidov -8ns

SCP_CLK low to SCP_CS falling tspicsl 7-ns

SCP_CLK low to SCP_CS rising tspicsh - 11*DCLKP +

(SCP_CLK PERIOD)/2 -ns

Bus free time between active SCP_CS tspicsx 3*DCLKP - ns

SCP_CLK falling to SCP_MOSI output high-Z tspidz -20ns

EE_CS

SCP_CLK

CP_MISO

CP_MOSI

012670567

tspicss

tspickl

tspickh

tspidsu tspidh tspidov

A6 A5 A0 R/W MSB LSB

MSB LSB

tspicsh

tspicsx

fspisck

tspidz

tspicsl

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5.11 Digital Switching Characteristics — Serial Control Port - I2C Slave Mode 2

Figure 6. Serial Cont rol Port - I2C Slave Mode Timing

Parameter Symbol Min Typical Max Units

SCP_CLK frequency1

1. fiicck indi cates the maximu m speed of the hard ware. The system des igner sho uld be aw are that th e actual maximum

speed of the communication port may be limited by the firmware application. Flow control using the SCP_BSY pin

should be implemented to prevent overflow of the input data buffer.

2. I2C Slave Address = 0x82

fiicck - 400 kHz

SCP_CLK rise time tiicr 150 ns

SCP_CLK fall time tiicf 150 ns

SCP_CLK low time tiicckl 1.25 - µs

SCP_CLK high time tiicckh 1.25 - µs

SCP_CL K rising to SCP_ SDA rising or falling for START or STOP

condition tiicckcmd 1.25 µs

START condition to SCP_CLK falling tiicstscl 1.25 - µs

SCP_CLK falling to STOP condition tiicstp 2.5 - µs

Bus free time between STOP and START conditions tiicbft 3-µs

Setup time SCP_SDA input valid to SCP_CLK rising tiicsu 100 ns

Hold time SCP_SDA input after SCP_CLK falling tiich 20 - ns

SCP_CLK low to SCP_SDA out valid tiicdov -18ns

SCP_CLK falling to SCP_IRQ rising tiicirqh -3

*DCLKP + 40 ns

NAK condition to SCP_IRQ low tiicirql 3*DCLKP + 20 ns

SCP_CLK rising to SCB_BSY low tiicbsyl -3

*DCLKP + 20 ns

CP_BSY

SCP_CLK

SCP_SDA

SCP_IRQ

01 67801 7

tiicckl

tiicckh

tiicsu tiich

A6 A0 R/W ACK LSB

tiicirqh tiicirql

ACK

MSB

tiicstp

tiiccbsyl

tiicdov tiicbft

tiicstscl

tiicckcmd

fiicck

tiicckcmd

tiicf

tiicr

Start Condition

Stop Conditio

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5.12 Digital Sw itching Cha racteristics — Serial Control Port - I2C Master Mode

Figure 7. Serial Control Port - I2C Master Mode Timing

Parameter Symbol Min Max Units

SCP_CLK frequency1

1.fiicck indicates the maximum speed of the hardware. The system designer should be aware that the actual maximum speed of the

communication port may be limited by the firmware application.

fiicck -400kHz

SCP_CLK rise time tiicr -150ns

SCP_CLK fall time tiicf -150ns

SCP_CLK low time tiicckl 1.25 - µs

SCP_CLK high time tiicckh 1.25 - µs

SCP_CLK rising to SCP_SDA rising or falling for START or STOP condition tiicckcmd 1.25 µs

START condition to SCP_CLK falling tiicstscl 1.25 - µs

SCP_CLK falling to STOP condition tiicstp 2.5 - µs

Bus free time between STOP and START conditions tiicbft 3-µs

Setup time SCP_SDA input valid to SCP_CLK rising tiicsu 100 ns

Hold time SCP_SDA input after SCP_CLK falling tiich 20 - ns

SCP_CLK low to SCP_SDA out valid tiicdov -18ns

CP_CLK

SCP_SDA

01 67801 7

tiicckl

tiicckh

tiicsu tiich

A6 A0 R/W ACK LSB

ACK

MSB

tiicstp

tiicdov tiicb

tiicstscl

tiicckcmd

fiicck

tiicckcmd

tiicf

tiicr

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5.13 Digita l Switching Characteristics — Digital Audio Slave Input Port

Figure 8. Digital Audio Input (DAI) Port Timing Diagram

Parameter Symbol Min Max Unit

DAI_SCLK period Tdaiclkp 20 - ns

DAI_SCLK duty cycle - 45 55 %

Setup time DAI_DATAn tdaidsu 8-ns

Hold time DAI_DATAn tdaidh 5-ns

DAI_SCLK

AI_DATAn

tdaidh

tdaidsu

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5.14 Digital Sw itching Cha racter istics — Digital Audio Output Port

Figure 9. Digital Audio Output Port Timing, Master Mode

Parameter Symbol Min Max Unit

DAO_MCLK period Tdaomclk 20 - ns

DAO_MCLK duty cycle - 45 55 %

DAO_SCLK period for Master or Slave mode1

1. Mas ter mode tim ing specifications are characterized, not production tested.

Tdaosclk 20 - ns

DAO_SCLK duty cycle for Master or Slave mode1-4060%

Master Mode (Output A1 Mode)1,2

2. Master mode is defined as the CS47048 driving both DAO_SCLK, DAO_LRCLK. When MCLK is an input, it

is divided to produce DAO_SCLK, DAO_LRCLK.

DAO_SCLK delay from DAO_MCLK rising edge,

DAO_MCLK as an input tdaomsck -19ns

DAO_L RCLK to DAO_S CLK non- active edge3, Se e Figure 9 A.

3. The DAO_LRCLK transition may occur on either side of the non-active edge of DAO_LRCLK. The active edge

of DAO_SCLK is the point at which the data is valid.

tdaomlrts -8ns

DAO_SCLK non-active edge3 to DAO_LRCLK, See Figure 9B tdaomstlr -8ns

DAO_DATA[3..0] delay from DAO_SCLK non-active edge3tdaomdv -8ns

Slave Mode (Output A0 Mode)4

4. Slave mode is defined as DAO_SCLK, DAO_LRCLK driven by an external source.

DAO_LRCLK to DAO_SCLK non-active edge3, See Figure 10A. tdaoslrts -15ns

DAO_SCLK non-active edge3 to DAO_LRCLK, See Figure 10B.

.tdaosstlr -30ns

DAO1_DATA[3..0] delay from DAO_SCLK non-active edge3tdaosdv -8ns

AO_MCLK

AO_SCLK

AO_LRCLK

AO_DATAn

tdaomsck

tdaomlrts

tdaomd

tdaomclk

AO_MCLK

AO_SCLK

AO_LRCLK

AO_DATAn

tdaomclk

tdaomstlr

tdaomdv

tdaomsck

A. DAO_LRCLK trans ition before DAO_SCLK non-active

edge. See Footnote 3 on page 22. B. DAO_LRCLK transition after DAO_SCLK non-active

edge. See Footnote 3 on page 22.

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Figure 10. Digital Audio Output Port Timing, Slave Mode

5.15 Digital Switching Characteristi cs — S/P DIF RX Por t

(Inputs: Logic 0 = VIL, Logic 1 = VIH; C L = 20 pF)

Parameter Symbol Min Typ Max Units

PLL Clock Recovery Sample Rate Range 30 - 200 kHz

AO_SCLK

DAO_LRCLK

DAO_DATAn

tdaosstlr

tdaosclk

tdaosdv

AO_SCLK

AO_LRCLK

tdaoslrts

tdaosdv

AOn_DATAn

tdaosclk

A. DAO_LRCLK transition before DAO_SCLK

non-active edge. See Footnote 3 on page 22. B. DAO_LRCLK transition after DAO_SCLK non-

active edge. See Footnote 3 on page 22.

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5.16 ADC Characteristic s

5.16.1 Analog Input Characteristics (Commercial)

(Test Conditions (unless otherwise specified): TA= 0 to +70°C; VDD = 1.8 V±5%, VDDA (VA)= 3.3 V±5%; 1 kHz

sine wave driven through the passive input filter (Ri=10kΩ) in Figure 11 on page 26 or Figure 12 on page 26; DSP

running test application; Measurement Bandwidth is 10 Hz to 20 kHz.)

Differential Single-Ended

Parameter Min Typ Max Min Typ Max Unit

Fs= 96 kHz, 192 kHz

Dynamic Range1,6,7 A-weighted

unweighted

40 kHz bandwidth unweighted

105

102

93 102

Total Harmonic Distortion + Noise6,7 -1 dB

-20 dB

-60 dB

40 kHz bandwidth -1 dB

-98

-82

-42

-90

-92

-95

-79

-39

-90

-89

AIN_1A/B Inte rc hannel Isol ati on - 95 - - 95 - dB

AIN_[2..6]A/B MUX Interchannel Isolation - 95 - - 95 - dB

DC Accuracy

Interchannel Gain Mismatch - 0.1 - - 0.1 - dB

Gain Drift - ±120 - - ±120 - ppm/°C

Analog Input

Full-Scale Input Voltage2,3 3.3•VA 3.5•VA 3.7•VA 1.65•VA 1.75•VA 1.85•VA VPP

Differential Input Impedance4- 400 - - - - Ω

Single-Ended Input Impedance5----200-Ω

Common Mode Rejection Ratio (CMRR)8-60- - - -dB

Parasitic Load Capacitance (CL)9--20--20pF

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5.16.2 Analog Input Characteristics (Automotive)

(Tes t Cond ition s (unl ess oth erwis e spec ified ): TA= -40 to +85°C; VDD = 1.8 V±5%, VDDA (VA)= 3.3 V±5%; 1 kHz

sine wave driven through the passive input filter (Ri=10kΩ) in Figure 11 on page 26 or Figure 12 on page 26; DSP

running test application; Measurement Bandwidth is 10 Hz to 20 kHz.)

Notes:

1. dB units referred to the typical full-scale voltage.

2. These full-scale values wer e measured with Ri=10k for both the single-ended and differential mode input circuits.

3. The full-scale voltage can be changed be scaling Ri.

Differential Full-Scale (Vpp) = (Ri+200)/(10k+200)*3.5*VDDA

Single-Ended Full-Scale (Vpp) = (Ri+200)/(10k+200)*1.75*VDDA

4. Measured between AIN_xx+ and AN_xx-.

5. Measured between AIN_xx+ and AGND.

6. Decreasing Full-Scale voltage by reducing Ri will cause the noise floor to increase.

7. Common mode input current should be kept to less than +/- 160uA to avoid performance degradation: |(Iip+Iin)/2| <

160uA. This corresponds to +/- 1.6V for Ri=10kΩ in the differential case.

8. This number was measured using perfectly matched external resistors (Ri). Mismatch in the external resistors will

typically reduce CMRR by 20 log (|ΔRi|/Ri + 0.001).

9. CL represents the parasitic load capacitance between Ri on the input circuit and the input pin of the CS47048

package.

Differential Single-Ended

Parameter Min Typ Max Min Typ Max Unit

Fs=96 kHz, 192 kHz

Dynamic Range1,6,7 A-weighted

unweighted

40 kHz bandwidth unweighted

105

102

91 102

Total Harmonic Distortion + Noise6,7 -1 dB

-20 dB

-60 dB

40 kHz bandwidth -1 dB

-98

-82

-42

-90

-95

-79

-39

-90

-87

AIN_1A/B Inte rc hannel Isol ati on - 95 - - 95 - dB

AIN_[2..6]A/B MUX Interchannel Isolation - 95 - - 95 - dB

DC Accuracy

Interchannel Gain Mismatch - 0.1 - - 0.1 - dB

Gain Drift - ±120 - - ±120 - ppm/°C

Analog Input

Full-Scale Input Voltage2,3 3.24•VA 3.5•VA 3.76•VA 1.62•VA 1.75•VA 1.88•VA VPP

Differential Input Impedance4- 400 - - - - Ω

Single-Ended Input Impedance5----200-Ω

Common Mode Rejection Ratio (CMRR)8-60- - - -dB

Parasitic Load Capacitance (CL)9--20--20pF

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Figure 11. ADC Single-Ended Input Test Circuit

Figure 12. ADC Differential Input Test Circuit

10µF

100K

AIN_xA+

AIN_xB+

10µF

IN+

100K

10µF

AIN-

100K

AIN_xA-

AIN_xB-

AIN_xA+

AIN_xB+

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5.16.3 ADC Digital Filter Chara cteristics

Notes:

1. Filter response is guaranteed by design.

2. Response is clock-dependent and will scale with Fs.

5.17 DAC Characteristic s

5.17.1 Analog Output Characteristics (Commercial)

(Test Conditions (unless otherwise specified): TA= 0 to +70°C; VDD = 1.8V±5%, VDDA(VA) = 3.3V±5%; 1 kHz

sine wave driven through a filter shown in Figu re 13 o n p age 2 8 or Figure 14 on page 29; DSP running test applica-

tion; Measurement Bandwidth is 20 Hz to 20 kHz.)

Parameter1, 2 Min Typ Max Unit

Fs = 96 kHz, 192 kHz

Passband (Frequency Response) to -0.1 dB corner 0 - 0.4896 Fs

Passband Ripple - - 0.08 dB

Stopband 0.5688 - - Fs

Stopband Attenuation 70 - - dB

Total Group Delay - 12/Fs - s

High-Pass Filter Characteristics

Frequency Response -3.0 dB

-0.13 dB -1

20 -

-Hz

Phas e Deviat ion @ 20 Hz - 10 - Deg

Passband Ripple - - 0 dB

Filter Settling Time - 105/Fs 0 s

Parameter Differential

Min Typ Max Single-Ended

Min Typ Max Unit

Fs = 96 kHz

Dynamic Range A-weighted

unweighted 102

99 108

105 -

-99

96 105

102 -

-dB

Total Harmonic Distortion + Noise

0 dB

-20 dB

-60 dB

-98

-88

-48

-90

-95

-85

-45

-87

Interchannel Isolation (1 kHz) - 95 - - 95 - dB

Analog Output

Full-Scale Output TBD 1.35•VA TBD TBD 0.68•VA TBD VPP

Interchannel Gain Mismatch - 0.1 - - 0.1 - dB

Gain Drift - ±120 - - ±120 - ppm/°C

Output Impedance - 100 - - 100 - Ω

DC Current draw from an AOUT pin1- - 10 - - 10 μA

AC-Load Res is tance (RL)23--3--kΩ

Load Capacitance (CL)2- - 100 - - 100 pF

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5.17.2 Analog Output Charact eristics (Automotive)

(Test Conditions (unless otherwise specified): TA= -40 to +85°C; VDD = 1.8V±5%, VDDA(VA) = 3.3V±5%; 1 kHz

sine wave driven through a filter shown in Figu re 13 o n p age 2 8 or Figure 14 on page 29; DSP running test applica-

tion; Measurement Bandwidth is 20 Hz to 20 kHz.)

Notes:

1. Guaranteed by design. The DC current draw represents the allowed current draw from the AOUT pin due to typical

leakage through the electrolytic DC-blocking capacitors.

2. Guarante ed by des ig n. RL and CL reflect the recommended minimum resistance and maximum capacitance

required for the internal op-amp's stability and signal integrity. In this circuit topology, CL represents any capacitive

loading that appears before the 560 Ω seri es re sistor (typical ly p aras itic), and wi ll ef fec tivel y mov e the domi nant p ole

of the two-pole amp in the output stage. Increasing this value beyond the recommended 100 pF can cause the

internal op-amp to become unstable.

Figure 13. DAC Single-Ended Output Test Circuit

Parameter Differential

Min Typ Max Single-Ended

Min Typ Max Unit

Fs = 96 kHz

Dynamic Range A-weighted

unweighted 100

97 108

105 -

-97

94 105

102 -

-dB

Total Harmonic Distortion + Noise

0 dB

-20 dB

-60 dB

-98

-88

-48

-90

-95

-85

-45

-87

Interchannel Isolation (1 kHz) - 95 - - 95 - dB

Analog Output

Full-Scale Output TBD 1.35•VA TBD TBD 0.68•VA TBD VPP

Interchannel Gain Mismatch - 0.1 - - 0.1 - dB

Gain Drift - ±120 - - ±120 - ppm/°C

Output Impedance - 100 - - 100 - Ω

DC Current draw from an AOUT pin1--10--10μA

AC-Load Res is tance (RL)23--3--kΩ

Load Capacitance (CL)2- - 100 - - 100 pF

AOUT_x+

3.3 µF

CLRL

AOU

2200pF

560

10k

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Figure 14. DAC Differential Output Test Circuit

Figure 15. Maximum Loading

5.17.3 Combined DAC Interpolation & On-chip Analog Filter Response

Parameter Min Typ Max Unit

Passband (Frequency Response) to 0.22 dB corner

to -3 dB cor ner 0

-0.4125

0.4979 Fs

Frequency Response 10 Hz to 20 kHz -0.02 - +0.02 dB

StopBand 0.5465 - - Fs

StopBand Attenuation 100 - - dB

Group Delay - 10/Fs - s

N outpu t: RL = 4.87k + ( [2πF*1800-12 ]-1 || ((2.43k + [2πF*470-12 ]-1 ) || 4.87k ))

AOU

AOUT_x+

AOUT_x- 1.96k

CL4700pF 1200pF

1.96k

22µF

953

4.87k 2.43k -

560

1800pF 470pF

4.87k

22µF

P output: RL = 1.96k + ( [2 πF*4700-12 ]-1 || (1.96k + [2πF*22-6 ]-1 ) || (953 + [2πF*1200-12 ]-1 ))

CL10k

100

2.5

51015

Safe Operatin g

Region

Capacitive Load -- C (pF)

Resistive Load -- R (k

)

125

320

CS47048 Data Sheet

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6. Ordering Information

The CS47048 DSP part numbers are described as follows:

CS47048I-XYZR

where

I - ROM ID Letter

X - Product Grade

Y - Package Type

Z - Lead (Pb) Free

R - Tape and Reel Packaging

NOTE: Please contact the factory for availability of the -D (automotive grade) package.

7. Environmental, Manufacturing, & Handling Information

* MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020.

Table 4. Ordering Information

Part No. Grade Temp. Range Package

CS47048B-CQZ Commercial 0 to +70 °C 100-pin LQFP

CS47048B-DQZ Automotive -40 to +85 °C

Table 5. Environmental, Manufacturing, & Handling Information

Model Number Peak Reflow Temp MSL Rating* Max Floor Life

CS47048B-CQZ 260 °C 3 7 days

CS47048B-DQZ

CS47048 Data Sheet

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8. Device Pinout Diagram

8.1 CS47048, 100-Pin LQFP Pinout Diagram

Figure 16. CS47048 Pinout Diagram

9. 100-pin LQFP with Exposed Pad Package Drawing

Figure 17 shows the CS47048 100-pin LQFP package with exposed pad.

VDD1

GND2

VDDIO1

GNDIO1

VDD2

GND1

GPIO1, DA I_D AT A2, TM2

GPIO2, DAI_DATA3, TM3, SPDIF RX

GPIO16, DAI_DATA0, TM0

GPIO0, DAI_DATA1, TM1

PIO5, DAO_DATA3, HS3, S/PD IF TXa

GPIO3, DAO_DATA1, HS1

GPIO6, DAO_DATA0, HS0

GPIO7, DAO_LRCLK

GPIO15, DAI_LRCLK

GPIO18, DAO_MCLK, HS4

GPIO17, DAI_SCLK

GPIO14, DAO_SCLK

PIO4, DAO_DATA2 , HS2, S/PDIF TXb

VDDIO2

GNDIO2

DBDA

DBCK

CS47048

100-Pi n LQ F P

GPIO10, SCP_MISO, SCP_SDA

GPIO9, SCP_MOSI

PIO8, SCP_CS, DAI_DATA4

GPIO12, SCP_IRQ

GPIO13, SCP_BSY, EE_CS

GNDIO3

GND_SUB

XTAL_OUT

GND3

XTI

XTO

GNDA_PLL

PLL_REF_RES

AIN_6B-

AIN_6B+

AIN_5B-

AIN_5B+

GPIO11, SCP_CLK

VDDIO3

VDD3

VDDA_PLL

AIN_4B-

AIN_4B+

AIN_3B-

AIN_3B+

AIN_2B-

AIN_2B+

AIN_1B-

AIN_5A-

BIASREF_DAC

AIN_5A+

VDDA3

AIN_1A-

AIN_1B+

GNDA3

AIN_1A+

AIN_4A-

AIN_3A-

AIN_3A+

BIASREF_ADC

VDD_ADC_MO

AIN_2A-

REXT

VDDA2

AIN_4A+

AIN_2A+

GNDA2

GND_DAC

VDD_DAC

AIN_6A-

AIN_6A+

100

AOUT_1

VDDA7

AOUT_2

AOUT_3

GNDA6

AOUT_4

AOUT_5

VDDA5

GNDA5

AOUT_6

RESET

GNDA7

VDDA6

AOUT_5

AOUT_7

VDDA4

GNDA4

AOUT_8

CS47048 Data Sheet

Audio SOC Processor Family

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Figure 17. 100-Pin LQFP Package Drawing

CS47048 Data Sheet

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10. Para meter Definitions

10.1 Dynamic Range

The ratio of the RMS value of the signal to the RMS sum of all other spectral components over the

specified bandwidth. Dynamic Range is a signal-to-noise ratio measurement over the specified

bandwidth made with a -60 dBFS signal. 60 dB is added to resulting measurement to refer the

measurement to full-scale. This technique ensures that the distortion components are below the

noise level and do not affect the measurement. This measurement technique has been accepted

by the Audio Engineering Society, AES17-1991, and the Electronic Industries Association of

Japan, EIAJ CP-307. Expressed in decibels.

10.2 Total Harmonic Distortion + Noise

The ratio of the RMS value of the signal to the RMS sum of all other spectral components over the

specified bandwidth (typically 10 Hz to 20 kHz), including distortion components. Expressed in

decibels. Measured at -1 and -20 dBFS as suggested in AES17-1991 Annex A.

10.3 Freque ncy Response

A measure of the amplitude response variation from 10 Hz to 20 kHz relative to the amplitude

response at 1 kHz. Units in decibels.

10.4 Interchannel Isolation

A measure of crosstalk between the left and right channels. Measured for each channel at the

converter's output with no signal to the input under test and a full-scale signal applied to the other

channel. Units in decibels.

10.5 Interchannel Gain Mismatch

The gain difference between left and right channel s. Units in decibel s.

10.6 Gain Error

The deviation from the nominal full-scale analog output for a full-scale digital input.

10.7 Gain Drift

The change in gain value with temperature. Units in ppm/°C.

11. Revision History

Revision Date Changes

A7 October 16, 2008 Initial Release

CS47048 Data Sheet

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