LTC1595/LTC1596/LTC1596-1
1
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Typical applicaTion
FeaTures DescripTion
Serial 16-Bit
Multiplying DACs
The LTC
®
1595/LTC1596/LTC1596-1 are serial input, 16-bit
multiplying current output DACs. The LTC1595 is pin and
hardware compatible with the 12-bit DAC8043 and comes
in 8-pin PDIP and SO packages. The LTC1596 is pin and
hardware compatible with the 12-bit DAC8143/AD7543
and comes in the 16-pin SO wide package.
Both are specified over the industrial temperature range.
Sensitivity of INL to op amp VOS is reduced by five times
compared to the industry standard 12-bit DACs, so most
systems can be easily upgraded to true 16-bit resolution
and linearity without requiring more precise op amps.
These DACs include an internal deglitching circuit that
reduces the glitch impulse by more than ten times to less
than 1nV-s typ.
The DACs have a clear input and a power-on reset. The
LTC1595 and LTC1596 reset to zero-scale. The LTC1596-1
is a version of the LTC1596 that resets to mid-scale.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
applicaTions
n SO-8 Package (LTC1595)
n DNL and INL: 1LSB Max
n Low Glitch Impulse: 1nV-s Typ
n Fast Settling to 1LSB: 2µs (with LT1468)
n Pin Compatible with Industry Standard
12-Bit DACs: DAC8043 and DAC8143/AD7543
n 4-Quadrant Multiplication
n Low Supply Current: 10µA Max
n Power-On Reset
LTC1595/LTC1596: Resets to Zero-Scale
LTC1596-1: Resets to Mid-Scale
n 3-Wire SPI and MICROWIRE Compatible
Serial Interface
n Daisy-Chain Serial Output (LTC1596)
n Asynchronous Clear Input
LTC1596: Clears to Zero-Scale
LTC1596-1: Clears to Mid-Scale
n Process Control and Industrial Automation
n Software Controlled Gain Adjustment
n Digitally Controlled Filter and Power Supplies
n Automatic Test Equipment
Integral Nonlinearity
SO-8 Multiplying 16-Bit DAC Has Easy 3-Wire Serial Interface
VDD VREF
LTC1595
RFB
GND
4
7
6
5
8
5V
V
IN
CLOCK
DATA
LOAD
CLK
SRI
LD
12
3
OUT1
33pF
VOUT
1595/96 TA01
–
+
LT®1468
DIGITAL INPUT CODE
0
–1.0
INTEGRAL NONLINEARITY (LSB)
–0.6
–0.8
–0.4
0.4
0.6
0.8
1.0
–0.2
0.2
0
16384 32768
1595/96 TA02
49152 65535
LTC1595/LTC1596/LTC1596-1
2
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absoluTe MaxiMuM raTings
VDD to AGND ............................................... –0.5V to 7V
VDD to DGND............................................... –0.5V to 7V
AGND to DGND ........................................... VDD + 0.5V
DGND to AGND ............................................VDD + 0.5V
VREF to AGND, DGND ..............................................±25V
RFB to AGND, DGND ................................................±25V
Digital Inputs to DGND ............... –0.5V to (VDD + 0.5V)
(Note 1)
1
2
3
4
TOP VIEW
S8 PACKAGE
8-LEAD PLASTIC SO
N8 PACKAGE
8-LEAD PDIP
8
7
6
5
VREF
RFB
OUT1
GND
VDD
CLK
SRI
LD
TJMAX = 150°C, θJA = 130°C/W (N)
TJMAX = 150°C, θJA = 190°C/W (S)
1
2
3
4
5
6
7
8
TOP VIEW
SW PACKAGE
16-LEAD PLASTIC SO WIDE
16
15
14
13
12
11
10
9
OUT1
OUT2
AGND
STB1
LD1
SRO
SRI
STB2
RFB
VREF
VDD
CLR
DGND
STB4
STB3
LD2
TJMAX = 150°C, θJA = 100°C/W (N)
TJMAX = 150°C, θJA = 130°C/W (SW)
pin conFiguraTion
VOUT1, VOUT2 to AGND ................. –0.5V to (VDD + 0.5V)
Maximum Junction Temperature .......................... 150°C
Operating Temperature Range
LTC1595C/LTC1596C/LTC1596-1C .......... 0°C to 70°C
LTC1595I/LTC1596I/LTC1596-1I ......... –40°C to 85°C
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec) .................. 300°C
LTC1595/LTC1596/LTC1596-1
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LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC1595ACN8#PBF LTC1595ACN8#TRPBF LTC1595ACN8 8-Lead PDIP 0°C to 70°C
LTC1595ACS8#PBF LTC1595ACS8#TRPBF 1595A 8-Lead Plastic SO 0°C to 70°C
LTC1595BCN8#PBF LTC1595BCN8#TRPBF LTC1595BCN8 8-Lead PDIP 0°C to 70°C
LTC1595BCS8#PBF LTC1595BCS8#TRPBF 1595B 8-Lead Plastic SO 0°C to 70°C
LTC1595CCN8#PBF LTC1595CCN8#TRPBF LTC1595CCN8 8-Lead PDIP 0°C to 70°C
LTC1595CCS8#PBF LTC1595CCS8#TRPBF 1595C 8-Lead Plastic SO 0°C to 70°C
LTC1595AIN8#PBF LTC1595AIN8#TRPBF LTC1595AIN8 8-Lead PDIP –40°C to 85°C
LTC1595AIS8#PBF LTC1595AIS8#TRPBF 1595AI 8-Lead Plastic SO –40°C to 85°C
LTC1595BIN8#PBF LTC1595BIN8#TRPBF LTC1595BIN8 8-Lead PDIP –40°C to 85°C
LTC1595BIS8#PBF LTC1595BIS8#TRPBF 1595BI 8-Lead Plastic SO –40°C to 85°C
LTC1595CIN8#PBF LTC1595CIN8#TRPBF LTC1595CIN8 8-Lead PDIP –40°C to 85°C
LTC1595CIS8#PBF LTC1595CIS8#TRPBF 1595CI 8-Lead Plastic SO –40°C to 85°C
LTC1596ACSW#PBF LTC1596ACSW#TRPBF LTC1596ACSW 16-Lead Plastic SO Wide 0°C to 70°C
LTC1596BCSW#PBF LTC1596BCSW#TRPBF LTC1596BCSW 16-Lead Plastic SO Wide 0°C to 70°C
LTC1596CCSW#PBF LTC1596CCSW#TRPBF LTC1596CCSW 16-Lead Plastic SO Wide 0°C to 70°C
LTC1596AISW#PBF LTC1596AISW#TRPBF LTC1596AISW 16-Lead Plastic SO Wide –40°C to 85°C
LTC1596BISW#PBF LTC1596BISW#TRPBF LTC1596BISW 16-Lead Plastic SO Wide –40°C to 85°C
LTC1596CISW#PBF LTC1596CISW#TRPBF LTC1596CISW 16-Lead Plastic SO Wide –40°C to 85°C
LTC1596-1ACSW#PBF LTC1596-1ACSW#TRPBF LTC1596-1ACSW 16-Lead Plastic SO Wide 0°C to 70°C
LTC1596-1BCSW#PBF LTC1596-1BCSW#TRPBF LTC1596-1BCSW 16-Lead Plastic SO Wide 0°C to 70°C
LTC1596-1CCSW#PBF LTC1596-1CCSW#TRPBF LTC1596-1CCSW 16-Lead Plastic SO Wide 0°C to 70°C
LTC1596-1AISW#PBF LTC1596-1AISW#TRPBF LTC1596-1AISW 16-Lead Plastic SO Wide –40°C to 85°C
LTC1596-1BISW#PBF LTC1596-1BISW#TRPBF LTC1596-1BISW 16-Lead Plastic SO Wide –40°C to 85°C
LTC1596-1CISW#PBF LTC1596-1CISW#TRPBF LTC1596-1CISW 16-Lead Plastic SO Wide –40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
orDer inForMaTion
LTC1595/LTC1596/LTC1596-1
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elecTrical characTerisTics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VDD = 5V ±10%, VREF = 10V, VOUT1 = VOUT2 = AGND = 0V, TA = TMIN to
TMAX, unless otherwise noted.
LTC1595A/96A/96-1A LTC1595B/96B/96-1B LTC1595C/96C/96-1C
SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
Accuracy
Resolution l16 16 16 Bits
Monotonicity l16 16 15 Bits
INL Integral Nonlinearity (Note 2) TA = 25°C
TMIN to TMAX
l
±0.25
±0.35
±1
±1
±2
±2
±4
±4
LSB
LSB
DNL Differential
Nonlinearity
TA = 25°C
TMIN to TMAX
l
±0.2
±0.2
±1
±1
±1
±1
±2
±2
LSB
LSB
GE Gain Error (Note 3) TA = 25°C
TMIN to TMAX
l
2
3
±16
±16
±16
±32
±32
±32
LSB
LSB
VDD = 5V ±10%, VREF = 10V, VOUT1 = VOUT2 = AGND = 0V, TA = TMIN to TMAX, unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Gain Temperature Coefficient (Note 4) ∆Gain/∆Temperature l1 2 ppm/°C
ILEAKAGE OUT1 Leakage Current (Note 5) TA = 25°C
TMIN to TMAX
l
±3
±15
nA
nA
Zero-Scale Error TA = 25°C
TMIN to TMAX
l
±0.2
±1
LSB
LSB
PSRR Power Supply Rejection VDD = 5V ±10% l±1 ±2 LSB/V
Reference Input
RREF VREF Input Resistance (Note 6) l5 7 10 kΩ
AC Performance
Output Current Settling Time (Notes 7, 8) 1 µs
Mid-Scale Glitch Impulse Using LT1122 Op Amp, CFEEDBACK = 33pF 1 nV-s
Digital-to-Analog Glitch Impulse Full-Scale Transition, VREF = 0V,
Using LT1122 Op Amp, CFEEDBACK = 33pF
2 nV-s
Multiplying Feedthrough Error VREF = ±10V, 10kHz Sine Wave 1 mVP-P
THD Total Harmonic Distortion (Note 9) 108 dB
Equivalent DAC Thermal Noise Voltage Density (Note 10) f = 1kHz 11 nV/√Hz
Analog Outputs (Note 4)
COUT Output Capacitance (Note 4) DAC Register Loaded to All 1s, COUT1 l115 130 pF
DAC Register Loaded to All 0s, COUT1 l70 80 pF
Digital Inputs
VIH Digital Input High Voltage l2.4 V
VIL Digital Input Low Voltage l0.8 V
IIN Digital Input Current l0.001 ±1 µA
CIN Digital Input Capacitance (Note 4) VIN = 0V l8 pF
Digital Outputs: SRO (LTC1596/LTC1596-1)
VOH Digital Output High Voltage IOH = 200µA l4 V
VOL Digital Output Low Voltage IOL = 1.6mA l0.4 V
LTC1595/LTC1596/LTC1596-1
5
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elecTrical characTerisTics
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: ±1LSB = ±0.0015% of full-scale = ±15.3ppm of full-scale.
Note 3: Using internal feedback resistor.
Note 4: Guaranteed by design, not subject to test.
Note 5: IOUT1 with DAC register loaded with all 0s.
Note 6: Typical temperature coefficient is 100ppm/°C.
Note 7: OUT1 load = 100Ω in parallel with 13pF.
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VDD = 5V ±10%, VREF = 10V, VOUT1 = GND = 0V, TA = TMIN to TMAX, unless
otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Timing Characteristics (LTC1595)
tDS Serial Input to CLK Setup Time l30 5 ns
tDH Serial Input to CLK Hold Time l30 5 ns
tSRI Serial Input Data Pulse Width l60 ns
tCH Clock Pulse Width High l60 ns
tCL Clock Pulse Width Low l60 ns
tLD Load Pulse Width l60 ns
tASB LSB Clocked into Input Register to DAC Register Load Time l0 ns
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Timing Characteristics (LTC1596/LTC1596-1)
tDS1 Serial Input to Strobe Setup Time STB1 Used as the Strobe l30 5 ns
tDS2 STB2 Used as the Strobe l20 –5 ns
tDS3 STB3 Used as the Strobe l25 0 ns
tDS4 STB4 Used as the Strobe l20 –5 ns
tDH1 Serial Input to Strobe Hold Time STB1 Used as the Strobe l30 5 ns
tDH2 STB2 Used as the Strobe l40 15 ns
tDH3 STB3 Used as the Strobe l35 10 ns
tDH4 STB4 Used as the Strobe l40 15 ns
tSRI Serial Input Data Pulse Width l60 ns
tSTB1 to tSTB4 Strobe Pulse Width (Note 11) l60 ns
tSTB1 to tSTB4 Strobe Pulse Width (Note 12) l60 ns
tLD1, tLD2 LD Pulse Width l60 ns
tASB LSB Strobed Into Input Register to Load DAC
Register Time
l0 ns
tCLR Clear Pulse Width l100 ns
tPD1 STB1 to SRO Propagation Delay CL = 50pF l30 150 ns
tPD STB2, STB3, STB4 to SRO Propagation Delay CL = 50pF l30 200 ns
Power Supply
VDD Supply Voltage l4.5 5 5.5 V
IDD Supply Current Digital Inputs = 0V or VDD l1.5 10 µA
VDD = 5V ±10%, VREF = 10V, VOUT1 = VOUT2 = AGND = 0V, TA = TMIN to TMAX, unless otherwise noted.
Note 8: To 0.0015% for a full-scale change, measured from the falling
edge of LD1, LD2 or LD.
Note 9: VREF = 6VRMS at 1kHz. DAC register loaded with all 1s;
op amp = LT1007.
Note 10: Calculation from en = √4kTRB where: k = Boltzmann constant
(J/°K); R = resistance (Ω); T = temperature (°K); B = bandwidth (Hz).
Note 11: Minimum high time for STB1, STB2, STB4. Minimum low time
for STB3.
Note 12: Minimum low time for STB1, STB2, STB4. Minimum high time
for STB3.
LTC1595/LTC1596/LTC1596-1
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Typical perForMance characTerisTics
Mid-Scale Glitch Impulse Integral Nonlinearity (INL) Differential Nonlinearity (INL)
Differential Nonlinearity
vs Reference Voltage
Full-Scale Settling Waveform
Integral Nonlinearity
vs Reference Voltage
Differential Nonlinearity
vs Supply Voltage
Multiplying Mode Frequency
Response vs Digital Code
Integral Nonlinearity
vs Supply Voltage
TIME (s)
01234
OUTPUT VOLTAGE (mV)
0
1595/96 G01
–10
+10
1nV-s TYP
USING LT1122 OP AMP
CFEEDBACK = 33pF
VREF = 10V
LD FALLING EDGE
DIGITAL INPUT CODE
0
–1.0
INTEGRAL NONLINEARITY (LSB)
–0.8
–0.4
–0.2
0
1.0
0.4
16384 32768 65535
1595/96 G02
–0.6
0.6
0.8
0.2
49152
DIGITAL INPUT CODE
0
–1.0
DIFFERENTIAL NONLINEARITY (LSB)
–0.8
–0.4
–0.2
0
1.0
0.4
16384 32768
1595/96 G03
–0.6
0.6
0.8
0.2
49152 65535
1µs/DIV
USING LT1122 OP AMP
CFEEDBACK = 33pF
1595/96 G04
DAC
OUTPUT
5V/DIV
GATED
SETTLING
WAVEFORM
500µV/DIV
REFERENCE VOLTAGE (V)
–10
INTEGRAL NONLINEARITY (LSB)
0.5
6
1595/96 G05
0–6 –2 010
1.0
2
–8 –4 8
4
REFERENCE VOLTAGE (V)
–10
DIFFERENTIAL NONLINEARITY (LSB)
0.5
6
1595/96 G06
0–6 –2 010
1.0
2
–8 –4 8
4
FREQUENCY (Hz)
100
ATTENUATION (dB)
–60
–40
–20
0
1M
1595/96 G07
–80
–100
–120 1k 10k 100k 10M
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
ALL
BITS OFF
ALL
BITS
ON
USING LT1122 OP AMP
CFEEDBACK = 33pF
SUPPLY VOLTAGE (V)
2
0
INTEGRAL NONLINEARITY (LSB)
1
2
467
1595/96 G08
3 5 8910
VREF = 10V
VREF = 2.5V
SUPPLY VOLTAGE (V)
2
0
DIFFERENTIAL NONLINEARITY (LSB)
0.5
1.0
467
1595/96 G09
3 5 8910
LTC1595/LTC1596/LTC1596-1
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Typical perForMance characTerisTics
Supply Current
vs Logic Input Voltage
Logic Threshold
vs Supply Voltage
INPUT VOLTAGE (V)
0
SUPPLY CURRENT (mA)
0.6
0.8
1.0
4
1595/96 G10
0.4
0.2
0.5
0.7
0.9
0.3
0.1
01235
VDD = 5V
SUPPLY VOLTAGE (V)
0
LOGIC THRESHOLD (V)
1.0
2.0
3.0
0.5
1.5
2.5
1595/96 G11
100 51 62 73 84 9
pin FuncTions
LTC1595
VREF (Pin 1): Reference Input.
RFB (Pin 2): Feedback Resistor. Normally tied to the output
of the current to voltage converter op amp.
OUT1 (Pin 3): Current Output Pin. Tie to inverting input
of current to voltage converter op amp.
GND (Pin 4): Ground Pin.
LD (Pin 5): The Serial Interface Load Control Input. When
LD is pulled low, data is loaded from the shift register into
the DAC register, updating the DAC output.
SRI (Pin 6): The Serial Data Input. Data on the SRI pin
is latched into the shift register on the rising edge of the
serial clock. Data is loaded MSB first.
CLK (Pin 7): The Serial Interface Clock Input.
VDD (Pin 8): The Positive Supply Input. 4.5V ≤ VDD ≤ 5.5V.
Requires a bypass capacitor to ground.
LTC1596/LTC1596-1
OUT1 (Pin 1): True Current Output Pin. Tie to inverting
input of current to voltage converter op amp.
OUT2 (Pin 2): Complement Current Output Pin. Tie to
analog ground.
AGND (Pin 3): Analog Ground Pin.
STB1, STB2, STB3, STB4 (Pins 4, 8, 10, 11): Serial
Interface Clock Inputs. STB1, STB2 and STB4 are rising
edge triggered inputs. STB3 is a falling edge triggered
input (see Truth Tables).
LD1, LD2 (Pins 5, 9): Serial Interface Load Control Inputs.
When LD1 and LD2 are pulled low, data is loaded from
the shift register into the DAC register, updating the DAC
output (see Truth Tables).
SRO (Pin 6): The Output of the Shift Register. Becomes
valid on the active edge of the serial clock.
SRI (Pin 7): The Serial Data Input. Data on the SRI pin
is latched into the shift register on the active edge of the
serial clock. Data is loaded MSB first.
DGND (Pin 12): Digital Ground Pin.
CLR (Pin 13): The Clear Pin for the DAC. Clears DAC to
zero-scale when pulled low on LTC1596. Clears DAC to
mid-scale when pulled low on LTC1596-1. This pin should
be tied to VDD for normal operation.
VDD (Pin 14): The Positive Supply Input. 4.5V ≤ VDD ≤
5.5V. Requires a bypass capacitor to ground.
VREF (Pin 15): Reference Input.
RFB (Pin 16): Feedback Resistor. Normally tied to the output
of the current to voltage converter op amp.
LTC1595/LTC1596/LTC1596-1
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Table 1. LTC1596/LTC1596-1 Input Register
CONTROL INPUTS
STB1 STB2 STB3 STB4 INPUT REGISTER AND SRO OPERATION
0 1 0 Serial Data Bit on SRI Loaded Into Input
Register, MSB First
Data Bit or SRI Appears on SRO Pin After
16 Clocked Bits
0 1 0
0 0 0
0 0 1
1 X X X No Input Register Operation
No SRO Operation
X 1 X X
X X 0 X
X X X 1
TruTh Tables
Table 2. LTC1596/LTC1596-1 DAC Register
CONTROL INPUTS
CLR LD1 LD2 DAC Register Operation
0 X X Reset DAC Register and Input Register to
All 0s (LTC1596) or to Mid-Scale (LTC1596-1)
(Asynchronous Operation)
1 1 X No DAC Register Operation
1 X 1
1 0 0 Load DAC Register with the Contents of Input
Register
block DiagraM
(LTC1595)
112k 7k
112k
56k
112k
56k
112k56k56k56k
DECODER
D15
(MSB) D13
D14 D12 D11 D0
(LSB)
CLK IN
LOAD
VDD
VREF RFB
OUT1
GND
SRI
6
1595 BD
DAC REGISTER
56k56k56k56k
INPUT 16-BIT SHIFT REGISTER
5
8
1
LD
7
CLK
4
3
2
• ••
TiMing DiagraM
(LTC1595)
SRI
LD
PREVIOUS
WORD D15
MSB D14 D1
1595 TD
D0
LSB
tDS tDH
tCH
tSRI
tASB
tCL
tLD
CLK INPUT
LTC1595/LTC1596/LTC1596-1
9
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block DiagraM
(LTC1596/LTC1596-1)
112k 7k
112k
56k
112k
56k
112k56k56k56k
DECODER
D15
(MSB) D13
D14 D12 D11 D0
(LSB)
CLR
CLK
OUT
CLR
SRO
IN
LOAD
DGND
VDD
VREF RFB
OUT1
OUT2
SRI
7
AGND
1596 BD
DAC REGISTER
56k56k56k56k
INPUT 16-BIT SHIFT REGISTER
9
8
10
12
11
4
6
5
13
14
15
STB1
STB2
STB3
STB4
LD1
CLR
LD2
3
2
1
16
• ••
TiMing DiagraM
(LTC1596/LTC1596-1)
D15
MSB D14 D13 D1
tDS1
tDS2
tDS3
tDS4
tDH1
tDH2
tDH3
tDH4 tSTB1
tSTB2
tSTB3
tSTB4 tSTB1
tSTB2
tSTB3
tSTB4
tASB
tLD1
tLD2
tSRI
D0
LSB
tPD
tPD1
STROBE INPUT
STB1, STB2, STB4
(INVERT FOR STB3)
SRI
SRO
LD1, LD2
1596 TD
D15 (MSB)
PREVIOUS WORD
D14
PREVIOUS WORD
D0 (LSB)
PREVIOUS WORD
D15 (MSB)
CURRENT WORD
D13
PREVIOUS WORD
LTC1595/LTC1596/LTC1596-1
10
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applicaTions inForMaTion
Description
The LTC1595/LTC1596 are 16-bit multiplying DACs which
have serial inputs and current outputs. They use preci-
sion R/2R technology to provide exceptional linearity and
stability. The devices operate from a single 5V supply and
provide ±10V reference input and voltage output ranges
when used with an external op amp. These devices have
a proprietary deglitcher that reduces glitch impulse to
1nV-s over a 0V to 10V output range.
Serial I/O
The LTC1595/LTC1596 have SPI/MICROWIRE compatible
serial ports that accept 16-bit serial words. Data is accepted
MSB first and loaded with a load pin.
The 8-pin LTC1595 has a 3-wire interface. Data is shifted
into the SRI data input on the rising edge of the CLK pin.
At the end of the data transfer, data is loaded into the DAC
register by pulling the LD pin low (see LTC1595 Timing
Diagram).
The 16-pin LTC1596 can operate in identical fashion to the
LTC1595 but offers additional pins for flexibility. Four clock
pins are available STB1, STB2, STB3 and STB4. STB1,
STB2 and STB4 operate like the CLK pin of the LTC1595,
capturing data on their rising edges. STB3 captures data
on its falling edge (see Truth Table 1).
The LTC1596 has two load pins, LD1 and LD2. To load data,
both pins must be taken low. If one of the pins is grounded,
the other pin will operate identically to LTC1595’s LD pin.
An asynchronous clear input (CLR) resets the LTC1596 to
zero-scale (and the LTC1596-1 to mid-scale) when pulled
low (see Truth Table 2).
The LTC1596 also has a data output pin SRO that can be
connected to the SRI input of another DAC to daisy chain
multiple DACs on one 3-wire interface (see LTC1596 Tim-
ing Diagram).
Unipolar (2-Quadrant Multiplying) Mode
(VOUT = 0V to –VREF)
The LTC1595/LTC1596 can be used with a single op amp
to provide 2-quadrant multiplying operation as shown in
Figure 1. With a fixed –10V reference, the circuits shown
give a precision unipolar 0V to 10V output swing.
Figure 1. Unipolar Operation (2-Quadrant Multiplication) VOUT = 0V to –VREF
(a)
(b)
Table 1. Unipolar Binary Code Table
DIGITAL INPUT BINARY NUMBER
IN DAC REGISTER ANALOG OUTPUT VOUT
MSB LSB
1111 1111 1111 1111 –VREF (65,535/65,536)
1000 0000 0000 0000 –VREF (32,768/65,536) = –VREF/2
0000 0000 0000 0001 –VREF (1/65,536)
0000 0000 0000 0000 0V
VDD VREF
LTC1596
RFB
AGNDDGND
3
12
10
4
7
5
6
9
8
11
2
1413
5V
VREF
–10V TO 10V
TO NEXT DAC
FOR DAISY-CHAINING
15 16
1
OUT1
33pF
0.1µF
VOUT
0V TO –VREF
1595/96 F01a
OUT2
–
+
LT1001
CLR
STB3
STB1
SRI
LD1
SRO
LD2
STB2
STB4
µP
VDD VREF
LTC1595
RFB
GND
4
7
6
5
8
5V VREF
–10V TO 10V
CLK
SRI
LD
12
3
OUT1
33pF
VOUT
0V TO –VREF
1595/96 F01b
–
+
LT1001
P
0.1µF
LTC1595/LTC1596/LTC1596-1
11
159561fb
applicaTions inForMaTion
Bipolar (4-Quadrant Multiplying) Mode
(VOUT = –VREF to VREF)
The LTC1595/LTC1596 can be used with a dual op amp
and three external resistors to provide 4-quadrant multi-
plying operation as shown in Figure 2 (last page). With a
fixed 10V reference, the circuits shown give a precision
bipolar –10V to 10V output swing. Using the LTC1596-1
will cause the power-on reset and clear pin to reset the
DAC to mid-scale (bipolar zero).
Op Amp Selection
Because of the extremely high accuracy of the 16-bit
LTC1595/LTC1596, thought should be given to op amp
selection in order to achieve the exceptional performance
of which the part is capable. Fortunately, the sensitivity of
INL and DNL to op amp offset has been greatly reduced
compared to previous generations of multiplying DACs.
Op amp offset will contribute mostly to output offset and
gain and will have minimal effect on INL and DNL. For
example, a 500µV op amp offset will cause about 0.55LSB
INL degradation and 0.15LSB DNL degradation with a 10V
full-scale range. The main effects of op amp offset will
be a degradation of zero-scale error equal to the op amp
offset, and a degradation of full-scale error equal to twice
the op amp offset. For example, the same 500µV op amp
offset will cause a 3.3LSB zero-scale error and a 6.5LSB
full-scale error with a 10V full-scale range.
Op amp input bias current (IBIAS) contributes only a zero-
scale error equal to IBIAS(RFB) = IBIAS(RREF) = IBIAS(7k).
Table 2 shows a selection of LTC op amps which are
suitable for use with the LTC1595/LTC1596. For a thor-
ough discussion of 16-bit DAC settling time and op amp
selection, refer to Application Note 74, “Component and
Measurement Advances Ensure 16-Bit DAC Settling Time. ”
Grounding
As with any high resolution converter, clean grounding
is important. A low impedance analog ground plane and
star grounding should be used. IOUT2 (LTC1596) and GND
(LTC1595) must be tied to the star ground with as low a
resistance as possible.
Table 2. 16-Bit Settling Time for Various Amplifiers Driven by the LT1595 DAC. LT1468 (Shaded) Offers Fastest Settling Time While
Maintaining Accuracy Over Temperature
AMPLIFIER CONSERVATIVE SETTLING TIME AND COMPENSATION VALUE COMMENTS
LT1001 120µs 100pF Good Low Speed Choice
LT1007 19µs 100pF IB Gives ≈1LSB Error at 25°C
LT1013 75µs 150pF ≈1LSB Error Due to VOS Over Temperature
LT1077 200µs 100pF
LT1097 120µs 75pF Good Low Speed Choice
LT1112 120µs 100pF Good Low Speed Choice Dual
LT1178 450µs 100pF Low Power Dual
LT1468 2.5µs 30pF Fastest Settling with 16-Bit Performance
LTC1595/LTC1596/LTC1596-1
12
159561fb
package DescripTion
N8 Package
8-Lead PDIP (Narrow .300 Inch)
(Reference LTC DWG # 05-08-1510 Rev I)
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
N8 REV I 0711
.065
(1.651)
TYP
.045 – .065
(1.143 – 1.651)
.130 ± .005
(3.302 ± 0.127)
.020
(0.508)
MIN
.018 ± .003
(0.457 ± 0.076)
.120
(3.048)
MIN
.008 – .015
(0.203 – 0.381)
.300 – .325
(7.620 – 8.255)
.325 +.035
–.015
+0.889
–0.381
8.255
( )
1 2 34
87 65
.255 ± .015*
(6.477 ± 0.381)
.400*
(10.160)
MAX
NOTE:
1. DIMENSIONS ARE INCHES
MILLIMETERS
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .010 INCH (0.254mm)
.100
(2.54)
BSC
N Package
8-Lead PDIP (Narrow .300 Inch)
(Reference LTC DWG # 05-08-1510 Rev I)
LTC1595/LTC1596/LTC1596-1
13
159561fb
package DescripTion
S8 Package
8-Lead Plastic Small Outline (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1610)
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
.016 – .050
(0.406 – 1.270)
.010 – .020
(0.254 – 0.508)¥ 45∞
0– 8 TYP
.008 – .010
(0.203 – 0.254)
SO8 0303
.053 – .069
(1.346 – 1.752)
.014 – .019
(0.355 – 0.483)
TYP
.004 – .010
(0.101 – 0.254)
.050
(1.270)
BSC
1234
.150 – .157
(3.810 – 3.988)
NOTE 3
8765
.189 – .197
(4.801 – 5.004)
NOTE 3
.228 – .244
(5.791 – 6.197)
.245
MIN .160 .005
RECOMMENDED SOLDER PAD LAYOUT
.045 .005
.050 BSC
.030 .005
TYP
INCHES
(MILLIMETERS)
NOTE:
1. DIMENSIONS IN
2. DRAWING NOT TO SCALE
3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)
LTC1595/LTC1596/LTC1596-1
14
159561fb
package DescripTion
SW Package
16-Lead Plastic Small Outline (Wide .300 Inch)
(Reference LTC DWG # 05-08-1620)
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
S16 (WIDE) 0502
NOTE 3
.398 – .413
(10.109 – 10.490)
NOTE 4
16 15 14 13 12 11 10 9
1
N
2 3 4567 8
N/2
.394 – .419
(10.007 – 10.643)
.037 – .045
(0.940 – 1.143)
.004 – .012
(0.102 – 0.305)
.093 – .104
(2.362 – 2.642)
.050
(1.270)
BSC .014 – .019
(0.356 – 0.482)
TYP
0 – 8 TYP
NOTE 3
.009 – .013
(0.229 – 0.330)
.005
(0.127)
RAD MIN
.016 – .050
(0.406 – 1.270)
.291 – .299
(7.391 – 7.595)
NOTE 4
¥ 45∞
.010 – .029
(0.254 – 0.737)
INCHES
(MILLIMETERS)
NOTE:
1. DIMENSIONS IN
2. DRAWING NOT TO SCALE
3. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS.
THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS
4. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)
.420
MIN
.325 .005
RECOMMENDED SOLDER PAD LAYOUT
.045 .005
N
1 2 3 N/2
.050 BSC
.030 .005
TYP
LTC1595/LTC1596/LTC1596-1
15
159561fb
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
revision hisTory
REV DATE DESCRIPTION PAGE NUMBER
B 02/12 Removed 16-Lead PDIP 1, 2
(Revision history begins at Rev B)
LTC1595/LTC1596/LTC1596-1
16
159561fb
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com
LINEAR TECHNOLOGY CORPORATION 1997
LT 0212 REV B • PRINTED IN USA
relaTeD parTs
Typical applicaTion
Figure 2. Bipolar Operation (4-Quadrant Multiplication) VOUT = –VREF to VREF
(a)
(b)
Table 3. Bipolar Offset Binary Code Table
DIGITAL INPUT BINARY NUMBER
IN DAC REGISTER ANALOG OUTPUT VOUT
MSB LSB
1111 1111 1111 1111 –VREF (32,767/32,768)
1000 0000 0000 0001 –VREF (1/32,768)
1000 0000 0000 0000 0V
0111 1111 1111 1111 –VREF (1/32,768)
0000 0000 0000 0000 –VREF
PART NUMBER DESCRIPTION COMMENTS
DACs
LTC1590 Dual Serial I/O Multiplying IOUT 12-Bit DAC 16-Pin SO and PDIP, SPI Interface
LTC1597 Parallel 16-Bit Current Output DAC Low Glitch, ±1LSB Maximum INL, DNL
LTC1650 Serial 16-Bit Voltage Output DAC Low Noise and Glitch Rail-to-Rail VOUT
LTC1658 Serial 14-Bit Voltage Output DAC Low Power, 8-Lead MSOP Rail-to-Rail VOUT
LTC7543/LTC8143/LTC8043 Serial I/O Multiplying IOUT 12-Bit DACs Clear Pin and Serial Data Output (LTC8143)
ADCs
LTC1418 14-Bit, 200ksps 5V Sampling ADC 16mW Dissipation, Serial and Parallel Outputs
LTC1604 16-Bit, 333ksps Sampling ADC ±2.5V Input, SINAD = 90dB, THD = 100dB
LTC1605 Single 5V, 16-Bit 100ksps ADC Low Power, ±10V Inputs
LTC2400 24-Bit, ∆∑ ADC in SO-8 1ppm (4ppm) Offset (Full-Scale), Internal 50Hz/60Hz Notches
Op Amps
LT1001 Precision Operational Amplifier Low Offset, Low Drift
LT1112 Dual Low Power, Precision Picoamp Input Op Amp Low Offset, Low Drift
LT1468 90MHz, 22V/µs, 16-Bit Accurate Op Amp Precise, 1µs Settling to 0.0015%
References
LT1236 Precision Reference Ultralow Drift, 5ppm/°C, High Accuracy 0.05%
LT1634 Micropower Reference Ultralow Drift, 10ppm/°C, High Accuracy 0.05%
VDD VREF
LTC1596-1
RFB
AGNDDGND
3
12
10
4
7
5
6
9
8
11
2
1413
5V
VREF
–10V TO 10V
TO NEXT DAC
FOR DAISY-CHAINING
15 16
1
OUT1
33pF
R1
10k
(20k 2)
R2
20k
R3
20k
0.1µF
VOUT
–VREF TO VREF
RESISTORS: CADDOCK T914-20K-010-02
(OR EQUIVALENT) 20k, 0.01%, TC TRACK = 2ppm/°C
1595/96 F02a
OUT2
–
+
1/2 LT1112
CLR
STB3
STB1
SRI
LD1
SRO
LD2
STB2
STB4
µP
–
+
1/2 LT1112
7
6
5
5V
µP
0.1F
VDD VREF
LTC1595
RFB
GND
4
8
VREF
–10V TO 10V
CLK
SRI
LD
12
3
OUT1
VOUT
–VREF TO VREF
1595/96 F02b
–
+
1/2 LT1112
R3
20k
R1
10k
(20k 2)
R2
20k
–
+
1/2 LT1112
33pF
